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Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_63 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_63( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_95 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_5 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg
module PE_5( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Directory_7 : input clock : Clock input reset : Reset output io : { flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, flip read : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>}}, result : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, ready : UInt<1>} smem cc_dir : UInt<13>[16] [2048] inst write_q of Queue1_DirectoryWrite_7 connect write_q.clock, clock connect write_q.reset, reset connect write_q.io.enq.valid, io.write.valid connect write_q.io.enq.bits.data.tag, io.write.bits.data.tag connect write_q.io.enq.bits.data.clients, io.write.bits.data.clients connect write_q.io.enq.bits.data.state, io.write.bits.data.state connect write_q.io.enq.bits.data.dirty, io.write.bits.data.dirty connect write_q.io.enq.bits.way, io.write.bits.way connect write_q.io.enq.bits.set, io.write.bits.set connect io.write.ready, write_q.io.enq.ready regreset wipeCount : UInt<12>, clock, reset, UInt<12>(0h0) regreset wipeOff : UInt<1>, clock, reset, UInt<1>(0h1) connect wipeOff, UInt<1>(0h0) node wipeDone = bits(wipeCount, 11, 11) node wipeSet = bits(wipeCount, 10, 0) connect io.ready, wipeDone node _T = eq(wipeDone, UInt<1>(0h0)) node _T_1 = eq(wipeOff, UInt<1>(0h0)) node _T_2 = and(_T, _T_1) when _T_2 : node _wipeCount_T = add(wipeCount, UInt<1>(0h1)) node _wipeCount_T_1 = tail(_wipeCount_T, 1) connect wipeCount, _wipeCount_T_1 node _T_3 = eq(io.read.valid, UInt<1>(0h0)) node _T_4 = or(wipeDone, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:86 assert (wipeDone || !io.read.valid)\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _wen_T = eq(wipeDone, UInt<1>(0h0)) node _wen_T_1 = eq(wipeOff, UInt<1>(0h0)) node _wen_T_2 = and(_wen_T, _wen_T_1) node wen = or(_wen_T_2, write_q.io.deq.valid) node _T_8 = eq(io.read.valid, UInt<1>(0h0)) node _T_9 = or(_T_8, wipeDone) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:91 assert (!io.read.valid || wipeDone)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 node _q_io_deq_ready_T = eq(io.read.valid, UInt<1>(0h0)) connect write_q.io.deq.ready, _q_io_deq_ready_T node _T_13 = eq(io.read.valid, UInt<1>(0h0)) node _T_14 = and(_T_13, wen) when _T_14 : node _T_15 = mux(wipeDone, write_q.io.deq.bits.set, wipeSet) node lo = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_16 = cat(hi, lo) node _T_17 = mux(wipeDone, _T_16, UInt<1>(0h0)) node lo_1 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_1 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_18 = cat(hi_1, lo_1) node _T_19 = mux(wipeDone, _T_18, UInt<1>(0h0)) node lo_2 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_2 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_20 = cat(hi_2, lo_2) node _T_21 = mux(wipeDone, _T_20, UInt<1>(0h0)) node lo_3 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_3 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_22 = cat(hi_3, lo_3) node _T_23 = mux(wipeDone, _T_22, UInt<1>(0h0)) node lo_4 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_4 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_24 = cat(hi_4, lo_4) node _T_25 = mux(wipeDone, _T_24, UInt<1>(0h0)) node lo_5 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_5 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_26 = cat(hi_5, lo_5) node _T_27 = mux(wipeDone, _T_26, UInt<1>(0h0)) node lo_6 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_6 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_28 = cat(hi_6, lo_6) node _T_29 = mux(wipeDone, _T_28, UInt<1>(0h0)) node lo_7 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_7 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_30 = cat(hi_7, lo_7) node _T_31 = mux(wipeDone, _T_30, UInt<1>(0h0)) node lo_8 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_8 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_32 = cat(hi_8, lo_8) node _T_33 = mux(wipeDone, _T_32, UInt<1>(0h0)) node lo_9 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_9 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_34 = cat(hi_9, lo_9) node _T_35 = mux(wipeDone, _T_34, UInt<1>(0h0)) node lo_10 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_10 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_36 = cat(hi_10, lo_10) node _T_37 = mux(wipeDone, _T_36, UInt<1>(0h0)) node lo_11 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_11 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_38 = cat(hi_11, lo_11) node _T_39 = mux(wipeDone, _T_38, UInt<1>(0h0)) node lo_12 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_12 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_40 = cat(hi_12, lo_12) node _T_41 = mux(wipeDone, _T_40, UInt<1>(0h0)) node lo_13 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_13 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_42 = cat(hi_13, lo_13) node _T_43 = mux(wipeDone, _T_42, UInt<1>(0h0)) node lo_14 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_14 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_44 = cat(hi_14, lo_14) node _T_45 = mux(wipeDone, _T_44, UInt<1>(0h0)) node lo_15 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_15 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_46 = cat(hi_15, lo_15) node _T_47 = mux(wipeDone, _T_46, UInt<1>(0h0)) wire _WIRE : UInt<13>[16] connect _WIRE[0], _T_17 connect _WIRE[1], _T_19 connect _WIRE[2], _T_21 connect _WIRE[3], _T_23 connect _WIRE[4], _T_25 connect _WIRE[5], _T_27 connect _WIRE[6], _T_29 connect _WIRE[7], _T_31 connect _WIRE[8], _T_33 connect _WIRE[9], _T_35 connect _WIRE[10], _T_37 connect _WIRE[11], _T_39 connect _WIRE[12], _T_41 connect _WIRE[13], _T_43 connect _WIRE[14], _T_45 connect _WIRE[15], _T_47 node shiftAmount = bits(write_q.io.deq.bits.way, 3, 0) node _T_48 = dshl(UInt<1>(0h1), shiftAmount) node _T_49 = bits(_T_48, 15, 0) node _T_50 = bits(_T_49, 0, 0) node _T_51 = bits(_T_49, 1, 1) node _T_52 = bits(_T_49, 2, 2) node _T_53 = bits(_T_49, 3, 3) node _T_54 = bits(_T_49, 4, 4) node _T_55 = bits(_T_49, 5, 5) node _T_56 = bits(_T_49, 6, 6) node _T_57 = bits(_T_49, 7, 7) node _T_58 = bits(_T_49, 8, 8) node _T_59 = bits(_T_49, 9, 9) node _T_60 = bits(_T_49, 10, 10) node _T_61 = bits(_T_49, 11, 11) node _T_62 = bits(_T_49, 12, 12) node _T_63 = bits(_T_49, 13, 13) node _T_64 = bits(_T_49, 14, 14) node _T_65 = bits(_T_49, 15, 15) node _T_66 = eq(wipeDone, UInt<1>(0h0)) node _T_67 = or(_T_50, _T_66) node _T_68 = eq(wipeDone, UInt<1>(0h0)) node _T_69 = or(_T_51, _T_68) node _T_70 = eq(wipeDone, UInt<1>(0h0)) node _T_71 = or(_T_52, _T_70) node _T_72 = eq(wipeDone, UInt<1>(0h0)) node _T_73 = or(_T_53, _T_72) node _T_74 = eq(wipeDone, UInt<1>(0h0)) node _T_75 = or(_T_54, _T_74) node _T_76 = eq(wipeDone, UInt<1>(0h0)) node _T_77 = or(_T_55, _T_76) node _T_78 = eq(wipeDone, UInt<1>(0h0)) node _T_79 = or(_T_56, _T_78) node _T_80 = eq(wipeDone, UInt<1>(0h0)) node _T_81 = or(_T_57, _T_80) node _T_82 = eq(wipeDone, UInt<1>(0h0)) node _T_83 = or(_T_58, _T_82) node _T_84 = eq(wipeDone, UInt<1>(0h0)) node _T_85 = or(_T_59, _T_84) node _T_86 = eq(wipeDone, UInt<1>(0h0)) node _T_87 = or(_T_60, _T_86) node _T_88 = eq(wipeDone, UInt<1>(0h0)) node _T_89 = or(_T_61, _T_88) node _T_90 = eq(wipeDone, UInt<1>(0h0)) node _T_91 = or(_T_62, _T_90) node _T_92 = eq(wipeDone, UInt<1>(0h0)) node _T_93 = or(_T_63, _T_92) node _T_94 = eq(wipeDone, UInt<1>(0h0)) node _T_95 = or(_T_64, _T_94) node _T_96 = eq(wipeDone, UInt<1>(0h0)) node _T_97 = or(_T_65, _T_96) write mport MPORT = cc_dir[_T_15], clock when _T_67 : connect MPORT[0], _WIRE[0] when _T_69 : connect MPORT[1], _WIRE[1] when _T_71 : connect MPORT[2], _WIRE[2] when _T_73 : connect MPORT[3], _WIRE[3] when _T_75 : connect MPORT[4], _WIRE[4] when _T_77 : connect MPORT[5], _WIRE[5] when _T_79 : connect MPORT[6], _WIRE[6] when _T_81 : connect MPORT[7], _WIRE[7] when _T_83 : connect MPORT[8], _WIRE[8] when _T_85 : connect MPORT[9], _WIRE[9] when _T_87 : connect MPORT[10], _WIRE[10] when _T_89 : connect MPORT[11], _WIRE[11] when _T_91 : connect MPORT[12], _WIRE[12] when _T_93 : connect MPORT[13], _WIRE[13] when _T_95 : connect MPORT[14], _WIRE[14] when _T_97 : connect MPORT[15], _WIRE[15] regreset ren1 : UInt<1>, clock, reset, UInt<1>(0h0) connect ren1, ren1 connect ren1, io.read.valid node _bypass_T = and(ren1, write_q.io.deq.valid) wire _regout_WIRE : UInt<11> invalidate _regout_WIRE when io.read.valid : connect _regout_WIRE, io.read.bits.set read mport regout = cc_dir[_regout_WIRE], clock reg tag : UInt<9>, clock when io.read.valid : connect tag, io.read.bits.tag reg set : UInt<11>, clock when io.read.valid : connect set, io.read.bits.set inst victimLFSR_prng of MaxPeriodFibonacciLFSR_7 connect victimLFSR_prng.clock, clock connect victimLFSR_prng.reset, reset connect victimLFSR_prng.io.seed.valid, UInt<1>(0h0) invalidate victimLFSR_prng.io.seed.bits[0] invalidate victimLFSR_prng.io.seed.bits[1] invalidate victimLFSR_prng.io.seed.bits[2] invalidate victimLFSR_prng.io.seed.bits[3] invalidate victimLFSR_prng.io.seed.bits[4] invalidate victimLFSR_prng.io.seed.bits[5] invalidate victimLFSR_prng.io.seed.bits[6] invalidate victimLFSR_prng.io.seed.bits[7] invalidate victimLFSR_prng.io.seed.bits[8] invalidate victimLFSR_prng.io.seed.bits[9] invalidate victimLFSR_prng.io.seed.bits[10] invalidate victimLFSR_prng.io.seed.bits[11] invalidate victimLFSR_prng.io.seed.bits[12] invalidate victimLFSR_prng.io.seed.bits[13] invalidate victimLFSR_prng.io.seed.bits[14] invalidate victimLFSR_prng.io.seed.bits[15] connect victimLFSR_prng.io.increment, io.read.valid node victimLFSR_lo_lo_lo = cat(victimLFSR_prng.io.out[1], victimLFSR_prng.io.out[0]) node victimLFSR_lo_lo_hi = cat(victimLFSR_prng.io.out[3], victimLFSR_prng.io.out[2]) node victimLFSR_lo_lo = cat(victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo) node victimLFSR_lo_hi_lo = cat(victimLFSR_prng.io.out[5], victimLFSR_prng.io.out[4]) node victimLFSR_lo_hi_hi = cat(victimLFSR_prng.io.out[7], victimLFSR_prng.io.out[6]) node victimLFSR_lo_hi = cat(victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo) node victimLFSR_lo = cat(victimLFSR_lo_hi, victimLFSR_lo_lo) node victimLFSR_hi_lo_lo = cat(victimLFSR_prng.io.out[9], victimLFSR_prng.io.out[8]) node victimLFSR_hi_lo_hi = cat(victimLFSR_prng.io.out[11], victimLFSR_prng.io.out[10]) node victimLFSR_hi_lo = cat(victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo) node victimLFSR_hi_hi_lo = cat(victimLFSR_prng.io.out[13], victimLFSR_prng.io.out[12]) node victimLFSR_hi_hi_hi = cat(victimLFSR_prng.io.out[15], victimLFSR_prng.io.out[14]) node victimLFSR_hi_hi = cat(victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo) node victimLFSR_hi = cat(victimLFSR_hi_hi, victimLFSR_hi_lo) node _victimLFSR_T = cat(victimLFSR_hi, victimLFSR_lo) node victimLFSR = bits(_victimLFSR_T, 9, 0) node _victimLTE_T = leq(UInt<1>(0h0), victimLFSR) node _victimLTE_T_1 = leq(UInt<7>(0h40), victimLFSR) node _victimLTE_T_2 = leq(UInt<8>(0h80), victimLFSR) node _victimLTE_T_3 = leq(UInt<8>(0hc0), victimLFSR) node _victimLTE_T_4 = leq(UInt<9>(0h100), victimLFSR) node _victimLTE_T_5 = leq(UInt<9>(0h140), victimLFSR) node _victimLTE_T_6 = leq(UInt<9>(0h180), victimLFSR) node _victimLTE_T_7 = leq(UInt<9>(0h1c0), victimLFSR) node _victimLTE_T_8 = leq(UInt<10>(0h200), victimLFSR) node _victimLTE_T_9 = leq(UInt<10>(0h240), victimLFSR) node _victimLTE_T_10 = leq(UInt<10>(0h280), victimLFSR) node _victimLTE_T_11 = leq(UInt<10>(0h2c0), victimLFSR) node _victimLTE_T_12 = leq(UInt<10>(0h300), victimLFSR) node _victimLTE_T_13 = leq(UInt<10>(0h340), victimLFSR) node _victimLTE_T_14 = leq(UInt<10>(0h380), victimLFSR) node _victimLTE_T_15 = leq(UInt<10>(0h3c0), victimLFSR) node victimLTE_lo_lo_lo = cat(_victimLTE_T_1, _victimLTE_T) node victimLTE_lo_lo_hi = cat(_victimLTE_T_3, _victimLTE_T_2) node victimLTE_lo_lo = cat(victimLTE_lo_lo_hi, victimLTE_lo_lo_lo) node victimLTE_lo_hi_lo = cat(_victimLTE_T_5, _victimLTE_T_4) node victimLTE_lo_hi_hi = cat(_victimLTE_T_7, _victimLTE_T_6) node victimLTE_lo_hi = cat(victimLTE_lo_hi_hi, victimLTE_lo_hi_lo) node victimLTE_lo = cat(victimLTE_lo_hi, victimLTE_lo_lo) node victimLTE_hi_lo_lo = cat(_victimLTE_T_9, _victimLTE_T_8) node victimLTE_hi_lo_hi = cat(_victimLTE_T_11, _victimLTE_T_10) node victimLTE_hi_lo = cat(victimLTE_hi_lo_hi, victimLTE_hi_lo_lo) node victimLTE_hi_hi_lo = cat(_victimLTE_T_13, _victimLTE_T_12) node victimLTE_hi_hi_hi = cat(_victimLTE_T_15, _victimLTE_T_14) node victimLTE_hi_hi = cat(victimLTE_hi_hi_hi, victimLTE_hi_hi_lo) node victimLTE_hi = cat(victimLTE_hi_hi, victimLTE_hi_lo) node victimLTE = cat(victimLTE_hi, victimLTE_lo) node _victimSimp_T = bits(victimLTE, 15, 1) node victimSimp_hi = cat(UInt<1>(0h0), _victimSimp_T) node victimSimp = cat(victimSimp_hi, UInt<1>(0h1)) node _victimWayOH_T = bits(victimSimp, 15, 0) node _victimWayOH_T_1 = shr(victimSimp, 1) node _victimWayOH_T_2 = not(_victimWayOH_T_1) node victimWayOH = and(_victimWayOH_T, _victimWayOH_T_2) node victimWay_hi = bits(victimWayOH, 15, 8) node victimWay_lo = bits(victimWayOH, 7, 0) node _victimWay_T = orr(victimWay_hi) node _victimWay_T_1 = or(victimWay_hi, victimWay_lo) node victimWay_hi_1 = bits(_victimWay_T_1, 7, 4) node victimWay_lo_1 = bits(_victimWay_T_1, 3, 0) node _victimWay_T_2 = orr(victimWay_hi_1) node _victimWay_T_3 = or(victimWay_hi_1, victimWay_lo_1) node victimWay_hi_2 = bits(_victimWay_T_3, 3, 2) node victimWay_lo_2 = bits(_victimWay_T_3, 1, 0) node _victimWay_T_4 = orr(victimWay_hi_2) node _victimWay_T_5 = or(victimWay_hi_2, victimWay_lo_2) node _victimWay_T_6 = bits(_victimWay_T_5, 1, 1) node _victimWay_T_7 = cat(_victimWay_T_4, _victimWay_T_6) node _victimWay_T_8 = cat(_victimWay_T_2, _victimWay_T_7) node victimWay = cat(_victimWay_T, _victimWay_T_8) node _T_98 = eq(ren1, UInt<1>(0h0)) node _T_99 = bits(victimLTE, 0, 0) node _T_100 = eq(_T_99, UInt<1>(0h1)) node _T_101 = or(_T_98, _T_100) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:121 assert (!ren2 || victimLTE(0) === 1.U)\n") : printf_2 assert(clock, _T_101, UInt<1>(0h1), "") : assert_2 node _T_105 = eq(ren1, UInt<1>(0h0)) node _T_106 = shr(victimSimp, 1) node _T_107 = not(victimSimp) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = or(_T_105, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:122 assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone\n") : printf_3 assert(clock, _T_110, UInt<1>(0h1), "") : assert_3 node _T_114 = eq(ren1, UInt<1>(0h0)) node _T_115 = bits(victimWayOH, 0, 0) node _T_116 = bits(victimWayOH, 1, 1) node _T_117 = bits(victimWayOH, 2, 2) node _T_118 = bits(victimWayOH, 3, 3) node _T_119 = bits(victimWayOH, 4, 4) node _T_120 = bits(victimWayOH, 5, 5) node _T_121 = bits(victimWayOH, 6, 6) node _T_122 = bits(victimWayOH, 7, 7) node _T_123 = bits(victimWayOH, 8, 8) node _T_124 = bits(victimWayOH, 9, 9) node _T_125 = bits(victimWayOH, 10, 10) node _T_126 = bits(victimWayOH, 11, 11) node _T_127 = bits(victimWayOH, 12, 12) node _T_128 = bits(victimWayOH, 13, 13) node _T_129 = bits(victimWayOH, 14, 14) node _T_130 = bits(victimWayOH, 15, 15) node _T_131 = add(_T_115, _T_116) node _T_132 = bits(_T_131, 1, 0) node _T_133 = add(_T_117, _T_118) node _T_134 = bits(_T_133, 1, 0) node _T_135 = add(_T_132, _T_134) node _T_136 = bits(_T_135, 2, 0) node _T_137 = add(_T_119, _T_120) node _T_138 = bits(_T_137, 1, 0) node _T_139 = add(_T_121, _T_122) node _T_140 = bits(_T_139, 1, 0) node _T_141 = add(_T_138, _T_140) node _T_142 = bits(_T_141, 2, 0) node _T_143 = add(_T_136, _T_142) node _T_144 = bits(_T_143, 3, 0) node _T_145 = add(_T_123, _T_124) node _T_146 = bits(_T_145, 1, 0) node _T_147 = add(_T_125, _T_126) node _T_148 = bits(_T_147, 1, 0) node _T_149 = add(_T_146, _T_148) node _T_150 = bits(_T_149, 2, 0) node _T_151 = add(_T_127, _T_128) node _T_152 = bits(_T_151, 1, 0) node _T_153 = add(_T_129, _T_130) node _T_154 = bits(_T_153, 1, 0) node _T_155 = add(_T_152, _T_154) node _T_156 = bits(_T_155, 2, 0) node _T_157 = add(_T_150, _T_156) node _T_158 = bits(_T_157, 3, 0) node _T_159 = add(_T_144, _T_158) node _T_160 = bits(_T_159, 4, 0) node _T_161 = eq(_T_160, UInt<1>(0h1)) node _T_162 = or(_T_114, _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:123 assert (!ren2 || PopCount(victimWayOH) === 1.U)\n") : printf_4 assert(clock, _T_162, UInt<1>(0h1), "") : assert_4 node _setQuash_T = eq(write_q.io.deq.bits.set, set) node setQuash = and(write_q.io.deq.valid, _setQuash_T) node tagMatch = eq(write_q.io.deq.bits.data.tag, tag) node wayMatch = eq(write_q.io.deq.bits.way, victimWay) wire ways_0 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE : UInt<13> connect _ways_WIRE, regout[0] node _ways_T = bits(_ways_WIRE, 8, 0) connect ways_0.tag, _ways_T node _ways_T_1 = bits(_ways_WIRE, 9, 9) connect ways_0.clients, _ways_T_1 node _ways_T_2 = bits(_ways_WIRE, 11, 10) connect ways_0.state, _ways_T_2 node _ways_T_3 = bits(_ways_WIRE, 12, 12) connect ways_0.dirty, _ways_T_3 wire ways_1 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_1 : UInt<13> connect _ways_WIRE_1, regout[1] node _ways_T_4 = bits(_ways_WIRE_1, 8, 0) connect ways_1.tag, _ways_T_4 node _ways_T_5 = bits(_ways_WIRE_1, 9, 9) connect ways_1.clients, _ways_T_5 node _ways_T_6 = bits(_ways_WIRE_1, 11, 10) connect ways_1.state, _ways_T_6 node _ways_T_7 = bits(_ways_WIRE_1, 12, 12) connect ways_1.dirty, _ways_T_7 wire ways_2 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_2 : UInt<13> connect _ways_WIRE_2, regout[2] node _ways_T_8 = bits(_ways_WIRE_2, 8, 0) connect ways_2.tag, _ways_T_8 node _ways_T_9 = bits(_ways_WIRE_2, 9, 9) connect ways_2.clients, _ways_T_9 node _ways_T_10 = bits(_ways_WIRE_2, 11, 10) connect ways_2.state, _ways_T_10 node _ways_T_11 = bits(_ways_WIRE_2, 12, 12) connect ways_2.dirty, _ways_T_11 wire ways_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_3 : UInt<13> connect _ways_WIRE_3, regout[3] node _ways_T_12 = bits(_ways_WIRE_3, 8, 0) connect ways_3.tag, _ways_T_12 node _ways_T_13 = bits(_ways_WIRE_3, 9, 9) connect ways_3.clients, _ways_T_13 node _ways_T_14 = bits(_ways_WIRE_3, 11, 10) connect ways_3.state, _ways_T_14 node _ways_T_15 = bits(_ways_WIRE_3, 12, 12) connect ways_3.dirty, _ways_T_15 wire ways_4 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_4 : UInt<13> connect _ways_WIRE_4, regout[4] node _ways_T_16 = bits(_ways_WIRE_4, 8, 0) connect ways_4.tag, _ways_T_16 node _ways_T_17 = bits(_ways_WIRE_4, 9, 9) connect ways_4.clients, _ways_T_17 node _ways_T_18 = bits(_ways_WIRE_4, 11, 10) connect ways_4.state, _ways_T_18 node _ways_T_19 = bits(_ways_WIRE_4, 12, 12) connect ways_4.dirty, _ways_T_19 wire ways_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_5 : UInt<13> connect _ways_WIRE_5, regout[5] node _ways_T_20 = bits(_ways_WIRE_5, 8, 0) connect ways_5.tag, _ways_T_20 node _ways_T_21 = bits(_ways_WIRE_5, 9, 9) connect ways_5.clients, _ways_T_21 node _ways_T_22 = bits(_ways_WIRE_5, 11, 10) connect ways_5.state, _ways_T_22 node _ways_T_23 = bits(_ways_WIRE_5, 12, 12) connect ways_5.dirty, _ways_T_23 wire ways_6 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_6 : UInt<13> connect _ways_WIRE_6, regout[6] node _ways_T_24 = bits(_ways_WIRE_6, 8, 0) connect ways_6.tag, _ways_T_24 node _ways_T_25 = bits(_ways_WIRE_6, 9, 9) connect ways_6.clients, _ways_T_25 node _ways_T_26 = bits(_ways_WIRE_6, 11, 10) connect ways_6.state, _ways_T_26 node _ways_T_27 = bits(_ways_WIRE_6, 12, 12) connect ways_6.dirty, _ways_T_27 wire ways_7 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_7 : UInt<13> connect _ways_WIRE_7, regout[7] node _ways_T_28 = bits(_ways_WIRE_7, 8, 0) connect ways_7.tag, _ways_T_28 node _ways_T_29 = bits(_ways_WIRE_7, 9, 9) connect ways_7.clients, _ways_T_29 node _ways_T_30 = bits(_ways_WIRE_7, 11, 10) connect ways_7.state, _ways_T_30 node _ways_T_31 = bits(_ways_WIRE_7, 12, 12) connect ways_7.dirty, _ways_T_31 wire ways_8 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_8 : UInt<13> connect _ways_WIRE_8, regout[8] node _ways_T_32 = bits(_ways_WIRE_8, 8, 0) connect ways_8.tag, _ways_T_32 node _ways_T_33 = bits(_ways_WIRE_8, 9, 9) connect ways_8.clients, _ways_T_33 node _ways_T_34 = bits(_ways_WIRE_8, 11, 10) connect ways_8.state, _ways_T_34 node _ways_T_35 = bits(_ways_WIRE_8, 12, 12) connect ways_8.dirty, _ways_T_35 wire ways_9 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_9 : UInt<13> connect _ways_WIRE_9, regout[9] node _ways_T_36 = bits(_ways_WIRE_9, 8, 0) connect ways_9.tag, _ways_T_36 node _ways_T_37 = bits(_ways_WIRE_9, 9, 9) connect ways_9.clients, _ways_T_37 node _ways_T_38 = bits(_ways_WIRE_9, 11, 10) connect ways_9.state, _ways_T_38 node _ways_T_39 = bits(_ways_WIRE_9, 12, 12) connect ways_9.dirty, _ways_T_39 wire ways_10 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_10 : UInt<13> connect _ways_WIRE_10, regout[10] node _ways_T_40 = bits(_ways_WIRE_10, 8, 0) connect ways_10.tag, _ways_T_40 node _ways_T_41 = bits(_ways_WIRE_10, 9, 9) connect ways_10.clients, _ways_T_41 node _ways_T_42 = bits(_ways_WIRE_10, 11, 10) connect ways_10.state, _ways_T_42 node _ways_T_43 = bits(_ways_WIRE_10, 12, 12) connect ways_10.dirty, _ways_T_43 wire ways_11 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_11 : UInt<13> connect _ways_WIRE_11, regout[11] node _ways_T_44 = bits(_ways_WIRE_11, 8, 0) connect ways_11.tag, _ways_T_44 node _ways_T_45 = bits(_ways_WIRE_11, 9, 9) connect ways_11.clients, _ways_T_45 node _ways_T_46 = bits(_ways_WIRE_11, 11, 10) connect ways_11.state, _ways_T_46 node _ways_T_47 = bits(_ways_WIRE_11, 12, 12) connect ways_11.dirty, _ways_T_47 wire ways_12 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_12 : UInt<13> connect _ways_WIRE_12, regout[12] node _ways_T_48 = bits(_ways_WIRE_12, 8, 0) connect ways_12.tag, _ways_T_48 node _ways_T_49 = bits(_ways_WIRE_12, 9, 9) connect ways_12.clients, _ways_T_49 node _ways_T_50 = bits(_ways_WIRE_12, 11, 10) connect ways_12.state, _ways_T_50 node _ways_T_51 = bits(_ways_WIRE_12, 12, 12) connect ways_12.dirty, _ways_T_51 wire ways_13 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_13 : UInt<13> connect _ways_WIRE_13, regout[13] node _ways_T_52 = bits(_ways_WIRE_13, 8, 0) connect ways_13.tag, _ways_T_52 node _ways_T_53 = bits(_ways_WIRE_13, 9, 9) connect ways_13.clients, _ways_T_53 node _ways_T_54 = bits(_ways_WIRE_13, 11, 10) connect ways_13.state, _ways_T_54 node _ways_T_55 = bits(_ways_WIRE_13, 12, 12) connect ways_13.dirty, _ways_T_55 wire ways_14 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_14 : UInt<13> connect _ways_WIRE_14, regout[14] node _ways_T_56 = bits(_ways_WIRE_14, 8, 0) connect ways_14.tag, _ways_T_56 node _ways_T_57 = bits(_ways_WIRE_14, 9, 9) connect ways_14.clients, _ways_T_57 node _ways_T_58 = bits(_ways_WIRE_14, 11, 10) connect ways_14.state, _ways_T_58 node _ways_T_59 = bits(_ways_WIRE_14, 12, 12) connect ways_14.dirty, _ways_T_59 wire ways_15 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_15 : UInt<13> connect _ways_WIRE_15, regout[15] node _ways_T_60 = bits(_ways_WIRE_15, 8, 0) connect ways_15.tag, _ways_T_60 node _ways_T_61 = bits(_ways_WIRE_15, 9, 9) connect ways_15.clients, _ways_T_61 node _ways_T_62 = bits(_ways_WIRE_15, 11, 10) connect ways_15.state, _ways_T_62 node _ways_T_63 = bits(_ways_WIRE_15, 12, 12) connect ways_15.dirty, _ways_T_63 node _hits_T = eq(ways_0.tag, tag) node _hits_T_1 = neq(ways_0.state, UInt<2>(0h0)) node _hits_T_2 = and(_hits_T, _hits_T_1) node _hits_T_3 = eq(setQuash, UInt<1>(0h0)) node _hits_T_4 = neq(UInt<1>(0h0), write_q.io.deq.bits.way) node _hits_T_5 = or(_hits_T_3, _hits_T_4) node _hits_T_6 = and(_hits_T_2, _hits_T_5) node _hits_T_7 = eq(ways_1.tag, tag) node _hits_T_8 = neq(ways_1.state, UInt<2>(0h0)) node _hits_T_9 = and(_hits_T_7, _hits_T_8) node _hits_T_10 = eq(setQuash, UInt<1>(0h0)) node _hits_T_11 = neq(UInt<1>(0h1), write_q.io.deq.bits.way) node _hits_T_12 = or(_hits_T_10, _hits_T_11) node _hits_T_13 = and(_hits_T_9, _hits_T_12) node _hits_T_14 = eq(ways_2.tag, tag) node _hits_T_15 = neq(ways_2.state, UInt<2>(0h0)) node _hits_T_16 = and(_hits_T_14, _hits_T_15) node _hits_T_17 = eq(setQuash, UInt<1>(0h0)) node _hits_T_18 = neq(UInt<2>(0h2), write_q.io.deq.bits.way) node _hits_T_19 = or(_hits_T_17, _hits_T_18) node _hits_T_20 = and(_hits_T_16, _hits_T_19) node _hits_T_21 = eq(ways_3.tag, tag) node _hits_T_22 = neq(ways_3.state, UInt<2>(0h0)) node _hits_T_23 = and(_hits_T_21, _hits_T_22) node _hits_T_24 = eq(setQuash, UInt<1>(0h0)) node _hits_T_25 = neq(UInt<2>(0h3), write_q.io.deq.bits.way) node _hits_T_26 = or(_hits_T_24, _hits_T_25) node _hits_T_27 = and(_hits_T_23, _hits_T_26) node _hits_T_28 = eq(ways_4.tag, tag) node _hits_T_29 = neq(ways_4.state, UInt<2>(0h0)) node _hits_T_30 = and(_hits_T_28, _hits_T_29) node _hits_T_31 = eq(setQuash, UInt<1>(0h0)) node _hits_T_32 = neq(UInt<3>(0h4), write_q.io.deq.bits.way) node _hits_T_33 = or(_hits_T_31, _hits_T_32) node _hits_T_34 = and(_hits_T_30, _hits_T_33) node _hits_T_35 = eq(ways_5.tag, tag) node _hits_T_36 = neq(ways_5.state, UInt<2>(0h0)) node _hits_T_37 = and(_hits_T_35, _hits_T_36) node _hits_T_38 = eq(setQuash, UInt<1>(0h0)) node _hits_T_39 = neq(UInt<3>(0h5), write_q.io.deq.bits.way) node _hits_T_40 = or(_hits_T_38, _hits_T_39) node _hits_T_41 = and(_hits_T_37, _hits_T_40) node _hits_T_42 = eq(ways_6.tag, tag) node _hits_T_43 = neq(ways_6.state, UInt<2>(0h0)) node _hits_T_44 = and(_hits_T_42, _hits_T_43) node _hits_T_45 = eq(setQuash, UInt<1>(0h0)) node _hits_T_46 = neq(UInt<3>(0h6), write_q.io.deq.bits.way) node _hits_T_47 = or(_hits_T_45, _hits_T_46) node _hits_T_48 = and(_hits_T_44, _hits_T_47) node _hits_T_49 = eq(ways_7.tag, tag) node _hits_T_50 = neq(ways_7.state, UInt<2>(0h0)) node _hits_T_51 = and(_hits_T_49, _hits_T_50) node _hits_T_52 = eq(setQuash, UInt<1>(0h0)) node _hits_T_53 = neq(UInt<3>(0h7), write_q.io.deq.bits.way) node _hits_T_54 = or(_hits_T_52, _hits_T_53) node _hits_T_55 = and(_hits_T_51, _hits_T_54) node _hits_T_56 = eq(ways_8.tag, tag) node _hits_T_57 = neq(ways_8.state, UInt<2>(0h0)) node _hits_T_58 = and(_hits_T_56, _hits_T_57) node _hits_T_59 = eq(setQuash, UInt<1>(0h0)) node _hits_T_60 = neq(UInt<4>(0h8), write_q.io.deq.bits.way) node _hits_T_61 = or(_hits_T_59, _hits_T_60) node _hits_T_62 = and(_hits_T_58, _hits_T_61) node _hits_T_63 = eq(ways_9.tag, tag) node _hits_T_64 = neq(ways_9.state, UInt<2>(0h0)) node _hits_T_65 = and(_hits_T_63, _hits_T_64) node _hits_T_66 = eq(setQuash, UInt<1>(0h0)) node _hits_T_67 = neq(UInt<4>(0h9), write_q.io.deq.bits.way) node _hits_T_68 = or(_hits_T_66, _hits_T_67) node _hits_T_69 = and(_hits_T_65, _hits_T_68) node _hits_T_70 = eq(ways_10.tag, tag) node _hits_T_71 = neq(ways_10.state, UInt<2>(0h0)) node _hits_T_72 = and(_hits_T_70, _hits_T_71) node _hits_T_73 = eq(setQuash, UInt<1>(0h0)) node _hits_T_74 = neq(UInt<4>(0ha), write_q.io.deq.bits.way) node _hits_T_75 = or(_hits_T_73, _hits_T_74) node _hits_T_76 = and(_hits_T_72, _hits_T_75) node _hits_T_77 = eq(ways_11.tag, tag) node _hits_T_78 = neq(ways_11.state, UInt<2>(0h0)) node _hits_T_79 = and(_hits_T_77, _hits_T_78) node _hits_T_80 = eq(setQuash, UInt<1>(0h0)) node _hits_T_81 = neq(UInt<4>(0hb), write_q.io.deq.bits.way) node _hits_T_82 = or(_hits_T_80, _hits_T_81) node _hits_T_83 = and(_hits_T_79, _hits_T_82) node _hits_T_84 = eq(ways_12.tag, tag) node _hits_T_85 = neq(ways_12.state, UInt<2>(0h0)) node _hits_T_86 = and(_hits_T_84, _hits_T_85) node _hits_T_87 = eq(setQuash, UInt<1>(0h0)) node _hits_T_88 = neq(UInt<4>(0hc), write_q.io.deq.bits.way) node _hits_T_89 = or(_hits_T_87, _hits_T_88) node _hits_T_90 = and(_hits_T_86, _hits_T_89) node _hits_T_91 = eq(ways_13.tag, tag) node _hits_T_92 = neq(ways_13.state, UInt<2>(0h0)) node _hits_T_93 = and(_hits_T_91, _hits_T_92) node _hits_T_94 = eq(setQuash, UInt<1>(0h0)) node _hits_T_95 = neq(UInt<4>(0hd), write_q.io.deq.bits.way) node _hits_T_96 = or(_hits_T_94, _hits_T_95) node _hits_T_97 = and(_hits_T_93, _hits_T_96) node _hits_T_98 = eq(ways_14.tag, tag) node _hits_T_99 = neq(ways_14.state, UInt<2>(0h0)) node _hits_T_100 = and(_hits_T_98, _hits_T_99) node _hits_T_101 = eq(setQuash, UInt<1>(0h0)) node _hits_T_102 = neq(UInt<4>(0he), write_q.io.deq.bits.way) node _hits_T_103 = or(_hits_T_101, _hits_T_102) node _hits_T_104 = and(_hits_T_100, _hits_T_103) node _hits_T_105 = eq(ways_15.tag, tag) node _hits_T_106 = neq(ways_15.state, UInt<2>(0h0)) node _hits_T_107 = and(_hits_T_105, _hits_T_106) node _hits_T_108 = eq(setQuash, UInt<1>(0h0)) node _hits_T_109 = neq(UInt<4>(0hf), write_q.io.deq.bits.way) node _hits_T_110 = or(_hits_T_108, _hits_T_109) node _hits_T_111 = and(_hits_T_107, _hits_T_110) node hits_lo_lo_lo = cat(_hits_T_13, _hits_T_6) node hits_lo_lo_hi = cat(_hits_T_27, _hits_T_20) node hits_lo_lo = cat(hits_lo_lo_hi, hits_lo_lo_lo) node hits_lo_hi_lo = cat(_hits_T_41, _hits_T_34) node hits_lo_hi_hi = cat(_hits_T_55, _hits_T_48) node hits_lo_hi = cat(hits_lo_hi_hi, hits_lo_hi_lo) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo_lo = cat(_hits_T_69, _hits_T_62) node hits_hi_lo_hi = cat(_hits_T_83, _hits_T_76) node hits_hi_lo = cat(hits_hi_lo_hi, hits_hi_lo_lo) node hits_hi_hi_lo = cat(_hits_T_97, _hits_T_90) node hits_hi_hi_hi = cat(_hits_T_111, _hits_T_104) node hits_hi_hi = cat(hits_hi_hi_hi, hits_hi_hi_lo) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node hits = cat(hits_hi, hits_lo) node hit = orr(hits) connect io.result.valid, ren1 node _view__T = bits(hits, 0, 0) node _view__T_1 = bits(hits, 1, 1) node _view__T_2 = bits(hits, 2, 2) node _view__T_3 = bits(hits, 3, 3) node _view__T_4 = bits(hits, 4, 4) node _view__T_5 = bits(hits, 5, 5) node _view__T_6 = bits(hits, 6, 6) node _view__T_7 = bits(hits, 7, 7) node _view__T_8 = bits(hits, 8, 8) node _view__T_9 = bits(hits, 9, 9) node _view__T_10 = bits(hits, 10, 10) node _view__T_11 = bits(hits, 11, 11) node _view__T_12 = bits(hits, 12, 12) node _view__T_13 = bits(hits, 13, 13) node _view__T_14 = bits(hits, 14, 14) node _view__T_15 = bits(hits, 15, 15) wire _view__WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_16 = mux(_view__T, ways_0.tag, UInt<1>(0h0)) node _view__T_17 = mux(_view__T_1, ways_1.tag, UInt<1>(0h0)) node _view__T_18 = mux(_view__T_2, ways_2.tag, UInt<1>(0h0)) node _view__T_19 = mux(_view__T_3, ways_3.tag, UInt<1>(0h0)) node _view__T_20 = mux(_view__T_4, ways_4.tag, UInt<1>(0h0)) node _view__T_21 = mux(_view__T_5, ways_5.tag, UInt<1>(0h0)) node _view__T_22 = mux(_view__T_6, ways_6.tag, UInt<1>(0h0)) node _view__T_23 = mux(_view__T_7, ways_7.tag, UInt<1>(0h0)) node _view__T_24 = mux(_view__T_8, ways_8.tag, UInt<1>(0h0)) node _view__T_25 = mux(_view__T_9, ways_9.tag, UInt<1>(0h0)) node _view__T_26 = mux(_view__T_10, ways_10.tag, UInt<1>(0h0)) node _view__T_27 = mux(_view__T_11, ways_11.tag, UInt<1>(0h0)) node _view__T_28 = mux(_view__T_12, ways_12.tag, UInt<1>(0h0)) node _view__T_29 = mux(_view__T_13, ways_13.tag, UInt<1>(0h0)) node _view__T_30 = mux(_view__T_14, ways_14.tag, UInt<1>(0h0)) node _view__T_31 = mux(_view__T_15, ways_15.tag, UInt<1>(0h0)) node _view__T_32 = or(_view__T_16, _view__T_17) node _view__T_33 = or(_view__T_32, _view__T_18) node _view__T_34 = or(_view__T_33, _view__T_19) node _view__T_35 = or(_view__T_34, _view__T_20) node _view__T_36 = or(_view__T_35, _view__T_21) node _view__T_37 = or(_view__T_36, _view__T_22) node _view__T_38 = or(_view__T_37, _view__T_23) node _view__T_39 = or(_view__T_38, _view__T_24) node _view__T_40 = or(_view__T_39, _view__T_25) node _view__T_41 = or(_view__T_40, _view__T_26) node _view__T_42 = or(_view__T_41, _view__T_27) node _view__T_43 = or(_view__T_42, _view__T_28) node _view__T_44 = or(_view__T_43, _view__T_29) node _view__T_45 = or(_view__T_44, _view__T_30) node _view__T_46 = or(_view__T_45, _view__T_31) wire _view__WIRE_1 : UInt<9> connect _view__WIRE_1, _view__T_46 connect _view__WIRE.tag, _view__WIRE_1 node _view__T_47 = mux(_view__T, ways_0.clients, UInt<1>(0h0)) node _view__T_48 = mux(_view__T_1, ways_1.clients, UInt<1>(0h0)) node _view__T_49 = mux(_view__T_2, ways_2.clients, UInt<1>(0h0)) node _view__T_50 = mux(_view__T_3, ways_3.clients, UInt<1>(0h0)) node _view__T_51 = mux(_view__T_4, ways_4.clients, UInt<1>(0h0)) node _view__T_52 = mux(_view__T_5, ways_5.clients, UInt<1>(0h0)) node _view__T_53 = mux(_view__T_6, ways_6.clients, UInt<1>(0h0)) node _view__T_54 = mux(_view__T_7, ways_7.clients, UInt<1>(0h0)) node _view__T_55 = mux(_view__T_8, ways_8.clients, UInt<1>(0h0)) node _view__T_56 = mux(_view__T_9, ways_9.clients, UInt<1>(0h0)) node _view__T_57 = mux(_view__T_10, ways_10.clients, UInt<1>(0h0)) node _view__T_58 = mux(_view__T_11, ways_11.clients, UInt<1>(0h0)) node _view__T_59 = mux(_view__T_12, ways_12.clients, UInt<1>(0h0)) node _view__T_60 = mux(_view__T_13, ways_13.clients, UInt<1>(0h0)) node _view__T_61 = mux(_view__T_14, ways_14.clients, UInt<1>(0h0)) node _view__T_62 = mux(_view__T_15, ways_15.clients, UInt<1>(0h0)) node _view__T_63 = or(_view__T_47, _view__T_48) node _view__T_64 = or(_view__T_63, _view__T_49) node _view__T_65 = or(_view__T_64, _view__T_50) node _view__T_66 = or(_view__T_65, _view__T_51) node _view__T_67 = or(_view__T_66, _view__T_52) node _view__T_68 = or(_view__T_67, _view__T_53) node _view__T_69 = or(_view__T_68, _view__T_54) node _view__T_70 = or(_view__T_69, _view__T_55) node _view__T_71 = or(_view__T_70, _view__T_56) node _view__T_72 = or(_view__T_71, _view__T_57) node _view__T_73 = or(_view__T_72, _view__T_58) node _view__T_74 = or(_view__T_73, _view__T_59) node _view__T_75 = or(_view__T_74, _view__T_60) node _view__T_76 = or(_view__T_75, _view__T_61) node _view__T_77 = or(_view__T_76, _view__T_62) wire _view__WIRE_2 : UInt<1> connect _view__WIRE_2, _view__T_77 connect _view__WIRE.clients, _view__WIRE_2 node _view__T_78 = mux(_view__T, ways_0.state, UInt<1>(0h0)) node _view__T_79 = mux(_view__T_1, ways_1.state, UInt<1>(0h0)) node _view__T_80 = mux(_view__T_2, ways_2.state, UInt<1>(0h0)) node _view__T_81 = mux(_view__T_3, ways_3.state, UInt<1>(0h0)) node _view__T_82 = mux(_view__T_4, ways_4.state, UInt<1>(0h0)) node _view__T_83 = mux(_view__T_5, ways_5.state, UInt<1>(0h0)) node _view__T_84 = mux(_view__T_6, ways_6.state, UInt<1>(0h0)) node _view__T_85 = mux(_view__T_7, ways_7.state, UInt<1>(0h0)) node _view__T_86 = mux(_view__T_8, ways_8.state, UInt<1>(0h0)) node _view__T_87 = mux(_view__T_9, ways_9.state, UInt<1>(0h0)) node _view__T_88 = mux(_view__T_10, ways_10.state, UInt<1>(0h0)) node _view__T_89 = mux(_view__T_11, ways_11.state, UInt<1>(0h0)) node _view__T_90 = mux(_view__T_12, ways_12.state, UInt<1>(0h0)) node _view__T_91 = mux(_view__T_13, ways_13.state, UInt<1>(0h0)) node _view__T_92 = mux(_view__T_14, ways_14.state, UInt<1>(0h0)) node _view__T_93 = mux(_view__T_15, ways_15.state, UInt<1>(0h0)) node _view__T_94 = or(_view__T_78, _view__T_79) node _view__T_95 = or(_view__T_94, _view__T_80) node _view__T_96 = or(_view__T_95, _view__T_81) node _view__T_97 = or(_view__T_96, _view__T_82) node _view__T_98 = or(_view__T_97, _view__T_83) node _view__T_99 = or(_view__T_98, _view__T_84) node _view__T_100 = or(_view__T_99, _view__T_85) node _view__T_101 = or(_view__T_100, _view__T_86) node _view__T_102 = or(_view__T_101, _view__T_87) node _view__T_103 = or(_view__T_102, _view__T_88) node _view__T_104 = or(_view__T_103, _view__T_89) node _view__T_105 = or(_view__T_104, _view__T_90) node _view__T_106 = or(_view__T_105, _view__T_91) node _view__T_107 = or(_view__T_106, _view__T_92) node _view__T_108 = or(_view__T_107, _view__T_93) wire _view__WIRE_3 : UInt<2> connect _view__WIRE_3, _view__T_108 connect _view__WIRE.state, _view__WIRE_3 node _view__T_109 = mux(_view__T, ways_0.dirty, UInt<1>(0h0)) node _view__T_110 = mux(_view__T_1, ways_1.dirty, UInt<1>(0h0)) node _view__T_111 = mux(_view__T_2, ways_2.dirty, UInt<1>(0h0)) node _view__T_112 = mux(_view__T_3, ways_3.dirty, UInt<1>(0h0)) node _view__T_113 = mux(_view__T_4, ways_4.dirty, UInt<1>(0h0)) node _view__T_114 = mux(_view__T_5, ways_5.dirty, UInt<1>(0h0)) node _view__T_115 = mux(_view__T_6, ways_6.dirty, UInt<1>(0h0)) node _view__T_116 = mux(_view__T_7, ways_7.dirty, UInt<1>(0h0)) node _view__T_117 = mux(_view__T_8, ways_8.dirty, UInt<1>(0h0)) node _view__T_118 = mux(_view__T_9, ways_9.dirty, UInt<1>(0h0)) node _view__T_119 = mux(_view__T_10, ways_10.dirty, UInt<1>(0h0)) node _view__T_120 = mux(_view__T_11, ways_11.dirty, UInt<1>(0h0)) node _view__T_121 = mux(_view__T_12, ways_12.dirty, UInt<1>(0h0)) node _view__T_122 = mux(_view__T_13, ways_13.dirty, UInt<1>(0h0)) node _view__T_123 = mux(_view__T_14, ways_14.dirty, UInt<1>(0h0)) node _view__T_124 = mux(_view__T_15, ways_15.dirty, UInt<1>(0h0)) node _view__T_125 = or(_view__T_109, _view__T_110) node _view__T_126 = or(_view__T_125, _view__T_111) node _view__T_127 = or(_view__T_126, _view__T_112) node _view__T_128 = or(_view__T_127, _view__T_113) node _view__T_129 = or(_view__T_128, _view__T_114) node _view__T_130 = or(_view__T_129, _view__T_115) node _view__T_131 = or(_view__T_130, _view__T_116) node _view__T_132 = or(_view__T_131, _view__T_117) node _view__T_133 = or(_view__T_132, _view__T_118) node _view__T_134 = or(_view__T_133, _view__T_119) node _view__T_135 = or(_view__T_134, _view__T_120) node _view__T_136 = or(_view__T_135, _view__T_121) node _view__T_137 = or(_view__T_136, _view__T_122) node _view__T_138 = or(_view__T_137, _view__T_123) node _view__T_139 = or(_view__T_138, _view__T_124) wire _view__WIRE_4 : UInt<1> connect _view__WIRE_4, _view__T_139 connect _view__WIRE.dirty, _view__WIRE_4 node _view__T_140 = or(tagMatch, wayMatch) node _view__T_141 = and(setQuash, _view__T_140) node _view__T_142 = bits(victimWayOH, 0, 0) node _view__T_143 = bits(victimWayOH, 1, 1) node _view__T_144 = bits(victimWayOH, 2, 2) node _view__T_145 = bits(victimWayOH, 3, 3) node _view__T_146 = bits(victimWayOH, 4, 4) node _view__T_147 = bits(victimWayOH, 5, 5) node _view__T_148 = bits(victimWayOH, 6, 6) node _view__T_149 = bits(victimWayOH, 7, 7) node _view__T_150 = bits(victimWayOH, 8, 8) node _view__T_151 = bits(victimWayOH, 9, 9) node _view__T_152 = bits(victimWayOH, 10, 10) node _view__T_153 = bits(victimWayOH, 11, 11) node _view__T_154 = bits(victimWayOH, 12, 12) node _view__T_155 = bits(victimWayOH, 13, 13) node _view__T_156 = bits(victimWayOH, 14, 14) node _view__T_157 = bits(victimWayOH, 15, 15) wire _view__WIRE_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_158 = mux(_view__T_142, ways_0.tag, UInt<1>(0h0)) node _view__T_159 = mux(_view__T_143, ways_1.tag, UInt<1>(0h0)) node _view__T_160 = mux(_view__T_144, ways_2.tag, UInt<1>(0h0)) node _view__T_161 = mux(_view__T_145, ways_3.tag, UInt<1>(0h0)) node _view__T_162 = mux(_view__T_146, ways_4.tag, UInt<1>(0h0)) node _view__T_163 = mux(_view__T_147, ways_5.tag, UInt<1>(0h0)) node _view__T_164 = mux(_view__T_148, ways_6.tag, UInt<1>(0h0)) node _view__T_165 = mux(_view__T_149, ways_7.tag, UInt<1>(0h0)) node _view__T_166 = mux(_view__T_150, ways_8.tag, UInt<1>(0h0)) node _view__T_167 = mux(_view__T_151, ways_9.tag, UInt<1>(0h0)) node _view__T_168 = mux(_view__T_152, ways_10.tag, UInt<1>(0h0)) node _view__T_169 = mux(_view__T_153, ways_11.tag, UInt<1>(0h0)) node _view__T_170 = mux(_view__T_154, ways_12.tag, UInt<1>(0h0)) node _view__T_171 = mux(_view__T_155, ways_13.tag, UInt<1>(0h0)) node _view__T_172 = mux(_view__T_156, ways_14.tag, UInt<1>(0h0)) node _view__T_173 = mux(_view__T_157, ways_15.tag, UInt<1>(0h0)) node _view__T_174 = or(_view__T_158, _view__T_159) node _view__T_175 = or(_view__T_174, _view__T_160) node _view__T_176 = or(_view__T_175, _view__T_161) node _view__T_177 = or(_view__T_176, _view__T_162) node _view__T_178 = or(_view__T_177, _view__T_163) node _view__T_179 = or(_view__T_178, _view__T_164) node _view__T_180 = or(_view__T_179, _view__T_165) node _view__T_181 = or(_view__T_180, _view__T_166) node _view__T_182 = or(_view__T_181, _view__T_167) node _view__T_183 = or(_view__T_182, _view__T_168) node _view__T_184 = or(_view__T_183, _view__T_169) node _view__T_185 = or(_view__T_184, _view__T_170) node _view__T_186 = or(_view__T_185, _view__T_171) node _view__T_187 = or(_view__T_186, _view__T_172) node _view__T_188 = or(_view__T_187, _view__T_173) wire _view__WIRE_6 : UInt<9> connect _view__WIRE_6, _view__T_188 connect _view__WIRE_5.tag, _view__WIRE_6 node _view__T_189 = mux(_view__T_142, ways_0.clients, UInt<1>(0h0)) node _view__T_190 = mux(_view__T_143, ways_1.clients, UInt<1>(0h0)) node _view__T_191 = mux(_view__T_144, ways_2.clients, UInt<1>(0h0)) node _view__T_192 = mux(_view__T_145, ways_3.clients, UInt<1>(0h0)) node _view__T_193 = mux(_view__T_146, ways_4.clients, UInt<1>(0h0)) node _view__T_194 = mux(_view__T_147, ways_5.clients, UInt<1>(0h0)) node _view__T_195 = mux(_view__T_148, ways_6.clients, UInt<1>(0h0)) node _view__T_196 = mux(_view__T_149, ways_7.clients, UInt<1>(0h0)) node _view__T_197 = mux(_view__T_150, ways_8.clients, UInt<1>(0h0)) node _view__T_198 = mux(_view__T_151, ways_9.clients, UInt<1>(0h0)) node _view__T_199 = mux(_view__T_152, ways_10.clients, UInt<1>(0h0)) node _view__T_200 = mux(_view__T_153, ways_11.clients, UInt<1>(0h0)) node _view__T_201 = mux(_view__T_154, ways_12.clients, UInt<1>(0h0)) node _view__T_202 = mux(_view__T_155, ways_13.clients, UInt<1>(0h0)) node _view__T_203 = mux(_view__T_156, ways_14.clients, UInt<1>(0h0)) node _view__T_204 = mux(_view__T_157, ways_15.clients, UInt<1>(0h0)) node _view__T_205 = or(_view__T_189, _view__T_190) node _view__T_206 = or(_view__T_205, _view__T_191) node _view__T_207 = or(_view__T_206, _view__T_192) node _view__T_208 = or(_view__T_207, _view__T_193) node _view__T_209 = or(_view__T_208, _view__T_194) node _view__T_210 = or(_view__T_209, _view__T_195) node _view__T_211 = or(_view__T_210, _view__T_196) node _view__T_212 = or(_view__T_211, _view__T_197) node _view__T_213 = or(_view__T_212, _view__T_198) node _view__T_214 = or(_view__T_213, _view__T_199) node _view__T_215 = or(_view__T_214, _view__T_200) node _view__T_216 = or(_view__T_215, _view__T_201) node _view__T_217 = or(_view__T_216, _view__T_202) node _view__T_218 = or(_view__T_217, _view__T_203) node _view__T_219 = or(_view__T_218, _view__T_204) wire _view__WIRE_7 : UInt<1> connect _view__WIRE_7, _view__T_219 connect _view__WIRE_5.clients, _view__WIRE_7 node _view__T_220 = mux(_view__T_142, ways_0.state, UInt<1>(0h0)) node _view__T_221 = mux(_view__T_143, ways_1.state, UInt<1>(0h0)) node _view__T_222 = mux(_view__T_144, ways_2.state, UInt<1>(0h0)) node _view__T_223 = mux(_view__T_145, ways_3.state, UInt<1>(0h0)) node _view__T_224 = mux(_view__T_146, ways_4.state, UInt<1>(0h0)) node _view__T_225 = mux(_view__T_147, ways_5.state, UInt<1>(0h0)) node _view__T_226 = mux(_view__T_148, ways_6.state, UInt<1>(0h0)) node _view__T_227 = mux(_view__T_149, ways_7.state, UInt<1>(0h0)) node _view__T_228 = mux(_view__T_150, ways_8.state, UInt<1>(0h0)) node _view__T_229 = mux(_view__T_151, ways_9.state, UInt<1>(0h0)) node _view__T_230 = mux(_view__T_152, ways_10.state, UInt<1>(0h0)) node _view__T_231 = mux(_view__T_153, ways_11.state, UInt<1>(0h0)) node _view__T_232 = mux(_view__T_154, ways_12.state, UInt<1>(0h0)) node _view__T_233 = mux(_view__T_155, ways_13.state, UInt<1>(0h0)) node _view__T_234 = mux(_view__T_156, ways_14.state, UInt<1>(0h0)) node _view__T_235 = mux(_view__T_157, ways_15.state, UInt<1>(0h0)) node _view__T_236 = or(_view__T_220, _view__T_221) node _view__T_237 = or(_view__T_236, _view__T_222) node _view__T_238 = or(_view__T_237, _view__T_223) node _view__T_239 = or(_view__T_238, _view__T_224) node _view__T_240 = or(_view__T_239, _view__T_225) node _view__T_241 = or(_view__T_240, _view__T_226) node _view__T_242 = or(_view__T_241, _view__T_227) node _view__T_243 = or(_view__T_242, _view__T_228) node _view__T_244 = or(_view__T_243, _view__T_229) node _view__T_245 = or(_view__T_244, _view__T_230) node _view__T_246 = or(_view__T_245, _view__T_231) node _view__T_247 = or(_view__T_246, _view__T_232) node _view__T_248 = or(_view__T_247, _view__T_233) node _view__T_249 = or(_view__T_248, _view__T_234) node _view__T_250 = or(_view__T_249, _view__T_235) wire _view__WIRE_8 : UInt<2> connect _view__WIRE_8, _view__T_250 connect _view__WIRE_5.state, _view__WIRE_8 node _view__T_251 = mux(_view__T_142, ways_0.dirty, UInt<1>(0h0)) node _view__T_252 = mux(_view__T_143, ways_1.dirty, UInt<1>(0h0)) node _view__T_253 = mux(_view__T_144, ways_2.dirty, UInt<1>(0h0)) node _view__T_254 = mux(_view__T_145, ways_3.dirty, UInt<1>(0h0)) node _view__T_255 = mux(_view__T_146, ways_4.dirty, UInt<1>(0h0)) node _view__T_256 = mux(_view__T_147, ways_5.dirty, UInt<1>(0h0)) node _view__T_257 = mux(_view__T_148, ways_6.dirty, UInt<1>(0h0)) node _view__T_258 = mux(_view__T_149, ways_7.dirty, UInt<1>(0h0)) node _view__T_259 = mux(_view__T_150, ways_8.dirty, UInt<1>(0h0)) node _view__T_260 = mux(_view__T_151, ways_9.dirty, UInt<1>(0h0)) node _view__T_261 = mux(_view__T_152, ways_10.dirty, UInt<1>(0h0)) node _view__T_262 = mux(_view__T_153, ways_11.dirty, UInt<1>(0h0)) node _view__T_263 = mux(_view__T_154, ways_12.dirty, UInt<1>(0h0)) node _view__T_264 = mux(_view__T_155, ways_13.dirty, UInt<1>(0h0)) node _view__T_265 = mux(_view__T_156, ways_14.dirty, UInt<1>(0h0)) node _view__T_266 = mux(_view__T_157, ways_15.dirty, UInt<1>(0h0)) node _view__T_267 = or(_view__T_251, _view__T_252) node _view__T_268 = or(_view__T_267, _view__T_253) node _view__T_269 = or(_view__T_268, _view__T_254) node _view__T_270 = or(_view__T_269, _view__T_255) node _view__T_271 = or(_view__T_270, _view__T_256) node _view__T_272 = or(_view__T_271, _view__T_257) node _view__T_273 = or(_view__T_272, _view__T_258) node _view__T_274 = or(_view__T_273, _view__T_259) node _view__T_275 = or(_view__T_274, _view__T_260) node _view__T_276 = or(_view__T_275, _view__T_261) node _view__T_277 = or(_view__T_276, _view__T_262) node _view__T_278 = or(_view__T_277, _view__T_263) node _view__T_279 = or(_view__T_278, _view__T_264) node _view__T_280 = or(_view__T_279, _view__T_265) node _view__T_281 = or(_view__T_280, _view__T_266) wire _view__WIRE_9 : UInt<1> connect _view__WIRE_9, _view__T_281 connect _view__WIRE_5.dirty, _view__WIRE_9 node _view__T_282 = mux(_view__T_141, write_q.io.deq.bits.data, _view__WIRE_5) node _view__T_283 = mux(hit, _view__WIRE, _view__T_282) connect io.result.bits.tag, _view__T_283.tag connect io.result.bits.clients, _view__T_283.clients connect io.result.bits.state, _view__T_283.state connect io.result.bits.dirty, _view__T_283.dirty node _io_result_bits_hit_T = and(setQuash, tagMatch) node _io_result_bits_hit_T_1 = neq(write_q.io.deq.bits.data.state, UInt<2>(0h0)) node _io_result_bits_hit_T_2 = and(_io_result_bits_hit_T, _io_result_bits_hit_T_1) node _io_result_bits_hit_T_3 = or(hit, _io_result_bits_hit_T_2) connect io.result.bits.hit, _io_result_bits_hit_T_3 node io_result_bits_way_hi = bits(hits, 15, 8) node io_result_bits_way_lo = bits(hits, 7, 0) node _io_result_bits_way_T = orr(io_result_bits_way_hi) node _io_result_bits_way_T_1 = or(io_result_bits_way_hi, io_result_bits_way_lo) node io_result_bits_way_hi_1 = bits(_io_result_bits_way_T_1, 7, 4) node io_result_bits_way_lo_1 = bits(_io_result_bits_way_T_1, 3, 0) node _io_result_bits_way_T_2 = orr(io_result_bits_way_hi_1) node _io_result_bits_way_T_3 = or(io_result_bits_way_hi_1, io_result_bits_way_lo_1) node io_result_bits_way_hi_2 = bits(_io_result_bits_way_T_3, 3, 2) node io_result_bits_way_lo_2 = bits(_io_result_bits_way_T_3, 1, 0) node _io_result_bits_way_T_4 = orr(io_result_bits_way_hi_2) node _io_result_bits_way_T_5 = or(io_result_bits_way_hi_2, io_result_bits_way_lo_2) node _io_result_bits_way_T_6 = bits(_io_result_bits_way_T_5, 1, 1) node _io_result_bits_way_T_7 = cat(_io_result_bits_way_T_4, _io_result_bits_way_T_6) node _io_result_bits_way_T_8 = cat(_io_result_bits_way_T_2, _io_result_bits_way_T_7) node _io_result_bits_way_T_9 = cat(_io_result_bits_way_T, _io_result_bits_way_T_8) node _io_result_bits_way_T_10 = and(setQuash, tagMatch) node _io_result_bits_way_T_11 = mux(_io_result_bits_way_T_10, write_q.io.deq.bits.way, victimWay) node _io_result_bits_way_T_12 = mux(hit, _io_result_bits_way_T_9, _io_result_bits_way_T_11) connect io.result.bits.way, _io_result_bits_way_T_12 node _T_166 = and(ren1, setQuash) node _T_167 = and(_T_166, tagMatch) node _T_168 = and(ren1, setQuash) node _T_169 = eq(tagMatch, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = and(_T_170, wayMatch)
module Directory_7( // @[Directory.scala:56:7] input clock, // @[Directory.scala:56:7] input reset, // @[Directory.scala:56:7] output io_write_ready, // @[Directory.scala:58:14] input io_write_valid, // @[Directory.scala:58:14] input [10:0] io_write_bits_set, // @[Directory.scala:58:14] input [3:0] io_write_bits_way, // @[Directory.scala:58:14] input io_write_bits_data_dirty, // @[Directory.scala:58:14] input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14] input io_write_bits_data_clients, // @[Directory.scala:58:14] input [8:0] io_write_bits_data_tag, // @[Directory.scala:58:14] input io_read_valid, // @[Directory.scala:58:14] input [10:0] io_read_bits_set, // @[Directory.scala:58:14] input [8:0] io_read_bits_tag, // @[Directory.scala:58:14] output io_result_bits_dirty, // @[Directory.scala:58:14] output [1:0] io_result_bits_state, // @[Directory.scala:58:14] output io_result_bits_clients, // @[Directory.scala:58:14] output [8:0] io_result_bits_tag, // @[Directory.scala:58:14] output io_result_bits_hit, // @[Directory.scala:58:14] output [3:0] io_result_bits_way, // @[Directory.scala:58:14] output io_ready // @[Directory.scala:58:14] ); wire cc_dir_MPORT_mask_15; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_14; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_13; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_12; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_11; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_10; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_9; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_8; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65] wire [12:0] _T_47; // @[Directory.scala:99:44] wire [12:0] _T_45; // @[Directory.scala:99:44] wire [12:0] _T_43; // @[Directory.scala:99:44] wire [12:0] _T_41; // @[Directory.scala:99:44] wire [12:0] _T_39; // @[Directory.scala:99:44] wire [12:0] _T_37; // @[Directory.scala:99:44] wire [12:0] _T_35; // @[Directory.scala:99:44] wire [12:0] _T_33; // @[Directory.scala:99:44] wire [12:0] _T_31; // @[Directory.scala:99:44] wire [12:0] _T_29; // @[Directory.scala:99:44] wire [12:0] _T_27; // @[Directory.scala:99:44] wire [12:0] _T_25; // @[Directory.scala:99:44] wire [12:0] _T_23; // @[Directory.scala:99:44] wire [12:0] _T_21; // @[Directory.scala:99:44] wire [12:0] _T_19; // @[Directory.scala:99:44] wire [12:0] _T_17; // @[Directory.scala:99:44] wire [10:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10] wire cc_dir_MPORT_en; // @[Directory.scala:96:14] wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_10; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_11; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_12; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_13; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_14; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_15; // @[PRNG.scala:91:22] wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [10:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21] wire [3:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21] wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21] wire [8:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21] wire [207:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_write_valid_0 = io_write_valid; // @[Directory.scala:56:7] wire [10:0] io_write_bits_set_0 = io_write_bits_set; // @[Directory.scala:56:7] wire [3:0] io_write_bits_way_0 = io_write_bits_way; // @[Directory.scala:56:7] wire io_write_bits_data_dirty_0 = io_write_bits_data_dirty; // @[Directory.scala:56:7] wire [1:0] io_write_bits_data_state_0 = io_write_bits_data_state; // @[Directory.scala:56:7] wire io_write_bits_data_clients_0 = io_write_bits_data_clients; // @[Directory.scala:56:7] wire [8:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[Directory.scala:56:7] wire io_read_valid_0 = io_read_valid; // @[Directory.scala:56:7] wire [10:0] io_read_bits_set_0 = io_read_bits_set; // @[Directory.scala:56:7] wire [8:0] io_read_bits_tag_0 = io_read_bits_tag; // @[Directory.scala:56:7] wire _victimLTE_T = 1'h1; // @[Directory.scala:117:43] wire [10:0] _regout_WIRE = io_read_bits_set_0; // @[Directory.scala:56:7, :110:41] wire _view__T_283_dirty; // @[Directory.scala:136:67] wire [1:0] _view__T_283_state; // @[Directory.scala:136:67] wire _view__T_283_clients; // @[Directory.scala:136:67] wire [8:0] _view__T_283_tag; // @[Directory.scala:136:67] wire _io_result_bits_hit_T_3; // @[Directory.scala:137:29] wire [3:0] _io_result_bits_way_T_12; // @[Directory.scala:138:28] wire wipeDone; // @[Directory.scala:81:27] wire io_write_ready_0; // @[Directory.scala:56:7] wire io_result_bits_dirty_0; // @[Directory.scala:56:7] wire [1:0] io_result_bits_state_0; // @[Directory.scala:56:7] wire io_result_bits_clients_0; // @[Directory.scala:56:7] wire [8:0] io_result_bits_tag_0; // @[Directory.scala:56:7] wire io_result_bits_hit_0; // @[Directory.scala:56:7] wire [3:0] io_result_bits_way_0; // @[Directory.scala:56:7] wire io_result_valid; // @[Directory.scala:56:7] wire io_ready_0; // @[Directory.scala:56:7] wire [12:0] _ways_WIRE = _cc_dir_RW0_rdata[12:0]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_1 = _cc_dir_RW0_rdata[25:13]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_2 = _cc_dir_RW0_rdata[38:26]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_3 = _cc_dir_RW0_rdata[51:39]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_4 = _cc_dir_RW0_rdata[64:52]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_5 = _cc_dir_RW0_rdata[77:65]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_6 = _cc_dir_RW0_rdata[90:78]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_7 = _cc_dir_RW0_rdata[103:91]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_8 = _cc_dir_RW0_rdata[116:104]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_9 = _cc_dir_RW0_rdata[129:117]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_10 = _cc_dir_RW0_rdata[142:130]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_11 = _cc_dir_RW0_rdata[155:143]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_12 = _cc_dir_RW0_rdata[168:156]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_13 = _cc_dir_RW0_rdata[181:169]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_14 = _cc_dir_RW0_rdata[194:182]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_15 = _cc_dir_RW0_rdata[207:195]; // @[DescribedSRAM.scala:17:26] reg [11:0] wipeCount; // @[Directory.scala:79:26] reg wipeOff; // @[Directory.scala:80:24] assign wipeDone = wipeCount[11]; // @[Directory.scala:79:26, :81:27] assign io_ready_0 = wipeDone; // @[Directory.scala:56:7, :81:27] wire [10:0] wipeSet = wipeCount[10:0]; // @[Directory.scala:79:26, :82:26] wire _wen_T_1 = ~wipeOff; // @[Directory.scala:80:24, :85:22, :90:27] wire [12:0] _wipeCount_T = {1'h0, wipeCount} + 13'h1; // @[Directory.scala:79:26, :85:57] wire [11:0] _wipeCount_T_1 = _wipeCount_T[11:0]; // @[Directory.scala:85:57] wire _wen_T = ~wipeDone; // @[Directory.scala:81:27, :85:9, :90:14] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Directory.scala:90:{14,24,27}] wire wen = _wen_T_2 | _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _q_io_deq_ready_T = ~io_read_valid_0; // @[Directory.scala:56:7, :86:23, :95:18] assign cc_dir_MPORT_en = ~io_read_valid_0 & wen; // @[Directory.scala:56:7, :86:23, :90:37, :96:14] assign cc_dir_MPORT_addr = wipeDone ? _write_q_io_deq_bits_set : wipeSet; // @[Decoupled.scala:362:21] wire [9:0] _GEN = {_write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag}; // @[Decoupled.scala:362:21] wire [9:0] lo; // @[Directory.scala:99:71] assign lo = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_1; // @[Directory.scala:99:71] assign lo_1 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_2; // @[Directory.scala:99:71] assign lo_2 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_3; // @[Directory.scala:99:71] assign lo_3 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_4; // @[Directory.scala:99:71] assign lo_4 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_5; // @[Directory.scala:99:71] assign lo_5 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_6; // @[Directory.scala:99:71] assign lo_6 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_7; // @[Directory.scala:99:71] assign lo_7 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_8; // @[Directory.scala:99:71] assign lo_8 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_9; // @[Directory.scala:99:71] assign lo_9 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_10; // @[Directory.scala:99:71] assign lo_10 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_11; // @[Directory.scala:99:71] assign lo_11 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_12; // @[Directory.scala:99:71] assign lo_12 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_13; // @[Directory.scala:99:71] assign lo_13 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_14; // @[Directory.scala:99:71] assign lo_14 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_15; // @[Directory.scala:99:71] assign lo_15 = _GEN; // @[Directory.scala:99:71] wire [2:0] _GEN_0 = {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state}; // @[Decoupled.scala:362:21] wire [2:0] hi; // @[Directory.scala:99:71] assign hi = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_1; // @[Directory.scala:99:71] assign hi_1 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_2; // @[Directory.scala:99:71] assign hi_2 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_3; // @[Directory.scala:99:71] assign hi_3 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_4; // @[Directory.scala:99:71] assign hi_4 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_5; // @[Directory.scala:99:71] assign hi_5 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_6; // @[Directory.scala:99:71] assign hi_6 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_7; // @[Directory.scala:99:71] assign hi_7 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_8; // @[Directory.scala:99:71] assign hi_8 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_9; // @[Directory.scala:99:71] assign hi_9 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_10; // @[Directory.scala:99:71] assign hi_10 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_11; // @[Directory.scala:99:71] assign hi_11 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_12; // @[Directory.scala:99:71] assign hi_12 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_13; // @[Directory.scala:99:71] assign hi_13 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_14; // @[Directory.scala:99:71] assign hi_14 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_15; // @[Directory.scala:99:71] assign hi_15 = _GEN_0; // @[Directory.scala:99:71] assign _T_17 = wipeDone ? {hi, lo} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_19 = wipeDone ? {hi_1, lo_1} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_21 = wipeDone ? {hi_2, lo_2} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_23 = wipeDone ? {hi_3, lo_3} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_25 = wipeDone ? {hi_4, lo_4} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_27 = wipeDone ? {hi_5, lo_5} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_29 = wipeDone ? {hi_6, lo_6} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_31 = wipeDone ? {hi_7, lo_7} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_33 = wipeDone ? {hi_8, lo_8} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_35 = wipeDone ? {hi_9, lo_9} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_37 = wipeDone ? {hi_10, lo_10} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_39 = wipeDone ? {hi_11, lo_11} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_41 = wipeDone ? {hi_12, lo_12} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_43 = wipeDone ? {hi_13, lo_13} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_45 = wipeDone ? {hi_14, lo_14} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_47 = wipeDone ? {hi_15, lo_15} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] wire [3:0] shiftAmount; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_0 = shiftAmount == 4'h0 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_1 = shiftAmount == 4'h1 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_2 = shiftAmount == 4'h2 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_3 = shiftAmount == 4'h3 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_4 = shiftAmount == 4'h4 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_5 = shiftAmount == 4'h5 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_6 = shiftAmount == 4'h6 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_7 = shiftAmount == 4'h7 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_8 = shiftAmount == 4'h8 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_9 = shiftAmount == 4'h9 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_10 = shiftAmount == 4'hA | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_11 = shiftAmount == 4'hB | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_12 = shiftAmount == 4'hC | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_13 = shiftAmount == 4'hD | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_14 = shiftAmount == 4'hE | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_15 = (&shiftAmount) | ~wipeDone; // @[OneHot.scala:64:49] reg ren1; // @[Directory.scala:103:21] assign io_result_valid = ren1; // @[Directory.scala:56:7, :103:21] wire _bypass_T = ren1 & _write_q_io_deq_valid; // @[Decoupled.scala:362:21] reg [8:0] tag; // @[Directory.scala:111:36] reg [10:0] set; // @[Directory.scala:112:36] wire [1:0] victimLFSR_lo_lo_lo = {_victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_lo_hi = {_victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_lo = {victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_lo_hi_lo = {_victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_hi_hi = {_victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_hi = {victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_lo = {victimLFSR_lo_hi, victimLFSR_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_lo_lo = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_lo_hi = {_victimLFSR_prng_io_out_11, _victimLFSR_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_lo = {victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_hi_lo = {_victimLFSR_prng_io_out_13, _victimLFSR_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_hi_hi = {_victimLFSR_prng_io_out_15, _victimLFSR_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_hi = {victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_hi = {victimLFSR_hi_hi, victimLFSR_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _victimLFSR_T = {victimLFSR_hi, victimLFSR_lo}; // @[PRNG.scala:95:17] wire [9:0] victimLFSR = _victimLFSR_T[9:0]; // @[PRNG.scala:95:17] wire _victimLTE_T_1 = |(victimLFSR[9:6]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_2 = |(victimLFSR[9:7]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_3 = victimLFSR > 10'hBF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_4 = |(victimLFSR[9:8]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_5 = victimLFSR > 10'h13F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_6 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_7 = victimLFSR > 10'h1BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_8 = victimLFSR[9]; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_9 = victimLFSR > 10'h23F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_10 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_11 = victimLFSR > 10'h2BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_12 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_13 = victimLFSR > 10'h33F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_14 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_15 = victimLFSR > 10'h3BF; // @[Directory.scala:115:63, :117:43] wire [1:0] victimLTE_lo_lo_lo = {_victimLTE_T_1, 1'h1}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_lo_hi = {_victimLTE_T_3, _victimLTE_T_2}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_lo = {victimLTE_lo_lo_hi, victimLTE_lo_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_lo_hi_lo = {_victimLTE_T_5, _victimLTE_T_4}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_hi_hi = {_victimLTE_T_7, _victimLTE_T_6}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_hi = {victimLTE_lo_hi_hi, victimLTE_lo_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_lo = {victimLTE_lo_hi, victimLTE_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_lo_lo = {_victimLTE_T_9, _victimLTE_T_8}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_lo_hi = {_victimLTE_T_11, _victimLTE_T_10}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_lo = {victimLTE_hi_lo_hi, victimLTE_hi_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_hi_lo = {_victimLTE_T_13, _victimLTE_T_12}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_hi_hi = {_victimLTE_T_15, _victimLTE_T_14}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_hi = {victimLTE_hi_hi_hi, victimLTE_hi_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_hi = {victimLTE_hi_hi, victimLTE_hi_lo}; // @[Directory.scala:117:23] wire [15:0] victimLTE = {victimLTE_hi, victimLTE_lo}; // @[Directory.scala:117:23] wire [14:0] _victimSimp_T = victimLTE[15:1]; // @[Directory.scala:117:23, :118:43] wire [15:0] victimSimp_hi = {1'h0, _victimSimp_T}; // @[Directory.scala:118:{23,43}] wire [16:0] victimSimp = {victimSimp_hi, 1'h1}; // @[Directory.scala:118:23] wire [15:0] _victimWayOH_T = victimSimp[15:0]; // @[Directory.scala:118:23, :119:31] wire [15:0] _victimWayOH_T_1 = victimSimp[16:1]; // @[Directory.scala:118:23, :119:70] wire [15:0] _victimWayOH_T_2 = ~_victimWayOH_T_1; // @[Directory.scala:119:{57,70}] wire [15:0] victimWayOH = _victimWayOH_T & _victimWayOH_T_2; // @[Directory.scala:119:{31,55,57}] wire [7:0] victimWay_hi = victimWayOH[15:8]; // @[OneHot.scala:30:18] wire [7:0] victimWay_lo = victimWayOH[7:0]; // @[OneHot.scala:31:18] wire _victimWay_T = |victimWay_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _victimWay_T_1 = victimWay_hi | victimWay_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] victimWay_hi_1 = _victimWay_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] victimWay_lo_1 = _victimWay_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_2 = |victimWay_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _victimWay_T_3 = victimWay_hi_1 | victimWay_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] victimWay_hi_2 = _victimWay_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] victimWay_lo_2 = _victimWay_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_4 = |victimWay_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _victimWay_T_5 = victimWay_hi_2 | victimWay_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _victimWay_T_6 = _victimWay_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _victimWay_T_7 = {_victimWay_T_4, _victimWay_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _victimWay_T_8 = {_victimWay_T_2, _victimWay_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] victimWay = {_victimWay_T, _victimWay_T_8}; // @[OneHot.scala:32:{10,14}] wire _view__T_142 = victimWayOH[0]; // @[Mux.scala:32:36] wire _view__T_143 = victimWayOH[1]; // @[Mux.scala:32:36] wire _view__T_144 = victimWayOH[2]; // @[Mux.scala:32:36] wire _view__T_145 = victimWayOH[3]; // @[Mux.scala:32:36] wire _view__T_146 = victimWayOH[4]; // @[Mux.scala:32:36] wire _view__T_147 = victimWayOH[5]; // @[Mux.scala:32:36] wire _view__T_148 = victimWayOH[6]; // @[Mux.scala:32:36] wire _view__T_149 = victimWayOH[7]; // @[Mux.scala:32:36] wire _view__T_150 = victimWayOH[8]; // @[Mux.scala:32:36] wire _view__T_151 = victimWayOH[9]; // @[Mux.scala:32:36] wire _view__T_152 = victimWayOH[10]; // @[Mux.scala:32:36] wire _view__T_153 = victimWayOH[11]; // @[Mux.scala:32:36] wire _view__T_154 = victimWayOH[12]; // @[Mux.scala:32:36] wire _view__T_155 = victimWayOH[13]; // @[Mux.scala:32:36] wire _view__T_156 = victimWayOH[14]; // @[Mux.scala:32:36] wire _view__T_157 = victimWayOH[15]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSource_Phit_16 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} wire sink_ready : UInt<1> connect sink_ready, UInt<1>(0h1) reg mem : { phit : UInt<32>}[8], clock node _widx_T = asAsyncReset(reset) node _widx_T_1 = and(io.enq.ready, io.enq.valid) node _widx_T_2 = eq(sink_ready, UInt<1>(0h0)) wire widx_incremented : UInt<4> regreset widx_widx_bin : UInt, clock, _widx_T, UInt<1>(0h0) connect widx_widx_bin, widx_incremented node _widx_incremented_T = add(widx_widx_bin, _widx_T_1) node _widx_incremented_T_1 = tail(_widx_incremented_T, 1) node _widx_incremented_T_2 = mux(_widx_T_2, UInt<1>(0h0), _widx_incremented_T_1) connect widx_incremented, _widx_incremented_T_2 node _widx_T_3 = shr(widx_incremented, 1) node widx = xor(widx_incremented, _widx_T_3) inst ridx_ridx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_32 connect ridx_ridx_gray.clock, clock connect ridx_ridx_gray.reset, reset connect ridx_ridx_gray.io.d, io.async.ridx wire ridx : UInt<4> connect ridx, ridx_ridx_gray.io.q node _ready_T = xor(ridx, UInt<4>(0hc)) node _ready_T_1 = neq(widx, _ready_T) node ready = and(sink_ready, _ready_T_1) node _index_T = bits(io.async.widx, 2, 0) node _index_T_1 = bits(io.async.widx, 3, 3) node _index_T_2 = shl(_index_T_1, 2) node index = xor(_index_T, _index_T_2) node _T = and(io.enq.ready, io.enq.valid) when _T : connect mem[index], io.enq.bits node _ready_reg_T = asAsyncReset(reset) regreset ready_reg : UInt<1>, clock, _ready_reg_T, UInt<1>(0h0) connect ready_reg, ready node _io_enq_ready_T = and(ready_reg, sink_ready) connect io.enq.ready, _io_enq_ready_T node _widx_reg_T = asAsyncReset(reset) regreset widx_gray : UInt, clock, _widx_reg_T, UInt<1>(0h0) connect widx_gray, widx connect io.async.widx, widx_gray connect io.async.mem, mem inst source_valid_0 of AsyncValidSync_152 inst source_valid_1 of AsyncValidSync_153 inst sink_extend of AsyncValidSync_154 inst sink_valid of AsyncValidSync_155 node _source_valid_0_reset_T = asUInt(reset) node _source_valid_0_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _source_valid_0_reset_T_2 = or(_source_valid_0_reset_T, _source_valid_0_reset_T_1) node _source_valid_0_reset_T_3 = asAsyncReset(_source_valid_0_reset_T_2) connect source_valid_0.reset, _source_valid_0_reset_T_3 node _source_valid_1_reset_T = asUInt(reset) node _source_valid_1_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _source_valid_1_reset_T_2 = or(_source_valid_1_reset_T, _source_valid_1_reset_T_1) node _source_valid_1_reset_T_3 = asAsyncReset(_source_valid_1_reset_T_2) connect source_valid_1.reset, _source_valid_1_reset_T_3 node _sink_extend_reset_T = asUInt(reset) node _sink_extend_reset_T_1 = eq(io.async.safe.sink_reset_n, UInt<1>(0h0)) node _sink_extend_reset_T_2 = or(_sink_extend_reset_T, _sink_extend_reset_T_1) node _sink_extend_reset_T_3 = asAsyncReset(_sink_extend_reset_T_2) connect sink_extend.reset, _sink_extend_reset_T_3 node _sink_valid_reset_T = asAsyncReset(reset) connect sink_valid.reset, _sink_valid_reset_T connect source_valid_0.clock, clock connect source_valid_1.clock, clock connect sink_extend.clock, clock connect sink_valid.clock, clock connect source_valid_0.io.in, UInt<1>(0h1) connect source_valid_1.io.in, source_valid_0.io.out connect io.async.safe.widx_valid, source_valid_1.io.out connect sink_extend.io.in, io.async.safe.ridx_valid connect sink_valid.io.in, sink_extend.io.out connect sink_ready, sink_valid.io.out node _io_async_safe_source_reset_n_T = asUInt(reset) node _io_async_safe_source_reset_n_T_1 = eq(_io_async_safe_source_reset_n_T, UInt<1>(0h0)) connect io.async.safe.source_reset_n, _io_async_safe_source_reset_n_T_1
module AsyncQueueSource_Phit_16( // @[AsyncQueue.scala:70:7] input clock, // @[AsyncQueue.scala:70:7] input reset, // @[AsyncQueue.scala:70:7] output io_enq_ready, // @[AsyncQueue.scala:73:14] input io_enq_valid, // @[AsyncQueue.scala:73:14] input [31:0] io_enq_bits_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:73:14] output [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:73:14] input [3:0] io_async_ridx, // @[AsyncQueue.scala:73:14] output [3:0] io_async_widx, // @[AsyncQueue.scala:73:14] input io_async_safe_ridx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_widx_valid, // @[AsyncQueue.scala:73:14] output io_async_safe_source_reset_n, // @[AsyncQueue.scala:73:14] input io_async_safe_sink_reset_n // @[AsyncQueue.scala:73:14] ); wire _sink_extend_io_out; // @[AsyncQueue.scala:105:30] wire _source_valid_0_io_out; // @[AsyncQueue.scala:102:32] wire io_enq_valid_0 = io_enq_valid; // @[AsyncQueue.scala:70:7] wire [31:0] io_enq_bits_phit_0 = io_enq_bits_phit; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_ridx_0 = io_async_ridx; // @[AsyncQueue.scala:70:7] wire io_async_safe_ridx_valid_0 = io_async_safe_ridx_valid; // @[AsyncQueue.scala:70:7] wire io_async_safe_sink_reset_n_0 = io_async_safe_sink_reset_n; // @[AsyncQueue.scala:70:7] wire _widx_T = reset; // @[AsyncQueue.scala:83:30] wire _ready_reg_T = reset; // @[AsyncQueue.scala:90:35] wire _widx_reg_T = reset; // @[AsyncQueue.scala:93:34] wire _source_valid_0_reset_T = reset; // @[AsyncQueue.scala:107:36] wire _source_valid_1_reset_T = reset; // @[AsyncQueue.scala:108:36] wire _sink_extend_reset_T = reset; // @[AsyncQueue.scala:109:36] wire _sink_valid_reset_T = reset; // @[AsyncQueue.scala:110:35] wire _io_async_safe_source_reset_n_T = reset; // @[AsyncQueue.scala:123:34] wire _io_enq_ready_T; // @[AsyncQueue.scala:91:29] wire _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:123:27] wire io_enq_ready_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_0_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_1_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_2_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_3_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_4_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_5_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_6_phit_0; // @[AsyncQueue.scala:70:7] wire [31:0] io_async_mem_7_phit_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_widx_valid_0; // @[AsyncQueue.scala:70:7] wire io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:70:7] wire [3:0] io_async_widx_0; // @[AsyncQueue.scala:70:7] wire sink_ready; // @[AsyncQueue.scala:81:28] reg [31:0] mem_0_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_0_phit_0 = mem_0_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_1_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_1_phit_0 = mem_1_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_2_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_2_phit_0 = mem_2_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_3_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_3_phit_0 = mem_3_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_4_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_4_phit_0 = mem_4_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_5_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_5_phit_0 = mem_5_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_6_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_6_phit_0 = mem_6_phit; // @[AsyncQueue.scala:70:7, :82:16] reg [31:0] mem_7_phit; // @[AsyncQueue.scala:82:16] assign io_async_mem_7_phit_0 = mem_7_phit; // @[AsyncQueue.scala:70:7, :82:16] wire _widx_T_1 = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire _widx_T_2 = ~sink_ready; // @[AsyncQueue.scala:81:28, :83:77] wire [3:0] _widx_incremented_T_2; // @[AsyncQueue.scala:53:23] wire [3:0] widx_incremented; // @[AsyncQueue.scala:51:27] reg [3:0] widx_widx_bin; // @[AsyncQueue.scala:52:25] wire [4:0] _widx_incremented_T = {1'h0, widx_widx_bin} + {4'h0, _widx_T_1}; // @[Decoupled.scala:51:35] wire [3:0] _widx_incremented_T_1 = _widx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43] assign _widx_incremented_T_2 = _widx_T_2 ? 4'h0 : _widx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :83:77] assign widx_incremented = _widx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23] wire [2:0] _widx_T_3 = widx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32] wire [3:0] widx = {widx_incremented[3], widx_incremented[2:0] ^ _widx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}] wire [3:0] ridx; // @[ShiftReg.scala:48:24] wire [3:0] _ready_T = ridx ^ 4'hC; // @[ShiftReg.scala:48:24] wire _ready_T_1 = widx != _ready_T; // @[AsyncQueue.scala:54:17, :85:{34,44}] wire ready = sink_ready & _ready_T_1; // @[AsyncQueue.scala:81:28, :85:{26,34}] wire [2:0] _index_T = io_async_widx_0[2:0]; // @[AsyncQueue.scala:70:7, :87:52] wire _index_T_1 = io_async_widx_0[3]; // @[AsyncQueue.scala:70:7, :87:80] wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:87:{80,93}] wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:87:{52,64,93}] reg ready_reg; // @[AsyncQueue.scala:90:56] assign _io_enq_ready_T = ready_reg & sink_ready; // @[AsyncQueue.scala:81:28, :90:56, :91:29] assign io_enq_ready_0 = _io_enq_ready_T; // @[AsyncQueue.scala:70:7, :91:29] reg [3:0] widx_gray; // @[AsyncQueue.scala:93:55] assign io_async_widx_0 = widx_gray; // @[AsyncQueue.scala:70:7, :93:55] wire _source_valid_0_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46] wire _source_valid_0_reset_T_2 = _source_valid_0_reset_T | _source_valid_0_reset_T_1; // @[AsyncQueue.scala:107:{36,43,46}] wire _source_valid_0_reset_T_3 = _source_valid_0_reset_T_2; // @[AsyncQueue.scala:107:{43,65}] wire _source_valid_1_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :108:46] wire _source_valid_1_reset_T_2 = _source_valid_1_reset_T | _source_valid_1_reset_T_1; // @[AsyncQueue.scala:108:{36,43,46}] wire _source_valid_1_reset_T_3 = _source_valid_1_reset_T_2; // @[AsyncQueue.scala:108:{43,65}] wire _sink_extend_reset_T_1 = ~io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:70:7, :107:46, :109:46] wire _sink_extend_reset_T_2 = _sink_extend_reset_T | _sink_extend_reset_T_1; // @[AsyncQueue.scala:109:{36,43,46}] wire _sink_extend_reset_T_3 = _sink_extend_reset_T_2; // @[AsyncQueue.scala:109:{43,65}] assign _io_async_safe_source_reset_n_T_1 = ~_io_async_safe_source_reset_n_T; // @[AsyncQueue.scala:123:{27,34}] assign io_async_safe_source_reset_n_0 = _io_async_safe_source_reset_n_T_1; // @[AsyncQueue.scala:70:7, :123:27] always @(posedge clock) begin // @[AsyncQueue.scala:70:7] if (_widx_T_1 & index == 3'h0) // @[Decoupled.scala:51:35] mem_0_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h1) // @[Decoupled.scala:51:35] mem_1_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h2) // @[Decoupled.scala:51:35] mem_2_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h3) // @[Decoupled.scala:51:35] mem_3_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h4) // @[Decoupled.scala:51:35] mem_4_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h5) // @[Decoupled.scala:51:35] mem_5_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & index == 3'h6) // @[Decoupled.scala:51:35] mem_6_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] if (_widx_T_1 & (&index)) // @[Decoupled.scala:51:35] mem_7_phit <= io_enq_bits_phit_0; // @[AsyncQueue.scala:70:7, :82:16] always @(posedge) always @(posedge clock or posedge _widx_T) begin // @[AsyncQueue.scala:70:7, :83:30] if (_widx_T) // @[AsyncQueue.scala:70:7, :83:30] widx_widx_bin <= 4'h0; // @[AsyncQueue.scala:52:25] else // @[AsyncQueue.scala:70:7] widx_widx_bin <= widx_incremented; // @[AsyncQueue.scala:51:27, :52:25] always @(posedge, posedge) always @(posedge clock or posedge _ready_reg_T) begin // @[AsyncQueue.scala:70:7, :90:35] if (_ready_reg_T) // @[AsyncQueue.scala:70:7, :90:35] ready_reg <= 1'h0; // @[AsyncQueue.scala:90:56] else // @[AsyncQueue.scala:70:7] ready_reg <= ready; // @[AsyncQueue.scala:85:26, :90:56] always @(posedge, posedge) always @(posedge clock or posedge _widx_reg_T) begin // @[AsyncQueue.scala:70:7, :93:34] if (_widx_reg_T) // @[AsyncQueue.scala:70:7, :93:34] widx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :93:55] else // @[AsyncQueue.scala:70:7] widx_gray <= widx; // @[AsyncQueue.scala:54:17, :93:55] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_46 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T
module MulAddRecFNToRaw_preMul_e8_s24_46(); // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [8:0] rawB_exp = 9'h100; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _rawB_isZero_T = 3'h4; // @[rawFloatFromRecFN.scala:52:28] wire [1:0] _rawA_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [1:0] _rawB_isSpecial_T = 2'h2; // @[rawFloatFromRecFN.scala:53:28] wire [9:0] rawA_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawA_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] rawB_sExp = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawB_out_sExp_T = 10'h100; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [1:0] _rawA_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [1:0] _rawB_out_sig_T_1 = 2'h1; // @[rawFloatFromRecFN.scala:61:32] wire [24:0] rawA_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawA_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] rawB_sig = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawB_out_sig_T_3 = 25'h800000; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = 9'h2B; // @[rawFloatFromRecFN.scala:51:21] wire [9:0] rawC_sExp = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [9:0] _rawC_out_sExp_T = 10'h2B; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire [22:0] _rawA_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawB_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [22:0] _rawC_out_sig_T_2 = 23'h0; // @[rawFloatFromRecFN.scala:61:49] wire [24:0] rawC_sig = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [24:0] _rawC_out_sig_T_3 = 25'h0; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [10:0] _sExpAlignedProd_T = 11'h200; // @[MulAddRecFN.scala:100:19] wire [11:0] _sExpAlignedProd_T_1 = 12'h11B; // @[MulAddRecFN.scala:100:32] wire [10:0] _sExpAlignedProd_T_2 = 11'h11B; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = 11'h11B; // @[MulAddRecFN.scala:100:32] wire [11:0] _sNatCAlignDist_T = 12'hF0; // @[MulAddRecFN.scala:106:42] wire [10:0] _sNatCAlignDist_T_1 = 11'hF0; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = 11'hF0; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = 10'hF0; // @[MulAddRecFN.scala:107:42] wire [6:0] _CAlignDist_T_1 = 7'h70; // @[MulAddRecFN.scala:115:33] wire [6:0] _CAlignDist_T_2 = 7'h4A; // @[MulAddRecFN.scala:112:12, :114:16] wire [6:0] CAlignDist = 7'h4A; // @[MulAddRecFN.scala:112:12, :114:16] wire [24:0] _mainAlignedSigC_T = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:{13,25}] wire [24:0] _mainAlignedSigC_T_1 = 25'h1FFFFFF; // @[MulAddRecFN.scala:120:{13,25}] wire [52:0] _mainAlignedSigC_T_2 = 53'h1FFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:53] wire [77:0] _mainAlignedSigC_T_3 = 78'h3FFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:{46,94,100}] wire [77:0] _mainAlignedSigC_T_4 = 78'h3FFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:{94,100}] wire [77:0] mainAlignedSigC = 78'h3FFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:120:{94,100}] wire [26:0] _reduced4CExtra_T = 27'h0; // @[MulAddRecFN.scala:122:30] wire [2:0] _rawC_isZero_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] _reduced4CExtra_reducedVec_6_T = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [2:0] reduced4CExtra_lo = 3'h0; // @[rawFloatFromRecFN.scala:52:28] wire [3:0] _reduced4CExtra_reducedVec_0_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_1_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_2_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_3_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_4_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] _reduced4CExtra_reducedVec_5_T = 4'h0; // @[primitives.scala:120:33, :124:20] wire [3:0] reduced4CExtra_hi = 4'h0; // @[primitives.scala:120:33, :124:20] wire [4:0] _reduced4CExtra_T_2 = 5'h12; // @[MulAddRecFN.scala:124:28] wire [32:0] reduced4CExtra_shift = 33'h1FFFFC000; // @[primitives.scala:76:56] wire [3:0] _reduced4CExtra_T_4 = 4'hF; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = 4'hF; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_5 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = 2'h3; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = 2'h3; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_3 = 6'h3F; // @[primitives.scala:77:20, :78:22] wire [5:0] _reduced4CExtra_T_18 = 6'h3F; // @[primitives.scala:77:20, :78:22] wire [6:0] _reduced4CExtra_T_1 = 7'h0; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_19 = 7'h0; // @[primitives.scala:124:20] wire [2:0] _alignedSigC_T_1 = 3'h7; // @[MulAddRecFN.scala:134:32, :135:32] wire [2:0] _alignedSigC_T_5 = 3'h7; // @[MulAddRecFN.scala:134:32, :135:32] wire [74:0] _alignedSigC_T = 75'h7FFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:132:{12,28}] wire [74:0] alignedSigC_hi = 75'h7FFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:132:12] wire [75:0] alignedSigC = 76'hFFFFFFFFFFFFFFFFFFF; // @[MulAddRecFN.scala:132:12] wire [11:0] _io_toPostMul_sExpSum_T = 12'h103; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = 11'h103; // @[MulAddRecFN.scala:158:{12,53}] wire [10:0] _io_toPostMul_sExpSum_T_2 = 11'h103; // @[MulAddRecFN.scala:158:{12,53}] wire [10:0] _io_toPostMul_sExpSum_T_3 = 11'h103; // @[MulAddRecFN.scala:158:{12,53}] wire [25:0] io_toPostMul_highAlignedSigC = 26'h3FFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :163:20] wire [25:0] _io_toPostMul_highAlignedSigC_T = 26'h3FFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :163:20] wire [4:0] io_toPostMul_CDom_CAlignDist = 5'hA; // @[MulAddRecFN.scala:71:7, :74:16, :161:47] wire [4:0] _io_toPostMul_CDom_CAlignDist_T = 5'hA; // @[MulAddRecFN.scala:71:7, :74:16, :161:47] wire [9:0] io_toPostMul_sExpSum = 10'h103; // @[MulAddRecFN.scala:71:7, :74:16, :157:28] wire io_toPostMul_signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_isZeroC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_doSubMags = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_bit0AlignedSigC = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawA_sign = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_sign_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawA_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawB_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawB_out_sig_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawC_isZero = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire rawC_isZero_0 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _rawC_out_isInf_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _signProd_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire signProd = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _doSubMags_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire doSubMags = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _reduced4CExtra_T_6 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _reduced4CExtra_T_7 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _reduced4CExtra_T_10 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _reduced4CExtra_T_11 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _reduced4CExtra_T_15 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _reduced4CExtra_T_16 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_2 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_3 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_6 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_7 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _alignedSigC_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_1 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_4 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_8 = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire _io_toPostMul_bit0AlignedSigC_T = 1'h1; // @[rawFloatFromRecFN.scala:52:53, :55:23, :57:36, :59:25, :61:35] wire io_toPostMul_isSigNaNAny = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isNaNAOrB = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isInfA = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isZeroA = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isInfB = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isZeroB = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isNaNC = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_isInfC = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire io_toPostMul_CIsDominant = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawA_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawA_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawA_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawA_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawA_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawA_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawA_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawA_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawA_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawB_isZero = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawB_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawB_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawB_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawB_isZero_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawB_sign = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawB_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawB_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawB_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawB_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawB_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawC_isSpecial = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawC_isNaN = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawC_isInf = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire rawC_sign = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawC_out_isNaN_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawC_out_isNaN_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawC_out_isInf_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawC_out_isInf_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawC_out_sign_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _rawC_out_sig_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _signProd_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _doSubMags_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _isMinCAlign_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _isMinCAlign_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire isMinCAlign = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _CIsDominant_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _CIsDominant_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _CIsDominant_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire CIsDominant = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _CAlignDist_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_0 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_3 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_4 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_5 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra_reducedVec_6 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_0_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_1_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_2_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_3_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_4_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_5_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _reduced4CExtra_reducedVec_6_T_1 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire reduced4CExtra = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_2 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_3 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_5 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_6 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_7 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_9 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isSigNaNAny_T_10 = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire _io_toPostMul_isNaNAOrB_T = 1'h0; // @[rawFloatFromRecFN.scala:52:53, :53:53, :55:23, :56:{33,41}, :57:{33,41}, :59:25, :61:35] wire [47:0] io_mulAddC = 48'hFFFFFFFFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :143:30] wire [47:0] _io_mulAddC_T = 48'hFFFFFFFFFFFF; // @[MulAddRecFN.scala:71:7, :74:16, :143:30] wire [23:0] io_mulAddA = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :141:16, :142:16] wire [23:0] io_mulAddB = 24'h800000; // @[MulAddRecFN.scala:71:7, :74:16, :141:16, :142:16] wire [32:0] io_c = 33'h15800000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [32:0] io_a = 33'h180000000; // @[MulAddRecFN.scala:71:7, :74:16] wire [1:0] io_op = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_isSpecial_T = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] _rawC_out_sig_T_1 = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_lo_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_lo = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] wire [1:0] reduced4CExtra_hi_hi = 2'h0; // @[rawFloatFromRecFN.scala:53:28, :61:32] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_55 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<7>(0h40))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<5>(0h14))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_31 = cvt(_T_30) node _T_32 = and(_T_31, asSInt(UInt<4>(0h8))) node _T_33 = asSInt(_T_32) node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_36 = cvt(_T_35) node _T_37 = and(_T_36, asSInt(UInt<6>(0h20))) node _T_38 = asSInt(_T_37) node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_41 = cvt(_T_40) node _T_42 = and(_T_41, asSInt(UInt<8>(0h80))) node _T_43 = asSInt(_T_42) node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0))) node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<9>(0h100))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_24, _T_29) node _T_51 = or(_T_50, _T_34) node _T_52 = or(_T_51, _T_39) node _T_53 = or(_T_52, _T_44) node _T_54 = or(_T_53, _T_49) node _T_55 = and(_T_19, _T_54) node _T_56 = or(UInt<1>(0h0), _T_55) node _T_57 = and(_T_18, _T_56) node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_T_57, UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_57, UInt<1>(0h1), "") : assert_2 node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_63 = and(_T_61, _T_62) node _T_64 = or(UInt<1>(0h0), _T_63) node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<7>(0h40))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<5>(0h14))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<4>(0h8))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<6>(0h20))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<8>(0h80))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<9>(0h100))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_69, _T_74) node _T_96 = or(_T_95, _T_79) node _T_97 = or(_T_96, _T_84) node _T_98 = or(_T_97, _T_89) node _T_99 = or(_T_98, _T_94) node _T_100 = and(_T_64, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_102, UInt<1>(0h1), "") : assert_3 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_109, UInt<1>(0h1), "") : assert_5 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_116, UInt<1>(0h1), "") : assert_7 node _T_120 = not(io.in.a.bits.mask) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_121, UInt<1>(0h1), "") : assert_8 node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_125, UInt<1>(0h1), "") : assert_9 node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_129 : node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_131 = and(UInt<1>(0h0), _T_130) node _T_132 = or(UInt<1>(0h0), _T_131) node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_135 = cvt(_T_134) node _T_136 = and(_T_135, asSInt(UInt<7>(0h40))) node _T_137 = asSInt(_T_136) node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0))) node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_140 = cvt(_T_139) node _T_141 = and(_T_140, asSInt(UInt<5>(0h14))) node _T_142 = asSInt(_T_141) node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0))) node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_145 = cvt(_T_144) node _T_146 = and(_T_145, asSInt(UInt<4>(0h8))) node _T_147 = asSInt(_T_146) node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_150 = cvt(_T_149) node _T_151 = and(_T_150, asSInt(UInt<6>(0h20))) node _T_152 = asSInt(_T_151) node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0))) node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<8>(0h80))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_160 = cvt(_T_159) node _T_161 = and(_T_160, asSInt(UInt<9>(0h100))) node _T_162 = asSInt(_T_161) node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0))) node _T_164 = or(_T_138, _T_143) node _T_165 = or(_T_164, _T_148) node _T_166 = or(_T_165, _T_153) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_163) node _T_169 = and(_T_133, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = and(_T_132, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_171, UInt<1>(0h1), "") : assert_10 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<7>(0h40))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<5>(0h14))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<4>(0h8))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<6>(0h20))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<8>(0h80))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<9>(0h100))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_183, _T_188) node _T_210 = or(_T_209, _T_193) node _T_211 = or(_T_210, _T_198) node _T_212 = or(_T_211, _T_203) node _T_213 = or(_T_212, _T_208) node _T_214 = and(_T_178, _T_213) node _T_215 = or(UInt<1>(0h0), _T_214) node _T_216 = and(UInt<1>(0h0), _T_215) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_216, UInt<1>(0h1), "") : assert_11 node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_224 = asUInt(reset) node _T_225 = eq(_T_224, UInt<1>(0h0)) when _T_225 : node _T_226 = eq(_T_223, UInt<1>(0h0)) when _T_226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_223, UInt<1>(0h1), "") : assert_13 node _T_227 = asUInt(reset) node _T_228 = eq(_T_227, UInt<1>(0h0)) when _T_228 : node _T_229 = eq(is_aligned, UInt<1>(0h0)) when _T_229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_231 = asUInt(reset) node _T_232 = eq(_T_231, UInt<1>(0h0)) when _T_232 : node _T_233 = eq(_T_230, UInt<1>(0h0)) when _T_233 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_230, UInt<1>(0h1), "") : assert_15 node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_234, UInt<1>(0h1), "") : assert_16 node _T_238 = not(io.in.a.bits.mask) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_239, UInt<1>(0h1), "") : assert_17 node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_243, UInt<1>(0h1), "") : assert_18 node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_247 : node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = asUInt(reset) node _T_253 = eq(_T_252, UInt<1>(0h0)) when _T_253 : node _T_254 = eq(_T_251, UInt<1>(0h0)) when _T_254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_251, UInt<1>(0h1), "") : assert_19 node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_257 = and(_T_255, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<7>(0h40))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<5>(0h14))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<4>(0h8))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<6>(0h20))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<8>(0h80))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<9>(0h100))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = or(_T_263, _T_268) node _T_290 = or(_T_289, _T_273) node _T_291 = or(_T_290, _T_278) node _T_292 = or(_T_291, _T_283) node _T_293 = or(_T_292, _T_288) node _T_294 = and(_T_258, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = asUInt(reset) node _T_297 = eq(_T_296, UInt<1>(0h0)) when _T_297 : node _T_298 = eq(_T_295, UInt<1>(0h0)) when _T_298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_295, UInt<1>(0h1), "") : assert_20 node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(is_aligned, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(_T_305, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_305, UInt<1>(0h1), "") : assert_23 node _T_309 = eq(io.in.a.bits.mask, mask) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_309, UInt<1>(0h1), "") : assert_24 node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_313, UInt<1>(0h1), "") : assert_25 node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_320 = and(_T_318, _T_319) node _T_321 = or(UInt<1>(0h0), _T_320) node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_324 = and(_T_322, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<7>(0h40))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<5>(0h14))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<4>(0h8))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<6>(0h20))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<8>(0h80))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<9>(0h100))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_330, _T_335) node _T_357 = or(_T_356, _T_340) node _T_358 = or(_T_357, _T_345) node _T_359 = or(_T_358, _T_350) node _T_360 = or(_T_359, _T_355) node _T_361 = and(_T_325, _T_360) node _T_362 = or(UInt<1>(0h0), _T_361) node _T_363 = and(_T_321, _T_362) node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_T_363, UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_363, UInt<1>(0h1), "") : assert_26 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(is_aligned, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_373, UInt<1>(0h1), "") : assert_29 node _T_377 = eq(io.in.a.bits.mask, mask) node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(_T_377, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_377, UInt<1>(0h1), "") : assert_30 node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_381 : node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_383 = and(UInt<1>(0h0), _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_387 = and(_T_385, _T_386) node _T_388 = or(UInt<1>(0h0), _T_387) node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<7>(0h40))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<5>(0h14))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<4>(0h8))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<6>(0h20))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<8>(0h80))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<9>(0h100))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = or(_T_393, _T_398) node _T_420 = or(_T_419, _T_403) node _T_421 = or(_T_420, _T_408) node _T_422 = or(_T_421, _T_413) node _T_423 = or(_T_422, _T_418) node _T_424 = and(_T_388, _T_423) node _T_425 = or(UInt<1>(0h0), _T_424) node _T_426 = and(_T_384, _T_425) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_426, UInt<1>(0h1), "") : assert_31 node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(is_aligned, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_436, UInt<1>(0h1), "") : assert_34 node _T_440 = not(mask) node _T_441 = and(io.in.a.bits.mask, _T_440) node _T_442 = eq(_T_441, UInt<1>(0h0)) node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_T_442, UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_442, UInt<1>(0h1), "") : assert_35 node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_446 : node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_448 = and(UInt<1>(0h0), _T_447) node _T_449 = or(UInt<1>(0h0), _T_448) node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<7>(0h40))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<5>(0h14))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<4>(0h8))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<6>(0h20))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<8>(0h80))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_477 = cvt(_T_476) node _T_478 = and(_T_477, asSInt(UInt<9>(0h100))) node _T_479 = asSInt(_T_478) node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0))) node _T_481 = or(_T_455, _T_460) node _T_482 = or(_T_481, _T_465) node _T_483 = or(_T_482, _T_470) node _T_484 = or(_T_483, _T_475) node _T_485 = or(_T_484, _T_480) node _T_486 = and(_T_450, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = and(_T_449, _T_487) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_488, UInt<1>(0h1), "") : assert_36 node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(is_aligned, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_498, UInt<1>(0h1), "") : assert_39 node _T_502 = eq(io.in.a.bits.mask, mask) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_502, UInt<1>(0h1), "") : assert_40 node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_506 : node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_508 = and(UInt<1>(0h0), _T_507) node _T_509 = or(UInt<1>(0h0), _T_508) node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<7>(0h40))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<5>(0h14))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<4>(0h8))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<6>(0h20))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_532 = cvt(_T_531) node _T_533 = and(_T_532, asSInt(UInt<8>(0h80))) node _T_534 = asSInt(_T_533) node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0))) node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_537 = cvt(_T_536) node _T_538 = and(_T_537, asSInt(UInt<9>(0h100))) node _T_539 = asSInt(_T_538) node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0))) node _T_541 = or(_T_515, _T_520) node _T_542 = or(_T_541, _T_525) node _T_543 = or(_T_542, _T_530) node _T_544 = or(_T_543, _T_535) node _T_545 = or(_T_544, _T_540) node _T_546 = and(_T_510, _T_545) node _T_547 = or(UInt<1>(0h0), _T_546) node _T_548 = and(_T_509, _T_547) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_548, UInt<1>(0h1), "") : assert_41 node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(is_aligned, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_558, UInt<1>(0h1), "") : assert_44 node _T_562 = eq(io.in.a.bits.mask, mask) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_562, UInt<1>(0h1), "") : assert_45 node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_566 : node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_568 = and(UInt<1>(0h0), _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_572 = cvt(_T_571) node _T_573 = and(_T_572, asSInt(UInt<7>(0h40))) node _T_574 = asSInt(_T_573) node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0))) node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44)) node _T_577 = cvt(_T_576) node _T_578 = and(_T_577, asSInt(UInt<5>(0h14))) node _T_579 = asSInt(_T_578) node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0))) node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58)) node _T_582 = cvt(_T_581) node _T_583 = and(_T_582, asSInt(UInt<4>(0h8))) node _T_584 = asSInt(_T_583) node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0))) node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60)) node _T_587 = cvt(_T_586) node _T_588 = and(_T_587, asSInt(UInt<6>(0h20))) node _T_589 = asSInt(_T_588) node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0))) node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80)) node _T_592 = cvt(_T_591) node _T_593 = and(_T_592, asSInt(UInt<8>(0h80))) node _T_594 = asSInt(_T_593) node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0))) node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100)) node _T_597 = cvt(_T_596) node _T_598 = and(_T_597, asSInt(UInt<9>(0h100))) node _T_599 = asSInt(_T_598) node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0))) node _T_601 = or(_T_575, _T_580) node _T_602 = or(_T_601, _T_585) node _T_603 = or(_T_602, _T_590) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_600) node _T_606 = and(_T_570, _T_605) node _T_607 = or(UInt<1>(0h0), _T_606) node _T_608 = and(_T_569, _T_607) node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(_T_608, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_608, UInt<1>(0h1), "") : assert_46 node _T_612 = asUInt(reset) node _T_613 = eq(_T_612, UInt<1>(0h0)) when _T_613 : node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(is_aligned, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_619 = asUInt(reset) node _T_620 = eq(_T_619, UInt<1>(0h0)) when _T_620 : node _T_621 = eq(_T_618, UInt<1>(0h0)) when _T_621 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_618, UInt<1>(0h1), "") : assert_49 node _T_622 = eq(io.in.a.bits.mask, mask) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_622, UInt<1>(0h1), "") : assert_50 node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_626, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_630, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_634 : node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_638, UInt<1>(0h1), "") : assert_54 node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_642, UInt<1>(0h1), "") : assert_55 node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_646, UInt<1>(0h1), "") : assert_56 node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_650, UInt<1>(0h1), "") : assert_57 node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_654 : node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_658 = asUInt(reset) node _T_659 = eq(_T_658, UInt<1>(0h0)) when _T_659 : node _T_660 = eq(sink_ok, UInt<1>(0h0)) when _T_660 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_662 = asUInt(reset) node _T_663 = eq(_T_662, UInt<1>(0h0)) when _T_663 : node _T_664 = eq(_T_661, UInt<1>(0h0)) when _T_664 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_661, UInt<1>(0h1), "") : assert_60 node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_666 = asUInt(reset) node _T_667 = eq(_T_666, UInt<1>(0h0)) when _T_667 : node _T_668 = eq(_T_665, UInt<1>(0h0)) when _T_668 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_665, UInt<1>(0h1), "") : assert_61 node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_669, UInt<1>(0h1), "") : assert_62 node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_674 = asUInt(reset) node _T_675 = eq(_T_674, UInt<1>(0h0)) when _T_675 : node _T_676 = eq(_T_673, UInt<1>(0h0)) when _T_676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_673, UInt<1>(0h1), "") : assert_63 node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_678 = or(UInt<1>(0h0), _T_677) node _T_679 = asUInt(reset) node _T_680 = eq(_T_679, UInt<1>(0h0)) when _T_680 : node _T_681 = eq(_T_678, UInt<1>(0h0)) when _T_681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_678, UInt<1>(0h1), "") : assert_64 node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_682 : node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(sink_ok, UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(_T_689, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_689, UInt<1>(0h1), "") : assert_67 node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_693, UInt<1>(0h1), "") : assert_68 node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_697, UInt<1>(0h1), "") : assert_69 node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_702 = or(_T_701, io.in.d.bits.corrupt) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_702, UInt<1>(0h1), "") : assert_70 node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_707 = or(UInt<1>(0h0), _T_706) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_707, UInt<1>(0h1), "") : assert_71 node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_711 : node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_716 = asUInt(reset) node _T_717 = eq(_T_716, UInt<1>(0h0)) when _T_717 : node _T_718 = eq(_T_715, UInt<1>(0h0)) when _T_718 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_715, UInt<1>(0h1), "") : assert_73 node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_T_719, UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_719, UInt<1>(0h1), "") : assert_74 node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_724 = or(UInt<1>(0h0), _T_723) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_724, UInt<1>(0h1), "") : assert_75 node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_728 : node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_732, UInt<1>(0h1), "") : assert_77 node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_737 = or(_T_736, io.in.d.bits.corrupt) node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(_T_737, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_737, UInt<1>(0h1), "") : assert_78 node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = asUInt(reset) node _T_744 = eq(_T_743, UInt<1>(0h0)) when _T_744 : node _T_745 = eq(_T_742, UInt<1>(0h0)) when _T_745 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_742, UInt<1>(0h1), "") : assert_79 node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_746 : node _T_747 = asUInt(reset) node _T_748 = eq(_T_747, UInt<1>(0h0)) when _T_748 : node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_749 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_751 = asUInt(reset) node _T_752 = eq(_T_751, UInt<1>(0h0)) when _T_752 : node _T_753 = eq(_T_750, UInt<1>(0h0)) when _T_753 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_750, UInt<1>(0h1), "") : assert_81 node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_755 = asUInt(reset) node _T_756 = eq(_T_755, UInt<1>(0h0)) when _T_756 : node _T_757 = eq(_T_754, UInt<1>(0h0)) when _T_757 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_754, UInt<1>(0h1), "") : assert_82 node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = asUInt(reset) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(_T_759, UInt<1>(0h0)) when _T_762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_759, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_764 = asUInt(reset) node _T_765 = eq(_T_764, UInt<1>(0h0)) when _T_765 : node _T_766 = eq(_T_763, UInt<1>(0h0)) when _T_766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_763, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(_T_767, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_767, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_T_771, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_771, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_775 = eq(a_first, UInt<1>(0h0)) node _T_776 = and(io.in.a.valid, _T_775) when _T_776 : node _T_777 = eq(io.in.a.bits.opcode, opcode) node _T_778 = asUInt(reset) node _T_779 = eq(_T_778, UInt<1>(0h0)) when _T_779 : node _T_780 = eq(_T_777, UInt<1>(0h0)) when _T_780 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_777, UInt<1>(0h1), "") : assert_87 node _T_781 = eq(io.in.a.bits.param, param) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_781, UInt<1>(0h1), "") : assert_88 node _T_785 = eq(io.in.a.bits.size, size) node _T_786 = asUInt(reset) node _T_787 = eq(_T_786, UInt<1>(0h0)) when _T_787 : node _T_788 = eq(_T_785, UInt<1>(0h0)) when _T_788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_785, UInt<1>(0h1), "") : assert_89 node _T_789 = eq(io.in.a.bits.source, source) node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(_T_789, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_789, UInt<1>(0h1), "") : assert_90 node _T_793 = eq(io.in.a.bits.address, address) node _T_794 = asUInt(reset) node _T_795 = eq(_T_794, UInt<1>(0h0)) when _T_795 : node _T_796 = eq(_T_793, UInt<1>(0h0)) when _T_796 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_793, UInt<1>(0h1), "") : assert_91 node _T_797 = and(io.in.a.ready, io.in.a.valid) node _T_798 = and(_T_797, a_first) when _T_798 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_799 = eq(d_first, UInt<1>(0h0)) node _T_800 = and(io.in.d.valid, _T_799) when _T_800 : node _T_801 = eq(io.in.d.bits.opcode, opcode_1) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_801, UInt<1>(0h1), "") : assert_92 node _T_805 = eq(io.in.d.bits.param, param_1) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_805, UInt<1>(0h1), "") : assert_93 node _T_809 = eq(io.in.d.bits.size, size_1) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_809, UInt<1>(0h1), "") : assert_94 node _T_813 = eq(io.in.d.bits.source, source_1) node _T_814 = asUInt(reset) node _T_815 = eq(_T_814, UInt<1>(0h0)) when _T_815 : node _T_816 = eq(_T_813, UInt<1>(0h0)) when _T_816 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_813, UInt<1>(0h1), "") : assert_95 node _T_817 = eq(io.in.d.bits.sink, sink) node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(_T_817, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_817, UInt<1>(0h1), "") : assert_96 node _T_821 = eq(io.in.d.bits.denied, denied) node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_T_821, UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_821, UInt<1>(0h1), "") : assert_97 node _T_825 = and(io.in.d.ready, io.in.d.valid) node _T_826 = and(_T_825, d_first) when _T_826 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_827 = and(io.in.a.valid, a_first_1) node _T_828 = and(_T_827, UInt<1>(0h1)) when _T_828 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_829 = and(io.in.a.ready, io.in.a.valid) node _T_830 = and(_T_829, a_first_1) node _T_831 = and(_T_830, UInt<1>(0h1)) when _T_831 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_832 = dshr(inflight, io.in.a.bits.source) node _T_833 = bits(_T_832, 0, 0) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(_T_834, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_834, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_838 = and(io.in.d.valid, d_first_1) node _T_839 = and(_T_838, UInt<1>(0h1)) node _T_840 = eq(d_release_ack, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) when _T_841 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_842 = and(io.in.d.ready, io.in.d.valid) node _T_843 = and(_T_842, d_first_1) node _T_844 = and(_T_843, UInt<1>(0h1)) node _T_845 = eq(d_release_ack, UInt<1>(0h0)) node _T_846 = and(_T_844, _T_845) when _T_846 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_847 = and(io.in.d.valid, d_first_1) node _T_848 = and(_T_847, UInt<1>(0h1)) node _T_849 = eq(d_release_ack, UInt<1>(0h0)) node _T_850 = and(_T_848, _T_849) when _T_850 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_851 = dshr(inflight, io.in.d.bits.source) node _T_852 = bits(_T_851, 0, 0) node _T_853 = or(_T_852, same_cycle_resp) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_853, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_859 = or(_T_857, _T_858) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_859, UInt<1>(0h1), "") : assert_100 node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_864 = asUInt(reset) node _T_865 = eq(_T_864, UInt<1>(0h0)) when _T_865 : node _T_866 = eq(_T_863, UInt<1>(0h0)) when _T_866 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_863, UInt<1>(0h1), "") : assert_101 else : node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_869 = or(_T_867, _T_868) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_869, UInt<1>(0h1), "") : assert_102 node _T_873 = eq(io.in.d.bits.size, a_size_lookup) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_873, UInt<1>(0h1), "") : assert_103 node _T_877 = and(io.in.d.valid, d_first_1) node _T_878 = and(_T_877, a_first_1) node _T_879 = and(_T_878, io.in.a.valid) node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_881 = and(_T_879, _T_880) node _T_882 = eq(d_release_ack, UInt<1>(0h0)) node _T_883 = and(_T_881, _T_882) when _T_883 : node _T_884 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_885 = or(_T_884, io.in.a.ready) node _T_886 = asUInt(reset) node _T_887 = eq(_T_886, UInt<1>(0h0)) when _T_887 : node _T_888 = eq(_T_885, UInt<1>(0h0)) when _T_888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_885, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_111 node _T_889 = orr(inflight) node _T_890 = eq(_T_889, UInt<1>(0h0)) node _T_891 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_892 = or(_T_890, _T_891) node _T_893 = lt(watchdog, plusarg_reader.out) node _T_894 = or(_T_892, _T_893) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_894, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_898 = and(io.in.a.ready, io.in.a.valid) node _T_899 = and(io.in.d.ready, io.in.d.valid) node _T_900 = or(_T_898, _T_899) when _T_900 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<9>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<9>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<9>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_901 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<9>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_902 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_903 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_904 = and(_T_902, _T_903) node _T_905 = and(_T_901, _T_904) when _T_905 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<9>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_906 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_907 = and(_T_906, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<9>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_908 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_909 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_910 = and(_T_908, _T_909) node _T_911 = and(_T_907, _T_910) when _T_911 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<9>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<9>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_912 = dshr(inflight_1, _WIRE_15.bits.source) node _T_913 = bits(_T_912, 0, 0) node _T_914 = eq(_T_913, UInt<1>(0h0)) node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(_T_914, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_914, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_918 = and(io.in.d.valid, d_first_2) node _T_919 = and(_T_918, UInt<1>(0h1)) node _T_920 = and(_T_919, d_release_ack_1) when _T_920 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_921 = and(io.in.d.ready, io.in.d.valid) node _T_922 = and(_T_921, d_first_2) node _T_923 = and(_T_922, UInt<1>(0h1)) node _T_924 = and(_T_923, d_release_ack_1) when _T_924 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_925 = and(io.in.d.valid, d_first_2) node _T_926 = and(_T_925, UInt<1>(0h1)) node _T_927 = and(_T_926, d_release_ack_1) when _T_927 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_928 = dshr(inflight_1, io.in.d.bits.source) node _T_929 = bits(_T_928, 0, 0) node _T_930 = or(_T_929, same_cycle_resp_1) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_930, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<9>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_934 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_934, UInt<1>(0h1), "") : assert_108 else : node _T_938 = eq(io.in.d.bits.size, c_size_lookup) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_938, UInt<1>(0h1), "") : assert_109 node _T_942 = and(io.in.d.valid, d_first_2) node _T_943 = and(_T_942, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<9>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_944 = and(_T_943, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<9>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_945 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_946 = and(_T_944, _T_945) node _T_947 = and(_T_946, d_release_ack_1) node _T_948 = eq(c_probe_ack, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) when _T_949 : node _T_950 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<9>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_951 = or(_T_950, _WIRE_23.ready) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_951, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_112 node _T_955 = orr(inflight_1) node _T_956 = eq(_T_955, UInt<1>(0h0)) node _T_957 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_958 = or(_T_956, _T_957) node _T_959 = lt(watchdog_1, plusarg_reader_1.out) node _T_960 = or(_T_958, _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:1862:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_960, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<9>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_964 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_965 = and(io.in.d.ready, io.in.d.valid) node _T_966 = or(_T_964, _T_965) when _T_966 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_113 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_114 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_55( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [8:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_first_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_first_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_wo_ready_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_wo_ready_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_interm_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_interm_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_opcodes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_opcodes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_sizes_set_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_sizes_set_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _c_probe_ack_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _c_probe_ack_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_1_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_2_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_3_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [8:0] _same_cycle_resp_WIRE_4_bits_address = 9'h0; // @[Bundles.scala:265:74] wire [8:0] _same_cycle_resp_WIRE_5_bits_address = 9'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [1:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [4:0] _GEN = 5'h3 << io_in_a_bits_size_0; // @[package.scala:243:71] wire [4:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [1:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [8:0] _is_aligned_T = {7'h0, io_in_a_bits_address_0[1:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 9'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = io_in_a_bits_size_0[1]; // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_898 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_898; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_898; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [8:0] address; // @[Monitor.scala:391:22] wire _T_966 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_966; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_966; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN_0 = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_2 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_3 = 2'h1 << _GEN_2; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_831 = _T_898 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_831 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_831 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_831 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _GEN_4 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [3:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_4; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_4; // @[Monitor.scala:659:79, :660:77] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_831 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_831 ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_877 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_877 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_846 = _T_966 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_846 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_846 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_846 ? _d_sizes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_942 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_942 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_924 = _T_966 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_924 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_924 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_924 ? _d_sizes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module L1MetadataArrayBank_3 : input clock : Clock input reset : Reset output io : { flip read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>}}, flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, resp : { coh : { state : UInt<2>}, tag : UInt<20>}[4]} wire rstVal_meta : { state : UInt<2>} connect rstVal_meta.state, UInt<2>(0h0) wire rstVal : { coh : { state : UInt<2>}, tag : UInt<20>} connect rstVal.tag, UInt<1>(0h0) connect rstVal.coh, rstVal_meta regreset rst_cnt : UInt<5>, clock, reset, UInt<5>(0h0) node rst = lt(rst_cnt, UInt<5>(0h10)) node waddr = mux(rst, rst_cnt, io.write.bits.idx) node _wdata_T = mux(rst, rstVal, io.write.bits.data) node wdata = cat(_wdata_T.coh.state, _wdata_T.tag) node _wmask_T = or(rst, UInt<1>(0h0)) node _wmask_T_1 = not(UInt<4>(0h0)) node _wmask_T_2 = mux(_wmask_T, _wmask_T_1, io.write.bits.way_en) node wmask_0 = bits(_wmask_T_2, 0, 0) node wmask_1 = bits(_wmask_T_2, 1, 1) node wmask_2 = bits(_wmask_T_2, 2, 2) node wmask_3 = bits(_wmask_T_2, 3, 3) node _rmask_T = or(rst, UInt<1>(0h0)) node _rmask_T_1 = not(UInt<4>(0h0)) node _rmask_T_2 = mux(_rmask_T, _rmask_T_1, io.read.bits.way_en) node rmask_0 = bits(_rmask_T_2, 0, 0) node rmask_1 = bits(_rmask_T_2, 1, 1) node rmask_2 = bits(_rmask_T_2, 2, 2) node rmask_3 = bits(_rmask_T_2, 3, 3) when rst : node _rst_cnt_T = add(rst_cnt, UInt<1>(0h1)) node _rst_cnt_T_1 = tail(_rst_cnt_T, 1) connect rst_cnt, _rst_cnt_T_1 smem tag_array : UInt<22>[4] [16] wire wen : UInt<1> wire ren : UInt<1> regreset stall_ctr : UInt<2>, clock, reset, UInt<2>(0h0) node _stall_read_T = not(UInt<2>(0h0)) node stall_read = eq(stall_ctr, _stall_read_T) wire force_stall : UInt<1> connect force_stall, UInt<1>(0h0) regreset rbuf_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg rbuf_idx : UInt<4>, clock reg rbuf : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock wire forward_from_rbuf : UInt<1> connect forward_from_rbuf, UInt<1>(0h0) node _T = and(io.read.valid, force_stall) when _T : node _stall_ctr_T = add(stall_ctr, UInt<1>(0h1)) node _stall_ctr_T_1 = tail(_stall_ctr_T, 1) connect stall_ctr, _stall_ctr_T_1 else : connect stall_ctr, UInt<1>(0h0) when rst : connect wen, UInt<1>(0h1) connect ren, UInt<1>(0h0) connect io.read.ready, UInt<1>(0h0) connect io.write.ready, UInt<1>(0h0) else : node _T_1 = eq(stall_read, UInt<1>(0h0)) node _T_2 = and(io.read.valid, _T_1) when _T_2 : node _T_3 = eq(io.read.bits.idx, rbuf_idx) node _T_4 = and(_T_3, rbuf_valid) when _T_4 : connect forward_from_rbuf, UInt<1>(0h1) connect ren, UInt<1>(0h0) connect wen, io.write.valid connect io.read.ready, UInt<1>(0h1) connect io.write.ready, UInt<1>(0h1) else : connect ren, UInt<1>(0h1) connect wen, UInt<1>(0h0) connect io.read.ready, UInt<1>(0h1) connect io.write.ready, UInt<1>(0h0) connect force_stall, io.write.valid else : connect ren, UInt<1>(0h0) connect wen, io.write.valid connect io.read.ready, UInt<1>(0h0) connect io.write.ready, UInt<1>(0h1) reg s1_read_idx : UInt<6>, clock when io.read.valid : connect s1_read_idx, io.read.bits.idx node _T_5 = and(io.read.ready, io.read.valid) node _T_6 = eq(forward_from_rbuf, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) reg REG : UInt<1>, clock connect REG, _T_7 node _T_8 = eq(io.write.bits.idx, s1_read_idx) node _T_9 = and(io.write.valid, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = and(REG, _T_10) when _T_11 : connect rbuf_valid, UInt<1>(0h1) connect rbuf_idx, s1_read_idx connect rbuf[0].tag, io.resp[0].tag connect rbuf[0].coh.state, io.resp[0].coh.state connect rbuf[1].tag, io.resp[1].tag connect rbuf[1].coh.state, io.resp[1].coh.state connect rbuf[2].tag, io.resp[2].tag connect rbuf[2].coh.state, io.resp[2].coh.state connect rbuf[3].tag, io.resp[3].tag connect rbuf[3].coh.state, io.resp[3].coh.state node _T_12 = eq(io.write.bits.idx, rbuf_idx) node _T_13 = and(io.write.valid, _T_12) when _T_13 : connect rbuf_valid, UInt<1>(0h0) when wen : wire _WIRE : UInt<22>[4] connect _WIRE[0], wdata connect _WIRE[1], wdata connect _WIRE[2], wdata connect _WIRE[3], wdata node _T_14 = bits(waddr, 3, 0) write mport MPORT = tag_array[_T_14], clock when wmask_0 : connect MPORT[0], _WIRE[0] when wmask_1 : connect MPORT[1], _WIRE[1] when wmask_2 : connect MPORT[2], _WIRE[2] when wmask_3 : connect MPORT[3], _WIRE[3] node _T_15 = eq(wen, UInt<1>(0h0)) node _T_16 = and(ren, _T_15) wire _WIRE_1 : UInt<6> invalidate _WIRE_1 when _T_16 : connect _WIRE_1, io.read.bits.idx node _T_17 = bits(_WIRE_1, 3, 0) read mport MPORT_1 = tag_array[_T_17], clock wire _WIRE_2 : { coh : { state : UInt<2>}, tag : UInt<20>} wire _WIRE_3 : UInt<22> connect _WIRE_3, MPORT_1[0] node _T_18 = bits(_WIRE_3, 19, 0) connect _WIRE_2.tag, _T_18 node _T_19 = bits(_WIRE_3, 21, 20) connect _WIRE_2.coh.state, _T_19 wire _WIRE_4 : { coh : { state : UInt<2>}, tag : UInt<20>} wire _WIRE_5 : UInt<22> connect _WIRE_5, MPORT_1[1] node _T_20 = bits(_WIRE_5, 19, 0) connect _WIRE_4.tag, _T_20 node _T_21 = bits(_WIRE_5, 21, 20) connect _WIRE_4.coh.state, _T_21 wire _WIRE_6 : { coh : { state : UInt<2>}, tag : UInt<20>} wire _WIRE_7 : UInt<22> connect _WIRE_7, MPORT_1[2] node _T_22 = bits(_WIRE_7, 19, 0) connect _WIRE_6.tag, _T_22 node _T_23 = bits(_WIRE_7, 21, 20) connect _WIRE_6.coh.state, _T_23 wire _WIRE_8 : { coh : { state : UInt<2>}, tag : UInt<20>} wire _WIRE_9 : UInt<22> connect _WIRE_9, MPORT_1[3] node _T_24 = bits(_WIRE_9, 19, 0) connect _WIRE_8.tag, _T_24 node _T_25 = bits(_WIRE_9, 21, 20) connect _WIRE_8.coh.state, _T_25 connect io.resp[0], _WIRE_2 connect io.resp[1], _WIRE_4 connect io.resp[2], _WIRE_6 connect io.resp[3], _WIRE_8 reg REG_1 : UInt<1>, clock connect REG_1, forward_from_rbuf when REG_1 : reg r : { coh : { state : UInt<2>}, tag : UInt<20>}[4], clock when forward_from_rbuf : connect r, rbuf connect io.resp, r
module L1MetadataArrayBank_3( // @[TagArray.scala:12:7] input clock, // @[TagArray.scala:12:7] input reset, // @[TagArray.scala:12:7] output io_read_ready, // @[TagArray.scala:14:14] input io_read_valid, // @[TagArray.scala:14:14] input [5:0] io_read_bits_idx, // @[TagArray.scala:14:14] input [3:0] io_read_bits_way_en, // @[TagArray.scala:14:14] input [19:0] io_read_bits_tag, // @[TagArray.scala:14:14] output io_write_ready, // @[TagArray.scala:14:14] input io_write_valid, // @[TagArray.scala:14:14] input [5:0] io_write_bits_idx, // @[TagArray.scala:14:14] input [3:0] io_write_bits_way_en, // @[TagArray.scala:14:14] input [19:0] io_write_bits_tag, // @[TagArray.scala:14:14] input [1:0] io_write_bits_data_coh_state, // @[TagArray.scala:14:14] input [19:0] io_write_bits_data_tag, // @[TagArray.scala:14:14] output [1:0] io_resp_0_coh_state, // @[TagArray.scala:14:14] output [19:0] io_resp_0_tag, // @[TagArray.scala:14:14] output [1:0] io_resp_1_coh_state, // @[TagArray.scala:14:14] output [19:0] io_resp_1_tag, // @[TagArray.scala:14:14] output [1:0] io_resp_2_coh_state, // @[TagArray.scala:14:14] output [19:0] io_resp_2_tag, // @[TagArray.scala:14:14] output [1:0] io_resp_3_coh_state, // @[TagArray.scala:14:14] output [19:0] io_resp_3_tag // @[TagArray.scala:14:14] ); wire [3:0] tag_array_MPORT_1_addr; // @[TagArray.scala:87:28] wire tag_array_MPORT_1_en; // @[TagArray.scala:87:51] wire [3:0] tag_array_MPORT_addr; // @[TagArray.scala:85:20] wire [87:0] _tag_array_RW0_rdata; // @[TagArray.scala:28:30] wire io_read_valid_0 = io_read_valid; // @[TagArray.scala:12:7] wire [5:0] io_read_bits_idx_0 = io_read_bits_idx; // @[TagArray.scala:12:7] wire [3:0] io_read_bits_way_en_0 = io_read_bits_way_en; // @[TagArray.scala:12:7] wire [19:0] io_read_bits_tag_0 = io_read_bits_tag; // @[TagArray.scala:12:7] wire io_write_valid_0 = io_write_valid; // @[TagArray.scala:12:7] wire [5:0] io_write_bits_idx_0 = io_write_bits_idx; // @[TagArray.scala:12:7] wire [3:0] io_write_bits_way_en_0 = io_write_bits_way_en; // @[TagArray.scala:12:7] wire [19:0] io_write_bits_tag_0 = io_write_bits_tag; // @[TagArray.scala:12:7] wire [1:0] io_write_bits_data_coh_state_0 = io_write_bits_data_coh_state; // @[TagArray.scala:12:7] wire [19:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[TagArray.scala:12:7] wire [1:0] rstVal_meta_state = 2'h0; // @[Metadata.scala:160:20] wire [1:0] rstVal_coh_state = 2'h0; // @[HellaCache.scala:305:20] wire [19:0] rstVal_tag = 20'h0; // @[HellaCache.scala:305:20] wire [3:0] _wmask_T_1 = 4'hF; // @[TagArray.scala:23:42] wire [3:0] _rmask_T_1 = 4'hF; // @[TagArray.scala:24:42] wire [1:0] _stall_read_T = 2'h3; // @[TagArray.scala:33:34] wire io_read_ready_0; // @[TagArray.scala:12:7] wire io_write_ready_0; // @[TagArray.scala:12:7] wire [1:0] io_resp_0_coh_state_0; // @[TagArray.scala:12:7] wire [19:0] io_resp_0_tag_0; // @[TagArray.scala:12:7] wire [1:0] io_resp_1_coh_state_0; // @[TagArray.scala:12:7] wire [19:0] io_resp_1_tag_0; // @[TagArray.scala:12:7] wire [1:0] io_resp_2_coh_state_0; // @[TagArray.scala:12:7] wire [19:0] io_resp_2_tag_0; // @[TagArray.scala:12:7] wire [1:0] io_resp_3_coh_state_0; // @[TagArray.scala:12:7] wire [19:0] io_resp_3_tag_0; // @[TagArray.scala:12:7] reg [4:0] rst_cnt; // @[TagArray.scala:19:24] wire rst = ~(rst_cnt[4]); // @[TagArray.scala:19:24, :20:21] wire _wmask_T = rst; // @[TagArray.scala:20:21, :23:23] wire _rmask_T = rst; // @[TagArray.scala:20:21, :24:23] wire [5:0] _GEN = {1'h0, rst_cnt}; // @[TagArray.scala:19:24, :21:18] wire [5:0] waddr = rst ? _GEN : io_write_bits_idx_0; // @[TagArray.scala:12:7, :20:21, :21:18] wire [1:0] _wdata_T_coh_state = rst ? 2'h0 : io_write_bits_data_coh_state_0; // @[TagArray.scala:12:7, :20:21, :22:18] wire [19:0] _wdata_T_tag = rst ? 20'h0 : io_write_bits_data_tag_0; // @[TagArray.scala:12:7, :20:21, :22:18] wire [21:0] wdata = {_wdata_T_coh_state, _wdata_T_tag}; // @[TagArray.scala:22:{18,52}] wire [3:0] _wmask_T_2 = _wmask_T ? 4'hF : io_write_bits_way_en_0; // @[TagArray.scala:12:7, :23:{18,23}] wire wmask_0 = _wmask_T_2[0]; // @[TagArray.scala:23:{18,81}] wire wmask_1 = _wmask_T_2[1]; // @[TagArray.scala:23:{18,81}] wire wmask_2 = _wmask_T_2[2]; // @[TagArray.scala:23:{18,81}] wire wmask_3 = _wmask_T_2[3]; // @[TagArray.scala:23:{18,81}] wire [3:0] _rmask_T_2 = _rmask_T ? 4'hF : io_read_bits_way_en_0; // @[TagArray.scala:12:7, :24:{18,23}] wire rmask_0 = _rmask_T_2[0]; // @[TagArray.scala:24:{18,80}] wire rmask_1 = _rmask_T_2[1]; // @[TagArray.scala:24:{18,80}] wire rmask_2 = _rmask_T_2[2]; // @[TagArray.scala:24:{18,80}] wire rmask_3 = _rmask_T_2[3]; // @[TagArray.scala:24:{18,80}] wire [5:0] _rst_cnt_T = _GEN + 6'h1; // @[TagArray.scala:21:18, :25:35] wire [4:0] _rst_cnt_T_1 = _rst_cnt_T[4:0]; // @[TagArray.scala:25:35] wire wen; // @[TagArray.scala:30:17] wire ren; // @[TagArray.scala:31:17] reg [1:0] stall_ctr; // @[TagArray.scala:32:26] wire stall_read = &stall_ctr; // @[TagArray.scala:32:26, :33:30] wire force_stall; // @[TagArray.scala:34:29] reg rbuf_valid; // @[TagArray.scala:36:27] reg [3:0] rbuf_idx; // @[TagArray.scala:37:21] reg [1:0] rbuf_0_coh_state; // @[TagArray.scala:38:17] reg [19:0] rbuf_0_tag; // @[TagArray.scala:38:17] reg [1:0] rbuf_1_coh_state; // @[TagArray.scala:38:17] reg [19:0] rbuf_1_tag; // @[TagArray.scala:38:17] reg [1:0] rbuf_2_coh_state; // @[TagArray.scala:38:17] reg [19:0] rbuf_2_tag; // @[TagArray.scala:38:17] reg [1:0] rbuf_3_coh_state; // @[TagArray.scala:38:17] reg [19:0] rbuf_3_tag; // @[TagArray.scala:38:17] wire forward_from_rbuf; // @[TagArray.scala:39:35] wire [2:0] _stall_ctr_T = {1'h0, stall_ctr} + 3'h1; // @[TagArray.scala:32:26, :42:28] wire [1:0] _stall_ctr_T_1 = _stall_ctr_T[1:0]; // @[TagArray.scala:42:28] wire _T_2 = io_read_valid_0 & ~stall_read; // @[TagArray.scala:12:7, :33:30, :53:{25,28}] wire [5:0] _GEN_0 = {2'h0, rbuf_idx}; // @[TagArray.scala:37:21, :54:30] wire _T_4 = io_read_bits_idx_0 == _GEN_0 & rbuf_valid; // @[TagArray.scala:12:7, :36:27, :54:{30,43}] assign forward_from_rbuf = ~rst & _T_2 & _T_4; // @[TagArray.scala:20:21, :39:35, :47:14, :53:{25,41}, :54:{43,58}] assign force_stall = ~rst & _T_2 & ~_T_4 & io_write_valid_0; // @[TagArray.scala:12:7, :20:21, :34:29, :39:35, :47:14, :53:{25,41}, :54:{43,58}, :65:21] assign ren = ~rst & _T_2 & ~_T_4; // @[TagArray.scala:20:21, :31:17, :39:35, :47:14, :49:9, :53:{25,41}, :54:{43,58}, :56:13, :61:13, :68:11] wire _GEN_1 = ~_T_2 | _T_4; // @[TagArray.scala:53:{25,41}, :54:{43,58}, :69:11] assign wen = rst | _GEN_1 & io_write_valid_0; // @[TagArray.scala:12:7, :20:21, :30:17, :47:14, :48:9, :53:41, :54:58, :69:11] assign io_read_ready_0 = ~rst & _T_2; // @[TagArray.scala:12:7, :20:21, :39:35, :47:14, :50:19, :53:{25,41}] assign io_write_ready_0 = ~rst & _GEN_1; // @[TagArray.scala:12:7, :20:21, :39:35, :47:14, :51:20, :53:41, :54:58, :69:11] reg [5:0] s1_read_idx; // @[TagArray.scala:74:30] reg REG; // @[TagArray.scala:75:16] assign tag_array_MPORT_addr = waddr[3:0]; // @[TagArray.scala:21:18, :85:20] assign tag_array_MPORT_1_en = ren & ~wen; // @[TagArray.scala:30:17, :31:17, :87:{51,54}] assign tag_array_MPORT_1_addr = io_read_bits_idx_0[3:0]; // @[TagArray.scala:12:7, :87:28] reg REG_1; // @[TagArray.scala:88:16] reg [1:0] r_0_coh_state; // @[TagArray.scala:89:25] reg [19:0] r_0_tag; // @[TagArray.scala:89:25] reg [1:0] r_1_coh_state; // @[TagArray.scala:89:25] reg [19:0] r_1_tag; // @[TagArray.scala:89:25] reg [1:0] r_2_coh_state; // @[TagArray.scala:89:25] reg [19:0] r_2_tag; // @[TagArray.scala:89:25] reg [1:0] r_3_coh_state; // @[TagArray.scala:89:25] reg [19:0] r_3_tag; // @[TagArray.scala:89:25] assign io_resp_0_coh_state_0 = REG_1 ? r_0_coh_state : _tag_array_RW0_rdata[21:20]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_0_tag_0 = REG_1 ? r_0_tag : _tag_array_RW0_rdata[19:0]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_1_coh_state_0 = REG_1 ? r_1_coh_state : _tag_array_RW0_rdata[43:42]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_1_tag_0 = REG_1 ? r_1_tag : _tag_array_RW0_rdata[41:22]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_2_coh_state_0 = REG_1 ? r_2_coh_state : _tag_array_RW0_rdata[65:64]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_2_tag_0 = REG_1 ? r_2_tag : _tag_array_RW0_rdata[63:44]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_3_coh_state_0 = REG_1 ? r_3_coh_state : _tag_array_RW0_rdata[87:86]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] assign io_resp_3_tag_0 = REG_1 ? r_3_tag : _tag_array_RW0_rdata[85:66]; // @[TagArray.scala:12:7, :28:30, :87:{11,74}, :88:{16,37}, :89:{13,25}] wire _T_11 = REG & ~(io_write_valid_0 & io_write_bits_idx_0 == s1_read_idx); // @[TagArray.scala:12:7, :74:30, :75:{16,53,56,73,94}] always @(posedge clock) begin // @[TagArray.scala:12:7] if (reset) begin // @[TagArray.scala:12:7] rst_cnt <= 5'h0; // @[TagArray.scala:19:24] stall_ctr <= 2'h0; // @[TagArray.scala:32:26] rbuf_valid <= 1'h0; // @[TagArray.scala:36:27] end else begin // @[TagArray.scala:12:7] if (rst) // @[TagArray.scala:20:21] rst_cnt <= _rst_cnt_T_1; // @[TagArray.scala:19:24, :25:35] stall_ctr <= io_read_valid_0 & force_stall ? _stall_ctr_T_1 : 2'h0; // @[TagArray.scala:12:7, :32:26, :34:29, :41:{23,39}, :42:{15,28}, :44:15] rbuf_valid <= ~(io_write_valid_0 & io_write_bits_idx_0 == _GEN_0) & (_T_11 | rbuf_valid); // @[TagArray.scala:12:7, :36:27, :54:30, :75:{53,112}, :76:16, :80:{24,45,59}, :81:16] end if (_T_11) begin // @[TagArray.scala:75:53] rbuf_idx <= s1_read_idx[3:0]; // @[TagArray.scala:37:21, :74:30, :77:14] rbuf_0_coh_state <= io_resp_0_coh_state_0; // @[TagArray.scala:12:7, :38:17] rbuf_0_tag <= io_resp_0_tag_0; // @[TagArray.scala:12:7, :38:17] rbuf_1_coh_state <= io_resp_1_coh_state_0; // @[TagArray.scala:12:7, :38:17] rbuf_1_tag <= io_resp_1_tag_0; // @[TagArray.scala:12:7, :38:17] rbuf_2_coh_state <= io_resp_2_coh_state_0; // @[TagArray.scala:12:7, :38:17] rbuf_2_tag <= io_resp_2_tag_0; // @[TagArray.scala:12:7, :38:17] rbuf_3_coh_state <= io_resp_3_coh_state_0; // @[TagArray.scala:12:7, :38:17] rbuf_3_tag <= io_resp_3_tag_0; // @[TagArray.scala:12:7, :38:17] end if (io_read_valid_0) // @[TagArray.scala:12:7] s1_read_idx <= io_read_bits_idx_0; // @[TagArray.scala:12:7, :74:30] REG <= io_read_ready_0 & io_read_valid_0 & ~forward_from_rbuf; // @[Decoupled.scala:51:35] REG_1 <= forward_from_rbuf; // @[TagArray.scala:39:35, :88:16] if (forward_from_rbuf) begin // @[TagArray.scala:39:35] r_0_coh_state <= rbuf_0_coh_state; // @[TagArray.scala:38:17, :89:25] r_0_tag <= rbuf_0_tag; // @[TagArray.scala:38:17, :89:25] r_1_coh_state <= rbuf_1_coh_state; // @[TagArray.scala:38:17, :89:25] r_1_tag <= rbuf_1_tag; // @[TagArray.scala:38:17, :89:25] r_2_coh_state <= rbuf_2_coh_state; // @[TagArray.scala:38:17, :89:25] r_2_tag <= rbuf_2_tag; // @[TagArray.scala:38:17, :89:25] r_3_coh_state <= rbuf_3_coh_state; // @[TagArray.scala:38:17, :89:25] r_3_tag <= rbuf_3_tag; // @[TagArray.scala:38:17, :89:25] end always @(posedge) tag_array_3 tag_array ( // @[TagArray.scala:28:30] .RW0_addr (wen ? tag_array_MPORT_addr : tag_array_MPORT_1_addr), // @[TagArray.scala:28:30, :30:17, :85:20, :87:28] .RW0_en (tag_array_MPORT_1_en | wen), // @[TagArray.scala:28:30, :30:17, :87:51] .RW0_clk (clock), .RW0_wmode (wen), // @[TagArray.scala:30:17] .RW0_wdata ({4{wdata}}), // @[TagArray.scala:22:52, :28:30] .RW0_rdata (_tag_array_RW0_rdata), .RW0_wmask ({wmask_3, wmask_2, wmask_1, wmask_0}) // @[TagArray.scala:23:81, :28:30] ); // @[TagArray.scala:28:30] assign io_read_ready = io_read_ready_0; // @[TagArray.scala:12:7] assign io_write_ready = io_write_ready_0; // @[TagArray.scala:12:7] assign io_resp_0_coh_state = io_resp_0_coh_state_0; // @[TagArray.scala:12:7] assign io_resp_0_tag = io_resp_0_tag_0; // @[TagArray.scala:12:7] assign io_resp_1_coh_state = io_resp_1_coh_state_0; // @[TagArray.scala:12:7] assign io_resp_1_tag = io_resp_1_tag_0; // @[TagArray.scala:12:7] assign io_resp_2_coh_state = io_resp_2_coh_state_0; // @[TagArray.scala:12:7] assign io_resp_2_tag = io_resp_2_tag_0; // @[TagArray.scala:12:7] assign io_resp_3_coh_state = io_resp_3_coh_state_0; // @[TagArray.scala:12:7] assign io_resp_3_tag = io_resp_3_tag_0; // @[TagArray.scala:12:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLCFromNoC_1 : input clock : Clock input reset : Reset output io : { protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, ingress_id : UInt}}} wire protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} regreset is_const : UInt<1>, clock, reset, UInt<1>(0h1) reg const_reg : UInt<48>, clock node const = mux(io.flit.bits.head, io.flit.bits.payload, const_reg) node _io_flit_ready_T = eq(io.flit.bits.tail, UInt<1>(0h0)) node _io_flit_ready_T_1 = and(is_const, _io_flit_ready_T) node _io_flit_ready_T_2 = or(_io_flit_ready_T_1, protocol.ready) connect io.flit.ready, _io_flit_ready_T_2 node _protocol_valid_T = eq(is_const, UInt<1>(0h0)) node _protocol_valid_T_1 = or(_protocol_valid_T, io.flit.bits.tail) node _protocol_valid_T_2 = and(_protocol_valid_T_1, io.flit.valid) connect protocol.valid, _protocol_valid_T_2 wire _protocol_bits_echo_WIRE : { } wire _protocol_bits_echo_WIRE_1 : UInt<0> connect _protocol_bits_echo_WIRE_1, const connect protocol.bits.echo, _protocol_bits_echo_WIRE node _T = shr(const, 0) wire _protocol_bits_user_WIRE : { } wire _protocol_bits_user_WIRE_1 : UInt<0> connect _protocol_bits_user_WIRE_1, _T connect protocol.bits.user, _protocol_bits_user_WIRE node _T_1 = shr(_T, 0) wire _protocol_bits_address_WIRE : UInt<32> connect _protocol_bits_address_WIRE, _T_1 connect protocol.bits.address, _protocol_bits_address_WIRE node _T_2 = shr(_T_1, 32) wire _protocol_bits_source_WIRE : UInt<6> connect _protocol_bits_source_WIRE, _T_2 connect protocol.bits.source, _protocol_bits_source_WIRE node _T_3 = shr(_T_2, 6) wire _protocol_bits_size_WIRE : UInt<4> connect _protocol_bits_size_WIRE, _T_3 connect protocol.bits.size, _protocol_bits_size_WIRE node _T_4 = shr(_T_3, 4) wire _protocol_bits_param_WIRE : UInt<3> connect _protocol_bits_param_WIRE, _T_4 connect protocol.bits.param, _protocol_bits_param_WIRE node _T_5 = shr(_T_4, 3) wire _protocol_bits_opcode_WIRE : UInt<3> connect _protocol_bits_opcode_WIRE, _T_5 connect protocol.bits.opcode, _protocol_bits_opcode_WIRE node _T_6 = shr(_T_5, 3) wire _protocol_bits_corrupt_WIRE : UInt<1> connect _protocol_bits_corrupt_WIRE, io.flit.bits.payload connect protocol.bits.corrupt, _protocol_bits_corrupt_WIRE node _T_7 = shr(io.flit.bits.payload, 1) wire _protocol_bits_data_WIRE : UInt<64> connect _protocol_bits_data_WIRE, _T_7 connect protocol.bits.data, _protocol_bits_data_WIRE node _T_8 = shr(_T_7, 64) node _T_9 = and(io.flit.ready, io.flit.valid) node _T_10 = and(_T_9, io.flit.bits.head) when _T_10 : connect is_const, UInt<1>(0h0) connect const_reg, io.flit.bits.payload node _T_11 = and(io.flit.ready, io.flit.valid) node _T_12 = and(_T_11, io.flit.bits.tail) when _T_12 : connect is_const, UInt<1>(0h1) connect io.protocol, protocol
module TLCFromNoC_1( // @[TilelinkAdapters.scala:167:7] input clock, // @[TilelinkAdapters.scala:167:7] input reset, // @[TilelinkAdapters.scala:167:7] input io_protocol_ready, // @[TilelinkAdapters.scala:56:14] output io_protocol_valid, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:56:14] output [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:56:14] output [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:56:14] output [5:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:56:14] output [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:56:14] output [63:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:56:14] output io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:56:14] output io_flit_ready, // @[TilelinkAdapters.scala:56:14] input io_flit_valid, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_head, // @[TilelinkAdapters.scala:56:14] input io_flit_bits_tail, // @[TilelinkAdapters.scala:56:14] input [64:0] io_flit_bits_payload // @[TilelinkAdapters.scala:56:14] ); reg is_const; // @[TilelinkAdapters.scala:68:25] reg [47:0] const_reg; // @[TilelinkAdapters.scala:69:22] wire [47:0] const_0 = io_flit_bits_head ? io_flit_bits_payload[47:0] : const_reg; // @[TilelinkAdapters.scala:56:14, :69:22, :70:18] wire io_flit_ready_0 = is_const & ~io_flit_bits_tail | io_protocol_ready; // @[TilelinkAdapters.scala:68:25, :71:{30,33,53}] wire _GEN = io_flit_ready_0 & io_flit_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = _GEN & io_flit_bits_head; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[TilelinkAdapters.scala:167:7] if (reset) // @[TilelinkAdapters.scala:167:7] is_const <= 1'h1; // @[TilelinkAdapters.scala:68:25, :167:7] else // @[TilelinkAdapters.scala:167:7] is_const <= _GEN & io_flit_bits_tail | ~_GEN_0 & is_const; // @[Decoupled.scala:51:35] if (_GEN_0) // @[TilelinkAdapters.scala:84:22] const_reg <= io_flit_bits_payload[47:0]; // @[TilelinkAdapters.scala:56:14, :69:22] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_2 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_2( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module CSRFile : input clock : Clock input reset : Reset output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<1>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]} connect io.rw_stall, UInt<1>(0h0) wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) connect _reset_mstatus_WIRE.v, UInt<1>(0h0) connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect reset_mstatus, _reset_mstatus_WIRE connect reset_mstatus.mpp, UInt<2>(0h3) connect reset_mstatus.prv, UInt<2>(0h3) connect reset_mstatus.xs, UInt<1>(0h0) regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus wire new_prv : UInt connect new_prv, reg_mstatus.prv node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2)) node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv) connect reg_mstatus.prv, _reg_mstatus_prv_T_1 wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) connect _reset_dcsr_WIRE.step, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) connect _reset_dcsr_WIRE.v, UInt<1>(0h0) connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect reset_dcsr, _reset_dcsr_WIRE connect reset_dcsr.xdebugver, UInt<1>(0h1) connect reset_dcsr.prv, UInt<2>(0h3) regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sup.usip, UInt<1>(0h0) connect sup.ssip, UInt<1>(0h1) connect sup.vssip, UInt<1>(0h0) connect sup.msip, UInt<1>(0h1) connect sup.utip, UInt<1>(0h0) connect sup.stip, UInt<1>(0h1) connect sup.vstip, UInt<1>(0h0) connect sup.mtip, UInt<1>(0h1) connect sup.ueip, UInt<1>(0h0) connect sup.seip, UInt<1>(0h1) connect sup.vseip, UInt<1>(0h0) connect sup.meip, UInt<1>(0h1) connect sup.sgeip, UInt<1>(0h0) connect sup.rocc, UInt<1>(0h0) connect sup.debug, UInt<1>(0h0) connect sup.zero1, UInt<1>(0h0) wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect del, sup connect del.msip, UInt<1>(0h0) connect del.mtip, UInt<1>(0h0) connect del.meip, UInt<1>(0h0) node lo_lo_lo = cat(sup.ssip, sup.usip) node lo_lo_hi = cat(sup.msip, sup.vssip) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(sup.stip, sup.utip) node lo_hi_hi = cat(sup.mtip, sup.vstip) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(sup.seip, sup.ueip) node hi_lo_hi = cat(sup.meip, sup.vseip) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(sup.rocc, sup.sgeip) node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node supported_interrupts = or(_T, UInt<1>(0h0)) node lo_lo_lo_1 = cat(del.ssip, del.usip) node lo_lo_hi_1 = cat(del.msip, del.vssip) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(del.stip, del.utip) node lo_hi_hi_1 = cat(del.mtip, del.vstip) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(del.seip, del.ueip) node hi_lo_hi_1 = cat(del.meip, del.vseip) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(del.rocc, del.sgeip) node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node delegable_interrupts = cat(hi_1, lo_1) wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _always_WIRE.usip, UInt<1>(0h0) connect _always_WIRE.ssip, UInt<1>(0h0) connect _always_WIRE.vssip, UInt<1>(0h0) connect _always_WIRE.msip, UInt<1>(0h0) connect _always_WIRE.utip, UInt<1>(0h0) connect _always_WIRE.stip, UInt<1>(0h0) connect _always_WIRE.vstip, UInt<1>(0h0) connect _always_WIRE.mtip, UInt<1>(0h0) connect _always_WIRE.ueip, UInt<1>(0h0) connect _always_WIRE.seip, UInt<1>(0h0) connect _always_WIRE.vseip, UInt<1>(0h0) connect _always_WIRE.meip, UInt<1>(0h0) connect _always_WIRE.sgeip, UInt<1>(0h0) connect _always_WIRE.rocc, UInt<1>(0h0) connect _always_WIRE.debug, UInt<1>(0h0) connect _always_WIRE.zero1, UInt<1>(0h0) wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect always, _always_WIRE connect always.vssip, UInt<1>(0h0) connect always.vstip, UInt<1>(0h0) connect always.vseip, UInt<1>(0h0) wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect deleg, always node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) node hi_2 = cat(hi_hi_2, hi_lo_2) node hs_delegable_interrupts = cat(hi_2, lo_2) node lo_lo_lo_3 = cat(always.ssip, always.usip) node lo_lo_hi_3 = cat(always.msip, always.vssip) node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) node lo_hi_lo_3 = cat(always.stip, always.utip) node lo_hi_hi_3 = cat(always.mtip, always.vstip) node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_lo_3 = cat(always.seip, always.ueip) node hi_lo_hi_3 = cat(always.meip, always.vseip) node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) node hi_hi_lo_3 = cat(always.rocc, always.sgeip) node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) node hi_3 = cat(hi_hi_3, hi_lo_3) node mideleg_always_hs = cat(hi_3, lo_3) regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) reg reg_dpc : UInt<40>, clock reg reg_dscratch0 : UInt<64>, clock reg reg_singleStepped : UInt<1>, clock reg reg_tselect : UInt<1>, clock reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock reg reg_mie : UInt<64>, clock reg reg_mideleg : UInt<64>, clock node _T_1 = and(reg_mideleg, delegable_interrupts) node _T_2 = or(_T_1, mideleg_always_hs) node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0)) reg reg_medeleg : UInt<64>, clock node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0)) reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock reg reg_mepc : UInt<40>, clock regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0) reg reg_mtval : UInt<40>, clock reg reg_mtval2 : UInt<40>, clock reg reg_mscratch : UInt<64>, clock regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect reset_mnstatus, _reset_mnstatus_WIRE connect reset_mnstatus.mpp, UInt<2>(0h3) reg reg_mnscratch : UInt<64>, clock reg reg_mnepc : UInt<40>, clock regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0) regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE reg reg_mcounteren : UInt<32>, clock node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0)) reg reg_scounteren : UInt<32>, clock node _T_5 = and(reg_scounteren, UInt<3>(0h7)) node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0)) reg reg_hideleg : UInt<64>, clock node _T_6 = and(reg_hideleg, hs_delegable_interrupts) node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) reg reg_hedeleg : UInt<64>, clock node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) reg reg_hcounteren : UInt<32>, clock node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_htval : UInt<40>, clock node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) node read_hie = and(reg_mie, hs_delegable_interrupts) reg reg_vstvec : UInt<40>, clock node _T_9 = bits(reg_vstvec, 0, 0) node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2)) node _T_11 = and(reg_vstvec, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = not(_T_12) node _T_14 = and(reg_vstvec, _T_13) node _T_15 = bits(_T_14, 39, 39) node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0)) node read_vstvec = cat(_T_16, _T_14) reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock reg reg_vsscratch : UInt<64>, clock reg reg_vsepc : UInt<40>, clock reg reg_vscause : UInt<64>, clock reg reg_vstval : UInt<40>, clock reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg reg_sepc : UInt<40>, clock reg reg_scause : UInt<64>, clock reg reg_stval : UInt<40>, clock reg reg_sscratch : UInt<64>, clock reg reg_stvec : UInt<39>, clock reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) reg reg_fflags : UInt<5>, clock reg reg_frm : UInt<3>, clock reg reg_mtinst_read_pseudo : UInt<1>, clock reg reg_htinst_read_pseudo : UInt<1>, clock node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo) node read_mtinst = cat(hi_4, UInt<12>(0h0)) node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo) node read_htinst = cat(hi_5, UInt<12>(0h0)) regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) connect io.inhibit_cycle, _io_inhibit_cycle_T node x3 = bits(reg_mcountinhibit, 2, 2) regreset small : UInt<6>, clock, reset, UInt<6>(0h0) node nextSmall = add(small, io.retire) node _T_17 = eq(x3, UInt<1>(0h0)) when _T_17 : connect small, nextSmall regreset large : UInt<58>, clock, reset, UInt<58>(0h0) node _large_T = bits(nextSmall, 6, 6) node _large_T_1 = eq(x3, UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node x10 = eq(io.csr_stall, UInt<1>(0h0)) node x11 = bits(reg_mcountinhibit, 0, 0) regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) node nextSmall_1 = add(small_1, x10) node _T_18 = eq(x11, UInt<1>(0h0)) when _T_18 : connect small_1, nextSmall_1 regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) node _large_T_3 = bits(nextSmall_1, 6, 6) node _large_T_4 = eq(x11, UInt<1>(0h0)) node _large_T_5 = and(_large_T_3, _large_T_4) when _large_T_5 : node _large_r_T_2 = add(large_1, UInt<1>(0h1)) node _large_r_T_3 = tail(_large_r_T_2, 1) connect large_1, _large_r_T_3 node value_1 = cat(large_1, small_1) wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect mip, reg_mip connect mip.mtip, io.interrupts.mtip connect mip.msip, io.interrupts.msip connect mip.meip, io.interrupts.meip node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip) connect mip.seip, _mip_seip_T connect mip.rocc, io.rocc_interrupt node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) node _read_mip_T = cat(read_mip_hi, read_mip_lo) node read_mip = and(_read_mip_T, supported_interrupts) node read_hip = and(read_mip, hs_delegable_interrupts) node _pending_interrupts_T = and(read_mip, reg_mie) node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) node d_interrupts = shl(io.interrupts.debug, 14) node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) node _m_interrupts_T_3 = not(pending_interrupts) node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) node _m_interrupts_T_5 = not(_m_interrupts_T_4) node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) node _s_interrupts_T_7 = not(read_hideleg) node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) node _any_T = bits(d_interrupts, 14, 14) node _any_T_1 = bits(d_interrupts, 13, 13) node _any_T_2 = bits(d_interrupts, 12, 12) node _any_T_3 = bits(d_interrupts, 11, 11) node _any_T_4 = bits(d_interrupts, 3, 3) node _any_T_5 = bits(d_interrupts, 7, 7) node _any_T_6 = bits(d_interrupts, 9, 9) node _any_T_7 = bits(d_interrupts, 1, 1) node _any_T_8 = bits(d_interrupts, 5, 5) node _any_T_9 = bits(d_interrupts, 10, 10) node _any_T_10 = bits(d_interrupts, 2, 2) node _any_T_11 = bits(d_interrupts, 6, 6) node _any_T_12 = bits(d_interrupts, 8, 8) node _any_T_13 = bits(d_interrupts, 0, 0) node _any_T_14 = bits(d_interrupts, 4, 4) node _any_T_15 = bits(m_interrupts, 15, 15) node _any_T_16 = bits(m_interrupts, 14, 14) node _any_T_17 = bits(m_interrupts, 13, 13) node _any_T_18 = bits(m_interrupts, 12, 12) node _any_T_19 = bits(m_interrupts, 11, 11) node _any_T_20 = bits(m_interrupts, 3, 3) node _any_T_21 = bits(m_interrupts, 7, 7) node _any_T_22 = bits(m_interrupts, 9, 9) node _any_T_23 = bits(m_interrupts, 1, 1) node _any_T_24 = bits(m_interrupts, 5, 5) node _any_T_25 = bits(m_interrupts, 10, 10) node _any_T_26 = bits(m_interrupts, 2, 2) node _any_T_27 = bits(m_interrupts, 6, 6) node _any_T_28 = bits(m_interrupts, 8, 8) node _any_T_29 = bits(m_interrupts, 0, 0) node _any_T_30 = bits(m_interrupts, 4, 4) node _any_T_31 = bits(s_interrupts, 15, 15) node _any_T_32 = bits(s_interrupts, 14, 14) node _any_T_33 = bits(s_interrupts, 13, 13) node _any_T_34 = bits(s_interrupts, 12, 12) node _any_T_35 = bits(s_interrupts, 11, 11) node _any_T_36 = bits(s_interrupts, 3, 3) node _any_T_37 = bits(s_interrupts, 7, 7) node _any_T_38 = bits(s_interrupts, 9, 9) node _any_T_39 = bits(s_interrupts, 1, 1) node _any_T_40 = bits(s_interrupts, 5, 5) node _any_T_41 = bits(s_interrupts, 10, 10) node _any_T_42 = bits(s_interrupts, 2, 2) node _any_T_43 = bits(s_interrupts, 6, 6) node _any_T_44 = bits(s_interrupts, 8, 8) node _any_T_45 = bits(s_interrupts, 0, 0) node _any_T_46 = bits(s_interrupts, 4, 4) node _any_T_47 = bits(vs_interrupts, 15, 15) node _any_T_48 = bits(vs_interrupts, 14, 14) node _any_T_49 = bits(vs_interrupts, 13, 13) node _any_T_50 = bits(vs_interrupts, 12, 12) node _any_T_51 = bits(vs_interrupts, 11, 11) node _any_T_52 = bits(vs_interrupts, 3, 3) node _any_T_53 = bits(vs_interrupts, 7, 7) node _any_T_54 = bits(vs_interrupts, 9, 9) node _any_T_55 = bits(vs_interrupts, 1, 1) node _any_T_56 = bits(vs_interrupts, 5, 5) node _any_T_57 = bits(vs_interrupts, 10, 10) node _any_T_58 = bits(vs_interrupts, 2, 2) node _any_T_59 = bits(vs_interrupts, 6, 6) node _any_T_60 = bits(vs_interrupts, 8, 8) node _any_T_61 = bits(vs_interrupts, 0, 0) node _any_T_62 = bits(vs_interrupts, 4, 4) node _any_T_63 = or(_any_T, _any_T_1) node _any_T_64 = or(_any_T_63, _any_T_2) node _any_T_65 = or(_any_T_64, _any_T_3) node _any_T_66 = or(_any_T_65, _any_T_4) node _any_T_67 = or(_any_T_66, _any_T_5) node _any_T_68 = or(_any_T_67, _any_T_6) node _any_T_69 = or(_any_T_68, _any_T_7) node _any_T_70 = or(_any_T_69, _any_T_8) node _any_T_71 = or(_any_T_70, _any_T_9) node _any_T_72 = or(_any_T_71, _any_T_10) node _any_T_73 = or(_any_T_72, _any_T_11) node _any_T_74 = or(_any_T_73, _any_T_12) node _any_T_75 = or(_any_T_74, _any_T_13) node _any_T_76 = or(_any_T_75, _any_T_14) node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) node _any_T_78 = or(_any_T_77, _any_T_15) node _any_T_79 = or(_any_T_78, _any_T_16) node _any_T_80 = or(_any_T_79, _any_T_17) node _any_T_81 = or(_any_T_80, _any_T_18) node _any_T_82 = or(_any_T_81, _any_T_19) node _any_T_83 = or(_any_T_82, _any_T_20) node _any_T_84 = or(_any_T_83, _any_T_21) node _any_T_85 = or(_any_T_84, _any_T_22) node _any_T_86 = or(_any_T_85, _any_T_23) node _any_T_87 = or(_any_T_86, _any_T_24) node _any_T_88 = or(_any_T_87, _any_T_25) node _any_T_89 = or(_any_T_88, _any_T_26) node _any_T_90 = or(_any_T_89, _any_T_27) node _any_T_91 = or(_any_T_90, _any_T_28) node _any_T_92 = or(_any_T_91, _any_T_29) node _any_T_93 = or(_any_T_92, _any_T_30) node _any_T_94 = or(_any_T_93, _any_T_31) node _any_T_95 = or(_any_T_94, _any_T_32) node _any_T_96 = or(_any_T_95, _any_T_33) node _any_T_97 = or(_any_T_96, _any_T_34) node _any_T_98 = or(_any_T_97, _any_T_35) node _any_T_99 = or(_any_T_98, _any_T_36) node _any_T_100 = or(_any_T_99, _any_T_37) node _any_T_101 = or(_any_T_100, _any_T_38) node _any_T_102 = or(_any_T_101, _any_T_39) node _any_T_103 = or(_any_T_102, _any_T_40) node _any_T_104 = or(_any_T_103, _any_T_41) node _any_T_105 = or(_any_T_104, _any_T_42) node _any_T_106 = or(_any_T_105, _any_T_43) node _any_T_107 = or(_any_T_106, _any_T_44) node _any_T_108 = or(_any_T_107, _any_T_45) node _any_T_109 = or(_any_T_108, _any_T_46) node _any_T_110 = or(_any_T_109, _any_T_47) node _any_T_111 = or(_any_T_110, _any_T_48) node _any_T_112 = or(_any_T_111, _any_T_49) node _any_T_113 = or(_any_T_112, _any_T_50) node _any_T_114 = or(_any_T_113, _any_T_51) node _any_T_115 = or(_any_T_114, _any_T_52) node _any_T_116 = or(_any_T_115, _any_T_53) node _any_T_117 = or(_any_T_116, _any_T_54) node _any_T_118 = or(_any_T_117, _any_T_55) node _any_T_119 = or(_any_T_118, _any_T_56) node _any_T_120 = or(_any_T_119, _any_T_57) node _any_T_121 = or(_any_T_120, _any_T_58) node _any_T_122 = or(_any_T_121, _any_T_59) node _any_T_123 = or(_any_T_122, _any_T_60) node _any_T_124 = or(_any_T_123, _any_T_61) node anyInterrupt = or(_any_T_124, _any_T_62) node _which_T = bits(d_interrupts, 14, 14) node _which_T_1 = bits(d_interrupts, 13, 13) node _which_T_2 = bits(d_interrupts, 12, 12) node _which_T_3 = bits(d_interrupts, 11, 11) node _which_T_4 = bits(d_interrupts, 3, 3) node _which_T_5 = bits(d_interrupts, 7, 7) node _which_T_6 = bits(d_interrupts, 9, 9) node _which_T_7 = bits(d_interrupts, 1, 1) node _which_T_8 = bits(d_interrupts, 5, 5) node _which_T_9 = bits(d_interrupts, 10, 10) node _which_T_10 = bits(d_interrupts, 2, 2) node _which_T_11 = bits(d_interrupts, 6, 6) node _which_T_12 = bits(d_interrupts, 8, 8) node _which_T_13 = bits(d_interrupts, 0, 0) node _which_T_14 = bits(d_interrupts, 4, 4) node _which_T_15 = bits(m_interrupts, 15, 15) node _which_T_16 = bits(m_interrupts, 14, 14) node _which_T_17 = bits(m_interrupts, 13, 13) node _which_T_18 = bits(m_interrupts, 12, 12) node _which_T_19 = bits(m_interrupts, 11, 11) node _which_T_20 = bits(m_interrupts, 3, 3) node _which_T_21 = bits(m_interrupts, 7, 7) node _which_T_22 = bits(m_interrupts, 9, 9) node _which_T_23 = bits(m_interrupts, 1, 1) node _which_T_24 = bits(m_interrupts, 5, 5) node _which_T_25 = bits(m_interrupts, 10, 10) node _which_T_26 = bits(m_interrupts, 2, 2) node _which_T_27 = bits(m_interrupts, 6, 6) node _which_T_28 = bits(m_interrupts, 8, 8) node _which_T_29 = bits(m_interrupts, 0, 0) node _which_T_30 = bits(m_interrupts, 4, 4) node _which_T_31 = bits(s_interrupts, 15, 15) node _which_T_32 = bits(s_interrupts, 14, 14) node _which_T_33 = bits(s_interrupts, 13, 13) node _which_T_34 = bits(s_interrupts, 12, 12) node _which_T_35 = bits(s_interrupts, 11, 11) node _which_T_36 = bits(s_interrupts, 3, 3) node _which_T_37 = bits(s_interrupts, 7, 7) node _which_T_38 = bits(s_interrupts, 9, 9) node _which_T_39 = bits(s_interrupts, 1, 1) node _which_T_40 = bits(s_interrupts, 5, 5) node _which_T_41 = bits(s_interrupts, 10, 10) node _which_T_42 = bits(s_interrupts, 2, 2) node _which_T_43 = bits(s_interrupts, 6, 6) node _which_T_44 = bits(s_interrupts, 8, 8) node _which_T_45 = bits(s_interrupts, 0, 0) node _which_T_46 = bits(s_interrupts, 4, 4) node _which_T_47 = bits(vs_interrupts, 15, 15) node _which_T_48 = bits(vs_interrupts, 14, 14) node _which_T_49 = bits(vs_interrupts, 13, 13) node _which_T_50 = bits(vs_interrupts, 12, 12) node _which_T_51 = bits(vs_interrupts, 11, 11) node _which_T_52 = bits(vs_interrupts, 3, 3) node _which_T_53 = bits(vs_interrupts, 7, 7) node _which_T_54 = bits(vs_interrupts, 9, 9) node _which_T_55 = bits(vs_interrupts, 1, 1) node _which_T_56 = bits(vs_interrupts, 5, 5) node _which_T_57 = bits(vs_interrupts, 10, 10) node _which_T_58 = bits(vs_interrupts, 2, 2) node _which_T_59 = bits(vs_interrupts, 6, 6) node _which_T_60 = bits(vs_interrupts, 8, 8) node _which_T_61 = bits(vs_interrupts, 0, 0) node _which_T_62 = bits(vs_interrupts, 4, 4) node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) node _interruptCause_T = shl(UInt<1>(0h0), 62) node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T) node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) node interruptCause = tail(_interruptCause_T_3, 1) node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) node _io_interrupt_T_3 = or(reg_debug, io.status.cease) node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) connect io.interrupt, _io_interrupt_T_5 connect io.interrupt_cause, interruptCause connect io.bp[0], reg_bp[0] connect io.mcontext, UInt<1>(0h0) connect io.scontext, UInt<1>(0h0) node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) connect io.fiom, _io_fiom_T_6 wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp.cfg, reg_pmp[0].cfg connect pmp.addr, reg_pmp[0].addr node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) node _pmp_mask_T_2 = not(_pmp_mask_T_1) node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) connect pmp.mask, _pmp_mask_T_4 wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_1.cfg, reg_pmp[1].cfg connect pmp_1.addr, reg_pmp[1].addr node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) node _pmp_mask_T_7 = not(_pmp_mask_T_6) node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) connect pmp_1.mask, _pmp_mask_T_9 wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_2.cfg, reg_pmp[2].cfg connect pmp_2.addr, reg_pmp[2].addr node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) node _pmp_mask_T_12 = not(_pmp_mask_T_11) node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) connect pmp_2.mask, _pmp_mask_T_14 wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_3.cfg, reg_pmp[3].cfg connect pmp_3.addr, reg_pmp[3].addr node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) node _pmp_mask_T_17 = not(_pmp_mask_T_16) node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) connect pmp_3.mask, _pmp_mask_T_19 wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_4.cfg, reg_pmp[4].cfg connect pmp_4.addr, reg_pmp[4].addr node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) node _pmp_mask_T_22 = not(_pmp_mask_T_21) node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) connect pmp_4.mask, _pmp_mask_T_24 wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_5.cfg, reg_pmp[5].cfg connect pmp_5.addr, reg_pmp[5].addr node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) node _pmp_mask_T_27 = not(_pmp_mask_T_26) node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) connect pmp_5.mask, _pmp_mask_T_29 wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_6.cfg, reg_pmp[6].cfg connect pmp_6.addr, reg_pmp[6].addr node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) node _pmp_mask_T_32 = not(_pmp_mask_T_31) node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) connect pmp_6.mask, _pmp_mask_T_34 wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_7.cfg, reg_pmp[7].cfg connect pmp_7.addr, reg_pmp[7].addr node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) node _pmp_mask_T_37 = not(_pmp_mask_T_36) node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) connect pmp_7.mask, _pmp_mask_T_39 connect io.pmp[0], pmp connect io.pmp[1], pmp_1 connect io.pmp[2], pmp_2 connect io.pmp[3], pmp_3 connect io.pmp[4], pmp_4 connect io.pmp[5], pmp_5 connect io.pmp[6], pmp_6 connect io.pmp[7], pmp_7 regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000094112d) node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) node read_mstatus = bits(_read_mstatus_T, 63, 0) node _read_mtvec_T = bits(reg_mtvec, 0, 0) node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) node _read_mtvec_T_4 = not(_read_mtvec_T_3) node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4) node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5) node _read_stvec_T = bits(reg_stvec, 0, 0) node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2)) node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) node _read_stvec_T_4 = not(_read_stvec_T_3) node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4) node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38) node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5) node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38) node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0)) node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address) node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) node _read_mapping_T_2 = not(reg_mepc) node _read_mapping_T_3 = bits(reg_misa, 2, 2) node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3)) node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4) node _read_mapping_T_6 = not(_read_mapping_T_5) node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39) node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6) node _read_mapping_T_9 = bits(reg_mtval, 39, 39) node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0)) node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval) node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) node _debug_csrs_T = not(reg_dpc) node _debug_csrs_T_1 = bits(reg_misa, 2, 2) node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) node _debug_csrs_T_4 = not(_debug_csrs_T_3) node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39) node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0)) node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4) wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect read_mnstatus, _read_mnstatus_WIRE connect read_mnstatus.mpp, reg_mnstatus.mpp connect read_mnstatus.mpv, reg_mnstatus.mpv connect read_mnstatus.mie, reg_rnmie node read_fcsr = cat(reg_frm, reg_fflags) node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom) node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie) node lo_4 = cat(lo_hi_4, lo_lo_4) node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze) node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte) node hi_6 = cat(hi_hi_4, hi_lo_4) node _T_19 = cat(hi_6, lo_4) wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) node _sie_mask_T_2 = not(_sie_mask_T_1) node sie_mask = and(read_mideleg, _sie_mask_T_2) node read_sie = and(reg_mie, sie_mask) node read_sip = and(read_mip, sie_mask) wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _read_sstatus_WIRE.uie, UInt<1>(0h0) connect _read_sstatus_WIRE.sie, UInt<1>(0h0) connect _read_sstatus_WIRE.hie, UInt<1>(0h0) connect _read_sstatus_WIRE.mie, UInt<1>(0h0) connect _read_sstatus_WIRE.upie, UInt<1>(0h0) connect _read_sstatus_WIRE.spie, UInt<1>(0h0) connect _read_sstatus_WIRE.ube, UInt<1>(0h0) connect _read_sstatus_WIRE.mpie, UInt<1>(0h0) connect _read_sstatus_WIRE.spp, UInt<1>(0h0) connect _read_sstatus_WIRE.vs, UInt<2>(0h0) connect _read_sstatus_WIRE.mpp, UInt<2>(0h0) connect _read_sstatus_WIRE.fs, UInt<2>(0h0) connect _read_sstatus_WIRE.xs, UInt<2>(0h0) connect _read_sstatus_WIRE.mprv, UInt<1>(0h0) connect _read_sstatus_WIRE.sum, UInt<1>(0h0) connect _read_sstatus_WIRE.mxr, UInt<1>(0h0) connect _read_sstatus_WIRE.tvm, UInt<1>(0h0) connect _read_sstatus_WIRE.tw, UInt<1>(0h0) connect _read_sstatus_WIRE.tsr, UInt<1>(0h0) connect _read_sstatus_WIRE.zero1, UInt<8>(0h0) connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _read_sstatus_WIRE.uxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sxl, UInt<2>(0h0) connect _read_sstatus_WIRE.sbe, UInt<1>(0h0) connect _read_sstatus_WIRE.mbe, UInt<1>(0h0) connect _read_sstatus_WIRE.gva, UInt<1>(0h0) connect _read_sstatus_WIRE.mpv, UInt<1>(0h0) connect _read_sstatus_WIRE.zero2, UInt<23>(0h0) connect _read_sstatus_WIRE.sd, UInt<1>(0h0) connect _read_sstatus_WIRE.v, UInt<1>(0h0) connect _read_sstatus_WIRE.prv, UInt<2>(0h0) connect _read_sstatus_WIRE.dv, UInt<1>(0h0) connect _read_sstatus_WIRE.dprv, UInt<2>(0h0) connect _read_sstatus_WIRE.isa, UInt<32>(0h0) connect _read_sstatus_WIRE.wfi, UInt<1>(0h0) connect _read_sstatus_WIRE.cease, UInt<1>(0h0) connect _read_sstatus_WIRE.debug, UInt<1>(0h0) wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect read_sstatus, _read_sstatus_WIRE connect read_sstatus.sd, io.status.sd connect read_sstatus.uxl, io.status.uxl connect read_sstatus.sd_rv32, io.status.sd_rv32 connect read_sstatus.mxr, io.status.mxr connect read_sstatus.sum, io.status.sum connect read_sstatus.xs, io.status.xs connect read_sstatus.fs, io.status.fs connect read_sstatus.vs, io.status.vs connect read_sstatus.spp, io.status.spp connect read_sstatus.spie, io.status.spie connect read_sstatus.sie, io.status.sie node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie) node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie) node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo) node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie) node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie) node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube) node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo) node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4) node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs) node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs) node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo) node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv) node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm) node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr) node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo) node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4) node lo_5 = cat(lo_hi_5, lo_lo_5) node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr) node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32) node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo) node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl) node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva) node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe) node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo) node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4) node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2) node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv) node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v) node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo) node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv) node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease) node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi) node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo) node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4) node hi_7 = cat(hi_hi_5, hi_lo_5) node _T_20 = cat(hi_7, lo_5) node _T_21 = bits(_T_20, 63, 0) node _T_22 = bits(reg_stval, 39, 39) node _T_23 = mux(_T_22, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_24 = cat(_T_23, reg_stval) node hi_8 = cat(reg_satp.mode, reg_satp.asid) node _T_25 = cat(hi_8, reg_satp.ppn) node _T_26 = not(reg_sepc) node _T_27 = bits(reg_misa, 2, 2) node _T_28 = mux(_T_27, UInt<1>(0h1), UInt<2>(0h3)) node _T_29 = or(_T_26, _T_28) node _T_30 = not(_T_29) node _T_31 = bits(_T_30, 39, 39) node _T_32 = mux(_T_31, UInt<24>(0hffffff), UInt<24>(0h0)) node _T_33 = cat(_T_32, _T_30) node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom) node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie) node lo_6 = cat(lo_hi_6, lo_lo_6) node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze) node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte) node hi_9 = cat(hi_hi_6, hi_lo_6) node _T_34 = cat(hi_9, lo_6) wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect read_pmp_15.mask, UInt<32>(0h0) connect read_pmp_15.addr, UInt<30>(0h0) connect read_pmp_15.cfg.r, UInt<1>(0h0) connect read_pmp_15.cfg.w, UInt<1>(0h0) connect read_pmp_15.cfg.x, UInt<1>(0h0) connect read_pmp_15.cfg.a, UInt<2>(0h0) connect read_pmp_15.cfg.res, UInt<2>(0h0) connect read_pmp_15.cfg.l, UInt<1>(0h0) node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r) node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a) node _T_35 = cat(hi_10, lo_7) node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r) node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a) node _T_36 = cat(hi_11, lo_8) node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r) node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a) node _T_37 = cat(hi_12, lo_9) node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r) node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a) node _T_38 = cat(hi_13, lo_10) node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r) node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a) node _T_39 = cat(hi_14, lo_11) node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r) node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a) node _T_40 = cat(hi_15, lo_12) node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r) node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a) node _T_41 = cat(hi_16, lo_13) node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r) node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a) node _T_42 = cat(hi_17, lo_14) node lo_lo_7 = cat(_T_36, _T_35) node lo_hi_15 = cat(_T_38, _T_37) node lo_15 = cat(lo_hi_15, lo_lo_7) node hi_lo_7 = cat(_T_40, _T_39) node hi_hi_15 = cat(_T_42, _T_41) node hi_18 = cat(hi_hi_15, hi_lo_7) node _T_43 = cat(hi_18, lo_15) node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r) node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a) node _T_44 = cat(hi_19, lo_16) node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r) node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a) node _T_45 = cat(hi_20, lo_17) node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r) node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a) node _T_46 = cat(hi_21, lo_18) node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r) node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a) node _T_47 = cat(hi_22, lo_19) node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r) node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a) node _T_48 = cat(hi_23, lo_20) node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r) node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a) node _T_49 = cat(hi_24, lo_21) node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r) node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a) node _T_50 = cat(hi_25, lo_22) node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r) node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a) node _T_51 = cat(hi_26, lo_23) node lo_lo_8 = cat(_T_45, _T_44) node lo_hi_24 = cat(_T_47, _T_46) node lo_24 = cat(lo_hi_24, lo_lo_8) node hi_lo_8 = cat(_T_49, _T_48) node hi_hi_24 = cat(_T_51, _T_50) node hi_27 = cat(hi_hi_24, hi_lo_8) node _T_52 = cat(hi_27, lo_24) regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h208) node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) connect io.customCSRs[0].ren, reg_custom_read node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) when _reg_custom_T : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1) node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) connect io.customCSRs[1].ren, reg_custom_read_1 node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) when _reg_custom_T_1 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) connect io.customCSRs[2].ren, reg_custom_read_2 node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) when _reg_custom_T_2 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004) node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) connect io.customCSRs[3].ren, reg_custom_read_3 node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) when _reg_custom_T_3 : connect io.rw_stall, UInt<1>(0h1) node decoded_addr_addr = cat(io.status.v, io.rw.addr) wire decoded_addr_decoded_decoded_plaInput : UInt<12> node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) wire decoded_addr_decoded_decoded : UInt<150> node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149) node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 149, 149) node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 148, 148) node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 147, 147) node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 146, 146) node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 145, 145) node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 144, 144) node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 143, 143) node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 142, 142) node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 141, 141) node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 140, 140) node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 139, 139) node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 138, 138) node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 137, 137) node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 136, 136) node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 135, 135) node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 134, 134) node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 133, 133) node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 132, 132) node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 131, 131) node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 130, 130) node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 129, 129) node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 128, 128) node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 127, 127) node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 126, 126) node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 125, 125) node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 124, 124) node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 123, 123) node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 122, 122) node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 121, 121) node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 120, 120) node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 119, 119) node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 118, 118) node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 117, 117) node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 116, 116) node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 115, 115) node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 114, 114) node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 113, 113) node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 112, 112) node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 111, 111) node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 110, 110) node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 109, 109) node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 108, 108) node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 107, 107) node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 106, 106) node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 105, 105) node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 104, 104) node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 103, 103) node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 102, 102) node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 101, 101) node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 100, 100) node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 99, 99) node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 98, 98) node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 97, 97) node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 96, 96) node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 95, 95) node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 94, 94) node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 93, 93) node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 92, 92) node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 91, 91) node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 90, 90) node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 89, 89) node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 88, 88) node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 87, 87) node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 86, 86) node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 85, 85) node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 84, 84) node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 83, 83) node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 82, 82) node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 81, 81) node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 80, 80) node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 79, 79) node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 78, 78) node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 77, 77) node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 76, 76) node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 75, 75) node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 74, 74) node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 73, 73) node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 72, 72) node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 71, 71) node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 70, 70) node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 69, 69) node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 68, 68) node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 67, 67) node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 66, 66) node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 65, 65) node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 64, 64) node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 63, 63) node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 62, 62) node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 61, 61) node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 60, 60) node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 59, 59) node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 58, 58) node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 57, 57) node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 56, 56) node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 55, 55) node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 54, 54) node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 53, 53) node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 52, 52) node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 51, 51) node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 50, 50) node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 49, 49) node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 48, 48) node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 47, 47) node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 46, 46) node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 45, 45) node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 44, 44) node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 43, 43) node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 42, 42) node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 41, 41) node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 40, 40) node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 39, 39) node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 38, 38) node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 37, 37) node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 36, 36) node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 35, 35) node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 34, 34) node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 33, 33) node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 32, 32) node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 31, 31) node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 30, 30) node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 29, 29) node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 28, 28) node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 27, 27) node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 26, 26) node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 25, 25) node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 24, 24) node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 23, 23) node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 22, 22) node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 21, 21) node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 20, 20) node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 19, 19) node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 18, 18) node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 17, 17) node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 16, 16) node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 15, 15) node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 14, 14) node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 13, 13) node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 12, 12) node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 11, 11) node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 10, 10) node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 9, 9) node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 8, 8) node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 7, 7) node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 6, 6) node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 5, 5) node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 4, 4) node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 3, 3) node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 2, 2) node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 1, 1) node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 0, 0) node decoded_addr_97_2 = bits(decoded_addr_decoded_0, 0, 0) node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0) node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0) node decoded_addr_118_2 = bits(decoded_addr_decoded_3, 0, 0) node decoded_addr_94_2 = bits(decoded_addr_decoded_4, 0, 0) node decoded_addr_100_2 = bits(decoded_addr_decoded_5, 0, 0) node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0) node decoded_addr_108_2 = bits(decoded_addr_decoded_7, 0, 0) node decoded_addr_76_2 = bits(decoded_addr_decoded_8, 0, 0) node decoded_addr_129_2 = bits(decoded_addr_decoded_9, 0, 0) node decoded_addr_132_2 = bits(decoded_addr_decoded_10, 0, 0) node decoded_addr_136_2 = bits(decoded_addr_decoded_11, 0, 0) node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0) node decoded_addr_131_2 = bits(decoded_addr_decoded_13, 0, 0) node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0) node decoded_addr_89_2 = bits(decoded_addr_decoded_15, 0, 0) node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0) node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0) node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0) node decoded_addr_99_2 = bits(decoded_addr_decoded_19, 0, 0) node decoded_addr_130_2 = bits(decoded_addr_decoded_20, 0, 0) node decoded_addr_103_2 = bits(decoded_addr_decoded_21, 0, 0) node decoded_addr_121_2 = bits(decoded_addr_decoded_22, 0, 0) node decoded_addr_146_2 = bits(decoded_addr_decoded_23, 0, 0) node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0) node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0) node decoded_addr_83_2 = bits(decoded_addr_decoded_26, 0, 0) node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0) node decoded_addr_144_2 = bits(decoded_addr_decoded_28, 0, 0) node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0) node decoded_addr_111_2 = bits(decoded_addr_decoded_30, 0, 0) node decoded_addr_82_2 = bits(decoded_addr_decoded_31, 0, 0) node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0) node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0) node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0) node decoded_addr_138_2 = bits(decoded_addr_decoded_35, 0, 0) node decoded_addr_126_2 = bits(decoded_addr_decoded_36, 0, 0) node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0) node decoded_addr_116_2 = bits(decoded_addr_decoded_38, 0, 0) node decoded_addr_90_2 = bits(decoded_addr_decoded_39, 0, 0) node decoded_addr_113_2 = bits(decoded_addr_decoded_40, 0, 0) node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0) node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0) node decoded_addr_78_2 = bits(decoded_addr_decoded_43, 0, 0) node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0) node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0) node decoded_addr_109_2 = bits(decoded_addr_decoded_46, 0, 0) node decoded_addr_91_2 = bits(decoded_addr_decoded_47, 0, 0) node decoded_addr_81_2 = bits(decoded_addr_decoded_48, 0, 0) node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0) node decoded_addr_105_2 = bits(decoded_addr_decoded_50, 0, 0) node decoded_addr_122_2 = bits(decoded_addr_decoded_51, 0, 0) node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0) node decoded_addr_124_2 = bits(decoded_addr_decoded_53, 0, 0) node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0) node decoded_addr_128_2 = bits(decoded_addr_decoded_55, 0, 0) node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0) node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0) node decoded_addr_77_2 = bits(decoded_addr_decoded_58, 0, 0) node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0) node decoded_addr_112_2 = bits(decoded_addr_decoded_60, 0, 0) node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0) node decoded_addr_92_2 = bits(decoded_addr_decoded_62, 0, 0) node decoded_addr_148_2 = bits(decoded_addr_decoded_63, 0, 0) node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0) node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0) node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0) node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0) node decoded_addr_133_2 = bits(decoded_addr_decoded_68, 0, 0) node decoded_addr_149_2 = bits(decoded_addr_decoded_69, 0, 0) node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0) node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0) node decoded_addr_102_2 = bits(decoded_addr_decoded_72, 0, 0) node decoded_addr_84_2 = bits(decoded_addr_decoded_73, 0, 0) node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0) node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0) node decoded_addr_120_2 = bits(decoded_addr_decoded_76, 0, 0) node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0) node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0) node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0) node decoded_addr_143_2 = bits(decoded_addr_decoded_80, 0, 0) node decoded_addr_117_2 = bits(decoded_addr_decoded_81, 0, 0) node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0) node decoded_addr_107_2 = bits(decoded_addr_decoded_83, 0, 0) node decoded_addr_88_2 = bits(decoded_addr_decoded_84, 0, 0) node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0) node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0) node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0) node decoded_addr_147_2 = bits(decoded_addr_decoded_88, 0, 0) node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0) node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0) node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0) node decoded_addr_79_2 = bits(decoded_addr_decoded_92, 0, 0) node decoded_addr_96_2 = bits(decoded_addr_decoded_93, 0, 0) node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0) node decoded_addr_101_2 = bits(decoded_addr_decoded_95, 0, 0) node decoded_addr_119_2 = bits(decoded_addr_decoded_96, 0, 0) node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0) node decoded_addr_139_2 = bits(decoded_addr_decoded_98, 0, 0) node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0) node decoded_addr_134_2 = bits(decoded_addr_decoded_100, 0, 0) node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0) node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0) node decoded_addr_86_2 = bits(decoded_addr_decoded_103, 0, 0) node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0) node decoded_addr_106_2 = bits(decoded_addr_decoded_105, 0, 0) node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0) node decoded_addr_87_2 = bits(decoded_addr_decoded_107, 0, 0) node decoded_addr_142_2 = bits(decoded_addr_decoded_108, 0, 0) node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0) node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0) node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0) node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0) node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0) node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0) node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0) node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0) node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0) node decoded_addr_145_2 = bits(decoded_addr_decoded_118, 0, 0) node decoded_addr_93_2 = bits(decoded_addr_decoded_119, 0, 0) node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0) node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0) node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0) node decoded_addr_137_2 = bits(decoded_addr_decoded_123, 0, 0) node decoded_addr_123_2 = bits(decoded_addr_decoded_124, 0, 0) node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0) node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0) node decoded_addr_141_2 = bits(decoded_addr_decoded_127, 0, 0) node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0) node decoded_addr_104_2 = bits(decoded_addr_decoded_129, 0, 0) node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0) node decoded_addr_125_2 = bits(decoded_addr_decoded_131, 0, 0) node decoded_addr_85_2 = bits(decoded_addr_decoded_132, 0, 0) node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0) node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0) node decoded_addr_135_2 = bits(decoded_addr_decoded_135, 0, 0) node decoded_addr_115_2 = bits(decoded_addr_decoded_136, 0, 0) node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0) node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0) node decoded_addr_110_2 = bits(decoded_addr_decoded_139, 0, 0) node decoded_addr_140_2 = bits(decoded_addr_decoded_140, 0, 0) node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0) node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0) node decoded_addr_80_2 = bits(decoded_addr_decoded_143, 0, 0) node decoded_addr_98_2 = bits(decoded_addr_decoded_144, 0, 0) node decoded_addr_18_2 = bits(decoded_addr_decoded_145, 0, 0) node decoded_addr_3_2 = bits(decoded_addr_decoded_146, 0, 0) node decoded_addr_38_2 = bits(decoded_addr_decoded_147, 0, 0) node decoded_addr_127_2 = bits(decoded_addr_decoded_148, 0, 0) node decoded_addr_95_2 = bits(decoded_addr_decoded_149, 0, 0) node _wdata_T = bits(io.rw.cmd, 1, 1) node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) node _wdata_T_3 = bits(io.rw.cmd, 1, 0) node _wdata_T_4 = andr(_wdata_T_3) node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) node _wdata_T_6 = not(_wdata_T_5) node wdata = and(_wdata_T_2, _wdata_T_6) node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) node _insn_T = shl(io.rw.addr, 20) node insn = or(UInt<7>(0h73), _insn_T) wire decoded_plaInput : UInt<32> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, insn node _T_53 = bits(decoded, 8, 8) node _T_54 = bits(decoded, 7, 7) node _T_55 = bits(decoded, 6, 6) node _T_56 = bits(decoded, 5, 5) node _T_57 = bits(decoded, 4, 4) node _T_58 = bits(decoded, 3, 3) node _T_59 = bits(decoded, 2, 2) node _T_60 = bits(decoded, 1, 1) node _T_61 = bits(decoded, 0, 0) node _T_62 = bits(_T_53, 0, 0) node insn_call = and(system_insn, _T_62) node _T_63 = bits(_T_54, 0, 0) node insn_break = and(system_insn, _T_63) node _T_64 = bits(_T_55, 0, 0) node insn_ret = and(system_insn, _T_64) node _T_65 = bits(_T_56, 0, 0) node insn_cease = and(system_insn, _T_65) node _T_66 = bits(_T_57, 0, 0) node insn_wfi = and(system_insn, _T_66) node _T_67 = bits(_T_58, 0, 0) node _T_68 = and(system_insn, _T_67) node _T_69 = bits(_T_59, 0, 0) node _T_70 = and(system_insn, _T_69) node _T_71 = bits(_T_60, 0, 0) node _T_72 = and(system_insn, _T_71) node _T_73 = bits(_T_61, 0, 0) node _T_74 = and(system_insn, _T_73) node addr = bits(io.decode[0].inst, 31, 20) wire decoded_plaInput_1 : UInt<32> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_1 : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, io.decode[0].inst node _T_75 = bits(decoded_1, 8, 8) node _T_76 = bits(decoded_1, 7, 7) node _T_77 = bits(decoded_1, 6, 6) node _T_78 = bits(decoded_1, 5, 5) node _T_79 = bits(decoded_1, 4, 4) node _T_80 = bits(decoded_1, 3, 3) node _T_81 = bits(decoded_1, 2, 2) node _T_82 = bits(decoded_1, 1, 1) node _T_83 = bits(decoded_1, 0, 0) node _T_84 = bits(_T_75, 0, 0) node is_break = bits(_T_76, 0, 0) node is_ret = bits(_T_77, 0, 0) node _T_85 = bits(_T_78, 0, 0) node is_wfi = bits(_T_79, 0, 0) node is_sfence = bits(_T_80, 0, 0) node is_hfence_vvma = bits(_T_81, 0, 0) node is_hfence_gvma = bits(_T_82, 0, 0) node is_hlsv = bits(_T_83, 0, 0) node _is_counter_T = geq(addr, UInt<12>(0hc00)) node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) node is_counter = or(_is_counter_T_2, _is_counter_T_5) node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T) node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T) node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T) node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) node counter_addr = bits(addr, 4, 0) node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21) node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5) connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6 wire io_decode_0_fp_csr_plaInput : UInt<12> node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) wire io_decode_0_fp_csr_plaOutput : UInt<1> node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10) node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11) node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3) node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1) node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo) node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T) node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2) node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0) connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs connect io_decode_0_fp_csr_plaInput, addr node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T wire io_decode_0_vector_csr_plaInput : UInt<12> node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) wire io_decode_0_vector_csr_plaOutput : UInt<1> connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_vector_csr_plaInput, addr node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 node _csr_addr_legal_T = bits(addr, 9, 8) node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) node _csr_addr_legal_T_6 = bits(addr, 9, 8) node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) node _csr_exists_T_17 = eq(addr, UInt<1>(0h1)) node _csr_exists_T_18 = eq(addr, UInt<2>(0h2)) node _csr_exists_T_19 = eq(addr, UInt<2>(0h3)) node _csr_exists_T_20 = eq(addr, UInt<10>(0h320)) node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00)) node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02)) node _csr_exists_T_23 = eq(addr, UInt<10>(0h323)) node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03)) node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03)) node _csr_exists_T_26 = eq(addr, UInt<10>(0h324)) node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04)) node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04)) node _csr_exists_T_29 = eq(addr, UInt<10>(0h325)) node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05)) node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05)) node _csr_exists_T_32 = eq(addr, UInt<10>(0h326)) node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06)) node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06)) node _csr_exists_T_35 = eq(addr, UInt<10>(0h327)) node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07)) node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07)) node _csr_exists_T_38 = eq(addr, UInt<10>(0h328)) node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08)) node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08)) node _csr_exists_T_41 = eq(addr, UInt<10>(0h329)) node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09)) node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09)) node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a)) node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a)) node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a)) node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b)) node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b)) node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b)) node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c)) node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c)) node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c)) node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d)) node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d)) node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d)) node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e)) node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e)) node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e)) node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f)) node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f)) node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f)) node _csr_exists_T_62 = eq(addr, UInt<10>(0h330)) node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10)) node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10)) node _csr_exists_T_65 = eq(addr, UInt<10>(0h331)) node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11)) node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11)) node _csr_exists_T_68 = eq(addr, UInt<10>(0h332)) node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12)) node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12)) node _csr_exists_T_71 = eq(addr, UInt<10>(0h333)) node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13)) node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13)) node _csr_exists_T_74 = eq(addr, UInt<10>(0h334)) node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14)) node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14)) node _csr_exists_T_77 = eq(addr, UInt<10>(0h335)) node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15)) node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15)) node _csr_exists_T_80 = eq(addr, UInt<10>(0h336)) node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16)) node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16)) node _csr_exists_T_83 = eq(addr, UInt<10>(0h337)) node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17)) node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17)) node _csr_exists_T_86 = eq(addr, UInt<10>(0h338)) node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18)) node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18)) node _csr_exists_T_89 = eq(addr, UInt<10>(0h339)) node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19)) node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19)) node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a)) node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a)) node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a)) node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b)) node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b)) node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b)) node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c)) node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c)) node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c)) node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d)) node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d)) node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d)) node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e)) node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e)) node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e)) node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f)) node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f)) node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f)) node _csr_exists_T_110 = eq(addr, UInt<10>(0h306)) node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00)) node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02)) node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a)) node _csr_exists_T_114 = eq(addr, UInt<9>(0h100)) node _csr_exists_T_115 = eq(addr, UInt<9>(0h144)) node _csr_exists_T_116 = eq(addr, UInt<9>(0h104)) node _csr_exists_T_117 = eq(addr, UInt<9>(0h140)) node _csr_exists_T_118 = eq(addr, UInt<9>(0h142)) node _csr_exists_T_119 = eq(addr, UInt<9>(0h143)) node _csr_exists_T_120 = eq(addr, UInt<9>(0h180)) node _csr_exists_T_121 = eq(addr, UInt<9>(0h141)) node _csr_exists_T_122 = eq(addr, UInt<9>(0h105)) node _csr_exists_T_123 = eq(addr, UInt<9>(0h106)) node _csr_exists_T_124 = eq(addr, UInt<10>(0h303)) node _csr_exists_T_125 = eq(addr, UInt<10>(0h302)) node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a)) node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0)) node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2)) node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0)) node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1)) node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2)) node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3)) node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4)) node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5)) node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6)) node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7)) node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8)) node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9)) node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba)) node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb)) node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc)) node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd)) node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be)) node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf)) node _csr_exists_T_145 = eq(addr, UInt<11>(0h7c1)) node _csr_exists_T_146 = eq(addr, UInt<12>(0hf12)) node _csr_exists_T_147 = eq(addr, UInt<12>(0hf11)) node _csr_exists_T_148 = eq(addr, UInt<12>(0hf13)) node _csr_exists_T_149 = eq(addr, UInt<12>(0hf15)) node _csr_exists_T_150 = or(_csr_exists_T, _csr_exists_T_1) node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_2) node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_3) node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_4) node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_5) node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_6) node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_7) node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_8) node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_9) node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_10) node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_11) node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_12) node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_13) node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_14) node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_15) node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_16) node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_17) node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_18) node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_19) node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_20) node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_21) node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_22) node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_23) node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_24) node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_25) node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_26) node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_27) node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_28) node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_29) node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_30) node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_31) node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_32) node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_33) node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_34) node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_35) node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_36) node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_37) node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_38) node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_39) node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_40) node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_41) node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_42) node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_43) node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_44) node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_45) node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_46) node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_47) node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_48) node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_49) node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_50) node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_51) node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_52) node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_53) node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_54) node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_55) node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_56) node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_57) node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_58) node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_59) node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_60) node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_61) node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_62) node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_63) node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_64) node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_65) node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_66) node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_67) node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_68) node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_69) node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_70) node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_71) node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_72) node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_73) node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_74) node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_75) node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_76) node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_77) node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_78) node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_79) node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_80) node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_81) node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_82) node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_83) node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_84) node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_85) node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_86) node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_87) node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_88) node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_89) node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_90) node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_91) node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_92) node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_93) node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_94) node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_95) node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_96) node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_97) node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_98) node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_99) node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_100) node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_101) node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_102) node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_103) node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_104) node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_105) node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_106) node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_107) node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_108) node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_109) node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_110) node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_111) node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_112) node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_113) node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_114) node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_115) node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_116) node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_117) node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_118) node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_119) node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_120) node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_121) node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_122) node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_123) node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_124) node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_125) node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_126) node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_127) node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_128) node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_129) node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_130) node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_131) node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_132) node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_133) node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_134) node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_135) node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_136) node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_137) node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_138) node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_139) node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_140) node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_141) node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_142) node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_143) node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_144) node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_145) node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_146) node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_147) node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_148) node csr_exists = or(_csr_exists_T_297, _csr_exists_T_149) node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) wire io_decode_0_read_illegal_plaInput : UInt<12> node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) wire io_decode_0_read_illegal_plaOutput : UInt<1> node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs connect io_decode_0_read_illegal_plaInput, addr node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) wire io_decode_0_read_illegal_plaInput_1 : UInt<12> node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) connect io_decode_0_read_illegal_plaInput_1, addr node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 node _io_decode_0_write_illegal_T = bits(addr, 11, 10) node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 node _cause_T = bits(reg_mstatus.prv, 0, 0) node _cause_T_1 = and(_cause_T, reg_mstatus.v) node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) node _cause_T_4 = tail(_cause_T_3, 1) node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) node cause = mux(insn_call, _cause_T_4, _cause_T_5) node cause_lsbs = bits(cause, 7, 0) node cause_deleg_lsbs = bits(cause, 5, 0) node _causeIsDebugInt_T = bits(cause, 63, 63) node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) node _causeIsDebugTrigger_T = bits(cause, 63, 63) node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) node _causeIsDebugBreak_T = bits(cause, 63, 63) node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T) node _delegate_T_2 = bits(cause, 63, 63) node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) node _delegate_T_4 = bits(_delegate_T_3, 0, 0) node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) node _delegate_T_6 = bits(_delegate_T_5, 0, 0) node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) node delegate = and(_delegate_T_1, _delegate_T_7) node _delegateVS_T = and(reg_mstatus.v, delegate) node _delegateVS_T_1 = bits(cause, 63, 63) node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) node delegateVS = and(_delegateVS_T, _delegateVS_T_6) node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0) node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8) node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63) node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6) node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) node _notDebugTVec_T = shr(notDebugTVec_base, 2) node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) node _causeIsRnmiInt_T = bits(cause, 63, 63) node _causeIsRnmiInt_T_1 = bits(cause, 62, 62) node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) node _causeIsRnmiBEU_T = bits(cause, 63, 63) node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62) node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) node nmiTVec = shl(_nmiTVec_T_1, 1) node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) node tvec = mux(trapToDebug, debugTVec, _tvec_T) connect io.evec, tvec connect io.ptbr, reg_satp connect io.hgatp, reg_hgatp connect io.vsatp, reg_vsatp node _io_eret_T = or(insn_call, insn_break) node _io_eret_T_1 = or(_io_eret_T, insn_ret) connect io.eret, _io_eret_T_1 node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) connect io.singleStep, _io_singleStep_T_1 connect io.status, reg_mstatus node _io_status_sd_T = andr(io.status.fs) node _io_status_sd_T_1 = andr(io.status.xs) node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) node _io_status_sd_T_3 = andr(io.status.vs) node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) connect io.status.sd, _io_status_sd_T_4 connect io.status.debug, reg_debug connect io.status.isa, reg_misa connect io.status.uxl, UInt<2>(0h2) connect io.status.sxl, UInt<2>(0h2) node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) connect io.status.dprv, _io_status_dprv_T_2 node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) connect io.status.dv, _io_status_dv_T_3 node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd) connect io.status.sd_rv32, _io_status_sd_rv32_T connect io.status.mpv, reg_mstatus.mpv connect io.status.gva, reg_mstatus.gva connect io.hstatus, reg_hstatus connect io.hstatus.vsxl, UInt<2>(0h2) connect io.gstatus, reg_vsstatus node _io_gstatus_sd_T = andr(io.gstatus.fs) node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) connect io.gstatus.sd, _io_gstatus_sd_T_4 connect io.gstatus.uxl, UInt<2>(0h2) node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd) connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T node _exception_T = or(insn_call, insn_break) node exception = or(_exception_T, io.exception) node _T_86 = add(insn_ret, insn_call) node _T_87 = bits(_T_86, 1, 0) node _T_88 = add(insn_break, io.exception) node _T_89 = bits(_T_88, 1, 0) node _T_90 = add(_T_87, _T_89) node _T_91 = bits(_T_90, 2, 0) node _T_92 = leq(_T_91, UInt<1>(0h1)) node _T_93 = asUInt(reset) node _T_94 = eq(_T_93, UInt<1>(0h0)) when _T_94 : node _T_95 = eq(_T_92, UInt<1>(0h0)) when _T_95 : printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf assert(clock, _T_92, UInt<1>(0h1), "") : assert node _T_96 = eq(io.singleStep, UInt<1>(0h0)) node _T_97 = and(insn_wfi, _T_96) node _T_98 = eq(reg_debug, UInt<1>(0h0)) node _T_99 = and(_T_97, _T_98) when _T_99 : connect reg_wfi, UInt<1>(0h1) node _T_100 = orr(pending_interrupts) node _T_101 = or(_T_100, io.interrupts.debug) node _T_102 = or(_T_101, exception) when _T_102 : connect reg_wfi, UInt<1>(0h0) node _T_103 = bits(io.retire, 0, 0) node _T_104 = or(_T_103, exception) when _T_104 : connect reg_singleStepped, UInt<1>(0h1) node _T_105 = eq(io.singleStep, UInt<1>(0h0)) when _T_105 : connect reg_singleStepped, UInt<1>(0h0) node _T_106 = eq(io.singleStep, UInt<1>(0h0)) node _T_107 = leq(io.retire, UInt<1>(0h1)) node _T_108 = or(_T_106, _T_107) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(reg_singleStepped, UInt<1>(0h0)) node _T_113 = eq(io.retire, UInt<1>(0h0)) node _T_114 = or(_T_112, _T_113) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2 assert(clock, _T_114, UInt<1>(0h1), "") : assert_2 node _epc_T = not(io.pc) node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) node epc = not(_epc_T_1) node tval = mux(insn_break, epc, io.tval) when exception : when trapToDebug : node _T_118 = eq(reg_debug, UInt<1>(0h0)) when _T_118 : connect reg_mstatus.v, UInt<1>(0h0) connect reg_debug, UInt<1>(0h1) connect reg_dpc, epc node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) connect reg_dcsr.cause, _reg_dcsr_cause_T_2 connect reg_dcsr.prv, reg_mstatus.prv connect reg_dcsr.v, reg_mstatus.v connect new_prv, UInt<2>(0h3) else : when trapToNmiInt : when reg_rnmie : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mnstatus.mpv, reg_mstatus.v connect reg_rnmie, UInt<1>(0h0) connect reg_mnepc, epc node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T) connect reg_mncause, _reg_mncause_T_1 connect reg_mnstatus.mpp, reg_mstatus.prv connect new_prv, UInt<2>(0h3) else : node _T_119 = and(delegateVS, reg_rnmie) when _T_119 : connect reg_mstatus.v, UInt<1>(0h1) connect reg_vsstatus.spp, reg_mstatus.prv connect reg_vsepc, epc node _reg_vscause_T = bits(cause, 63, 63) node _reg_vscause_T_1 = bits(cause, 63, 2) node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) connect reg_vscause, _reg_vscause_T_3 connect reg_vstval, tval connect reg_vsstatus.spie, reg_vsstatus.sie connect reg_vsstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : node _T_120 = and(delegate, reg_rnmie) when _T_120 : connect reg_mstatus.v, UInt<1>(0h0) node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 connect reg_hstatus.gva, io.gva connect reg_hstatus.spv, reg_mstatus.v connect reg_sepc, epc connect reg_scause, cause connect reg_stval, tval connect reg_htval, io.htval connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.spie, reg_mstatus.sie connect reg_mstatus.spp, reg_mstatus.prv connect reg_mstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mstatus.mpv, reg_mstatus.v connect reg_mstatus.gva, io.gva connect reg_mepc, epc connect reg_mcause, cause connect reg_mtval, tval connect reg_mtval2, io.htval connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.mpie, reg_mstatus.mie connect reg_mstatus.mpp, reg_mstatus.prv connect reg_mstatus.mie, UInt<1>(0h0) connect new_prv, UInt<2>(0h3) node _en_T = and(supported_interrupts, UInt<1>(0h1)) node _en_T_1 = neq(_en_T, UInt<1>(0h0)) node _en_T_2 = and(exception, _en_T_1) node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0)) node _en_T_4 = tail(_en_T_3, 1) node _en_T_5 = eq(cause, _en_T_4) node en = and(_en_T_2, _en_T_5) node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) node delegable = neq(_delegable_T, UInt<1>(0h0)) node _T_121 = eq(delegate, UInt<1>(0h0)) node _T_122 = and(en, _T_121) node _T_123 = and(en, delegable) node _T_124 = and(_T_123, delegate) node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) node _en_T_8 = and(exception, _en_T_7) node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1)) node _en_T_10 = tail(_en_T_9, 1) node _en_T_11 = eq(cause, _en_T_10) node en_1 = and(_en_T_8, _en_T_11) node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) node _T_125 = eq(delegate, UInt<1>(0h0)) node _T_126 = and(en_1, _T_125) node _T_127 = and(en_1, delegable_1) node _T_128 = and(_T_127, delegate) node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) node _en_T_14 = and(exception, _en_T_13) node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2)) node _en_T_16 = tail(_en_T_15, 1) node _en_T_17 = eq(cause, _en_T_16) node en_2 = and(_en_T_14, _en_T_17) node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) node _T_129 = eq(delegate, UInt<1>(0h0)) node _T_130 = and(en_2, _T_129) node _T_131 = and(en_2, delegable_2) node _T_132 = and(_T_131, delegate) node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) node _en_T_20 = and(exception, _en_T_19) node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3)) node _en_T_22 = tail(_en_T_21, 1) node _en_T_23 = eq(cause, _en_T_22) node en_3 = and(_en_T_20, _en_T_23) node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) node _T_133 = eq(delegate, UInt<1>(0h0)) node _T_134 = and(en_3, _T_133) node _T_135 = and(en_3, delegable_3) node _T_136 = and(_T_135, delegate) node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) node _en_T_26 = and(exception, _en_T_25) node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4)) node _en_T_28 = tail(_en_T_27, 1) node _en_T_29 = eq(cause, _en_T_28) node en_4 = and(_en_T_26, _en_T_29) node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) node _T_137 = eq(delegate, UInt<1>(0h0)) node _T_138 = and(en_4, _T_137) node _T_139 = and(en_4, delegable_4) node _T_140 = and(_T_139, delegate) node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) node _en_T_32 = and(exception, _en_T_31) node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5)) node _en_T_34 = tail(_en_T_33, 1) node _en_T_35 = eq(cause, _en_T_34) node en_5 = and(_en_T_32, _en_T_35) node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) node _T_141 = eq(delegate, UInt<1>(0h0)) node _T_142 = and(en_5, _T_141) node _T_143 = and(en_5, delegable_5) node _T_144 = and(_T_143, delegate) node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) node _en_T_38 = and(exception, _en_T_37) node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6)) node _en_T_40 = tail(_en_T_39, 1) node _en_T_41 = eq(cause, _en_T_40) node en_6 = and(_en_T_38, _en_T_41) node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) node _T_145 = eq(delegate, UInt<1>(0h0)) node _T_146 = and(en_6, _T_145) node _T_147 = and(en_6, delegable_6) node _T_148 = and(_T_147, delegate) node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) node _en_T_44 = and(exception, _en_T_43) node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7)) node _en_T_46 = tail(_en_T_45, 1) node _en_T_47 = eq(cause, _en_T_46) node en_7 = and(_en_T_44, _en_T_47) node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) node _T_149 = eq(delegate, UInt<1>(0h0)) node _T_150 = and(en_7, _T_149) node _T_151 = and(en_7, delegable_7) node _T_152 = and(_T_151, delegate) node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) node _en_T_50 = and(exception, _en_T_49) node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8)) node _en_T_52 = tail(_en_T_51, 1) node _en_T_53 = eq(cause, _en_T_52) node en_8 = and(_en_T_50, _en_T_53) node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) node _T_153 = eq(delegate, UInt<1>(0h0)) node _T_154 = and(en_8, _T_153) node _T_155 = and(en_8, delegable_8) node _T_156 = and(_T_155, delegate) node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) node _en_T_56 = and(exception, _en_T_55) node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9)) node _en_T_58 = tail(_en_T_57, 1) node _en_T_59 = eq(cause, _en_T_58) node en_9 = and(_en_T_56, _en_T_59) node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) node _T_157 = eq(delegate, UInt<1>(0h0)) node _T_158 = and(en_9, _T_157) node _T_159 = and(en_9, delegable_9) node _T_160 = and(_T_159, delegate) node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) node _en_T_62 = and(exception, _en_T_61) node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha)) node _en_T_64 = tail(_en_T_63, 1) node _en_T_65 = eq(cause, _en_T_64) node en_10 = and(_en_T_62, _en_T_65) node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) node _T_161 = eq(delegate, UInt<1>(0h0)) node _T_162 = and(en_10, _T_161) node _T_163 = and(en_10, delegable_10) node _T_164 = and(_T_163, delegate) node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) node _en_T_68 = and(exception, _en_T_67) node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb)) node _en_T_70 = tail(_en_T_69, 1) node _en_T_71 = eq(cause, _en_T_70) node en_11 = and(_en_T_68, _en_T_71) node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) node _T_165 = eq(delegate, UInt<1>(0h0)) node _T_166 = and(en_11, _T_165) node _T_167 = and(en_11, delegable_11) node _T_168 = and(_T_167, delegate) node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) node _en_T_74 = and(exception, _en_T_73) node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc)) node _en_T_76 = tail(_en_T_75, 1) node _en_T_77 = eq(cause, _en_T_76) node en_12 = and(_en_T_74, _en_T_77) node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) node _T_169 = eq(delegate, UInt<1>(0h0)) node _T_170 = and(en_12, _T_169) node _T_171 = and(en_12, delegable_12) node _T_172 = and(_T_171, delegate) node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) node _en_T_80 = and(exception, _en_T_79) node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd)) node _en_T_82 = tail(_en_T_81, 1) node _en_T_83 = eq(cause, _en_T_82) node en_13 = and(_en_T_80, _en_T_83) node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) node _T_173 = eq(delegate, UInt<1>(0h0)) node _T_174 = and(en_13, _T_173) node _T_175 = and(en_13, delegable_13) node _T_176 = and(_T_175, delegate) node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) node _en_T_86 = and(exception, _en_T_85) node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he)) node _en_T_88 = tail(_en_T_87, 1) node _en_T_89 = eq(cause, _en_T_88) node en_14 = and(_en_T_86, _en_T_89) node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) node _T_177 = eq(delegate, UInt<1>(0h0)) node _T_178 = and(en_14, _T_177) node _T_179 = and(en_14, delegable_14) node _T_180 = and(_T_179, delegate) node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) node _en_T_92 = and(exception, _en_T_91) node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf)) node _en_T_94 = tail(_en_T_93, 1) node _en_T_95 = eq(cause, _en_T_94) node en_15 = and(_en_T_92, _en_T_95) node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) node _T_181 = eq(delegate, UInt<1>(0h0)) node _T_182 = and(en_15, _T_181) node _T_183 = and(en_15, delegable_15) node _T_184 = and(_T_183, delegate) node _en_T_96 = eq(cause, UInt<1>(0h0)) node en_16 = and(exception, _en_T_96) node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) node _T_185 = eq(delegate, UInt<1>(0h0)) node _T_186 = and(en_16, _T_185) node _T_187 = and(en_16, delegable_16) node _T_188 = and(_T_187, delegate) node _en_T_97 = eq(cause, UInt<1>(0h1)) node en_17 = and(exception, _en_T_97) node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) node _T_189 = eq(delegate, UInt<1>(0h0)) node _T_190 = and(en_17, _T_189) node _T_191 = and(en_17, delegable_17) node _T_192 = and(_T_191, delegate) node _en_T_98 = eq(cause, UInt<2>(0h2)) node en_18 = and(exception, _en_T_98) node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) node _T_193 = eq(delegate, UInt<1>(0h0)) node _T_194 = and(en_18, _T_193) node _T_195 = and(en_18, delegable_18) node _T_196 = and(_T_195, delegate) node _en_T_99 = eq(cause, UInt<2>(0h3)) node en_19 = and(exception, _en_T_99) node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) node _T_197 = eq(delegate, UInt<1>(0h0)) node _T_198 = and(en_19, _T_197) node _T_199 = and(en_19, delegable_19) node _T_200 = and(_T_199, delegate) node _en_T_100 = eq(cause, UInt<3>(0h4)) node en_20 = and(exception, _en_T_100) node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) node _T_201 = eq(delegate, UInt<1>(0h0)) node _T_202 = and(en_20, _T_201) node _T_203 = and(en_20, delegable_20) node _T_204 = and(_T_203, delegate) node _en_T_101 = eq(cause, UInt<3>(0h5)) node en_21 = and(exception, _en_T_101) node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) node _T_205 = eq(delegate, UInt<1>(0h0)) node _T_206 = and(en_21, _T_205) node _T_207 = and(en_21, delegable_21) node _T_208 = and(_T_207, delegate) node _en_T_102 = eq(cause, UInt<3>(0h6)) node en_22 = and(exception, _en_T_102) node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) node _T_209 = eq(delegate, UInt<1>(0h0)) node _T_210 = and(en_22, _T_209) node _T_211 = and(en_22, delegable_22) node _T_212 = and(_T_211, delegate) node _en_T_103 = eq(cause, UInt<3>(0h7)) node en_23 = and(exception, _en_T_103) node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) node _T_213 = eq(delegate, UInt<1>(0h0)) node _T_214 = and(en_23, _T_213) node _T_215 = and(en_23, delegable_23) node _T_216 = and(_T_215, delegate) node _en_T_104 = eq(cause, UInt<4>(0h8)) node en_24 = and(exception, _en_T_104) node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<9>(0h100)) node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) node _T_217 = eq(delegate, UInt<1>(0h0)) node _T_218 = and(en_24, _T_217) node _T_219 = and(en_24, delegable_24) node _T_220 = and(_T_219, delegate) node _en_T_105 = eq(cause, UInt<4>(0h9)) node en_25 = and(exception, _en_T_105) node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<10>(0h200)) node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0)) node _T_221 = eq(delegate, UInt<1>(0h0)) node _T_222 = and(en_25, _T_221) node _T_223 = and(en_25, delegable_25) node _T_224 = and(_T_223, delegate) node _en_T_106 = eq(cause, UInt<4>(0hb)) node en_26 = and(exception, _en_T_106) node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<12>(0h800)) node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0)) node _T_225 = eq(delegate, UInt<1>(0h0)) node _T_226 = and(en_26, _T_225) node _T_227 = and(en_26, delegable_26) node _T_228 = and(_T_227, delegate) node _en_T_107 = eq(cause, UInt<4>(0hc)) node en_27 = and(exception, _en_T_107) node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<13>(0h1000)) node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0)) node _T_229 = eq(delegate, UInt<1>(0h0)) node _T_230 = and(en_27, _T_229) node _T_231 = and(en_27, delegable_27) node _T_232 = and(_T_231, delegate) node _en_T_108 = eq(cause, UInt<4>(0hd)) node en_28 = and(exception, _en_T_108) node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<14>(0h2000)) node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0)) node _T_233 = eq(delegate, UInt<1>(0h0)) node _T_234 = and(en_28, _T_233) node _T_235 = and(en_28, delegable_28) node _T_236 = and(_T_235, delegate) node _en_T_109 = eq(cause, UInt<4>(0hf)) node en_29 = and(exception, _en_T_109) node _delegable_T_29 = and(UInt<16>(0hb15d), UInt<16>(0h8000)) node delegable_29 = neq(_delegable_T_29, UInt<1>(0h0)) node _T_237 = eq(delegate, UInt<1>(0h0)) node _T_238 = and(en_29, _T_237) node _T_239 = and(en_29, delegable_29) node _T_240 = and(_T_239, delegate) when insn_ret : wire ret_prv : UInt invalidate ret_prv node _T_241 = bits(io.rw.addr, 9, 9) node _T_242 = eq(_T_241, UInt<1>(0h0)) node _T_243 = and(UInt<1>(0h1), _T_242) when _T_243 : node _T_244 = eq(reg_mstatus.v, UInt<1>(0h0)) when _T_244 : connect reg_mstatus.sie, reg_mstatus.spie connect reg_mstatus.spie, UInt<1>(0h1) connect reg_mstatus.spp, UInt<1>(0h0) connect ret_prv, reg_mstatus.spp node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) connect reg_mstatus.v, _reg_mstatus_v_T node _io_evec_T = not(reg_sepc) node _io_evec_T_1 = bits(reg_misa, 2, 2) node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) node _io_evec_T_4 = not(_io_evec_T_3) connect io.evec, _io_evec_T_4 connect reg_hstatus.spv, UInt<1>(0h0) else : connect reg_vsstatus.sie, reg_vsstatus.spie connect reg_vsstatus.spie, UInt<1>(0h1) connect reg_vsstatus.spp, UInt<1>(0h0) connect ret_prv, reg_vsstatus.spp connect reg_mstatus.v, UInt<1>(0h0) node _io_evec_T_5 = not(reg_vsepc) node _io_evec_T_6 = bits(reg_misa, 2, 2) node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) node _io_evec_T_9 = not(_io_evec_T_8) connect io.evec, _io_evec_T_9 else : node _T_245 = bits(io.rw.addr, 10, 10) node _T_246 = and(UInt<1>(0h1), _T_245) node _T_247 = bits(io.rw.addr, 7, 7) node _T_248 = and(_T_246, _T_247) when _T_248 : connect ret_prv, reg_dcsr.prv node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) connect reg_mstatus.v, _reg_mstatus_v_T_3 connect reg_debug, UInt<1>(0h0) node _io_evec_T_10 = not(reg_dpc) node _io_evec_T_11 = bits(reg_misa, 2, 2) node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) node _io_evec_T_14 = not(_io_evec_T_13) connect io.evec, _io_evec_T_14 else : node _T_249 = bits(io.rw.addr, 10, 10) node _T_250 = and(UInt<1>(0h0), _T_249) node _T_251 = bits(io.rw.addr, 7, 7) node _T_252 = eq(_T_251, UInt<1>(0h0)) node _T_253 = and(_T_250, _T_252) when _T_253 : connect ret_prv, reg_mnstatus.mpp node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) connect reg_mstatus.v, _reg_mstatus_v_T_6 connect reg_rnmie, UInt<1>(0h1) node _io_evec_T_15 = not(reg_mnepc) node _io_evec_T_16 = bits(reg_misa, 2, 2) node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) node _io_evec_T_19 = not(_io_evec_T_18) connect io.evec, _io_evec_T_19 else : connect reg_mstatus.mie, reg_mstatus.mpie connect reg_mstatus.mpie, UInt<1>(0h1) node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2)) node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0)) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1 connect reg_mstatus.mpv, UInt<1>(0h0) connect ret_prv, reg_mstatus.mpp node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) connect reg_mstatus.v, _reg_mstatus_v_T_9 node _io_evec_T_20 = not(reg_mepc) node _io_evec_T_21 = bits(reg_misa, 2, 2) node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) node _io_evec_T_24 = not(_io_evec_T_23) connect io.evec, _io_evec_T_24 connect new_prv, ret_prv node _T_254 = leq(ret_prv, UInt<1>(0h1)) node _T_255 = and(UInt<1>(0h1), _T_254) when _T_255 : connect reg_mstatus.mprv, UInt<1>(0h0) connect io.time, value_1 node _io_csr_stall_T = or(reg_wfi, io.status.cease) connect io.csr_stall, _io_csr_stall_T regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) when insn_cease : connect io_status_cease_r, UInt<1>(0h1) connect io.status.cease, io_status_cease_r connect io.status.wfi, reg_wfi connect io.customCSRs[0].wen, UInt<1>(0h0) connect io.customCSRs[0].wdata, wdata connect io.customCSRs[0].value, reg_custom_0 connect io.customCSRs[1].wen, UInt<1>(0h0) connect io.customCSRs[1].wdata, wdata connect io.customCSRs[1].value, reg_custom_1 connect io.customCSRs[2].wen, UInt<1>(0h0) connect io.customCSRs[2].wdata, wdata connect io.customCSRs[2].value, reg_custom_2 connect io.customCSRs[3].wen, UInt<1>(0h0) connect io.customCSRs[3].wdata, wdata connect io.customCSRs[3].value, reg_custom_3 node _io_rw_rdata_T = mux(decoded_addr_97_2, reg_tselect, UInt<1>(0h0)) node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0)) node _io_rw_rdata_T_3 = mux(decoded_addr_118_2, read_mapping_3_2, UInt<1>(0h0)) node _io_rw_rdata_T_4 = mux(decoded_addr_94_2, reg_misa, UInt<1>(0h0)) node _io_rw_rdata_T_5 = mux(decoded_addr_100_2, read_mstatus, UInt<1>(0h0)) node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0)) node _io_rw_rdata_T_7 = mux(decoded_addr_108_2, read_mip, UInt<1>(0h0)) node _io_rw_rdata_T_8 = mux(decoded_addr_76_2, reg_mie, UInt<1>(0h0)) node _io_rw_rdata_T_9 = mux(decoded_addr_129_2, reg_mscratch, UInt<1>(0h0)) node _io_rw_rdata_T_10 = mux(decoded_addr_132_2, read_mapping_10_2, UInt<1>(0h0)) node _io_rw_rdata_T_11 = mux(decoded_addr_136_2, read_mapping_11_2, UInt<1>(0h0)) node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0)) node _io_rw_rdata_T_13 = mux(decoded_addr_131_2, io.hartid, UInt<1>(0h0)) node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0)) node _io_rw_rdata_T_15 = mux(decoded_addr_89_2, debug_csrs_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0)) node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0)) node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0)) node _io_rw_rdata_T_19 = mux(decoded_addr_99_2, read_fcsr, UInt<1>(0h0)) node _io_rw_rdata_T_20 = mux(decoded_addr_130_2, reg_mcountinhibit, UInt<1>(0h0)) node _io_rw_rdata_T_21 = mux(decoded_addr_103_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_22 = mux(decoded_addr_121_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_23 = mux(decoded_addr_146_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_26 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_28 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_30 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_31 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_35 = mux(decoded_addr_138_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_36 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_38 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_39 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_40 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_43 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_46 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_47 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_48 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_50 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_51 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_53 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_55 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_58 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_60 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_62 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_63 = mux(decoded_addr_148_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_68 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_69 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_72 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_73 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_76 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_80 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_81 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_83 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_84 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_88 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_92 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_93 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_95 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_96 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_98 = mux(decoded_addr_139_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_100 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_103 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_105 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_107 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_108 = mux(decoded_addr_142_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0)) node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_19, UInt<1>(0h0)) node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_21, UInt<1>(0h0)) node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0)) node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0)) node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0)) node _io_rw_rdata_T_118 = mux(decoded_addr_145_2, reg_scause, UInt<1>(0h0)) node _io_rw_rdata_T_119 = mux(decoded_addr_93_2, _T_24, UInt<1>(0h0)) node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_25, UInt<1>(0h0)) node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_33, UInt<1>(0h0)) node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0)) node _io_rw_rdata_T_123 = mux(decoded_addr_137_2, read_scounteren, UInt<1>(0h0)) node _io_rw_rdata_T_124 = mux(decoded_addr_123_2, read_mideleg, UInt<1>(0h0)) node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0)) node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_34, UInt<1>(0h0)) node _io_rw_rdata_T_127 = mux(decoded_addr_141_2, _T_43, UInt<1>(0h0)) node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_52, UInt<1>(0h0)) node _io_rw_rdata_T_129 = mux(decoded_addr_104_2, reg_pmp[0].addr, UInt<1>(0h0)) node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0)) node _io_rw_rdata_T_131 = mux(decoded_addr_125_2, reg_pmp[2].addr, UInt<1>(0h0)) node _io_rw_rdata_T_132 = mux(decoded_addr_85_2, reg_pmp[3].addr, UInt<1>(0h0)) node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0)) node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0)) node _io_rw_rdata_T_135 = mux(decoded_addr_135_2, reg_pmp[6].addr, UInt<1>(0h0)) node _io_rw_rdata_T_136 = mux(decoded_addr_115_2, reg_pmp[7].addr, UInt<1>(0h0)) node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_139 = mux(decoded_addr_110_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_140 = mux(decoded_addr_140_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_143 = mux(decoded_addr_80_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_144 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_145 = mux(decoded_addr_18_2, reg_custom_0, UInt<1>(0h0)) node _io_rw_rdata_T_146 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) node _io_rw_rdata_T_147 = mux(decoded_addr_38_2, reg_custom_2, UInt<1>(0h0)) node _io_rw_rdata_T_148 = mux(decoded_addr_127_2, reg_custom_3, UInt<1>(0h0)) node _io_rw_rdata_T_149 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_150 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_2) node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_3) node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_4) node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_5) node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_6) node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_7) node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_8) node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_9) node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_10) node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_11) node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_12) node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_13) node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_14) node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_15) node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_16) node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_17) node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_18) node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_19) node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_20) node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_21) node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_22) node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_23) node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_24) node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_25) node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_26) node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_27) node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_28) node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_29) node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_30) node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_31) node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_32) node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_33) node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_34) node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_35) node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_36) node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_37) node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_38) node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_39) node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_40) node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_41) node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_42) node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_43) node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_44) node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_45) node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_46) node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_47) node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_48) node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_49) node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_50) node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_51) node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_52) node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_53) node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_54) node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_55) node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_56) node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_57) node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_58) node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_59) node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_60) node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_61) node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_62) node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_63) node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_64) node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_65) node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_66) node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_67) node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_68) node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_69) node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_70) node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_71) node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_72) node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_73) node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_74) node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_75) node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_76) node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_77) node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_78) node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_79) node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_80) node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_81) node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_82) node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_83) node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_84) node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_85) node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_86) node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_87) node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_88) node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_89) node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_90) node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_91) node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_92) node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_93) node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_94) node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_95) node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_96) node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_97) node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_98) node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_99) node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_100) node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_101) node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_102) node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_103) node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_104) node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_105) node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_106) node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_107) node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_108) node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_109) node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_110) node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_111) node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_112) node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_113) node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_114) node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_115) node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_116) node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_117) node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_118) node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_119) node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_120) node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_121) node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_122) node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_123) node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_124) node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_125) node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_126) node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_127) node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_128) node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_129) node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_130) node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_131) node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_132) node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_133) node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_134) node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_135) node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_136) node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_137) node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_138) node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_139) node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_140) node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_141) node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_142) node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_143) node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_144) node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_145) node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_146) node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_147) node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_148) node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_149) wire _io_rw_rdata_WIRE : UInt connect _io_rw_rdata_WIRE, _io_rw_rdata_T_298 connect io.rw.rdata, _io_rw_rdata_WIRE node _T_256 = andr(UInt<2>(0h1)) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_259 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_260 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_261 = or(_T_258, _T_259) node _T_262 = or(_T_261, _T_260) node _T_263 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_264 = and(_T_262, _T_263) else : node _T_265 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_266 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_267 = and(_T_265, _T_266) node _T_268 = andr(UInt<2>(0h1)) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_271 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_272 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_273 = or(_T_270, _T_271) node _T_274 = or(_T_273, _T_272) node _T_275 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_276 = and(_T_274, _T_275) else : node _T_277 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_278 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_279 = and(_T_277, _T_278) node _T_280 = andr(UInt<2>(0h1)) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_283 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_284 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_285 = or(_T_282, _T_283) node _T_286 = or(_T_285, _T_284) node _T_287 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_288 = and(_T_286, _T_287) else : node _T_289 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_290 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_291 = and(_T_289, _T_290) node _T_292 = andr(UInt<2>(0h1)) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_295 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_296 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_297 = or(_T_294, _T_295) node _T_298 = or(_T_297, _T_296) node _T_299 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_300 = and(_T_298, _T_299) else : node _T_301 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_302 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_303 = and(_T_301, _T_302) node _T_304 = andr(UInt<2>(0h0)) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_307 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_308 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_309 = or(_T_306, _T_307) node _T_310 = or(_T_309, _T_308) node _T_311 = eq(io.rw.addr, UInt<10>(0h301)) node _T_312 = and(_T_310, _T_311) else : node _T_313 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_314 = eq(io.rw.addr, UInt<10>(0h301)) node _T_315 = and(_T_313, _T_314) node _T_316 = andr(UInt<2>(0h0)) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_319 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_320 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_321 = or(_T_318, _T_319) node _T_322 = or(_T_321, _T_320) node _T_323 = eq(io.rw.addr, UInt<10>(0h300)) node _T_324 = and(_T_322, _T_323) else : node _T_325 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_326 = eq(io.rw.addr, UInt<10>(0h300)) node _T_327 = and(_T_325, _T_326) node _T_328 = andr(UInt<2>(0h0)) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_331 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_332 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_333 = or(_T_330, _T_331) node _T_334 = or(_T_333, _T_332) node _T_335 = eq(io.rw.addr, UInt<10>(0h305)) node _T_336 = and(_T_334, _T_335) else : node _T_337 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_338 = eq(io.rw.addr, UInt<10>(0h305)) node _T_339 = and(_T_337, _T_338) node _T_340 = andr(UInt<2>(0h0)) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_343 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_344 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_345 = or(_T_342, _T_343) node _T_346 = or(_T_345, _T_344) node _T_347 = eq(io.rw.addr, UInt<10>(0h344)) node _T_348 = and(_T_346, _T_347) else : node _T_349 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_350 = eq(io.rw.addr, UInt<10>(0h344)) node _T_351 = and(_T_349, _T_350) node _T_352 = andr(UInt<2>(0h0)) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_355 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_356 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_357 = or(_T_354, _T_355) node _T_358 = or(_T_357, _T_356) node _T_359 = eq(io.rw.addr, UInt<10>(0h304)) node _T_360 = and(_T_358, _T_359) else : node _T_361 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_362 = eq(io.rw.addr, UInt<10>(0h304)) node _T_363 = and(_T_361, _T_362) node _T_364 = andr(UInt<2>(0h0)) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_367 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_368 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_369 = or(_T_366, _T_367) node _T_370 = or(_T_369, _T_368) node _T_371 = eq(io.rw.addr, UInt<10>(0h340)) node _T_372 = and(_T_370, _T_371) else : node _T_373 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_374 = eq(io.rw.addr, UInt<10>(0h340)) node _T_375 = and(_T_373, _T_374) node _T_376 = andr(UInt<2>(0h0)) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_379 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_380 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_381 = or(_T_378, _T_379) node _T_382 = or(_T_381, _T_380) node _T_383 = eq(io.rw.addr, UInt<10>(0h341)) node _T_384 = and(_T_382, _T_383) else : node _T_385 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_386 = eq(io.rw.addr, UInt<10>(0h341)) node _T_387 = and(_T_385, _T_386) node _T_388 = andr(UInt<2>(0h0)) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_391 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_392 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_393 = or(_T_390, _T_391) node _T_394 = or(_T_393, _T_392) node _T_395 = eq(io.rw.addr, UInt<10>(0h343)) node _T_396 = and(_T_394, _T_395) else : node _T_397 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_398 = eq(io.rw.addr, UInt<10>(0h343)) node _T_399 = and(_T_397, _T_398) node _T_400 = andr(UInt<2>(0h0)) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_403 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_404 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_405 = or(_T_402, _T_403) node _T_406 = or(_T_405, _T_404) node _T_407 = eq(io.rw.addr, UInt<10>(0h342)) node _T_408 = and(_T_406, _T_407) else : node _T_409 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_410 = eq(io.rw.addr, UInt<10>(0h342)) node _T_411 = and(_T_409, _T_410) node _T_412 = andr(UInt<2>(0h3)) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_415 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_416 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_417 = or(_T_414, _T_415) node _T_418 = or(_T_417, _T_416) node _T_419 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_420 = and(_T_418, _T_419) else : node _T_421 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_422 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_423 = and(_T_421, _T_422) node _T_424 = andr(UInt<2>(0h1)) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_427 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_428 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_429 = or(_T_426, _T_427) node _T_430 = or(_T_429, _T_428) node _T_431 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_432 = and(_T_430, _T_431) else : node _T_433 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_434 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_435 = and(_T_433, _T_434) node _T_436 = andr(UInt<2>(0h1)) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_439 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_440 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_441 = or(_T_438, _T_439) node _T_442 = or(_T_441, _T_440) node _T_443 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_444 = and(_T_442, _T_443) else : node _T_445 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_446 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_447 = and(_T_445, _T_446) node _T_448 = andr(UInt<2>(0h1)) node _T_449 = eq(_T_448, UInt<1>(0h0)) when _T_449 : node _T_450 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_451 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_452 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_453 = or(_T_450, _T_451) node _T_454 = or(_T_453, _T_452) node _T_455 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_456 = and(_T_454, _T_455) else : node _T_457 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_458 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_459 = and(_T_457, _T_458) node _T_460 = andr(UInt<2>(0h0)) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_463 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_464 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_465 = or(_T_462, _T_463) node _T_466 = or(_T_465, _T_464) node _T_467 = eq(io.rw.addr, UInt<1>(0h1)) node _T_468 = and(_T_466, _T_467) else : node _T_469 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_470 = eq(io.rw.addr, UInt<1>(0h1)) node _T_471 = and(_T_469, _T_470) node _T_472 = andr(UInt<2>(0h0)) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_475 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_476 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_477 = or(_T_474, _T_475) node _T_478 = or(_T_477, _T_476) node _T_479 = eq(io.rw.addr, UInt<2>(0h2)) node _T_480 = and(_T_478, _T_479) else : node _T_481 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_482 = eq(io.rw.addr, UInt<2>(0h2)) node _T_483 = and(_T_481, _T_482) node _T_484 = andr(UInt<2>(0h0)) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_487 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_488 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_489 = or(_T_486, _T_487) node _T_490 = or(_T_489, _T_488) node _T_491 = eq(io.rw.addr, UInt<2>(0h3)) node _T_492 = and(_T_490, _T_491) else : node _T_493 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_494 = eq(io.rw.addr, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = andr(UInt<2>(0h0)) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_499 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_500 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_501 = or(_T_498, _T_499) node _T_502 = or(_T_501, _T_500) node _T_503 = eq(io.rw.addr, UInt<10>(0h320)) node _T_504 = and(_T_502, _T_503) else : node _T_505 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_506 = eq(io.rw.addr, UInt<10>(0h320)) node _T_507 = and(_T_505, _T_506) node _T_508 = andr(UInt<2>(0h2)) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_511 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_512 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_513 = or(_T_510, _T_511) node _T_514 = or(_T_513, _T_512) node _T_515 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_516 = and(_T_514, _T_515) else : node _T_517 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_518 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_519 = and(_T_517, _T_518) node _T_520 = andr(UInt<2>(0h2)) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_523 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_524 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_525 = or(_T_522, _T_523) node _T_526 = or(_T_525, _T_524) node _T_527 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_528 = and(_T_526, _T_527) else : node _T_529 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_530 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_531 = and(_T_529, _T_530) node _T_532 = andr(UInt<2>(0h0)) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_535 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_536 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_537 = or(_T_534, _T_535) node _T_538 = or(_T_537, _T_536) node _T_539 = eq(io.rw.addr, UInt<10>(0h323)) node _T_540 = and(_T_538, _T_539) else : node _T_541 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_542 = eq(io.rw.addr, UInt<10>(0h323)) node _T_543 = and(_T_541, _T_542) node _T_544 = andr(UInt<2>(0h2)) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_547 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_548 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_549 = or(_T_546, _T_547) node _T_550 = or(_T_549, _T_548) node _T_551 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_552 = and(_T_550, _T_551) else : node _T_553 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_554 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_555 = and(_T_553, _T_554) node _T_556 = andr(UInt<2>(0h0)) node _T_557 = eq(_T_556, UInt<1>(0h0)) when _T_557 : node _T_558 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_559 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_560 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_561 = or(_T_558, _T_559) node _T_562 = or(_T_561, _T_560) node _T_563 = eq(io.rw.addr, UInt<10>(0h324)) node _T_564 = and(_T_562, _T_563) else : node _T_565 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_566 = eq(io.rw.addr, UInt<10>(0h324)) node _T_567 = and(_T_565, _T_566) node _T_568 = andr(UInt<2>(0h2)) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_571 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_572 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_573 = or(_T_570, _T_571) node _T_574 = or(_T_573, _T_572) node _T_575 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_576 = and(_T_574, _T_575) else : node _T_577 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_578 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_579 = and(_T_577, _T_578) node _T_580 = andr(UInt<2>(0h0)) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_583 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_584 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_585 = or(_T_582, _T_583) node _T_586 = or(_T_585, _T_584) node _T_587 = eq(io.rw.addr, UInt<10>(0h325)) node _T_588 = and(_T_586, _T_587) else : node _T_589 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_590 = eq(io.rw.addr, UInt<10>(0h325)) node _T_591 = and(_T_589, _T_590) node _T_592 = andr(UInt<2>(0h2)) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_595 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_596 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_597 = or(_T_594, _T_595) node _T_598 = or(_T_597, _T_596) node _T_599 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_600 = and(_T_598, _T_599) else : node _T_601 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_602 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_603 = and(_T_601, _T_602) node _T_604 = andr(UInt<2>(0h0)) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_607 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_608 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_609 = or(_T_606, _T_607) node _T_610 = or(_T_609, _T_608) node _T_611 = eq(io.rw.addr, UInt<10>(0h326)) node _T_612 = and(_T_610, _T_611) else : node _T_613 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_614 = eq(io.rw.addr, UInt<10>(0h326)) node _T_615 = and(_T_613, _T_614) node _T_616 = andr(UInt<2>(0h2)) node _T_617 = eq(_T_616, UInt<1>(0h0)) when _T_617 : node _T_618 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_619 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_620 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_621 = or(_T_618, _T_619) node _T_622 = or(_T_621, _T_620) node _T_623 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_624 = and(_T_622, _T_623) else : node _T_625 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_626 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_627 = and(_T_625, _T_626) node _T_628 = andr(UInt<2>(0h0)) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_631 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_632 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_633 = or(_T_630, _T_631) node _T_634 = or(_T_633, _T_632) node _T_635 = eq(io.rw.addr, UInt<10>(0h327)) node _T_636 = and(_T_634, _T_635) else : node _T_637 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_638 = eq(io.rw.addr, UInt<10>(0h327)) node _T_639 = and(_T_637, _T_638) node _T_640 = andr(UInt<2>(0h2)) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_643 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_644 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_645 = or(_T_642, _T_643) node _T_646 = or(_T_645, _T_644) node _T_647 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_648 = and(_T_646, _T_647) else : node _T_649 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_650 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_651 = and(_T_649, _T_650) node _T_652 = andr(UInt<2>(0h0)) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_655 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_656 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_657 = or(_T_654, _T_655) node _T_658 = or(_T_657, _T_656) node _T_659 = eq(io.rw.addr, UInt<10>(0h328)) node _T_660 = and(_T_658, _T_659) else : node _T_661 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_662 = eq(io.rw.addr, UInt<10>(0h328)) node _T_663 = and(_T_661, _T_662) node _T_664 = andr(UInt<2>(0h2)) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_667 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_668 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_669 = or(_T_666, _T_667) node _T_670 = or(_T_669, _T_668) node _T_671 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_672 = and(_T_670, _T_671) else : node _T_673 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_674 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_675 = and(_T_673, _T_674) node _T_676 = andr(UInt<2>(0h0)) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_679 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_680 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_681 = or(_T_678, _T_679) node _T_682 = or(_T_681, _T_680) node _T_683 = eq(io.rw.addr, UInt<10>(0h329)) node _T_684 = and(_T_682, _T_683) else : node _T_685 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_686 = eq(io.rw.addr, UInt<10>(0h329)) node _T_687 = and(_T_685, _T_686) node _T_688 = andr(UInt<2>(0h2)) node _T_689 = eq(_T_688, UInt<1>(0h0)) when _T_689 : node _T_690 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_691 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_692 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_693 = or(_T_690, _T_691) node _T_694 = or(_T_693, _T_692) node _T_695 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_696 = and(_T_694, _T_695) else : node _T_697 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_698 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_699 = and(_T_697, _T_698) node _T_700 = andr(UInt<2>(0h0)) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_703 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_704 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_705 = or(_T_702, _T_703) node _T_706 = or(_T_705, _T_704) node _T_707 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_708 = and(_T_706, _T_707) else : node _T_709 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_710 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_711 = and(_T_709, _T_710) node _T_712 = andr(UInt<2>(0h2)) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_715 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_716 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_717 = or(_T_714, _T_715) node _T_718 = or(_T_717, _T_716) node _T_719 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_720 = and(_T_718, _T_719) else : node _T_721 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_722 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_723 = and(_T_721, _T_722) node _T_724 = andr(UInt<2>(0h0)) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_727 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_728 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_729 = or(_T_726, _T_727) node _T_730 = or(_T_729, _T_728) node _T_731 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_732 = and(_T_730, _T_731) else : node _T_733 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_734 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_735 = and(_T_733, _T_734) node _T_736 = andr(UInt<2>(0h2)) node _T_737 = eq(_T_736, UInt<1>(0h0)) when _T_737 : node _T_738 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_739 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_740 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_741 = or(_T_738, _T_739) node _T_742 = or(_T_741, _T_740) node _T_743 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_744 = and(_T_742, _T_743) else : node _T_745 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_746 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_747 = and(_T_745, _T_746) node _T_748 = andr(UInt<2>(0h0)) node _T_749 = eq(_T_748, UInt<1>(0h0)) when _T_749 : node _T_750 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_751 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_752 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_753 = or(_T_750, _T_751) node _T_754 = or(_T_753, _T_752) node _T_755 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_756 = and(_T_754, _T_755) else : node _T_757 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_758 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_759 = and(_T_757, _T_758) node _T_760 = andr(UInt<2>(0h2)) node _T_761 = eq(_T_760, UInt<1>(0h0)) when _T_761 : node _T_762 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_763 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_764 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_765 = or(_T_762, _T_763) node _T_766 = or(_T_765, _T_764) node _T_767 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_768 = and(_T_766, _T_767) else : node _T_769 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_770 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_771 = and(_T_769, _T_770) node _T_772 = andr(UInt<2>(0h0)) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_775 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_776 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_777 = or(_T_774, _T_775) node _T_778 = or(_T_777, _T_776) node _T_779 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_780 = and(_T_778, _T_779) else : node _T_781 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_782 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_783 = and(_T_781, _T_782) node _T_784 = andr(UInt<2>(0h2)) node _T_785 = eq(_T_784, UInt<1>(0h0)) when _T_785 : node _T_786 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_787 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_788 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_789 = or(_T_786, _T_787) node _T_790 = or(_T_789, _T_788) node _T_791 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_792 = and(_T_790, _T_791) else : node _T_793 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_794 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_795 = and(_T_793, _T_794) node _T_796 = andr(UInt<2>(0h0)) node _T_797 = eq(_T_796, UInt<1>(0h0)) when _T_797 : node _T_798 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_799 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_800 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_801 = or(_T_798, _T_799) node _T_802 = or(_T_801, _T_800) node _T_803 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_804 = and(_T_802, _T_803) else : node _T_805 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_806 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_807 = and(_T_805, _T_806) node _T_808 = andr(UInt<2>(0h2)) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_811 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_812 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_813 = or(_T_810, _T_811) node _T_814 = or(_T_813, _T_812) node _T_815 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_816 = and(_T_814, _T_815) else : node _T_817 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_818 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_819 = and(_T_817, _T_818) node _T_820 = andr(UInt<2>(0h0)) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_823 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_824 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_825 = or(_T_822, _T_823) node _T_826 = or(_T_825, _T_824) node _T_827 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_828 = and(_T_826, _T_827) else : node _T_829 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_830 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_831 = and(_T_829, _T_830) node _T_832 = andr(UInt<2>(0h2)) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_835 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_836 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_837 = or(_T_834, _T_835) node _T_838 = or(_T_837, _T_836) node _T_839 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_840 = and(_T_838, _T_839) else : node _T_841 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_842 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_843 = and(_T_841, _T_842) node _T_844 = andr(UInt<2>(0h0)) node _T_845 = eq(_T_844, UInt<1>(0h0)) when _T_845 : node _T_846 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_847 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_848 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_849 = or(_T_846, _T_847) node _T_850 = or(_T_849, _T_848) node _T_851 = eq(io.rw.addr, UInt<10>(0h330)) node _T_852 = and(_T_850, _T_851) else : node _T_853 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_854 = eq(io.rw.addr, UInt<10>(0h330)) node _T_855 = and(_T_853, _T_854) node _T_856 = andr(UInt<2>(0h2)) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_859 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_860 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_864 = and(_T_862, _T_863) else : node _T_865 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_866 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_867 = and(_T_865, _T_866) node _T_868 = andr(UInt<2>(0h0)) node _T_869 = eq(_T_868, UInt<1>(0h0)) when _T_869 : node _T_870 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_871 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_872 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_873 = or(_T_870, _T_871) node _T_874 = or(_T_873, _T_872) node _T_875 = eq(io.rw.addr, UInt<10>(0h331)) node _T_876 = and(_T_874, _T_875) else : node _T_877 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_878 = eq(io.rw.addr, UInt<10>(0h331)) node _T_879 = and(_T_877, _T_878) node _T_880 = andr(UInt<2>(0h2)) node _T_881 = eq(_T_880, UInt<1>(0h0)) when _T_881 : node _T_882 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_883 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_884 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_885 = or(_T_882, _T_883) node _T_886 = or(_T_885, _T_884) node _T_887 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_888 = and(_T_886, _T_887) else : node _T_889 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_890 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_891 = and(_T_889, _T_890) node _T_892 = andr(UInt<2>(0h0)) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_895 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_896 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_897 = or(_T_894, _T_895) node _T_898 = or(_T_897, _T_896) node _T_899 = eq(io.rw.addr, UInt<10>(0h332)) node _T_900 = and(_T_898, _T_899) else : node _T_901 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_902 = eq(io.rw.addr, UInt<10>(0h332)) node _T_903 = and(_T_901, _T_902) node _T_904 = andr(UInt<2>(0h2)) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_907 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_908 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_909 = or(_T_906, _T_907) node _T_910 = or(_T_909, _T_908) node _T_911 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_912 = and(_T_910, _T_911) else : node _T_913 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_914 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_915 = and(_T_913, _T_914) node _T_916 = andr(UInt<2>(0h0)) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_919 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_920 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_921 = or(_T_918, _T_919) node _T_922 = or(_T_921, _T_920) node _T_923 = eq(io.rw.addr, UInt<10>(0h333)) node _T_924 = and(_T_922, _T_923) else : node _T_925 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_926 = eq(io.rw.addr, UInt<10>(0h333)) node _T_927 = and(_T_925, _T_926) node _T_928 = andr(UInt<2>(0h2)) node _T_929 = eq(_T_928, UInt<1>(0h0)) when _T_929 : node _T_930 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_931 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_932 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_933 = or(_T_930, _T_931) node _T_934 = or(_T_933, _T_932) node _T_935 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_936 = and(_T_934, _T_935) else : node _T_937 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_938 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_939 = and(_T_937, _T_938) node _T_940 = andr(UInt<2>(0h0)) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_943 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_944 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_945 = or(_T_942, _T_943) node _T_946 = or(_T_945, _T_944) node _T_947 = eq(io.rw.addr, UInt<10>(0h334)) node _T_948 = and(_T_946, _T_947) else : node _T_949 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_950 = eq(io.rw.addr, UInt<10>(0h334)) node _T_951 = and(_T_949, _T_950) node _T_952 = andr(UInt<2>(0h2)) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_955 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_956 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_957 = or(_T_954, _T_955) node _T_958 = or(_T_957, _T_956) node _T_959 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_960 = and(_T_958, _T_959) else : node _T_961 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_962 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_963 = and(_T_961, _T_962) node _T_964 = andr(UInt<2>(0h0)) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_967 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_968 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_969 = or(_T_966, _T_967) node _T_970 = or(_T_969, _T_968) node _T_971 = eq(io.rw.addr, UInt<10>(0h335)) node _T_972 = and(_T_970, _T_971) else : node _T_973 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_974 = eq(io.rw.addr, UInt<10>(0h335)) node _T_975 = and(_T_973, _T_974) node _T_976 = andr(UInt<2>(0h2)) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_979 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_980 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_981 = or(_T_978, _T_979) node _T_982 = or(_T_981, _T_980) node _T_983 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_984 = and(_T_982, _T_983) else : node _T_985 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_986 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_987 = and(_T_985, _T_986) node _T_988 = andr(UInt<2>(0h0)) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_991 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_992 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_993 = or(_T_990, _T_991) node _T_994 = or(_T_993, _T_992) node _T_995 = eq(io.rw.addr, UInt<10>(0h336)) node _T_996 = and(_T_994, _T_995) else : node _T_997 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_998 = eq(io.rw.addr, UInt<10>(0h336)) node _T_999 = and(_T_997, _T_998) node _T_1000 = andr(UInt<2>(0h2)) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1005 = or(_T_1002, _T_1003) node _T_1006 = or(_T_1005, _T_1004) node _T_1007 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1008 = and(_T_1006, _T_1007) else : node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1010 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = andr(UInt<2>(0h0)) node _T_1013 = eq(_T_1012, UInt<1>(0h0)) when _T_1013 : node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1017 = or(_T_1014, _T_1015) node _T_1018 = or(_T_1017, _T_1016) node _T_1019 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1020 = and(_T_1018, _T_1019) else : node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1022 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = andr(UInt<2>(0h2)) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1029 = or(_T_1026, _T_1027) node _T_1030 = or(_T_1029, _T_1028) node _T_1031 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1032 = and(_T_1030, _T_1031) else : node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1034 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1035 = and(_T_1033, _T_1034) node _T_1036 = andr(UInt<2>(0h0)) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1041 = or(_T_1038, _T_1039) node _T_1042 = or(_T_1041, _T_1040) node _T_1043 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1044 = and(_T_1042, _T_1043) else : node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1046 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1047 = and(_T_1045, _T_1046) node _T_1048 = andr(UInt<2>(0h2)) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1053 = or(_T_1050, _T_1051) node _T_1054 = or(_T_1053, _T_1052) node _T_1055 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1056 = and(_T_1054, _T_1055) else : node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1058 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1059 = and(_T_1057, _T_1058) node _T_1060 = andr(UInt<2>(0h0)) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1065 = or(_T_1062, _T_1063) node _T_1066 = or(_T_1065, _T_1064) node _T_1067 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1068 = and(_T_1066, _T_1067) else : node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1070 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = andr(UInt<2>(0h2)) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1077 = or(_T_1074, _T_1075) node _T_1078 = or(_T_1077, _T_1076) node _T_1079 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1080 = and(_T_1078, _T_1079) else : node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1082 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1083 = and(_T_1081, _T_1082) node _T_1084 = andr(UInt<2>(0h0)) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1089 = or(_T_1086, _T_1087) node _T_1090 = or(_T_1089, _T_1088) node _T_1091 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1092 = and(_T_1090, _T_1091) else : node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1094 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1095 = and(_T_1093, _T_1094) node _T_1096 = andr(UInt<2>(0h2)) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1101 = or(_T_1098, _T_1099) node _T_1102 = or(_T_1101, _T_1100) node _T_1103 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1104 = and(_T_1102, _T_1103) else : node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1106 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1107 = and(_T_1105, _T_1106) node _T_1108 = andr(UInt<2>(0h0)) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1113 = or(_T_1110, _T_1111) node _T_1114 = or(_T_1113, _T_1112) node _T_1115 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1116 = and(_T_1114, _T_1115) else : node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1118 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1119 = and(_T_1117, _T_1118) node _T_1120 = andr(UInt<2>(0h2)) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1125 = or(_T_1122, _T_1123) node _T_1126 = or(_T_1125, _T_1124) node _T_1127 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1128 = and(_T_1126, _T_1127) else : node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1130 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = andr(UInt<2>(0h0)) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1137 = or(_T_1134, _T_1135) node _T_1138 = or(_T_1137, _T_1136) node _T_1139 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1140 = and(_T_1138, _T_1139) else : node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1142 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1143 = and(_T_1141, _T_1142) node _T_1144 = andr(UInt<2>(0h2)) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1149 = or(_T_1146, _T_1147) node _T_1150 = or(_T_1149, _T_1148) node _T_1151 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1152 = and(_T_1150, _T_1151) else : node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1154 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1155 = and(_T_1153, _T_1154) node _T_1156 = andr(UInt<2>(0h0)) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1161 = or(_T_1158, _T_1159) node _T_1162 = or(_T_1161, _T_1160) node _T_1163 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1164 = and(_T_1162, _T_1163) else : node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1166 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1167 = and(_T_1165, _T_1166) node _T_1168 = andr(UInt<2>(0h2)) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1173 = or(_T_1170, _T_1171) node _T_1174 = or(_T_1173, _T_1172) node _T_1175 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1176 = and(_T_1174, _T_1175) else : node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1178 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1179 = and(_T_1177, _T_1178) node _T_1180 = andr(UInt<2>(0h0)) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1185 = or(_T_1182, _T_1183) node _T_1186 = or(_T_1185, _T_1184) node _T_1187 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1188 = and(_T_1186, _T_1187) else : node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1190 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = andr(UInt<2>(0h2)) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1197 = or(_T_1194, _T_1195) node _T_1198 = or(_T_1197, _T_1196) node _T_1199 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1200 = and(_T_1198, _T_1199) else : node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1202 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1203 = and(_T_1201, _T_1202) node _T_1204 = andr(UInt<2>(0h0)) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1209 = or(_T_1206, _T_1207) node _T_1210 = or(_T_1209, _T_1208) node _T_1211 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1212 = and(_T_1210, _T_1211) else : node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1214 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1215 = and(_T_1213, _T_1214) node _T_1216 = andr(UInt<2>(0h2)) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1221 = or(_T_1218, _T_1219) node _T_1222 = or(_T_1221, _T_1220) node _T_1223 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1224 = and(_T_1222, _T_1223) else : node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1226 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1227 = and(_T_1225, _T_1226) node _T_1228 = andr(UInt<2>(0h0)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1233 = or(_T_1230, _T_1231) node _T_1234 = or(_T_1233, _T_1232) node _T_1235 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1236 = and(_T_1234, _T_1235) else : node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1238 = eq(io.rw.addr, UInt<10>(0h306)) node _T_1239 = and(_T_1237, _T_1238) node _T_1240 = andr(UInt<2>(0h3)) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1245 = or(_T_1242, _T_1243) node _T_1246 = or(_T_1245, _T_1244) node _T_1247 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1248 = and(_T_1246, _T_1247) else : node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1250 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1251 = and(_T_1249, _T_1250) node _T_1252 = andr(UInt<2>(0h3)) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1257 = or(_T_1254, _T_1255) node _T_1258 = or(_T_1257, _T_1256) node _T_1259 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1260 = and(_T_1258, _T_1259) else : node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1262 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1263 = and(_T_1261, _T_1262) node _T_1264 = andr(UInt<2>(0h0)) node _T_1265 = eq(_T_1264, UInt<1>(0h0)) when _T_1265 : node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1269 = or(_T_1266, _T_1267) node _T_1270 = or(_T_1269, _T_1268) node _T_1271 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1272 = and(_T_1270, _T_1271) else : node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1274 = eq(io.rw.addr, UInt<10>(0h30a)) node _T_1275 = and(_T_1273, _T_1274) node _T_1276 = andr(UInt<2>(0h0)) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1281 = or(_T_1278, _T_1279) node _T_1282 = or(_T_1281, _T_1280) node _T_1283 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1284 = and(_T_1282, _T_1283) else : node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1286 = eq(io.rw.addr, UInt<9>(0h100)) node _T_1287 = and(_T_1285, _T_1286) node _T_1288 = andr(UInt<2>(0h0)) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1293 = or(_T_1290, _T_1291) node _T_1294 = or(_T_1293, _T_1292) node _T_1295 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1296 = and(_T_1294, _T_1295) else : node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1298 = eq(io.rw.addr, UInt<9>(0h144)) node _T_1299 = and(_T_1297, _T_1298) node _T_1300 = andr(UInt<2>(0h0)) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1305 = or(_T_1302, _T_1303) node _T_1306 = or(_T_1305, _T_1304) node _T_1307 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1308 = and(_T_1306, _T_1307) else : node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1310 = eq(io.rw.addr, UInt<9>(0h104)) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = andr(UInt<2>(0h0)) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1317 = or(_T_1314, _T_1315) node _T_1318 = or(_T_1317, _T_1316) node _T_1319 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1320 = and(_T_1318, _T_1319) else : node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1322 = eq(io.rw.addr, UInt<9>(0h140)) node _T_1323 = and(_T_1321, _T_1322) node _T_1324 = andr(UInt<2>(0h0)) node _T_1325 = eq(_T_1324, UInt<1>(0h0)) when _T_1325 : node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1329 = or(_T_1326, _T_1327) node _T_1330 = or(_T_1329, _T_1328) node _T_1331 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1332 = and(_T_1330, _T_1331) else : node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1334 = eq(io.rw.addr, UInt<9>(0h142)) node _T_1335 = and(_T_1333, _T_1334) node _T_1336 = andr(UInt<2>(0h0)) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1341 = or(_T_1338, _T_1339) node _T_1342 = or(_T_1341, _T_1340) node _T_1343 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1344 = and(_T_1342, _T_1343) else : node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1346 = eq(io.rw.addr, UInt<9>(0h143)) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = andr(UInt<2>(0h0)) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1353 = or(_T_1350, _T_1351) node _T_1354 = or(_T_1353, _T_1352) node _T_1355 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1356 = and(_T_1354, _T_1355) else : node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1358 = eq(io.rw.addr, UInt<9>(0h180)) node _T_1359 = and(_T_1357, _T_1358) node _T_1360 = andr(UInt<2>(0h0)) node _T_1361 = eq(_T_1360, UInt<1>(0h0)) when _T_1361 : node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1365 = or(_T_1362, _T_1363) node _T_1366 = or(_T_1365, _T_1364) node _T_1367 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1368 = and(_T_1366, _T_1367) else : node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1370 = eq(io.rw.addr, UInt<9>(0h141)) node _T_1371 = and(_T_1369, _T_1370) node _T_1372 = andr(UInt<2>(0h0)) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1377 = or(_T_1374, _T_1375) node _T_1378 = or(_T_1377, _T_1376) node _T_1379 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1380 = and(_T_1378, _T_1379) else : node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1382 = eq(io.rw.addr, UInt<9>(0h105)) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = andr(UInt<2>(0h0)) node _T_1385 = eq(_T_1384, UInt<1>(0h0)) when _T_1385 : node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1389 = or(_T_1386, _T_1387) node _T_1390 = or(_T_1389, _T_1388) node _T_1391 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1392 = and(_T_1390, _T_1391) else : node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1394 = eq(io.rw.addr, UInt<9>(0h106)) node _T_1395 = and(_T_1393, _T_1394) node _T_1396 = andr(UInt<2>(0h0)) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1401 = or(_T_1398, _T_1399) node _T_1402 = or(_T_1401, _T_1400) node _T_1403 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1404 = and(_T_1402, _T_1403) else : node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1406 = eq(io.rw.addr, UInt<10>(0h303)) node _T_1407 = and(_T_1405, _T_1406) node _T_1408 = andr(UInt<2>(0h0)) node _T_1409 = eq(_T_1408, UInt<1>(0h0)) when _T_1409 : node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1413 = or(_T_1410, _T_1411) node _T_1414 = or(_T_1413, _T_1412) node _T_1415 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1416 = and(_T_1414, _T_1415) else : node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1418 = eq(io.rw.addr, UInt<10>(0h302)) node _T_1419 = and(_T_1417, _T_1418) node _T_1420 = andr(UInt<2>(0h0)) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1425 = or(_T_1422, _T_1423) node _T_1426 = or(_T_1425, _T_1424) node _T_1427 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1428 = and(_T_1426, _T_1427) else : node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1430 = eq(io.rw.addr, UInt<9>(0h10a)) node _T_1431 = and(_T_1429, _T_1430) node _T_1432 = andr(UInt<2>(0h0)) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1437 = or(_T_1434, _T_1435) node _T_1438 = or(_T_1437, _T_1436) node _T_1439 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1440 = and(_T_1438, _T_1439) else : node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1442 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1443 = and(_T_1441, _T_1442) node _T_1444 = andr(UInt<2>(0h0)) node _T_1445 = eq(_T_1444, UInt<1>(0h0)) when _T_1445 : node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1449 = or(_T_1446, _T_1447) node _T_1450 = or(_T_1449, _T_1448) node _T_1451 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1452 = and(_T_1450, _T_1451) else : node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1454 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_1455 = and(_T_1453, _T_1454) node _T_1456 = andr(UInt<2>(0h0)) node _T_1457 = eq(_T_1456, UInt<1>(0h0)) when _T_1457 : node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1461 = or(_T_1458, _T_1459) node _T_1462 = or(_T_1461, _T_1460) node _T_1463 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1464 = and(_T_1462, _T_1463) else : node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1466 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_1467 = and(_T_1465, _T_1466) node _T_1468 = andr(UInt<2>(0h0)) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) when _T_1469 : node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1473 = or(_T_1470, _T_1471) node _T_1474 = or(_T_1473, _T_1472) node _T_1475 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1476 = and(_T_1474, _T_1475) else : node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1478 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_1479 = and(_T_1477, _T_1478) node _T_1480 = andr(UInt<2>(0h0)) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1485 = or(_T_1482, _T_1483) node _T_1486 = or(_T_1485, _T_1484) node _T_1487 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1488 = and(_T_1486, _T_1487) else : node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1490 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_1491 = and(_T_1489, _T_1490) node _T_1492 = andr(UInt<2>(0h0)) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1495 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1496 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1497 = or(_T_1494, _T_1495) node _T_1498 = or(_T_1497, _T_1496) node _T_1499 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1500 = and(_T_1498, _T_1499) else : node _T_1501 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1502 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_1503 = and(_T_1501, _T_1502) node _T_1504 = andr(UInt<2>(0h0)) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1507 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1508 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1509 = or(_T_1506, _T_1507) node _T_1510 = or(_T_1509, _T_1508) node _T_1511 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1512 = and(_T_1510, _T_1511) else : node _T_1513 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1514 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_1515 = and(_T_1513, _T_1514) node _T_1516 = andr(UInt<2>(0h0)) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1519 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1520 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1521 = or(_T_1518, _T_1519) node _T_1522 = or(_T_1521, _T_1520) node _T_1523 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1524 = and(_T_1522, _T_1523) else : node _T_1525 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1526 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = andr(UInt<2>(0h0)) node _T_1529 = eq(_T_1528, UInt<1>(0h0)) when _T_1529 : node _T_1530 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1531 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1532 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1533 = or(_T_1530, _T_1531) node _T_1534 = or(_T_1533, _T_1532) node _T_1535 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1536 = and(_T_1534, _T_1535) else : node _T_1537 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1538 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_1539 = and(_T_1537, _T_1538) node _T_1540 = andr(UInt<2>(0h0)) node _T_1541 = eq(_T_1540, UInt<1>(0h0)) when _T_1541 : node _T_1542 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1543 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1544 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1545 = or(_T_1542, _T_1543) node _T_1546 = or(_T_1545, _T_1544) node _T_1547 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1548 = and(_T_1546, _T_1547) else : node _T_1549 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1550 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_1551 = and(_T_1549, _T_1550) node _T_1552 = andr(UInt<2>(0h0)) node _T_1553 = eq(_T_1552, UInt<1>(0h0)) when _T_1553 : node _T_1554 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1555 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1556 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1557 = or(_T_1554, _T_1555) node _T_1558 = or(_T_1557, _T_1556) node _T_1559 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1560 = and(_T_1558, _T_1559) else : node _T_1561 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1562 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_1563 = and(_T_1561, _T_1562) node _T_1564 = andr(UInt<2>(0h0)) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) when _T_1565 : node _T_1566 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1567 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1568 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1569 = or(_T_1566, _T_1567) node _T_1570 = or(_T_1569, _T_1568) node _T_1571 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1572 = and(_T_1570, _T_1571) else : node _T_1573 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1574 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_1575 = and(_T_1573, _T_1574) node _T_1576 = andr(UInt<2>(0h0)) node _T_1577 = eq(_T_1576, UInt<1>(0h0)) when _T_1577 : node _T_1578 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1579 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1580 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1581 = or(_T_1578, _T_1579) node _T_1582 = or(_T_1581, _T_1580) node _T_1583 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1584 = and(_T_1582, _T_1583) else : node _T_1585 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1586 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_1587 = and(_T_1585, _T_1586) node _T_1588 = andr(UInt<2>(0h0)) node _T_1589 = eq(_T_1588, UInt<1>(0h0)) when _T_1589 : node _T_1590 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1591 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1592 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1593 = or(_T_1590, _T_1591) node _T_1594 = or(_T_1593, _T_1592) node _T_1595 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1596 = and(_T_1594, _T_1595) else : node _T_1597 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1598 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_1599 = and(_T_1597, _T_1598) node _T_1600 = andr(UInt<2>(0h0)) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1603 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1604 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1605 = or(_T_1602, _T_1603) node _T_1606 = or(_T_1605, _T_1604) node _T_1607 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1608 = and(_T_1606, _T_1607) else : node _T_1609 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1610 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_1611 = and(_T_1609, _T_1610) node _T_1612 = andr(UInt<2>(0h0)) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1615 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1616 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1617 = or(_T_1614, _T_1615) node _T_1618 = or(_T_1617, _T_1616) node _T_1619 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1620 = and(_T_1618, _T_1619) else : node _T_1621 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1622 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_1623 = and(_T_1621, _T_1622) node _T_1624 = andr(UInt<2>(0h0)) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1627 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1628 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1629 = or(_T_1626, _T_1627) node _T_1630 = or(_T_1629, _T_1628) node _T_1631 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1632 = and(_T_1630, _T_1631) else : node _T_1633 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1634 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_1635 = and(_T_1633, _T_1634) node _T_1636 = andr(UInt<2>(0h0)) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1639 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1640 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1641 = or(_T_1638, _T_1639) node _T_1642 = or(_T_1641, _T_1640) node _T_1643 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1644 = and(_T_1642, _T_1643) else : node _T_1645 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1646 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_1647 = and(_T_1645, _T_1646) node _T_1648 = andr(UInt<2>(0h1)) node _T_1649 = eq(_T_1648, UInt<1>(0h0)) when _T_1649 : node _T_1650 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1651 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1652 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1653 = or(_T_1650, _T_1651) node _T_1654 = or(_T_1653, _T_1652) node _T_1655 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1656 = and(_T_1654, _T_1655) else : node _T_1657 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1658 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_1659 = and(_T_1657, _T_1658) node _T_1660 = andr(UInt<2>(0h3)) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1663 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1664 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1665 = or(_T_1662, _T_1663) node _T_1666 = or(_T_1665, _T_1664) node _T_1667 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1668 = and(_T_1666, _T_1667) else : node _T_1669 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1670 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_1671 = and(_T_1669, _T_1670) node _T_1672 = andr(UInt<2>(0h3)) node _T_1673 = eq(_T_1672, UInt<1>(0h0)) when _T_1673 : node _T_1674 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1675 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1676 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1677 = or(_T_1674, _T_1675) node _T_1678 = or(_T_1677, _T_1676) node _T_1679 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1680 = and(_T_1678, _T_1679) else : node _T_1681 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1682 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_1683 = and(_T_1681, _T_1682) node _T_1684 = andr(UInt<2>(0h3)) node _T_1685 = eq(_T_1684, UInt<1>(0h0)) when _T_1685 : node _T_1686 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1687 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1688 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1689 = or(_T_1686, _T_1687) node _T_1690 = or(_T_1689, _T_1688) node _T_1691 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1692 = and(_T_1690, _T_1691) else : node _T_1693 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1694 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_1695 = and(_T_1693, _T_1694) node _T_1696 = andr(UInt<2>(0h3)) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1699 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1700 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1701 = or(_T_1698, _T_1699) node _T_1702 = or(_T_1701, _T_1700) node _T_1703 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1704 = and(_T_1702, _T_1703) else : node _T_1705 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1706 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_1707 = and(_T_1705, _T_1706) wire set_vs_dirty : UInt<1> connect set_vs_dirty, UInt<1>(0h0) wire set_fs_dirty : UInt<1> connect set_fs_dirty, UInt<1>(0h0) connect io.fcsr_rm, reg_frm when io.fcsr_flags.valid : node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) connect reg_fflags, _reg_fflags_T connect set_fs_dirty, UInt<1>(0h1) node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) connect io.csrw_counter, _io_csrw_counter_T_11 when csr_wen : when decoded_addr_100_2 : wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_mstatus_WIRE : UInt<105> connect _new_mstatus_WIRE, wdata node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) connect new_mstatus.uie, _new_mstatus_T node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) connect new_mstatus.sie, _new_mstatus_T_1 node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) connect new_mstatus.hie, _new_mstatus_T_2 node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) connect new_mstatus.mie, _new_mstatus_T_3 node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) connect new_mstatus.upie, _new_mstatus_T_4 node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) connect new_mstatus.spie, _new_mstatus_T_5 node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) connect new_mstatus.ube, _new_mstatus_T_6 node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) connect new_mstatus.mpie, _new_mstatus_T_7 node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) connect new_mstatus.spp, _new_mstatus_T_8 node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) connect new_mstatus.vs, _new_mstatus_T_9 node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) connect new_mstatus.mpp, _new_mstatus_T_10 node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) connect new_mstatus.fs, _new_mstatus_T_11 node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) connect new_mstatus.xs, _new_mstatus_T_12 node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) connect new_mstatus.mprv, _new_mstatus_T_13 node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) connect new_mstatus.sum, _new_mstatus_T_14 node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) connect new_mstatus.mxr, _new_mstatus_T_15 node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) connect new_mstatus.tvm, _new_mstatus_T_16 node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) connect new_mstatus.tw, _new_mstatus_T_17 node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) connect new_mstatus.tsr, _new_mstatus_T_18 node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) connect new_mstatus.zero1, _new_mstatus_T_19 node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) connect new_mstatus.sd_rv32, _new_mstatus_T_20 node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) connect new_mstatus.uxl, _new_mstatus_T_21 node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) connect new_mstatus.sxl, _new_mstatus_T_22 node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) connect new_mstatus.sbe, _new_mstatus_T_23 node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) connect new_mstatus.mbe, _new_mstatus_T_24 node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) connect new_mstatus.gva, _new_mstatus_T_25 node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) connect new_mstatus.mpv, _new_mstatus_T_26 node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) connect new_mstatus.zero2, _new_mstatus_T_27 node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) connect new_mstatus.sd, _new_mstatus_T_28 node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) connect new_mstatus.v, _new_mstatus_T_29 node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) connect new_mstatus.prv, _new_mstatus_T_30 node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) connect new_mstatus.dv, _new_mstatus_T_31 node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) connect new_mstatus.dprv, _new_mstatus_T_32 node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) connect new_mstatus.isa, _new_mstatus_T_33 node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) connect new_mstatus.wfi, _new_mstatus_T_34 node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) connect new_mstatus.cease, _new_mstatus_T_35 node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) connect new_mstatus.debug, _new_mstatus_T_36 connect reg_mstatus.mie, new_mstatus.mie connect reg_mstatus.mpie, new_mstatus.mpie connect reg_mstatus.mprv, new_mstatus.mprv node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2)) node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp) connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3 connect reg_mstatus.spp, new_mstatus.spp connect reg_mstatus.spie, new_mstatus.spie connect reg_mstatus.sie, new_mstatus.sie connect reg_mstatus.tw, new_mstatus.tw connect reg_mstatus.tsr, new_mstatus.tsr connect reg_mstatus.mxr, new_mstatus.mxr connect reg_mstatus.sum, new_mstatus.sum connect reg_mstatus.tvm, new_mstatus.tvm node _reg_mstatus_fs_T = orr(new_mstatus.fs) node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_1 connect reg_mstatus.vs, UInt<1>(0h0) when decoded_addr_94_2 : node f = bits(wdata, 5, 5) node _T_1708 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_1709 = bits(io.pc, 1, 1) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) node _T_1711 = or(_T_1708, _T_1710) node _T_1712 = bits(wdata, 2, 2) node _T_1713 = or(_T_1711, _T_1712) when _T_1713 : node _reg_misa_T = not(wdata) node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) node _reg_misa_T_4 = not(_reg_misa_T_3) node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d)) node _reg_misa_T_6 = not(UInt<64>(0h102d)) node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) connect reg_misa, _reg_misa_T_8 when decoded_addr_108_2 : node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) node _new_mip_T = cat(new_mip_hi, new_mip_lo) node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) node _new_mip_T_5 = andr(_new_mip_T_4) node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) node _new_mip_T_7 = not(_new_mip_T_6) node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_mip_WIRE : UInt<16> connect _new_mip_WIRE, _new_mip_T_8 node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) connect new_mip.usip, _new_mip_T_9 node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) connect new_mip.ssip, _new_mip_T_10 node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) connect new_mip.vssip, _new_mip_T_11 node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) connect new_mip.msip, _new_mip_T_12 node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) connect new_mip.utip, _new_mip_T_13 node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) connect new_mip.stip, _new_mip_T_14 node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) connect new_mip.vstip, _new_mip_T_15 node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) connect new_mip.mtip, _new_mip_T_16 node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) connect new_mip.ueip, _new_mip_T_17 node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) connect new_mip.seip, _new_mip_T_18 node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) connect new_mip.vseip, _new_mip_T_19 node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) connect new_mip.meip, _new_mip_T_20 node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) connect new_mip.sgeip, _new_mip_T_21 node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) connect new_mip.rocc, _new_mip_T_22 node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) connect new_mip.debug, _new_mip_T_23 node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) connect new_mip.zero1, _new_mip_T_24 connect reg_mip.ssip, new_mip.ssip connect reg_mip.stip, new_mip.stip connect reg_mip.seip, new_mip.seip when decoded_addr_76_2 : node _reg_mie_T = and(wdata, supported_interrupts) connect reg_mie, _reg_mie_T when decoded_addr_132_2 : node _reg_mepc_T = not(wdata) node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) node _reg_mepc_T_2 = not(_reg_mepc_T_1) connect reg_mepc, _reg_mepc_T_2 when decoded_addr_129_2 : connect reg_mscratch, wdata when decoded_addr_72_2 : connect reg_mtvec, wdata when decoded_addr_29_2 : node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f)) connect reg_mcause, _reg_mcause_T when decoded_addr_136_2 : connect reg_mtval, wdata when decoded_addr_130_2 : node _reg_mcountinhibit_T = not(UInt<64>(0h2)) node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) connect reg_mcountinhibit, _reg_mcountinhibit_T_1 when decoded_addr_103_2 : node _T_1714 = bits(wdata, 63, 0) connect small_1, _T_1714 node _large_T_6 = shr(_T_1714, 6) connect large_1, _large_T_6 when decoded_addr_121_2 : node _T_1715 = bits(wdata, 63, 0) connect small, _T_1715 node _large_T_7 = shr(_T_1715, 6) connect large, _large_T_7 when decoded_addr_36_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata when decoded_addr_68_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_frm, wdata when decoded_addr_99_2 : connect set_fs_dirty, UInt<1>(0h1) connect reg_fflags, wdata node _reg_frm_T = shr(wdata, 5) connect reg_frm, _reg_frm_T when decoded_addr_49_2 : wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} wire _new_dcsr_WIRE : UInt<32> connect _new_dcsr_WIRE, wdata node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) connect new_dcsr.prv, _new_dcsr_T node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) connect new_dcsr.step, _new_dcsr_T_1 node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) connect new_dcsr.zero1, _new_dcsr_T_2 node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) connect new_dcsr.v, _new_dcsr_T_3 node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) connect new_dcsr.cause, _new_dcsr_T_4 node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) connect new_dcsr.stoptime, _new_dcsr_T_5 node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) connect new_dcsr.stopcycle, _new_dcsr_T_6 node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) connect new_dcsr.zero2, _new_dcsr_T_7 node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) connect new_dcsr.ebreaku, _new_dcsr_T_8 node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) connect new_dcsr.ebreaks, _new_dcsr_T_9 node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) connect new_dcsr.ebreakh, _new_dcsr_T_10 node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) connect new_dcsr.ebreakm, _new_dcsr_T_11 node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) connect new_dcsr.zero3, _new_dcsr_T_12 node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) connect new_dcsr.zero4, _new_dcsr_T_13 node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) connect new_dcsr.xdebugver, _new_dcsr_T_14 connect reg_dcsr.step, new_dcsr.step connect reg_dcsr.ebreakm, new_dcsr.ebreakm connect reg_dcsr.ebreaks, new_dcsr.ebreaks connect reg_dcsr.ebreaku, new_dcsr.ebreaku node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2)) node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv) connect reg_dcsr.prv, _reg_dcsr_prv_T_1 when decoded_addr_89_2 : node _reg_dpc_T = not(wdata) node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) node _reg_dpc_T_2 = not(_reg_dpc_T_1) connect reg_dpc, _reg_dpc_T_2 when decoded_addr_57_2 : connect reg_dscratch0, wdata when decoded_addr_61_2 : wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_sstatus_WIRE : UInt<105> connect _new_sstatus_WIRE, wdata node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0) connect new_sstatus.uie, _new_sstatus_T node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1) connect new_sstatus.sie, _new_sstatus_T_1 node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2) connect new_sstatus.hie, _new_sstatus_T_2 node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3) connect new_sstatus.mie, _new_sstatus_T_3 node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4) connect new_sstatus.upie, _new_sstatus_T_4 node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5) connect new_sstatus.spie, _new_sstatus_T_5 node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6) connect new_sstatus.ube, _new_sstatus_T_6 node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7) connect new_sstatus.mpie, _new_sstatus_T_7 node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8) connect new_sstatus.spp, _new_sstatus_T_8 node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9) connect new_sstatus.vs, _new_sstatus_T_9 node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11) connect new_sstatus.mpp, _new_sstatus_T_10 node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13) connect new_sstatus.fs, _new_sstatus_T_11 node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15) connect new_sstatus.xs, _new_sstatus_T_12 node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17) connect new_sstatus.mprv, _new_sstatus_T_13 node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18) connect new_sstatus.sum, _new_sstatus_T_14 node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19) connect new_sstatus.mxr, _new_sstatus_T_15 node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20) connect new_sstatus.tvm, _new_sstatus_T_16 node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21) connect new_sstatus.tw, _new_sstatus_T_17 node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22) connect new_sstatus.tsr, _new_sstatus_T_18 node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23) connect new_sstatus.zero1, _new_sstatus_T_19 node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31) connect new_sstatus.sd_rv32, _new_sstatus_T_20 node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32) connect new_sstatus.uxl, _new_sstatus_T_21 node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34) connect new_sstatus.sxl, _new_sstatus_T_22 node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36) connect new_sstatus.sbe, _new_sstatus_T_23 node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37) connect new_sstatus.mbe, _new_sstatus_T_24 node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38) connect new_sstatus.gva, _new_sstatus_T_25 node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39) connect new_sstatus.mpv, _new_sstatus_T_26 node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40) connect new_sstatus.zero2, _new_sstatus_T_27 node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63) connect new_sstatus.sd, _new_sstatus_T_28 node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64) connect new_sstatus.v, _new_sstatus_T_29 node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65) connect new_sstatus.prv, _new_sstatus_T_30 node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67) connect new_sstatus.dv, _new_sstatus_T_31 node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68) connect new_sstatus.dprv, _new_sstatus_T_32 node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70) connect new_sstatus.isa, _new_sstatus_T_33 node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102) connect new_sstatus.wfi, _new_sstatus_T_34 node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103) connect new_sstatus.cease, _new_sstatus_T_35 node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104) connect new_sstatus.debug, _new_sstatus_T_36 connect reg_mstatus.sie, new_sstatus.sie connect reg_mstatus.spie, new_sstatus.spie connect reg_mstatus.spp, new_sstatus.spp node _reg_mstatus_fs_T_2 = orr(new_sstatus.fs) node _reg_mstatus_fs_T_3 = mux(_reg_mstatus_fs_T_2, UInt<2>(0h3), UInt<2>(0h0)) connect reg_mstatus.fs, _reg_mstatus_fs_T_3 connect reg_mstatus.vs, UInt<1>(0h0) connect reg_mstatus.mxr, new_sstatus.mxr connect reg_mstatus.sum, new_sstatus.sum when decoded_addr_48_2 : node _new_sip_T = not(read_mideleg) node _new_sip_T_1 = and(read_mip, _new_sip_T) node _new_sip_T_2 = and(wdata, read_mideleg) node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2) wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_sip_WIRE : UInt<16> connect _new_sip_WIRE, _new_sip_T_3 node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0) connect new_sip.usip, _new_sip_T_4 node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1) connect new_sip.ssip, _new_sip_T_5 node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2) connect new_sip.vssip, _new_sip_T_6 node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3) connect new_sip.msip, _new_sip_T_7 node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4) connect new_sip.utip, _new_sip_T_8 node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5) connect new_sip.stip, _new_sip_T_9 node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6) connect new_sip.vstip, _new_sip_T_10 node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7) connect new_sip.mtip, _new_sip_T_11 node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8) connect new_sip.ueip, _new_sip_T_12 node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9) connect new_sip.seip, _new_sip_T_13 node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10) connect new_sip.vseip, _new_sip_T_14 node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11) connect new_sip.meip, _new_sip_T_15 node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12) connect new_sip.sgeip, _new_sip_T_16 node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13) connect new_sip.rocc, _new_sip_T_17 node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14) connect new_sip.debug, _new_sip_T_18 node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15) connect new_sip.zero1, _new_sip_T_19 connect reg_mip.ssip, new_sip.ssip when decoded_addr_6_2 : wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>} wire _new_satp_WIRE : UInt<64> connect _new_satp_WIRE, wdata node _new_satp_T = bits(_new_satp_WIRE, 43, 0) connect new_satp.ppn, _new_satp_T node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44) connect new_satp.asid, _new_satp_T_1 node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60) connect new_satp.mode, _new_satp_T_2 node _T_1716 = eq(new_satp.mode, UInt<1>(0h0)) node _T_1717 = eq(new_satp.mode, UInt<4>(0h8)) node _T_1718 = or(_T_1716, _T_1717) when _T_1718 : node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8)) connect reg_satp.mode, _reg_satp_mode_T node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0) connect reg_satp.ppn, _reg_satp_ppn_T when decoded_addr_44_2 : node _reg_mie_T_1 = not(sie_mask) node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1) node _reg_mie_T_3 = and(wdata, sie_mask) node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3) connect reg_mie, _reg_mie_T_4 when decoded_addr_15_2 : connect reg_sscratch, wdata when decoded_addr_28_2 : node _reg_sepc_T = not(wdata) node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1)) node _reg_sepc_T_2 = not(_reg_sepc_T_1) connect reg_sepc, _reg_sepc_T_2 when decoded_addr_25_2 : connect reg_stvec, wdata when decoded_addr_145_2 : node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f)) connect reg_scause, _reg_scause_T when decoded_addr_93_2 : connect reg_stval, wdata when decoded_addr_123_2 : connect reg_mideleg, wdata when decoded_addr_23_2 : connect reg_medeleg, wdata when decoded_addr_137_2 : connect reg_scounteren, wdata when decoded_addr_69_2 : wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE : UInt<64> connect _new_envcfg_WIRE, wdata node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0) connect new_envcfg.fiom, _new_envcfg_T node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1) connect new_envcfg.zero3, _new_envcfg_T_1 node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4) connect new_envcfg.cbie, _new_envcfg_T_2 node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6) connect new_envcfg.cbcfe, _new_envcfg_T_3 node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7) connect new_envcfg.cbze, _new_envcfg_T_4 node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8) connect new_envcfg.zero54, _new_envcfg_T_5 node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62) connect new_envcfg.pbmte, _new_envcfg_T_6 node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63) connect new_envcfg.stce, _new_envcfg_T_7 connect reg_senvcfg.fiom, new_envcfg.fiom when decoded_addr_35_2 : connect reg_mcounteren, wdata when decoded_addr_42_2 : wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} wire _new_envcfg_WIRE_1 : UInt<64> connect _new_envcfg_WIRE_1, wdata node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0) connect new_envcfg_1.fiom, _new_envcfg_T_8 node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1) connect new_envcfg_1.zero3, _new_envcfg_T_9 node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4) connect new_envcfg_1.cbie, _new_envcfg_T_10 node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6) connect new_envcfg_1.cbcfe, _new_envcfg_T_11 node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7) connect new_envcfg_1.cbze, _new_envcfg_T_12 node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8) connect new_envcfg_1.zero54, _new_envcfg_T_13 node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62) connect new_envcfg_1.pbmte, _new_envcfg_T_14 node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63) connect new_envcfg_1.stce, _new_envcfg_T_15 connect reg_menvcfg.fiom, new_envcfg_1.fiom when decoded_addr_97_2 : connect reg_tselect, wdata node _T_1719 = eq(UInt<1>(0h0), reg_tselect) node _T_1720 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) node _T_1721 = or(_T_1720, reg_debug) node _T_1722 = and(_T_1719, _T_1721) when _T_1722 : when decoded_addr_10_2 : connect reg_bp[0].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_0_control_WIRE_1 : UInt<64> connect _reg_bp_0_control_WIRE_1, wdata node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13) connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53) connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59) connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60) connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 connect reg_bp[0].control, _reg_bp_0_control_WIRE node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) node _newBPC_T = cat(newBPC_hi, newBPC_lo) node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) node _newBPC_T_5 = andr(_newBPC_T_4) node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_7 = not(_newBPC_T_6) node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE : UInt<64> connect _newBPC_WIRE, _newBPC_T_8 node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) connect newBPC.r, _newBPC_T_9 node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) connect newBPC.w, _newBPC_T_10 node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) connect newBPC.x, _newBPC_T_11 node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) connect newBPC.u, _newBPC_T_12 node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) connect newBPC.s, _newBPC_T_13 node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) connect newBPC.h, _newBPC_T_14 node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) connect newBPC.m, _newBPC_T_15 node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) connect newBPC.tmatch, _newBPC_T_16 node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) connect newBPC.zero, _newBPC_T_17 node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) connect newBPC.chain, _newBPC_T_18 node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) connect newBPC.action, _newBPC_T_19 node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13) connect newBPC.reserved, _newBPC_T_20 node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53) connect newBPC.maskmax, _newBPC_T_21 node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59) connect newBPC.dmode, _newBPC_T_22 node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60) connect newBPC.ttype, _newBPC_T_23 node _dMode_T = and(newBPC.dmode, reg_debug) node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) node dMode = and(_dMode_T, _dMode_T_2) connect reg_bp[0].control.dmode, dMode node _T_1723 = gt(newBPC.action, UInt<1>(0h1)) node _T_1724 = or(dMode, _T_1723) when _T_1724 : connect reg_bp[0].control.action, newBPC.action else : connect reg_bp[0].control.action, UInt<1>(0h0) node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 node _T_1725 = eq(UInt<1>(0h1), reg_tselect) node _T_1726 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) node _T_1727 = or(_T_1726, reg_debug) node _T_1728 = and(_T_1725, _T_1727) when _T_1728 : when decoded_addr_10_2 : connect reg_bp[1].address, wdata when decoded_addr_118_2 : skip when decoded_addr_55_2 : wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_1_control_WIRE_1 : UInt<64> connect _reg_bp_1_control_WIRE_1, wdata node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13) connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53) connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59) connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60) connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 connect reg_bp[1].control, _reg_bp_1_control_WIRE node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) node _newBPC_T_29 = andr(_newBPC_T_28) node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_31 = not(_newBPC_T_30) node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE_1 : UInt<64> connect _newBPC_WIRE_1, _newBPC_T_32 node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) connect newBPC_1.r, _newBPC_T_33 node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) connect newBPC_1.w, _newBPC_T_34 node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) connect newBPC_1.x, _newBPC_T_35 node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) connect newBPC_1.u, _newBPC_T_36 node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) connect newBPC_1.s, _newBPC_T_37 node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) connect newBPC_1.h, _newBPC_T_38 node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) connect newBPC_1.m, _newBPC_T_39 node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) connect newBPC_1.tmatch, _newBPC_T_40 node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) connect newBPC_1.zero, _newBPC_T_41 node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) connect newBPC_1.chain, _newBPC_T_42 node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) connect newBPC_1.action, _newBPC_T_43 node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13) connect newBPC_1.reserved, _newBPC_T_44 node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53) connect newBPC_1.maskmax, _newBPC_T_45 node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59) connect newBPC_1.dmode, _newBPC_T_46 node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60) connect newBPC_1.ttype, _newBPC_T_47 node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) node dMode_1 = and(_dMode_T_3, _dMode_T_5) connect reg_bp[1].control.dmode, dMode_1 node _T_1729 = gt(newBPC_1.action, UInt<1>(0h1)) node _T_1730 = or(dMode_1, _T_1729) when _T_1730 : connect reg_bp[1].control.action, newBPC_1.action else : connect reg_bp[1].control.action, UInt<1>(0h0) node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 node _T_1731 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) node _T_1732 = and(decoded_addr_141_2, _T_1731) when _T_1732 : node _newCfg_T = shr(wdata, 0) wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE : UInt<8> connect _newCfg_WIRE, _newCfg_T node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) connect newCfg.r, _newCfg_T_1 node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) connect newCfg.w, _newCfg_T_2 node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) connect newCfg.x, _newCfg_T_3 node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) connect newCfg.a, _newCfg_T_4 node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) connect newCfg.res, _newCfg_T_5 node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) connect newCfg.l, _newCfg_T_6 connect reg_pmp[0].cfg, newCfg node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T node _T_1733 = bits(reg_pmp[1].cfg.a, 1, 1) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) node _T_1735 = bits(reg_pmp[1].cfg.a, 0, 0) node _T_1736 = and(_T_1734, _T_1735) node _T_1737 = and(reg_pmp[1].cfg.l, _T_1736) node _T_1738 = or(reg_pmp[0].cfg.l, _T_1737) node _T_1739 = eq(_T_1738, UInt<1>(0h0)) node _T_1740 = and(decoded_addr_104_2, _T_1739) when _T_1740 : connect reg_pmp[0].addr, wdata node _T_1741 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) node _T_1742 = and(decoded_addr_141_2, _T_1741) when _T_1742 : node _newCfg_T_7 = shr(wdata, 8) wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_1 : UInt<8> connect _newCfg_WIRE_1, _newCfg_T_7 node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) connect newCfg_1.r, _newCfg_T_8 node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) connect newCfg_1.w, _newCfg_T_9 node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) connect newCfg_1.x, _newCfg_T_10 node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) connect newCfg_1.a, _newCfg_T_11 node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) connect newCfg_1.res, _newCfg_T_12 node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) connect newCfg_1.l, _newCfg_T_13 connect reg_pmp[1].cfg, newCfg_1 node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T node _T_1743 = bits(reg_pmp[2].cfg.a, 1, 1) node _T_1744 = eq(_T_1743, UInt<1>(0h0)) node _T_1745 = bits(reg_pmp[2].cfg.a, 0, 0) node _T_1746 = and(_T_1744, _T_1745) node _T_1747 = and(reg_pmp[2].cfg.l, _T_1746) node _T_1748 = or(reg_pmp[1].cfg.l, _T_1747) node _T_1749 = eq(_T_1748, UInt<1>(0h0)) node _T_1750 = and(decoded_addr_8_2, _T_1749) when _T_1750 : connect reg_pmp[1].addr, wdata node _T_1751 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) node _T_1752 = and(decoded_addr_141_2, _T_1751) when _T_1752 : node _newCfg_T_14 = shr(wdata, 16) wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_2 : UInt<8> connect _newCfg_WIRE_2, _newCfg_T_14 node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) connect newCfg_2.r, _newCfg_T_15 node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) connect newCfg_2.w, _newCfg_T_16 node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) connect newCfg_2.x, _newCfg_T_17 node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) connect newCfg_2.a, _newCfg_T_18 node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) connect newCfg_2.res, _newCfg_T_19 node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) connect newCfg_2.l, _newCfg_T_20 connect reg_pmp[2].cfg, newCfg_2 node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T node _T_1753 = bits(reg_pmp[3].cfg.a, 1, 1) node _T_1754 = eq(_T_1753, UInt<1>(0h0)) node _T_1755 = bits(reg_pmp[3].cfg.a, 0, 0) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = and(reg_pmp[3].cfg.l, _T_1756) node _T_1758 = or(reg_pmp[2].cfg.l, _T_1757) node _T_1759 = eq(_T_1758, UInt<1>(0h0)) node _T_1760 = and(decoded_addr_125_2, _T_1759) when _T_1760 : connect reg_pmp[2].addr, wdata node _T_1761 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) node _T_1762 = and(decoded_addr_141_2, _T_1761) when _T_1762 : node _newCfg_T_21 = shr(wdata, 24) wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_3 : UInt<8> connect _newCfg_WIRE_3, _newCfg_T_21 node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) connect newCfg_3.r, _newCfg_T_22 node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) connect newCfg_3.w, _newCfg_T_23 node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) connect newCfg_3.x, _newCfg_T_24 node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) connect newCfg_3.a, _newCfg_T_25 node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) connect newCfg_3.res, _newCfg_T_26 node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) connect newCfg_3.l, _newCfg_T_27 connect reg_pmp[3].cfg, newCfg_3 node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T node _T_1763 = bits(reg_pmp[4].cfg.a, 1, 1) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) node _T_1765 = bits(reg_pmp[4].cfg.a, 0, 0) node _T_1766 = and(_T_1764, _T_1765) node _T_1767 = and(reg_pmp[4].cfg.l, _T_1766) node _T_1768 = or(reg_pmp[3].cfg.l, _T_1767) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) node _T_1770 = and(decoded_addr_85_2, _T_1769) when _T_1770 : connect reg_pmp[3].addr, wdata node _T_1771 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) node _T_1772 = and(decoded_addr_141_2, _T_1771) when _T_1772 : node _newCfg_T_28 = shr(wdata, 32) wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_4 : UInt<8> connect _newCfg_WIRE_4, _newCfg_T_28 node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) connect newCfg_4.r, _newCfg_T_29 node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) connect newCfg_4.w, _newCfg_T_30 node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) connect newCfg_4.x, _newCfg_T_31 node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) connect newCfg_4.a, _newCfg_T_32 node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) connect newCfg_4.res, _newCfg_T_33 node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) connect newCfg_4.l, _newCfg_T_34 connect reg_pmp[4].cfg, newCfg_4 node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T node _T_1773 = bits(reg_pmp[5].cfg.a, 1, 1) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) node _T_1775 = bits(reg_pmp[5].cfg.a, 0, 0) node _T_1776 = and(_T_1774, _T_1775) node _T_1777 = and(reg_pmp[5].cfg.l, _T_1776) node _T_1778 = or(reg_pmp[4].cfg.l, _T_1777) node _T_1779 = eq(_T_1778, UInt<1>(0h0)) node _T_1780 = and(decoded_addr_54_2, _T_1779) when _T_1780 : connect reg_pmp[4].addr, wdata node _T_1781 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) node _T_1782 = and(decoded_addr_141_2, _T_1781) when _T_1782 : node _newCfg_T_35 = shr(wdata, 40) wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_5 : UInt<8> connect _newCfg_WIRE_5, _newCfg_T_35 node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) connect newCfg_5.r, _newCfg_T_36 node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) connect newCfg_5.w, _newCfg_T_37 node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) connect newCfg_5.x, _newCfg_T_38 node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) connect newCfg_5.a, _newCfg_T_39 node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) connect newCfg_5.res, _newCfg_T_40 node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) connect newCfg_5.l, _newCfg_T_41 connect reg_pmp[5].cfg, newCfg_5 node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T node _T_1783 = bits(reg_pmp[6].cfg.a, 1, 1) node _T_1784 = eq(_T_1783, UInt<1>(0h0)) node _T_1785 = bits(reg_pmp[6].cfg.a, 0, 0) node _T_1786 = and(_T_1784, _T_1785) node _T_1787 = and(reg_pmp[6].cfg.l, _T_1786) node _T_1788 = or(reg_pmp[5].cfg.l, _T_1787) node _T_1789 = eq(_T_1788, UInt<1>(0h0)) node _T_1790 = and(decoded_addr_20_2, _T_1789) when _T_1790 : connect reg_pmp[5].addr, wdata node _T_1791 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) node _T_1792 = and(decoded_addr_141_2, _T_1791) when _T_1792 : node _newCfg_T_42 = shr(wdata, 48) wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_6 : UInt<8> connect _newCfg_WIRE_6, _newCfg_T_42 node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) connect newCfg_6.r, _newCfg_T_43 node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) connect newCfg_6.w, _newCfg_T_44 node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) connect newCfg_6.x, _newCfg_T_45 node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) connect newCfg_6.a, _newCfg_T_46 node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) connect newCfg_6.res, _newCfg_T_47 node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) connect newCfg_6.l, _newCfg_T_48 connect reg_pmp[6].cfg, newCfg_6 node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T node _T_1793 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1794 = eq(_T_1793, UInt<1>(0h0)) node _T_1795 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1796 = and(_T_1794, _T_1795) node _T_1797 = and(reg_pmp[7].cfg.l, _T_1796) node _T_1798 = or(reg_pmp[6].cfg.l, _T_1797) node _T_1799 = eq(_T_1798, UInt<1>(0h0)) node _T_1800 = and(decoded_addr_135_2, _T_1799) when _T_1800 : connect reg_pmp[6].addr, wdata node _T_1801 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) node _T_1802 = and(decoded_addr_141_2, _T_1801) when _T_1802 : node _newCfg_T_49 = shr(wdata, 56) wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_7 : UInt<8> connect _newCfg_WIRE_7, _newCfg_T_49 node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) connect newCfg_7.r, _newCfg_T_50 node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) connect newCfg_7.w, _newCfg_T_51 node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) connect newCfg_7.x, _newCfg_T_52 node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) connect newCfg_7.a, _newCfg_T_53 node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) connect newCfg_7.res, _newCfg_T_54 node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) connect newCfg_7.l, _newCfg_T_55 connect reg_pmp[7].cfg, newCfg_7 node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T node _T_1803 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_1804 = eq(_T_1803, UInt<1>(0h0)) node _T_1805 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_1806 = and(_T_1804, _T_1805) node _T_1807 = and(reg_pmp[7].cfg.l, _T_1806) node _T_1808 = or(reg_pmp[7].cfg.l, _T_1807) node _T_1809 = eq(_T_1808, UInt<1>(0h0)) node _T_1810 = and(decoded_addr_115_2, _T_1809) when _T_1810 : connect reg_pmp[7].addr, wdata when decoded_addr_18_2 : node _reg_custom_0_T = and(wdata, UInt<64>(0h208)) node _reg_custom_0_T_1 = not(UInt<64>(0h208)) node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) connect reg_custom_0, _reg_custom_0_T_3 connect io.customCSRs[0].wen, UInt<1>(0h1) when decoded_addr_3_2 : node _reg_custom_1_T = and(wdata, UInt<64>(0h0)) node _reg_custom_1_T_1 = not(UInt<64>(0h0)) node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) connect reg_custom_1, _reg_custom_1_T_3 connect io.customCSRs[1].wen, UInt<1>(0h1) when decoded_addr_38_2 : node _reg_custom_2_T = and(wdata, UInt<64>(0h0)) node _reg_custom_2_T_1 = not(UInt<64>(0h0)) node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) connect reg_custom_2, _reg_custom_2_T_3 connect io.customCSRs[2].wen, UInt<1>(0h1) when decoded_addr_127_2 : node _reg_custom_3_T = and(wdata, UInt<64>(0h0)) node _reg_custom_3_T_1 = not(UInt<64>(0h0)) node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) connect reg_custom_3, _reg_custom_3_T_3 connect io.customCSRs[3].wen, UInt<1>(0h1) when io.customCSRs[0].set : node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h208)) node _reg_custom_0_T_5 = not(UInt<64>(0h208)) node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) connect reg_custom_0, _reg_custom_0_T_7 when io.customCSRs[1].set : node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0)) node _reg_custom_1_T_5 = not(UInt<64>(0h0)) node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) connect reg_custom_1, _reg_custom_1_T_7 when io.customCSRs[2].set : node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0)) node _reg_custom_2_T_5 = not(UInt<64>(0h0)) node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) connect reg_custom_2, _reg_custom_2_T_7 when io.customCSRs[3].set : node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0)) node _reg_custom_3_T_5 = not(UInt<64>(0h0)) node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) connect reg_custom_3, _reg_custom_3_T_7 node _T_1811 = asUInt(reset) when _T_1811 : connect reg_satp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_vsatp.ppn, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_hgatp.ppn, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_vsstatus.xs, UInt<1>(0h0) connect reg_tselect, UInt<1>(0h0) connect reg_bp[0].control.ttype, UInt<2>(0h2) connect reg_bp[0].control.maskmax, UInt<3>(0h4) connect reg_bp[0].control.reserved, UInt<1>(0h0) connect reg_bp[0].control.zero, UInt<1>(0h0) connect reg_bp[0].control.h, UInt<1>(0h0) node _T_1812 = asUInt(reset) when _T_1812 : connect reg_bp[0].control.action, UInt<1>(0h0) connect reg_bp[0].control.dmode, UInt<1>(0h0) connect reg_bp[0].control.chain, UInt<1>(0h0) connect reg_bp[0].control.r, UInt<1>(0h0) connect reg_bp[0].control.w, UInt<1>(0h0) connect reg_bp[0].control.x, UInt<1>(0h0) connect reg_bp[1].control.ttype, UInt<2>(0h2) connect reg_bp[1].control.maskmax, UInt<3>(0h4) connect reg_bp[1].control.reserved, UInt<1>(0h0) connect reg_bp[1].control.zero, UInt<1>(0h0) connect reg_bp[1].control.h, UInt<1>(0h0) node _T_1813 = asUInt(reset) when _T_1813 : connect reg_bp[1].control.action, UInt<1>(0h0) connect reg_bp[1].control.dmode, UInt<1>(0h0) connect reg_bp[1].control.chain, UInt<1>(0h0) connect reg_bp[1].control.r, UInt<1>(0h0) connect reg_bp[1].control.w, UInt<1>(0h0) connect reg_bp[1].control.x, UInt<1>(0h0) connect reg_bp[0].textra.mselect, UInt<1>(0h0) connect reg_bp[0].textra.sselect, UInt<1>(0h0) connect reg_bp[1].textra.mselect, UInt<1>(0h0) connect reg_bp[1].textra.sselect, UInt<1>(0h0) wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.svalue connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0) connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.mvalue connect _reg_bp_1_WIRE.address, UInt<39>(0h0) connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0) connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) connect reg_bp[1], _reg_bp_1_WIRE connect reg_pmp[0].cfg.res, UInt<1>(0h0) node _T_1814 = asUInt(reset) when _T_1814 : connect reg_pmp[0].cfg.a, UInt<1>(0h0) connect reg_pmp[0].cfg.l, UInt<1>(0h0) connect reg_pmp[1].cfg.res, UInt<1>(0h0) node _T_1815 = asUInt(reset) when _T_1815 : connect reg_pmp[1].cfg.a, UInt<1>(0h0) connect reg_pmp[1].cfg.l, UInt<1>(0h0) connect reg_pmp[2].cfg.res, UInt<1>(0h0) node _T_1816 = asUInt(reset) when _T_1816 : connect reg_pmp[2].cfg.a, UInt<1>(0h0) connect reg_pmp[2].cfg.l, UInt<1>(0h0) connect reg_pmp[3].cfg.res, UInt<1>(0h0) node _T_1817 = asUInt(reset) when _T_1817 : connect reg_pmp[3].cfg.a, UInt<1>(0h0) connect reg_pmp[3].cfg.l, UInt<1>(0h0) connect reg_pmp[4].cfg.res, UInt<1>(0h0) node _T_1818 = asUInt(reset) when _T_1818 : connect reg_pmp[4].cfg.a, UInt<1>(0h0) connect reg_pmp[4].cfg.l, UInt<1>(0h0) connect reg_pmp[5].cfg.res, UInt<1>(0h0) node _T_1819 = asUInt(reset) when _T_1819 : connect reg_pmp[5].cfg.a, UInt<1>(0h0) connect reg_pmp[5].cfg.l, UInt<1>(0h0) connect reg_pmp[6].cfg.res, UInt<1>(0h0) node _T_1820 = asUInt(reset) when _T_1820 : connect reg_pmp[6].cfg.a, UInt<1>(0h0) connect reg_pmp[6].cfg.l, UInt<1>(0h0) connect reg_pmp[7].cfg.res, UInt<1>(0h0) node _T_1821 = asUInt(reset) when _T_1821 : connect reg_pmp[7].cfg.a, UInt<1>(0h0) connect reg_pmp[7].cfg.l, UInt<1>(0h0) node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) connect io.trace[0].exception, _io_trace_0_exception_T_1 node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) connect io.trace[0].valid, _io_trace_0_valid_T_1 connect io.trace[0].insn, io.inst[0] connect io.trace[0].iaddr, io.pc node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) connect io.trace[0].priv, _io_trace_0_priv_T connect io.trace[0].cause, cause node _io_trace_0_interrupt_T = bits(cause, 63, 63) connect io.trace[0].interrupt, _io_trace_0_interrupt_T connect io.trace[0].tval, io.tval
module CSRFile( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_interrupts_seip, // @[CSR.scala:384:14] input io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [63:0] io_rw_rdata, // @[CSR.scala:384:14] input [63:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_fp_illegal, // @[CSR.scala:384:14] output io_decode_0_fp_csr, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output [1:0] io_status_dprv, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output [1:0] io_status_prv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_sd, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output io_status_tsr, // @[CSR.scala:384:14] output io_status_tw, // @[CSR.scala:384:14] output io_status_tvm, // @[CSR.scala:384:14] output io_status_mxr, // @[CSR.scala:384:14] output io_status_sum, // @[CSR.scala:384:14] output io_status_mprv, // @[CSR.scala:384:14] output [1:0] io_status_fs, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_spp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_spie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_status_sie, // @[CSR.scala:384:14] output io_hstatus_spvp, // @[CSR.scala:384:14] output io_hstatus_spv, // @[CSR.scala:384:14] output io_hstatus_gva, // @[CSR.scala:384:14] output io_gstatus_debug, // @[CSR.scala:384:14] output io_gstatus_cease, // @[CSR.scala:384:14] output io_gstatus_wfi, // @[CSR.scala:384:14] output [31:0] io_gstatus_isa, // @[CSR.scala:384:14] output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14] output io_gstatus_dv, // @[CSR.scala:384:14] output [1:0] io_gstatus_prv, // @[CSR.scala:384:14] output io_gstatus_v, // @[CSR.scala:384:14] output io_gstatus_sd, // @[CSR.scala:384:14] output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14] output io_gstatus_mpv, // @[CSR.scala:384:14] output io_gstatus_gva, // @[CSR.scala:384:14] output io_gstatus_mbe, // @[CSR.scala:384:14] output io_gstatus_sbe, // @[CSR.scala:384:14] output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14] output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14] output io_gstatus_tsr, // @[CSR.scala:384:14] output io_gstatus_tw, // @[CSR.scala:384:14] output io_gstatus_tvm, // @[CSR.scala:384:14] output io_gstatus_mxr, // @[CSR.scala:384:14] output io_gstatus_sum, // @[CSR.scala:384:14] output io_gstatus_mprv, // @[CSR.scala:384:14] output [1:0] io_gstatus_fs, // @[CSR.scala:384:14] output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14] output [1:0] io_gstatus_vs, // @[CSR.scala:384:14] output io_gstatus_spp, // @[CSR.scala:384:14] output io_gstatus_mpie, // @[CSR.scala:384:14] output io_gstatus_ube, // @[CSR.scala:384:14] output io_gstatus_spie, // @[CSR.scala:384:14] output io_gstatus_upie, // @[CSR.scala:384:14] output io_gstatus_mie, // @[CSR.scala:384:14] output io_gstatus_hie, // @[CSR.scala:384:14] output io_gstatus_sie, // @[CSR.scala:384:14] output io_gstatus_uie, // @[CSR.scala:384:14] output [3:0] io_ptbr_mode, // @[CSR.scala:384:14] output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14] output [39:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [63:0] io_cause, // @[CSR.scala:384:14] input [39:0] io_pc, // @[CSR.scala:384:14] input [39:0] io_tval, // @[CSR.scala:384:14] input [39:0] io_htval, // @[CSR.scala:384:14] input io_mhtinst_read_pseudo, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [63:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] input io_fcsr_flags_valid, // @[CSR.scala:384:14] input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [63:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_dmode, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_m, // @[CSR.scala:384:14] output io_bp_0_control_s, // @[CSR.scala:384:14] output io_bp_0_control_u, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [38:0] io_bp_0_address, // @[CSR.scala:384:14] output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14] output io_bp_0_textra_pad1, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output [2:0] io_trace_0_priv, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output io_trace_0_interrupt, // @[CSR.scala:384:14] output [63:0] io_trace_0_cause, // @[CSR.scala:384:14] output [39:0] io_trace_0_tval, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14] output io_customCSRs_2_ren, // @[CSR.scala:384:14] output io_customCSRs_2_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14] output io_customCSRs_3_ren, // @[CSR.scala:384:14] output io_customCSRs_3_wen, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14] output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14] ); wire io_status_sie_0; // @[CSR.scala:377:7] wire io_status_spie_0; // @[CSR.scala:377:7] wire io_status_spp_0; // @[CSR.scala:377:7] wire [1:0] io_status_fs_0; // @[CSR.scala:377:7] wire io_status_sum_0; // @[CSR.scala:377:7] wire io_status_mxr_0; // @[CSR.scala:377:7] wire io_status_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7] wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7] wire io_gva_0 = io_gva; // @[CSR.scala:377:7] wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7] wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_seip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_stip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire sup_ssip = 1'h1; // @[CSR.scala:406:19] wire del_seip = 1'h1; // @[CSR.scala:426:26] wire del_stip = 1'h1; // @[CSR.scala:426:26] wire del_ssip = 1'h1; // @[CSR.scala:426:26] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71] wire delegable_1 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71] wire delegable_5 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71] wire delegable_9 = 1'h1; // @[CSR.scala:1097:65] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_16 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_20 = 1'h1; // @[CSR.scala:1109:67] wire delegable_22 = 1'h1; // @[CSR.scala:1109:67] wire delegable_24 = 1'h1; // @[CSR.scala:1109:67] wire delegable_27 = 1'h1; // @[CSR.scala:1109:67] wire delegable_28 = 1'h1; // @[CSR.scala:1109:67] wire delegable_29 = 1'h1; // @[CSR.scala:1109:67] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48] wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48] wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48] wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35] wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16] wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_17 = 1'h0; // @[CSR.scala:1109:67] wire delegable_21 = 1'h0; // @[CSR.scala:1109:67] wire delegable_23 = 1'h0; // @[CSR.scala:1109:67] wire delegable_25 = 1'h0; // @[CSR.scala:1109:67] wire delegable_26 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35] wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48] wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48] wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48] wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_xs = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35] wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35] wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51] wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51] wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36] wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67] wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45] wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51] wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51] wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7] wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7] wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7] wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23] wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7] wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14] wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14] wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26] wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15] wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153] wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26] wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67] wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9] wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23] wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24] wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49] wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49] wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67] wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67] wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49] wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51] wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51] wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36] wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67] wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48] wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67] wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49] wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32] wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7] wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23] wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46] wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7] wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50] wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35] wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168] wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41] wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40] wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41] wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78] wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFFFEFD2; // @[CSR.scala:1263:75] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45] wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120] wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120] wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120] wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120] wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120] wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43] wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120] wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120] wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120] wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43] wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120] wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120] wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120] wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120] wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43] wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120] wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39] wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120] wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39] wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48] wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27] wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27] wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51] wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51] wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51] wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32] wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] delegable_interrupts = 16'h222; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h2; // @[CSR.scala:431:50] wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50] wire [15:0] supported_interrupts = 16'hAAA; // @[CSR.scala:431:17] wire [7:0] hi = 8'hA; // @[CSR.scala:431:10] wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10] wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45] wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120] wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120] wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120] wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120] wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120] wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120] wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120] wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120] wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120] wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120] wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120] wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120] wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120] wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120] wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120] wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50] wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45] wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28] wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73] wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91] wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_status_sd_T_4; // @[CSR.scala:1003:58] wire read_sstatus_sd = io_status_sd_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35] wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35] wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35] wire _io_gstatus_sd_T_4; // @[CSR.scala:1016:61] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7] wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7] wire [63:0] value_1; // @[Counters.scala:55:30] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [63:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [63:0] cause; // @[CSR.scala:959:8] wire _io_fiom_T_6; // @[CSR.scala:631:113] wire reg_custom_read; // @[CSR.scala:799:36] wire [63:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire reg_custom_read_2; // @[CSR.scala:799:36] wire reg_custom_read_3; // @[CSR.scala:799:36] wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [31:0] io_status_isa_0; // @[CSR.scala:377:7] wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire [1:0] io_status_prv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire io_status_tsr_0; // @[CSR.scala:377:7] wire io_status_tw_0; // @[CSR.scala:377:7] wire io_status_tvm_0; // @[CSR.scala:377:7] wire io_status_mprv_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_hstatus_spvp_0; // @[CSR.scala:377:7] wire io_hstatus_spv_0; // @[CSR.scala:377:7] wire io_hstatus_gva_0; // @[CSR.scala:377:7] wire io_gstatus_sd_0; // @[CSR.scala:377:7] wire io_gstatus_spp_0; // @[CSR.scala:377:7] wire io_gstatus_spie_0; // @[CSR.scala:377:7] wire io_gstatus_sie_0; // @[CSR.scala:377:7] wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7] wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7] wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7] wire io_bp_0_control_action_0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7] wire io_bp_0_control_m_0; // @[CSR.scala:377:7] wire io_bp_0_control_s_0; // @[CSR.scala:377:7] wire io_bp_0_control_u_0; // @[CSR.scala:377:7] wire io_bp_0_control_x_0; // @[CSR.scala:377:7] wire io_bp_0_control_w_0; // @[CSR.scala:377:7] wire io_bp_0_control_r_0; // @[CSR.scala:377:7] wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid_0; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7] wire io_trace_0_exception_0; // @[CSR.scala:377:7] wire io_trace_0_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7] wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7] wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret_0; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [39:0] io_evec_0; // @[CSR.scala:377:7] wire [63:0] io_time_0; // @[CSR.scala:377:7] wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle_0; // @[CSR.scala:377:7] wire io_fiom; // @[CSR.scala:377:7] reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28] assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tsr; // @[CSR.scala:395:28] assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tw; // @[CSR.scala:395:28] assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_tvm; // @[CSR.scala:395:28] assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mxr; // @[CSR.scala:395:28] assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sum; // @[CSR.scala:395:28] assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mprv; // @[CSR.scala:395:28] assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28] assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spp; // @[CSR.scala:395:28] assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_spie; // @[CSR.scala:395:28] assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_sie; // @[CSR.scala:395:28] assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28] wire [1:0] new_prv; // @[CSR.scala:397:28] wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35] wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg reg_dcsr_ebreaks; // @[CSR.scala:403:25] reg reg_dcsr_ebreaku; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [39:0] reg_dpc; // @[CSR.scala:483:20] reg [63:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_m; // @[CSR.scala:492:19] assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_s; // @[CSR.scala:492:19] assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_u; // @[CSR.scala:492:19] assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19] reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19] assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [63:0] reg_mie; // @[CSR.scala:495:20] reg [63:0] reg_mideleg; // @[CSR.scala:497:18] wire [63:0] read_mideleg = {54'h0, reg_mideleg[9:1] & 9'h111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}] reg [63:0] reg_medeleg; // @[CSR.scala:501:18] wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}] reg reg_mip_seip; // @[CSR.scala:504:20] reg reg_mip_stip; // @[CSR.scala:504:20] wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24] reg reg_mip_ssip; // @[CSR.scala:504:20] wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24] reg [39:0] reg_mepc; // @[CSR.scala:505:21] reg [63:0] reg_mcause; // @[CSR.scala:506:27] reg [39:0] reg_mtval; // @[CSR.scala:507:22] reg [39:0] reg_mtval2; // @[CSR.scala:508:23] reg [63:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] reg reg_menvcfg_fiom; // @[CSR.scala:525:28] reg reg_senvcfg_fiom; // @[CSR.scala:526:28] reg [31:0] reg_mcounteren; // @[CSR.scala:531:18] wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}] reg [31:0] reg_scounteren; // @[CSR.scala:535:18] wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}] reg reg_hstatus_spvp; // @[CSR.scala:552:28] assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_spv; // @[CSR.scala:552:28] assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28] reg reg_hstatus_gva; // @[CSR.scala:552:28] assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28] reg [39:0] reg_htval; // @[CSR.scala:554:22] wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27] assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59] assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27] assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27] wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59] assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27] wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27] assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27] wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59] assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_vsstatus_spp; // @[CSR.scala:562:25] assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_spie; // @[CSR.scala:562:25] assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25] reg reg_vsstatus_sie; // @[CSR.scala:562:25] assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25] reg [39:0] reg_vsepc; // @[CSR.scala:564:22] reg [63:0] reg_vscause; // @[CSR.scala:565:24] reg [39:0] reg_vstval; // @[CSR.scala:566:23] reg [39:0] reg_sepc; // @[CSR.scala:569:21] reg [63:0] reg_scause; // @[CSR.scala:570:23] reg [39:0] reg_stval; // @[CSR.scala:571:22] reg [63:0] reg_sscratch; // @[CSR.scala:572:25] reg [38:0] reg_stvec; // @[CSR.scala:573:22] reg [3:0] reg_satp_mode; // @[CSR.scala:574:21] assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21] reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21] assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg [4:0] reg_fflags; // @[CSR.scala:577:23] reg [2:0] reg_frm; // @[CSR.scala:578:20] assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] reg reg_htinst_read_pseudo; // @[CSR.scala:585:35] wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] assign io_time_0 = value_1; // @[Counters.scala:55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire _mip_seip_T; // @[CSR.scala:606:57] wire mip_seip; // @[CSR.scala:600:24] assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57] assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'hAAA; // @[CSR.scala:610:{22,29}] wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61] wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60] wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62] wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42] wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51] wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}] wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}] wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68] wire _s_interrupts_T; // @[CSR.scala:621:68] assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68] wire _vs_interrupts_T; // @[CSR.scala:622:70] assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70] wire _io_fiom_T_2; // @[CSR.scala:631:82] assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82] wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}] wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98] wire _s_interrupts_T_2; // @[CSR.scala:621:98] assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98] wire _vs_interrupts_T_1; // @[CSR.scala:622:99] assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99] wire _csr_addr_legal_T_4; // @[CSR.scala:921:62] assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62] wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}] wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151] wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}] wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}] wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}] wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}] wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}] wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76] wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76] wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76] wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76] wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76] wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76] wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76] wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76] wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76] wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76] wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76] wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76] wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76] wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76] wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76] wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76] wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}] wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}] wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}] wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}] wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}] wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}] wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}] wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}] wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}] wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}] wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}] wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}] wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}] wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}] wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}] wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70] wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31] wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}] wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}] wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}] assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}] assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] reg [63:0] reg_misa; // @[CSR.scala:648:25] wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h0, io_status_fs_0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32] wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32] wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32] wire [23:0] read_mstatus_hi_hi_lo_lo = {io_status_sd_0, 23'h0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35] wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41] wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}] wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}] wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35] wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}] wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35] wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48] assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67] assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67] wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48] wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48] assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67] assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48] assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67] assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67] wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48] wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48] wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48] wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48] assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48] wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67] assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48] assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48] wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67] assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67] wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48] wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48] wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48] assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48] wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67] assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67] wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48] wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48] wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48] wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38] wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}] wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47] wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47] wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}] wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}] wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38] wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}] wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27] wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27] wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38] wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}] wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}] wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22] wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49] wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49] wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18] wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28] wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29] wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51] wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51] wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51] wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51] wire [3:0] lo_hi_lo_hi = {2'h0, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51] wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51] wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51] wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51] wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51] wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51] wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51] wire [23:0] hi_hi_lo_lo = {read_sstatus_sd, 23'h0}; // @[CSR.scala:755:35, :768:51] wire [27:0] hi_hi_lo_4 = {4'h0, hi_hi_lo_lo}; // @[CSR.scala:768:51] wire [64:0] hi_hi_5 = {37'h0, hi_hi_lo_4}; // @[CSR.scala:768:51] wire [82:0] hi_7 = {hi_hi_5, 18'h800}; // @[CSR.scala:768:51] wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43] wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28] wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}] wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49] wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49] wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}] wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}] wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27] wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}] wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}] wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27] reg [63:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_2; // @[CSR.scala:798:43] assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36] reg [63:0] reg_custom_3; // @[CSR.scala:798:43] assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43] wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38] wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39] wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39] wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53] wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53] wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53] wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}] wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74] wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}] wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}] wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77] wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}] wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81] wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}] wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}] wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}] wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79] wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}] wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70] wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}] wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46] wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}] wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}] wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57] wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39] wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}] wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T | _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}] wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103] wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}] assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 | _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}] assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107] wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29] wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53] wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31] assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105] wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93] wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120; // @[CSR.scala:899:93] assign _csr_exists_T_120 = _GEN_14; // @[CSR.scala:899:93] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12] wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59] wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56] wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21] wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17] wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14] wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17] wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40] wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105] wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53] wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46] wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34] wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64] wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37] wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61] wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61] wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}] wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}] wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}] wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41] wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}] wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}] wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44] wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}] wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}] wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}] wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31] wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55] wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}] wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100] wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}] wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34] wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80] wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80] wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}] wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15] wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15] wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33] wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38] wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_19 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32] wire _io_status_sd_T_2 = _io_status_sd_T; // @[CSR.scala:1003:{32,37}] assign _io_status_sd_T_4 = _io_status_sd_T_2; // @[CSR.scala:1003:{37,58}] assign io_status_sd_0 = _io_status_sd_T_4; // @[CSR.scala:377:7, :1003:58] assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}] assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}] assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}] wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}] assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34] wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}] wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78] assign _io_gstatus_sd_T_4 = _io_gstatus_sd_T_2 | _io_gstatus_sd_T_3; // @[CSR.scala:1016:{39,61,78}] assign io_gstatus_sd_0 = _io_gstatus_sd_T_4; // @[CSR.scala:377:7, :1016:61] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37]
Generate the Verilog code corresponding to this FIRRTL code module Tile_154 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_410 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_154( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_410 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s1k3z4c_5 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn.e.bits.sink invalidate nodeIn.e.valid invalidate nodeIn.e.ready invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.c.bits.corrupt invalidate nodeIn.c.bits.data invalidate nodeIn.c.bits.address invalidate nodeIn.c.bits.source invalidate nodeIn.c.bits.size invalidate nodeIn.c.bits.param invalidate nodeIn.c.bits.opcode invalidate nodeIn.c.valid invalidate nodeIn.c.ready invalidate nodeIn.b.bits.corrupt invalidate nodeIn.b.bits.data invalidate nodeIn.b.bits.mask invalidate nodeIn.b.bits.address invalidate nodeIn.b.bits.source invalidate nodeIn.b.bits.size invalidate nodeIn.b.bits.param invalidate nodeIn.b.bits.opcode invalidate nodeIn.b.valid invalidate nodeIn.b.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_77 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink connect monitor.io.in.e.valid, nodeIn.e.valid connect monitor.io.in.e.ready, nodeIn.e.ready connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt connect monitor.io.in.c.bits.data, nodeIn.c.bits.data connect monitor.io.in.c.bits.address, nodeIn.c.bits.address connect monitor.io.in.c.bits.source, nodeIn.c.bits.source connect monitor.io.in.c.bits.size, nodeIn.c.bits.size connect monitor.io.in.c.bits.param, nodeIn.c.bits.param connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode connect monitor.io.in.c.valid, nodeIn.c.valid connect monitor.io.in.c.ready, nodeIn.c.ready connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt connect monitor.io.in.b.bits.data, nodeIn.b.bits.data connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask connect monitor.io.in.b.bits.address, nodeIn.b.bits.address connect monitor.io.in.b.bits.source, nodeIn.b.bits.source connect monitor.io.in.b.bits.size, nodeIn.b.bits.size connect monitor.io.in.b.bits.param, nodeIn.b.bits.param connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode connect monitor.io.in.b.valid, nodeIn.b.valid connect monitor.io.in.b.ready, nodeIn.b.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeOut.e.bits.sink invalidate nodeOut.e.valid invalidate nodeOut.e.ready invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.c.bits.corrupt invalidate nodeOut.c.bits.data invalidate nodeOut.c.bits.address invalidate nodeOut.c.bits.source invalidate nodeOut.c.bits.size invalidate nodeOut.c.bits.param invalidate nodeOut.c.bits.opcode invalidate nodeOut.c.valid invalidate nodeOut.c.ready invalidate nodeOut.b.bits.corrupt invalidate nodeOut.b.bits.data invalidate nodeOut.b.bits.mask invalidate nodeOut.b.bits.address invalidate nodeOut.b.bits.source invalidate nodeOut.b.bits.size invalidate nodeOut.b.bits.param invalidate nodeOut.b.bits.opcode invalidate nodeOut.b.valid invalidate nodeOut.b.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s1k3z4c_5 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s1k3z4c_5 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s1k3z4c_5 connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s1k3z4c_5 connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s1k3z4c_5 connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready
module TLBuffer_a32d64s1k3z4c_5( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25] input auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_b_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_e_ready, // @[LazyModuleImp.scala:107:25] output auto_out_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9] wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9] wire auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9] wire auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9] wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9] wire nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_b_ready; // @[MixedNode.scala:542:17] wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9] wire nodeOut_c_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9] wire nodeOut_e_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_e_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9] assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_77 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s1k3z4c_5 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s1k3z4c_5 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s1k3z4c_5 nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_b_ready), .io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17] .io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_b_valid), .io_deq_bits_opcode (nodeIn_b_bits_opcode), .io_deq_bits_param (nodeIn_b_bits_param), .io_deq_bits_size (nodeIn_b_bits_size), .io_deq_bits_source (nodeIn_b_bits_source), .io_deq_bits_address (nodeIn_b_bits_address), .io_deq_bits_mask (nodeIn_b_bits_mask), .io_deq_bits_data (nodeIn_b_bits_data), .io_deq_bits_corrupt (nodeIn_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s1k3z4c_5 nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_c_ready), .io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_c_valid), .io_deq_bits_opcode (nodeOut_c_bits_opcode), .io_deq_bits_param (nodeOut_c_bits_param), .io_deq_bits_size (nodeOut_c_bits_size), .io_deq_bits_source (nodeOut_c_bits_source), .io_deq_bits_address (nodeOut_c_bits_address), .io_deq_bits_data (nodeOut_c_bits_data), .io_deq_bits_corrupt (nodeOut_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s1k3z4c_5 nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_e_ready), .io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_e_valid), .io_deq_bits_sink (nodeOut_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ResetCatchAndSync_d3_4 : input clock : Clock input reset : Reset output io : { sync_reset : UInt<1>, flip psd : { test_mode : UInt<1>, test_mode_reset : UInt<1>}} node _post_psd_reset_T = asUInt(reset) node post_psd_reset = mux(io.psd.test_mode, io.psd.test_mode_reset, _post_psd_reset_T) inst io_sync_reset_chain of AsyncResetSynchronizerShiftReg_w1_d3_i0_199 connect io_sync_reset_chain.clock, clock connect io_sync_reset_chain.reset, post_psd_reset connect io_sync_reset_chain.io.d, UInt<1>(0h1) wire _io_sync_reset_WIRE : UInt<1> connect _io_sync_reset_WIRE, io_sync_reset_chain.io.q node _io_sync_reset_T = not(_io_sync_reset_WIRE) node _io_sync_reset_T_1 = mux(io.psd.test_mode, io.psd.test_mode_reset, _io_sync_reset_T) connect io.sync_reset, _io_sync_reset_T_1 extmodule ClockSourceAtFreqMHz : input power : UInt<1> input gate : UInt<1> output clk : Clock defname = ClockSourceAtFreqMHz parameter PERIOD = 2.0 extmodule ClockSourceAtFreqMHz_1 : input power : UInt<1> input gate : UInt<1> output clk : Clock defname = ClockSourceAtFreqMHz parameter PERIOD = 10.0
module ResetCatchAndSync_d3_4( // @[ResetCatchAndSync.scala:13:7] input clock, // @[ResetCatchAndSync.scala:13:7] input reset, // @[ResetCatchAndSync.scala:13:7] output io_sync_reset // @[ResetCatchAndSync.scala:17:14] ); wire _post_psd_reset_T = reset; // @[ResetCatchAndSync.scala:26:76] wire io_psd_test_mode = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire io_psd_test_mode_reset = 1'h0; // @[ResetCatchAndSync.scala:13:7, :17:14] wire _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:28:25] wire io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] wire post_psd_reset = _post_psd_reset_T; // @[ResetCatchAndSync.scala:26:{27,76}] wire _io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] wire _io_sync_reset_T = ~_io_sync_reset_WIRE; // @[ShiftReg.scala:48:24] assign _io_sync_reset_T_1 = _io_sync_reset_T; // @[ResetCatchAndSync.scala:28:25, :29:7] assign io_sync_reset_0 = _io_sync_reset_T_1; // @[ResetCatchAndSync.scala:13:7, :28:25] AsyncResetSynchronizerShiftReg_w1_d3_i0_199 io_sync_reset_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (post_psd_reset), // @[ResetCatchAndSync.scala:26:27] .io_q (_io_sync_reset_WIRE) ); // @[ShiftReg.scala:45:23] assign io_sync_reset = io_sync_reset_0; // @[ResetCatchAndSync.scala:13:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_206 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_206( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_11 : input clock : Clock input reset : Reset output io : { flip inR : { bits : UInt<32>}, flip inD : { bits : UInt<32>}, outL : { bits : UInt<32>}, outU : { bits : UInt<32>}, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : { bits : UInt<32>}, clock when io.en : connect reg.bits, _reg_T_1.bits connect io.outU, reg connect io.outL, reg
module PE_11( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [31:0] io_inR_bits, // @[Transposer.scala:101:16] input [31:0] io_inD_bits, // @[Transposer.scala:101:16] output [31:0] io_outL_bits, // @[Transposer.scala:101:16] output [31:0] io_outU_bits, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [31:0] io_inR_bits_0 = io_inR_bits; // @[Transposer.scala:100:9] wire [31:0] io_inD_bits_0 = io_inD_bits; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [31:0] io_outL_bits_0; // @[Transposer.scala:100:9] wire [31:0] io_outU_bits_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [31:0] _reg_T_1_bits = _reg_T ? io_inR_bits_0 : io_inD_bits_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [31:0] reg_bits; // @[Transposer.scala:110:24] assign io_outL_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] assign io_outU_bits_0 = reg_bits; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_bits <= _reg_T_1_bits; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL_bits = io_outL_bits_0; // @[Transposer.scala:100:9] assign io_outU_bits = io_outU_bits_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_61 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_61 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_61 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1b)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_10 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_11 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_12 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_13 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_14 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_15 : connect states[7].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) node _T_35 = or(_T_34, vcalloc_vals[6]) node _T_36 = or(_T_35, vcalloc_vals[7]) when _T_36 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_38 : UInt<3> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38 wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<2> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<5> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<2> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<5> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<3> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[3] invalidate vcalloc_reqs[0].vc_sel.`3`[4] invalidate vcalloc_reqs[0].vc_sel.`3`[5] invalidate vcalloc_reqs[0].vc_sel.`3`[6] invalidate vcalloc_reqs[0].vc_sel.`3`[7] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_37 = bits(vcalloc_sel, 1, 1) node _T_38 = and(vcalloc_vals[1], _T_37) node _T_39 = and(_T_38, io.vcalloc_req.ready) when _T_39 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_40 = bits(vcalloc_sel, 2, 2) node _T_41 = and(vcalloc_vals[2], _T_40) node _T_42 = and(_T_41, io.vcalloc_req.ready) when _T_42 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_43 = bits(vcalloc_sel, 3, 3) node _T_44 = and(vcalloc_vals[3], _T_43) node _T_45 = and(_T_44, io.vcalloc_req.ready) when _T_45 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_46 = bits(vcalloc_sel, 4, 4) node _T_47 = and(vcalloc_vals[4], _T_46) node _T_48 = and(_T_47, io.vcalloc_req.ready) when _T_48 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_49 = bits(vcalloc_sel, 5, 5) node _T_50 = and(vcalloc_vals[5], _T_49) node _T_51 = and(_T_50, io.vcalloc_req.ready) when _T_51 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].flow, states[6].flow node _T_52 = bits(vcalloc_sel, 6, 6) node _T_53 = and(vcalloc_vals[6], _T_52) node _T_54 = and(_T_53, io.vcalloc_req.ready) when _T_54 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].flow, states[7].flow node _T_55 = bits(vcalloc_sel, 7, 7) node _T_56 = and(vcalloc_vals[7], _T_55) node _T_57 = and(_T_56, io.vcalloc_req.ready) when _T_57 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_58 : node _T_59 = bits(vcalloc_sel, 0, 0) when _T_59 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_60 = eq(states[0].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_60, UInt<1>(0h1), "") : assert_3 node _T_64 = bits(vcalloc_sel, 1, 1) when _T_64 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_65 = eq(states[1].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_65, UInt<1>(0h1), "") : assert_4 node _T_69 = bits(vcalloc_sel, 2, 2) when _T_69 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_70 = eq(states[2].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _T_74 = bits(vcalloc_sel, 3, 3) when _T_74 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_75 = eq(states[3].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_75, UInt<1>(0h1), "") : assert_6 node _T_79 = bits(vcalloc_sel, 4, 4) when _T_79 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_80 = eq(states[4].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_80, UInt<1>(0h1), "") : assert_7 node _T_84 = bits(vcalloc_sel, 5, 5) when _T_84 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_85 = eq(states[5].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_85, UInt<1>(0h1), "") : assert_8 node _T_89 = bits(vcalloc_sel, 6, 6) when _T_89 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].g, UInt<3>(0h3) node _T_90 = eq(states[6].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = bits(vcalloc_sel, 7, 7) when _T_94 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].g, UInt<3>(0h3) node _T_95 = eq(states[7].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_95, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_153 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7] node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5) node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail) when _T_100 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11) node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11) node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail) when _T_102 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23) node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27) node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail) when _T_104 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33) node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35) node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35) node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38) node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42) node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail) when _T_106 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44) node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47) node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49) node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53) node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail) when _T_108 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57) node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60) node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62) node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64) node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail) when _T_110 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48) node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49) node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50) node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51) node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66) node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68) node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52) node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53) node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54) node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55) node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73) node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69) node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75) node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail) when _T_112 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34) node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_38 node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_113 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`3`[3] invalidate states[0].vc_sel.`3`[4] invalidate states[0].vc_sel.`3`[5] invalidate states[0].vc_sel.`3`[6] invalidate states[0].vc_sel.`3`[7] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[3], UInt<1>(0h0) connect states[2].vc_sel.`2`[4], UInt<1>(0h0) connect states[2].vc_sel.`2`[5], UInt<1>(0h0) connect states[2].vc_sel.`2`[6], UInt<1>(0h0) connect states[2].vc_sel.`2`[7], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[2], UInt<1>(0h0) connect states[3].vc_sel.`2`[3], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[2], UInt<1>(0h0) connect states[4].vc_sel.`2`[3], UInt<1>(0h0) connect states[4].vc_sel.`2`[4], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[2], UInt<1>(0h0) connect states[5].vc_sel.`2`[3], UInt<1>(0h0) connect states[5].vc_sel.`2`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[5], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[2], UInt<1>(0h0) connect states[6].vc_sel.`2`[3], UInt<1>(0h0) connect states[6].vc_sel.`2`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[5], UInt<1>(0h0) connect states[6].vc_sel.`2`[6], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[2], UInt<1>(0h0) connect states[7].vc_sel.`2`[3], UInt<1>(0h0) connect states[7].vc_sel.`2`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[5], UInt<1>(0h0) connect states[7].vc_sel.`2`[6], UInt<1>(0h0) connect states[7].vc_sel.`2`[7], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_114 = asUInt(reset) when _T_114 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)
module InputUnit_61( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e5_s11_8 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_8 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e5_s11_8( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [6:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [13:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_detectTininess, // @[RoundAnyRawFNToRecFN.scala:299:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [6:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [13:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess_0 = io_detectTininess; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie5_is13_oe5_os11_8 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_detectTininess (io_detectTininess_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_59 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 13, 0) node _source_ok_T = shr(io.in.a.bits.source, 14) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<14>(0h200f)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits = bits(_uncommonBits_T, 13, 0) node _T_4 = shr(io.in.a.bits.source, 14) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<14>(0h200f)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 13, 0) node _T_24 = shr(io.in.a.bits.source, 14) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<14>(0h200f)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<17>(0h10000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 13, 0) node _T_86 = shr(io.in.a.bits.source, 14) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<14>(0h200f)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<17>(0h10000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<17>(0h10000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 13, 0) node _T_152 = shr(io.in.a.bits.source, 14) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<14>(0h200f)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<17>(0h10000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 13, 0) node _T_199 = shr(io.in.a.bits.source, 14) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<14>(0h200f)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<17>(0h10000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = and(_T_207, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = and(_T_206, _T_214) node _T_216 = asUInt(reset) node _T_217 = eq(_T_216, UInt<1>(0h0)) when _T_217 : node _T_218 = eq(_T_215, UInt<1>(0h0)) when _T_218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_215, UInt<1>(0h1), "") : assert_26 node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(is_aligned, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_225 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(io.in.a.bits.mask, mask) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_229, UInt<1>(0h1), "") : assert_30 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 13, 0) node _T_237 = shr(io.in.a.bits.source, 14) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_5) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_5, UInt<14>(0h200f)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<17>(0h10000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = and(_T_245, _T_250) node _T_252 = or(UInt<1>(0h0), _T_251) node _T_253 = and(_T_244, _T_252) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_253, UInt<1>(0h1), "") : assert_31 node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_263 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_263, UInt<1>(0h1), "") : assert_34 node _T_267 = not(mask) node _T_268 = and(io.in.a.bits.mask, _T_267) node _T_269 = eq(_T_268, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_269, UInt<1>(0h1), "") : assert_35 node _T_273 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_273 : node _T_274 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_275 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_276 = and(_T_274, _T_275) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 13, 0) node _T_277 = shr(io.in.a.bits.source, 14) node _T_278 = eq(_T_277, UInt<1>(0h0)) node _T_279 = leq(UInt<1>(0h0), uncommonBits_6) node _T_280 = and(_T_278, _T_279) node _T_281 = leq(uncommonBits_6, UInt<14>(0h200f)) node _T_282 = and(_T_280, _T_281) node _T_283 = and(_T_276, _T_282) node _T_284 = or(UInt<1>(0h0), _T_283) node _T_285 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_286 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_287 = cvt(_T_286) node _T_288 = and(_T_287, asSInt(UInt<17>(0h10000))) node _T_289 = asSInt(_T_288) node _T_290 = eq(_T_289, asSInt(UInt<1>(0h0))) node _T_291 = and(_T_285, _T_290) node _T_292 = or(UInt<1>(0h0), _T_291) node _T_293 = and(_T_284, _T_292) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_293, UInt<1>(0h1), "") : assert_36 node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(is_aligned, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_303 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_304 = asUInt(reset) node _T_305 = eq(_T_304, UInt<1>(0h0)) when _T_305 : node _T_306 = eq(_T_303, UInt<1>(0h0)) when _T_306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_303, UInt<1>(0h1), "") : assert_39 node _T_307 = eq(io.in.a.bits.mask, mask) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_307, UInt<1>(0h1), "") : assert_40 node _T_311 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_311 : node _T_312 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_313 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_314 = and(_T_312, _T_313) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 13, 0) node _T_315 = shr(io.in.a.bits.source, 14) node _T_316 = eq(_T_315, UInt<1>(0h0)) node _T_317 = leq(UInt<1>(0h0), uncommonBits_7) node _T_318 = and(_T_316, _T_317) node _T_319 = leq(uncommonBits_7, UInt<14>(0h200f)) node _T_320 = and(_T_318, _T_319) node _T_321 = and(_T_314, _T_320) node _T_322 = or(UInt<1>(0h0), _T_321) node _T_323 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_324 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<17>(0h10000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = and(_T_323, _T_328) node _T_330 = or(UInt<1>(0h0), _T_329) node _T_331 = and(_T_322, _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_331, UInt<1>(0h1), "") : assert_41 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(is_aligned, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_341 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_342 = asUInt(reset) node _T_343 = eq(_T_342, UInt<1>(0h0)) when _T_343 : node _T_344 = eq(_T_341, UInt<1>(0h0)) when _T_344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_341, UInt<1>(0h1), "") : assert_44 node _T_345 = eq(io.in.a.bits.mask, mask) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_345, UInt<1>(0h1), "") : assert_45 node _T_349 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_349 : node _T_350 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_351 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_352 = and(_T_350, _T_351) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<14>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 13, 0) node _T_353 = shr(io.in.a.bits.source, 14) node _T_354 = eq(_T_353, UInt<1>(0h0)) node _T_355 = leq(UInt<1>(0h0), uncommonBits_8) node _T_356 = and(_T_354, _T_355) node _T_357 = leq(uncommonBits_8, UInt<14>(0h200f)) node _T_358 = and(_T_356, _T_357) node _T_359 = and(_T_352, _T_358) node _T_360 = or(UInt<1>(0h0), _T_359) node _T_361 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = and(_T_361, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = and(_T_360, _T_368) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_369, UInt<1>(0h1), "") : assert_46 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(is_aligned, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_379 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_379, UInt<1>(0h1), "") : assert_49 node _T_383 = eq(io.in.a.bits.mask, mask) node _T_384 = asUInt(reset) node _T_385 = eq(_T_384, UInt<1>(0h0)) when _T_385 : node _T_386 = eq(_T_383, UInt<1>(0h0)) when _T_386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_383, UInt<1>(0h1), "") : assert_50 node _T_387 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_387, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_391 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_T_391, UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_391, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<14>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 13, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 14) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<14>(0h200f)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_395 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_395 : node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_399 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_399, UInt<1>(0h1), "") : assert_54 node _T_403 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_403, UInt<1>(0h1), "") : assert_55 node _T_407 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_407, UInt<1>(0h1), "") : assert_56 node _T_411 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_411, UInt<1>(0h1), "") : assert_57 node _T_415 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_415 : node _T_416 = asUInt(reset) node _T_417 = eq(_T_416, UInt<1>(0h0)) when _T_417 : node _T_418 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(sink_ok, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_422 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_422, UInt<1>(0h1), "") : assert_60 node _T_426 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(_T_426, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_426, UInt<1>(0h1), "") : assert_61 node _T_430 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_430, UInt<1>(0h1), "") : assert_62 node _T_434 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_434, UInt<1>(0h1), "") : assert_63 node _T_438 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_439, UInt<1>(0h1), "") : assert_64 node _T_443 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_443 : node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(sink_ok, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_450 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_450, UInt<1>(0h1), "") : assert_67 node _T_454 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_454, UInt<1>(0h1), "") : assert_68 node _T_458 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_459 = asUInt(reset) node _T_460 = eq(_T_459, UInt<1>(0h0)) when _T_460 : node _T_461 = eq(_T_458, UInt<1>(0h0)) when _T_461 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_458, UInt<1>(0h1), "") : assert_69 node _T_462 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_463 = or(_T_462, io.in.d.bits.corrupt) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_463, UInt<1>(0h1), "") : assert_70 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_468, UInt<1>(0h1), "") : assert_71 node _T_472 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_472 : node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_476 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_476, UInt<1>(0h1), "") : assert_73 node _T_480 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_480, UInt<1>(0h1), "") : assert_74 node _T_484 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_485, UInt<1>(0h1), "") : assert_75 node _T_489 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_493 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_494 = asUInt(reset) node _T_495 = eq(_T_494, UInt<1>(0h0)) when _T_495 : node _T_496 = eq(_T_493, UInt<1>(0h0)) when _T_496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_493, UInt<1>(0h1), "") : assert_77 node _T_497 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_498 = or(_T_497, io.in.d.bits.corrupt) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_498, UInt<1>(0h1), "") : assert_78 node _T_502 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_503, UInt<1>(0h1), "") : assert_79 node _T_507 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_507 : node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_511 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_512 = asUInt(reset) node _T_513 = eq(_T_512, UInt<1>(0h0)) when _T_513 : node _T_514 = eq(_T_511, UInt<1>(0h0)) when _T_514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_511, UInt<1>(0h1), "") : assert_81 node _T_515 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(_T_515, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_515, UInt<1>(0h1), "") : assert_82 node _T_519 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_520 = or(UInt<1>(0h0), _T_519) node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(_T_520, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_520, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<14>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<14>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_524 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_524, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<14>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_528 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_528, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_532 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_532, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(UInt<1>(0h0), a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_536 = eq(a_first, UInt<1>(0h0)) node _T_537 = and(io.in.a.valid, _T_536) when _T_537 : node _T_538 = eq(io.in.a.bits.opcode, opcode) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_538, UInt<1>(0h1), "") : assert_87 node _T_542 = eq(io.in.a.bits.param, param) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_542, UInt<1>(0h1), "") : assert_88 node _T_546 = eq(io.in.a.bits.size, size) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_546, UInt<1>(0h1), "") : assert_89 node _T_550 = eq(io.in.a.bits.source, source) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_550, UInt<1>(0h1), "") : assert_90 node _T_554 = eq(io.in.a.bits.address, address) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_554, UInt<1>(0h1), "") : assert_91 node _T_558 = and(io.in.a.ready, io.in.a.valid) node _T_559 = and(_T_558, a_first) when _T_559 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(UInt<1>(0h1), d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_560 = eq(d_first, UInt<1>(0h0)) node _T_561 = and(io.in.d.valid, _T_560) when _T_561 : node _T_562 = eq(io.in.d.bits.opcode, opcode_1) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_562, UInt<1>(0h1), "") : assert_92 node _T_566 = eq(io.in.d.bits.param, param_1) node _T_567 = asUInt(reset) node _T_568 = eq(_T_567, UInt<1>(0h0)) when _T_568 : node _T_569 = eq(_T_566, UInt<1>(0h0)) when _T_569 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_566, UInt<1>(0h1), "") : assert_93 node _T_570 = eq(io.in.d.bits.size, size_1) node _T_571 = asUInt(reset) node _T_572 = eq(_T_571, UInt<1>(0h0)) when _T_572 : node _T_573 = eq(_T_570, UInt<1>(0h0)) when _T_573 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_570, UInt<1>(0h1), "") : assert_94 node _T_574 = eq(io.in.d.bits.source, source_1) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_574, UInt<1>(0h1), "") : assert_95 node _T_578 = eq(io.in.d.bits.sink, sink) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_578, UInt<1>(0h1), "") : assert_96 node _T_582 = eq(io.in.d.bits.denied, denied) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_582, UInt<1>(0h1), "") : assert_97 node _T_586 = and(io.in.d.ready, io.in.d.valid) node _T_587 = and(_T_586, d_first) when _T_587 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes : UInt<32832>, clock, reset, UInt<32832>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(UInt<1>(0h0), a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(UInt<1>(0h1), d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<8208> connect a_set, UInt<8208>(0h0) wire a_set_wo_ready : UInt<8208> connect a_set_wo_ready, UInt<8208>(0h0) wire a_opcodes_set : UInt<32832> connect a_opcodes_set, UInt<32832>(0h0) wire a_sizes_set : UInt<32832> connect a_sizes_set, UInt<32832>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_588 = and(io.in.a.valid, a_first_1) node _T_589 = and(_T_588, UInt<1>(0h1)) when _T_589 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_590 = and(io.in.a.ready, io.in.a.valid) node _T_591 = and(_T_590, a_first_1) node _T_592 = and(_T_591, UInt<1>(0h1)) when _T_592 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_593 = dshr(inflight, io.in.a.bits.source) node _T_594 = bits(_T_593, 0, 0) node _T_595 = eq(_T_594, UInt<1>(0h0)) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_595, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<8208> connect d_clr, UInt<8208>(0h0) wire d_clr_wo_ready : UInt<8208> connect d_clr_wo_ready, UInt<8208>(0h0) wire d_opcodes_clr : UInt<32832> connect d_opcodes_clr, UInt<32832>(0h0) wire d_sizes_clr : UInt<32832> connect d_sizes_clr, UInt<32832>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_599 = and(io.in.d.valid, d_first_1) node _T_600 = and(_T_599, UInt<1>(0h1)) node _T_601 = eq(d_release_ack, UInt<1>(0h0)) node _T_602 = and(_T_600, _T_601) when _T_602 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_603 = and(io.in.d.ready, io.in.d.valid) node _T_604 = and(_T_603, d_first_1) node _T_605 = and(_T_604, UInt<1>(0h1)) node _T_606 = eq(d_release_ack, UInt<1>(0h0)) node _T_607 = and(_T_605, _T_606) when _T_607 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_608 = and(io.in.d.valid, d_first_1) node _T_609 = and(_T_608, UInt<1>(0h1)) node _T_610 = eq(d_release_ack, UInt<1>(0h0)) node _T_611 = and(_T_609, _T_610) when _T_611 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_612 = dshr(inflight, io.in.d.bits.source) node _T_613 = bits(_T_612, 0, 0) node _T_614 = or(_T_613, same_cycle_resp) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_614, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_618 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_619 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_620 = or(_T_618, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_620, UInt<1>(0h1), "") : assert_100 node _T_624 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_624, UInt<1>(0h1), "") : assert_101 else : node _T_628 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_629 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_630 = or(_T_628, _T_629) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_630, UInt<1>(0h1), "") : assert_102 node _T_634 = eq(io.in.d.bits.size, a_size_lookup) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_634, UInt<1>(0h1), "") : assert_103 node _T_638 = and(io.in.d.valid, d_first_1) node _T_639 = and(_T_638, a_first_1) node _T_640 = and(_T_639, io.in.a.valid) node _T_641 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_642 = and(_T_640, _T_641) node _T_643 = eq(d_release_ack, UInt<1>(0h0)) node _T_644 = and(_T_642, _T_643) when _T_644 : node _T_645 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_646 = or(_T_645, io.in.a.ready) node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(_T_646, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_646, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_119 node _T_650 = orr(inflight) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_653 = or(_T_651, _T_652) node _T_654 = lt(watchdog, plusarg_reader.out) node _T_655 = or(_T_653, _T_654) node _T_656 = asUInt(reset) node _T_657 = eq(_T_656, UInt<1>(0h0)) when _T_657 : node _T_658 = eq(_T_655, UInt<1>(0h0)) when _T_658 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_655, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_659 = and(io.in.a.ready, io.in.a.valid) node _T_660 = and(io.in.d.ready, io.in.d.valid) node _T_661 = or(_T_659, _T_660) when _T_661 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<8208>, clock, reset, UInt<8208>(0h0) regreset inflight_opcodes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) regreset inflight_sizes_1 : UInt<32832>, clock, reset, UInt<32832>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<17>(0h0) connect _c_first_WIRE.bits.source, UInt<14>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<17>(0h0) connect _c_first_WIRE_2.bits.source, UInt<14>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(UInt<1>(0h1), d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<8208> connect c_set, UInt<8208>(0h0) wire c_set_wo_ready : UInt<8208> connect c_set_wo_ready, UInt<8208>(0h0) wire c_opcodes_set : UInt<32832> connect c_opcodes_set, UInt<32832>(0h0) wire c_sizes_set : UInt<32832> connect c_sizes_set, UInt<32832>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<17>(0h0) connect _WIRE_6.bits.source, UInt<14>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_662 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<17>(0h0) connect _WIRE_8.bits.source, UInt<14>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_663 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_664 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_665 = and(_T_663, _T_664) node _T_666 = and(_T_662, _T_665) when _T_666 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<17>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<17>(0h0) connect _WIRE_10.bits.source, UInt<14>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_667 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_668 = and(_T_667, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<17>(0h0) connect _WIRE_12.bits.source, UInt<14>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_669 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_670 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_671 = and(_T_669, _T_670) node _T_672 = and(_T_668, _T_671) when _T_672 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<17>(0h0) connect _c_set_WIRE.bits.source, UInt<14>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<17>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<17>(0h0) connect _WIRE_14.bits.source, UInt<14>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_673 = dshr(inflight_1, _WIRE_15.bits.source) node _T_674 = bits(_T_673, 0, 0) node _T_675 = eq(_T_674, UInt<1>(0h0)) node _T_676 = asUInt(reset) node _T_677 = eq(_T_676, UInt<1>(0h0)) when _T_677 : node _T_678 = eq(_T_675, UInt<1>(0h0)) when _T_678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_675, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<17>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<8208> connect d_clr_1, UInt<8208>(0h0) wire d_clr_wo_ready_1 : UInt<8208> connect d_clr_wo_ready_1, UInt<8208>(0h0) wire d_opcodes_clr_1 : UInt<32832> connect d_opcodes_clr_1, UInt<32832>(0h0) wire d_sizes_clr_1 : UInt<32832> connect d_sizes_clr_1, UInt<32832>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_679 = and(io.in.d.valid, d_first_2) node _T_680 = and(_T_679, UInt<1>(0h1)) node _T_681 = and(_T_680, d_release_ack_1) when _T_681 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_682 = and(io.in.d.ready, io.in.d.valid) node _T_683 = and(_T_682, d_first_2) node _T_684 = and(_T_683, UInt<1>(0h1)) node _T_685 = and(_T_684, d_release_ack_1) when _T_685 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_686 = and(io.in.d.valid, d_first_2) node _T_687 = and(_T_686, UInt<1>(0h1)) node _T_688 = and(_T_687, d_release_ack_1) when _T_688 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<17>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_689 = dshr(inflight_1, io.in.d.bits.source) node _T_690 = bits(_T_689, 0, 0) node _T_691 = or(_T_690, same_cycle_resp_1) node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(_T_691, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_691, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<17>(0h0) connect _WIRE_16.bits.source, UInt<14>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_695 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_696 = asUInt(reset) node _T_697 = eq(_T_696, UInt<1>(0h0)) when _T_697 : node _T_698 = eq(_T_695, UInt<1>(0h0)) when _T_698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_695, UInt<1>(0h1), "") : assert_108 else : node _T_699 = eq(io.in.d.bits.size, c_size_lookup) node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(_T_699, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_699, UInt<1>(0h1), "") : assert_109 node _T_703 = and(io.in.d.valid, d_first_2) node _T_704 = and(_T_703, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<17>(0h0) connect _WIRE_18.bits.source, UInt<14>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_705 = and(_T_704, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<17>(0h0) connect _WIRE_20.bits.source, UInt<14>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_706 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_707 = and(_T_705, _T_706) node _T_708 = and(_T_707, d_release_ack_1) node _T_709 = eq(c_probe_ack, UInt<1>(0h0)) node _T_710 = and(_T_708, _T_709) when _T_710 : node _T_711 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<17>(0h0) connect _WIRE_22.bits.source, UInt<14>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_712 = or(_T_711, _WIRE_23.ready) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_120 node _T_716 = orr(inflight_1) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_719 = or(_T_717, _T_718) node _T_720 = lt(watchdog_1, plusarg_reader_1.out) node _T_721 = or(_T_719, _T_720) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BootROM.scala:89:18)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_721, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<17>(0h0) connect _WIRE_24.bits.source, UInt<14>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<14>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_725 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_726 = and(io.in.d.ready, io.in.d.valid) node _T_727 = or(_T_725, _T_726) when _T_727 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_59( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [16:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [13:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [1:0] size; // @[Monitor.scala:389:22] reg [13:0] source; // @[Monitor.scala:390:22] reg [16:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [1:0] size_1; // @[Monitor.scala:540:22] reg [13:0] source_1; // @[Monitor.scala:541:22] reg [8207:0] inflight; // @[Monitor.scala:614:27] reg [32831:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [32831:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire _GEN = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] reg [31:0] watchdog; // @[Monitor.scala:709:27]
Generate the Verilog code corresponding to this FIRRTL code module CtlPath : input clock : Clock input reset : Reset output io : { flip dcpath : { halt : UInt<1>}, imem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, dmem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip dat : { inst : UInt<32>, imiss : UInt<1>, br_eq : UInt<1>, br_lt : UInt<1>, br_ltu : UInt<1>, csr_eret : UInt<1>, csr_interrupt : UInt<1>, inst_misaligned : UInt<1>, mem_address_low : UInt<3>}, ctl : { stall : UInt<1>, dmiss : UInt<1>, pc_sel : UInt<3>, op1_sel : UInt<2>, op2_sel : UInt<2>, alu_fun : UInt<4>, wb_sel : UInt<2>, rf_wen : UInt<1>, csr_cmd : UInt<3>, exception : UInt<1>, exception_cause : UInt<32>, pc_sel_no_xept : UInt<3>}} invalidate io.ctl.pc_sel_no_xept invalidate io.ctl.exception_cause invalidate io.ctl.exception invalidate io.ctl.csr_cmd invalidate io.ctl.rf_wen invalidate io.ctl.wb_sel invalidate io.ctl.alu_fun invalidate io.ctl.op2_sel invalidate io.ctl.op1_sel invalidate io.ctl.pc_sel invalidate io.ctl.dmiss invalidate io.ctl.stall invalidate io.dat.mem_address_low invalidate io.dat.inst_misaligned invalidate io.dat.csr_interrupt invalidate io.dat.csr_eret invalidate io.dat.br_ltu invalidate io.dat.br_lt invalidate io.dat.br_eq invalidate io.dat.imiss invalidate io.dat.inst invalidate io.dmem.resp.bits.data invalidate io.dmem.resp.valid invalidate io.dmem.req.bits.typ invalidate io.dmem.req.bits.fcn invalidate io.dmem.req.bits.data invalidate io.dmem.req.bits.addr invalidate io.dmem.req.valid invalidate io.dmem.req.ready invalidate io.imem.resp.bits.data invalidate io.imem.resp.valid invalidate io.imem.req.bits.typ invalidate io.imem.req.bits.fcn invalidate io.imem.req.bits.data invalidate io.imem.req.bits.addr invalidate io.imem.req.valid invalidate io.imem.req.ready invalidate io.dcpath.halt node _csignals_T = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_1 = eq(UInt<14>(0h2003), _csignals_T) node _csignals_T_2 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_3 = eq(UInt<2>(0h3), _csignals_T_2) node _csignals_T_4 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_5 = eq(UInt<15>(0h4003), _csignals_T_4) node _csignals_T_6 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_7 = eq(UInt<13>(0h1003), _csignals_T_6) node _csignals_T_8 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_9 = eq(UInt<15>(0h5003), _csignals_T_8) node _csignals_T_10 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_11 = eq(UInt<14>(0h2023), _csignals_T_10) node _csignals_T_12 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_13 = eq(UInt<6>(0h23), _csignals_T_12) node _csignals_T_14 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_15 = eq(UInt<13>(0h1023), _csignals_T_14) node _csignals_T_16 = and(io.dat.inst, UInt<7>(0h7f)) node _csignals_T_17 = eq(UInt<5>(0h17), _csignals_T_16) node _csignals_T_18 = and(io.dat.inst, UInt<7>(0h7f)) node _csignals_T_19 = eq(UInt<6>(0h37), _csignals_T_18) node _csignals_T_20 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_21 = eq(UInt<5>(0h13), _csignals_T_20) node _csignals_T_22 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_23 = eq(UInt<15>(0h7013), _csignals_T_22) node _csignals_T_24 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_25 = eq(UInt<15>(0h6013), _csignals_T_24) node _csignals_T_26 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_27 = eq(UInt<15>(0h4013), _csignals_T_26) node _csignals_T_28 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_29 = eq(UInt<14>(0h2013), _csignals_T_28) node _csignals_T_30 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_31 = eq(UInt<14>(0h3013), _csignals_T_30) node _csignals_T_32 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_33 = eq(UInt<13>(0h1013), _csignals_T_32) node _csignals_T_34 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_35 = eq(UInt<31>(0h40005013), _csignals_T_34) node _csignals_T_36 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_37 = eq(UInt<15>(0h5013), _csignals_T_36) node _csignals_T_38 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_39 = eq(UInt<13>(0h1033), _csignals_T_38) node _csignals_T_40 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_41 = eq(UInt<6>(0h33), _csignals_T_40) node _csignals_T_42 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_43 = eq(UInt<31>(0h40000033), _csignals_T_42) node _csignals_T_44 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_45 = eq(UInt<14>(0h2033), _csignals_T_44) node _csignals_T_46 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_47 = eq(UInt<14>(0h3033), _csignals_T_46) node _csignals_T_48 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_49 = eq(UInt<15>(0h7033), _csignals_T_48) node _csignals_T_50 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_51 = eq(UInt<15>(0h6033), _csignals_T_50) node _csignals_T_52 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_53 = eq(UInt<15>(0h4033), _csignals_T_52) node _csignals_T_54 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_55 = eq(UInt<31>(0h40005033), _csignals_T_54) node _csignals_T_56 = and(io.dat.inst, UInt<32>(0hfe00707f)) node _csignals_T_57 = eq(UInt<15>(0h5033), _csignals_T_56) node _csignals_T_58 = and(io.dat.inst, UInt<7>(0h7f)) node _csignals_T_59 = eq(UInt<7>(0h6f), _csignals_T_58) node _csignals_T_60 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_61 = eq(UInt<7>(0h67), _csignals_T_60) node _csignals_T_62 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_63 = eq(UInt<7>(0h63), _csignals_T_62) node _csignals_T_64 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_65 = eq(UInt<13>(0h1063), _csignals_T_64) node _csignals_T_66 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_67 = eq(UInt<15>(0h5063), _csignals_T_66) node _csignals_T_68 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_69 = eq(UInt<15>(0h7063), _csignals_T_68) node _csignals_T_70 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_71 = eq(UInt<15>(0h4063), _csignals_T_70) node _csignals_T_72 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_73 = eq(UInt<15>(0h6063), _csignals_T_72) node _csignals_T_74 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_75 = eq(UInt<15>(0h5073), _csignals_T_74) node _csignals_T_76 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_77 = eq(UInt<15>(0h6073), _csignals_T_76) node _csignals_T_78 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_79 = eq(UInt<15>(0h7073), _csignals_T_78) node _csignals_T_80 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_81 = eq(UInt<13>(0h1073), _csignals_T_80) node _csignals_T_82 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_83 = eq(UInt<14>(0h2073), _csignals_T_82) node _csignals_T_84 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_85 = eq(UInt<14>(0h3073), _csignals_T_84) node _csignals_T_86 = and(io.dat.inst, UInt<32>(0hffffffff)) node _csignals_T_87 = eq(UInt<7>(0h73), _csignals_T_86) node _csignals_T_88 = and(io.dat.inst, UInt<32>(0hffffffff)) node _csignals_T_89 = eq(UInt<30>(0h30200073), _csignals_T_88) node _csignals_T_90 = and(io.dat.inst, UInt<32>(0hffffffff)) node _csignals_T_91 = eq(UInt<31>(0h7b200073), _csignals_T_90) node _csignals_T_92 = and(io.dat.inst, UInt<32>(0hffffffff)) node _csignals_T_93 = eq(UInt<21>(0h100073), _csignals_T_92) node _csignals_T_94 = and(io.dat.inst, UInt<32>(0hffffffff)) node _csignals_T_95 = eq(UInt<29>(0h10500073), _csignals_T_94) node _csignals_T_96 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_97 = eq(UInt<13>(0h100f), _csignals_T_96) node _csignals_T_98 = and(io.dat.inst, UInt<15>(0h707f)) node _csignals_T_99 = eq(UInt<4>(0hf), _csignals_T_98) node _csignals_T_100 = mux(_csignals_T_99, UInt<1>(0h1), UInt<1>(0h0)) node _csignals_T_101 = mux(_csignals_T_97, UInt<1>(0h1), _csignals_T_100) node _csignals_T_102 = mux(_csignals_T_95, UInt<1>(0h1), _csignals_T_101) node _csignals_T_103 = mux(_csignals_T_93, UInt<1>(0h1), _csignals_T_102) node _csignals_T_104 = mux(_csignals_T_91, UInt<1>(0h1), _csignals_T_103) node _csignals_T_105 = mux(_csignals_T_89, UInt<1>(0h1), _csignals_T_104) node _csignals_T_106 = mux(_csignals_T_87, UInt<1>(0h1), _csignals_T_105) node _csignals_T_107 = mux(_csignals_T_85, UInt<1>(0h1), _csignals_T_106) node _csignals_T_108 = mux(_csignals_T_83, UInt<1>(0h1), _csignals_T_107) node _csignals_T_109 = mux(_csignals_T_81, UInt<1>(0h1), _csignals_T_108) node _csignals_T_110 = mux(_csignals_T_79, UInt<1>(0h1), _csignals_T_109) node _csignals_T_111 = mux(_csignals_T_77, UInt<1>(0h1), _csignals_T_110) node _csignals_T_112 = mux(_csignals_T_75, UInt<1>(0h1), _csignals_T_111) node _csignals_T_113 = mux(_csignals_T_73, UInt<1>(0h1), _csignals_T_112) node _csignals_T_114 = mux(_csignals_T_71, UInt<1>(0h1), _csignals_T_113) node _csignals_T_115 = mux(_csignals_T_69, UInt<1>(0h1), _csignals_T_114) node _csignals_T_116 = mux(_csignals_T_67, UInt<1>(0h1), _csignals_T_115) node _csignals_T_117 = mux(_csignals_T_65, UInt<1>(0h1), _csignals_T_116) node _csignals_T_118 = mux(_csignals_T_63, UInt<1>(0h1), _csignals_T_117) node _csignals_T_119 = mux(_csignals_T_61, UInt<1>(0h1), _csignals_T_118) node _csignals_T_120 = mux(_csignals_T_59, UInt<1>(0h1), _csignals_T_119) node _csignals_T_121 = mux(_csignals_T_57, UInt<1>(0h1), _csignals_T_120) node _csignals_T_122 = mux(_csignals_T_55, UInt<1>(0h1), _csignals_T_121) node _csignals_T_123 = mux(_csignals_T_53, UInt<1>(0h1), _csignals_T_122) node _csignals_T_124 = mux(_csignals_T_51, UInt<1>(0h1), _csignals_T_123) node _csignals_T_125 = mux(_csignals_T_49, UInt<1>(0h1), _csignals_T_124) node _csignals_T_126 = mux(_csignals_T_47, UInt<1>(0h1), _csignals_T_125) node _csignals_T_127 = mux(_csignals_T_45, UInt<1>(0h1), _csignals_T_126) node _csignals_T_128 = mux(_csignals_T_43, UInt<1>(0h1), _csignals_T_127) node _csignals_T_129 = mux(_csignals_T_41, UInt<1>(0h1), _csignals_T_128) node _csignals_T_130 = mux(_csignals_T_39, UInt<1>(0h1), _csignals_T_129) node _csignals_T_131 = mux(_csignals_T_37, UInt<1>(0h1), _csignals_T_130) node _csignals_T_132 = mux(_csignals_T_35, UInt<1>(0h1), _csignals_T_131) node _csignals_T_133 = mux(_csignals_T_33, UInt<1>(0h1), _csignals_T_132) node _csignals_T_134 = mux(_csignals_T_31, UInt<1>(0h1), _csignals_T_133) node _csignals_T_135 = mux(_csignals_T_29, UInt<1>(0h1), _csignals_T_134) node _csignals_T_136 = mux(_csignals_T_27, UInt<1>(0h1), _csignals_T_135) node _csignals_T_137 = mux(_csignals_T_25, UInt<1>(0h1), _csignals_T_136) node _csignals_T_138 = mux(_csignals_T_23, UInt<1>(0h1), _csignals_T_137) node _csignals_T_139 = mux(_csignals_T_21, UInt<1>(0h1), _csignals_T_138) node _csignals_T_140 = mux(_csignals_T_19, UInt<1>(0h1), _csignals_T_139) node _csignals_T_141 = mux(_csignals_T_17, UInt<1>(0h1), _csignals_T_140) node _csignals_T_142 = mux(_csignals_T_15, UInt<1>(0h1), _csignals_T_141) node _csignals_T_143 = mux(_csignals_T_13, UInt<1>(0h1), _csignals_T_142) node _csignals_T_144 = mux(_csignals_T_11, UInt<1>(0h1), _csignals_T_143) node _csignals_T_145 = mux(_csignals_T_9, UInt<1>(0h1), _csignals_T_144) node _csignals_T_146 = mux(_csignals_T_7, UInt<1>(0h1), _csignals_T_145) node _csignals_T_147 = mux(_csignals_T_5, UInt<1>(0h1), _csignals_T_146) node _csignals_T_148 = mux(_csignals_T_3, UInt<1>(0h1), _csignals_T_147) node csignals_0 = mux(_csignals_T_1, UInt<1>(0h1), _csignals_T_148) node _csignals_T_149 = mux(_csignals_T_99, UInt<4>(0h0), UInt<4>(0h0)) node _csignals_T_150 = mux(_csignals_T_97, UInt<4>(0h0), _csignals_T_149) node _csignals_T_151 = mux(_csignals_T_95, UInt<4>(0h0), _csignals_T_150) node _csignals_T_152 = mux(_csignals_T_93, UInt<4>(0h0), _csignals_T_151) node _csignals_T_153 = mux(_csignals_T_91, UInt<4>(0h0), _csignals_T_152) node _csignals_T_154 = mux(_csignals_T_89, UInt<4>(0h0), _csignals_T_153) node _csignals_T_155 = mux(_csignals_T_87, UInt<4>(0h0), _csignals_T_154) node _csignals_T_156 = mux(_csignals_T_85, UInt<4>(0h0), _csignals_T_155) node _csignals_T_157 = mux(_csignals_T_83, UInt<4>(0h0), _csignals_T_156) node _csignals_T_158 = mux(_csignals_T_81, UInt<4>(0h0), _csignals_T_157) node _csignals_T_159 = mux(_csignals_T_79, UInt<4>(0h0), _csignals_T_158) node _csignals_T_160 = mux(_csignals_T_77, UInt<4>(0h0), _csignals_T_159) node _csignals_T_161 = mux(_csignals_T_75, UInt<4>(0h0), _csignals_T_160) node _csignals_T_162 = mux(_csignals_T_73, UInt<4>(0h6), _csignals_T_161) node _csignals_T_163 = mux(_csignals_T_71, UInt<4>(0h5), _csignals_T_162) node _csignals_T_164 = mux(_csignals_T_69, UInt<4>(0h4), _csignals_T_163) node _csignals_T_165 = mux(_csignals_T_67, UInt<4>(0h3), _csignals_T_164) node _csignals_T_166 = mux(_csignals_T_65, UInt<4>(0h1), _csignals_T_165) node _csignals_T_167 = mux(_csignals_T_63, UInt<4>(0h2), _csignals_T_166) node _csignals_T_168 = mux(_csignals_T_61, UInt<4>(0h8), _csignals_T_167) node _csignals_T_169 = mux(_csignals_T_59, UInt<4>(0h7), _csignals_T_168) node _csignals_T_170 = mux(_csignals_T_57, UInt<4>(0h0), _csignals_T_169) node _csignals_T_171 = mux(_csignals_T_55, UInt<4>(0h0), _csignals_T_170) node _csignals_T_172 = mux(_csignals_T_53, UInt<4>(0h0), _csignals_T_171) node _csignals_T_173 = mux(_csignals_T_51, UInt<4>(0h0), _csignals_T_172) node _csignals_T_174 = mux(_csignals_T_49, UInt<4>(0h0), _csignals_T_173) node _csignals_T_175 = mux(_csignals_T_47, UInt<4>(0h0), _csignals_T_174) node _csignals_T_176 = mux(_csignals_T_45, UInt<4>(0h0), _csignals_T_175) node _csignals_T_177 = mux(_csignals_T_43, UInt<4>(0h0), _csignals_T_176) node _csignals_T_178 = mux(_csignals_T_41, UInt<4>(0h0), _csignals_T_177) node _csignals_T_179 = mux(_csignals_T_39, UInt<4>(0h0), _csignals_T_178) node _csignals_T_180 = mux(_csignals_T_37, UInt<4>(0h0), _csignals_T_179) node _csignals_T_181 = mux(_csignals_T_35, UInt<4>(0h0), _csignals_T_180) node _csignals_T_182 = mux(_csignals_T_33, UInt<4>(0h0), _csignals_T_181) node _csignals_T_183 = mux(_csignals_T_31, UInt<4>(0h0), _csignals_T_182) node _csignals_T_184 = mux(_csignals_T_29, UInt<4>(0h0), _csignals_T_183) node _csignals_T_185 = mux(_csignals_T_27, UInt<4>(0h0), _csignals_T_184) node _csignals_T_186 = mux(_csignals_T_25, UInt<4>(0h0), _csignals_T_185) node _csignals_T_187 = mux(_csignals_T_23, UInt<4>(0h0), _csignals_T_186) node _csignals_T_188 = mux(_csignals_T_21, UInt<4>(0h0), _csignals_T_187) node _csignals_T_189 = mux(_csignals_T_19, UInt<4>(0h0), _csignals_T_188) node _csignals_T_190 = mux(_csignals_T_17, UInt<4>(0h0), _csignals_T_189) node _csignals_T_191 = mux(_csignals_T_15, UInt<4>(0h0), _csignals_T_190) node _csignals_T_192 = mux(_csignals_T_13, UInt<4>(0h0), _csignals_T_191) node _csignals_T_193 = mux(_csignals_T_11, UInt<4>(0h0), _csignals_T_192) node _csignals_T_194 = mux(_csignals_T_9, UInt<4>(0h0), _csignals_T_193) node _csignals_T_195 = mux(_csignals_T_7, UInt<4>(0h0), _csignals_T_194) node _csignals_T_196 = mux(_csignals_T_5, UInt<4>(0h0), _csignals_T_195) node _csignals_T_197 = mux(_csignals_T_3, UInt<4>(0h0), _csignals_T_196) node csignals_1 = mux(_csignals_T_1, UInt<4>(0h0), _csignals_T_197) node _csignals_T_198 = mux(_csignals_T_99, UInt<2>(0h0), UInt<2>(0h0)) node _csignals_T_199 = mux(_csignals_T_97, UInt<2>(0h0), _csignals_T_198) node _csignals_T_200 = mux(_csignals_T_95, UInt<2>(0h0), _csignals_T_199) node _csignals_T_201 = mux(_csignals_T_93, UInt<2>(0h0), _csignals_T_200) node _csignals_T_202 = mux(_csignals_T_91, UInt<2>(0h0), _csignals_T_201) node _csignals_T_203 = mux(_csignals_T_89, UInt<2>(0h0), _csignals_T_202) node _csignals_T_204 = mux(_csignals_T_87, UInt<2>(0h0), _csignals_T_203) node _csignals_T_205 = mux(_csignals_T_85, UInt<2>(0h0), _csignals_T_204) node _csignals_T_206 = mux(_csignals_T_83, UInt<2>(0h0), _csignals_T_205) node _csignals_T_207 = mux(_csignals_T_81, UInt<2>(0h0), _csignals_T_206) node _csignals_T_208 = mux(_csignals_T_79, UInt<2>(0h2), _csignals_T_207) node _csignals_T_209 = mux(_csignals_T_77, UInt<2>(0h2), _csignals_T_208) node _csignals_T_210 = mux(_csignals_T_75, UInt<2>(0h2), _csignals_T_209) node _csignals_T_211 = mux(_csignals_T_73, UInt<2>(0h0), _csignals_T_210) node _csignals_T_212 = mux(_csignals_T_71, UInt<2>(0h0), _csignals_T_211) node _csignals_T_213 = mux(_csignals_T_69, UInt<2>(0h0), _csignals_T_212) node _csignals_T_214 = mux(_csignals_T_67, UInt<2>(0h0), _csignals_T_213) node _csignals_T_215 = mux(_csignals_T_65, UInt<2>(0h0), _csignals_T_214) node _csignals_T_216 = mux(_csignals_T_63, UInt<2>(0h0), _csignals_T_215) node _csignals_T_217 = mux(_csignals_T_61, UInt<2>(0h0), _csignals_T_216) node _csignals_T_218 = mux(_csignals_T_59, UInt<2>(0h0), _csignals_T_217) node _csignals_T_219 = mux(_csignals_T_57, UInt<2>(0h0), _csignals_T_218) node _csignals_T_220 = mux(_csignals_T_55, UInt<2>(0h0), _csignals_T_219) node _csignals_T_221 = mux(_csignals_T_53, UInt<2>(0h0), _csignals_T_220) node _csignals_T_222 = mux(_csignals_T_51, UInt<2>(0h0), _csignals_T_221) node _csignals_T_223 = mux(_csignals_T_49, UInt<2>(0h0), _csignals_T_222) node _csignals_T_224 = mux(_csignals_T_47, UInt<2>(0h0), _csignals_T_223) node _csignals_T_225 = mux(_csignals_T_45, UInt<2>(0h0), _csignals_T_224) node _csignals_T_226 = mux(_csignals_T_43, UInt<2>(0h0), _csignals_T_225) node _csignals_T_227 = mux(_csignals_T_41, UInt<2>(0h0), _csignals_T_226) node _csignals_T_228 = mux(_csignals_T_39, UInt<2>(0h0), _csignals_T_227) node _csignals_T_229 = mux(_csignals_T_37, UInt<2>(0h0), _csignals_T_228) node _csignals_T_230 = mux(_csignals_T_35, UInt<2>(0h0), _csignals_T_229) node _csignals_T_231 = mux(_csignals_T_33, UInt<2>(0h0), _csignals_T_230) node _csignals_T_232 = mux(_csignals_T_31, UInt<2>(0h0), _csignals_T_231) node _csignals_T_233 = mux(_csignals_T_29, UInt<2>(0h0), _csignals_T_232) node _csignals_T_234 = mux(_csignals_T_27, UInt<2>(0h0), _csignals_T_233) node _csignals_T_235 = mux(_csignals_T_25, UInt<2>(0h0), _csignals_T_234) node _csignals_T_236 = mux(_csignals_T_23, UInt<2>(0h0), _csignals_T_235) node _csignals_T_237 = mux(_csignals_T_21, UInt<2>(0h0), _csignals_T_236) node _csignals_T_238 = mux(_csignals_T_19, UInt<2>(0h1), _csignals_T_237) node _csignals_T_239 = mux(_csignals_T_17, UInt<2>(0h1), _csignals_T_238) node _csignals_T_240 = mux(_csignals_T_15, UInt<2>(0h0), _csignals_T_239) node _csignals_T_241 = mux(_csignals_T_13, UInt<2>(0h0), _csignals_T_240) node _csignals_T_242 = mux(_csignals_T_11, UInt<2>(0h0), _csignals_T_241) node _csignals_T_243 = mux(_csignals_T_9, UInt<2>(0h0), _csignals_T_242) node _csignals_T_244 = mux(_csignals_T_7, UInt<2>(0h0), _csignals_T_243) node _csignals_T_245 = mux(_csignals_T_5, UInt<2>(0h0), _csignals_T_244) node _csignals_T_246 = mux(_csignals_T_3, UInt<2>(0h0), _csignals_T_245) node csignals_2 = mux(_csignals_T_1, UInt<2>(0h0), _csignals_T_246) node _csignals_T_247 = mux(_csignals_T_99, UInt<2>(0h0), UInt<2>(0h0)) node _csignals_T_248 = mux(_csignals_T_97, UInt<2>(0h0), _csignals_T_247) node _csignals_T_249 = mux(_csignals_T_95, UInt<2>(0h0), _csignals_T_248) node _csignals_T_250 = mux(_csignals_T_93, UInt<2>(0h0), _csignals_T_249) node _csignals_T_251 = mux(_csignals_T_91, UInt<2>(0h0), _csignals_T_250) node _csignals_T_252 = mux(_csignals_T_89, UInt<2>(0h0), _csignals_T_251) node _csignals_T_253 = mux(_csignals_T_87, UInt<2>(0h0), _csignals_T_252) node _csignals_T_254 = mux(_csignals_T_85, UInt<2>(0h0), _csignals_T_253) node _csignals_T_255 = mux(_csignals_T_83, UInt<2>(0h0), _csignals_T_254) node _csignals_T_256 = mux(_csignals_T_81, UInt<2>(0h0), _csignals_T_255) node _csignals_T_257 = mux(_csignals_T_79, UInt<2>(0h0), _csignals_T_256) node _csignals_T_258 = mux(_csignals_T_77, UInt<2>(0h0), _csignals_T_257) node _csignals_T_259 = mux(_csignals_T_75, UInt<2>(0h0), _csignals_T_258) node _csignals_T_260 = mux(_csignals_T_73, UInt<2>(0h0), _csignals_T_259) node _csignals_T_261 = mux(_csignals_T_71, UInt<2>(0h0), _csignals_T_260) node _csignals_T_262 = mux(_csignals_T_69, UInt<2>(0h0), _csignals_T_261) node _csignals_T_263 = mux(_csignals_T_67, UInt<2>(0h0), _csignals_T_262) node _csignals_T_264 = mux(_csignals_T_65, UInt<2>(0h0), _csignals_T_263) node _csignals_T_265 = mux(_csignals_T_63, UInt<2>(0h0), _csignals_T_264) node _csignals_T_266 = mux(_csignals_T_61, UInt<2>(0h1), _csignals_T_265) node _csignals_T_267 = mux(_csignals_T_59, UInt<2>(0h0), _csignals_T_266) node _csignals_T_268 = mux(_csignals_T_57, UInt<2>(0h0), _csignals_T_267) node _csignals_T_269 = mux(_csignals_T_55, UInt<2>(0h0), _csignals_T_268) node _csignals_T_270 = mux(_csignals_T_53, UInt<2>(0h0), _csignals_T_269) node _csignals_T_271 = mux(_csignals_T_51, UInt<2>(0h0), _csignals_T_270) node _csignals_T_272 = mux(_csignals_T_49, UInt<2>(0h0), _csignals_T_271) node _csignals_T_273 = mux(_csignals_T_47, UInt<2>(0h0), _csignals_T_272) node _csignals_T_274 = mux(_csignals_T_45, UInt<2>(0h0), _csignals_T_273) node _csignals_T_275 = mux(_csignals_T_43, UInt<2>(0h0), _csignals_T_274) node _csignals_T_276 = mux(_csignals_T_41, UInt<2>(0h0), _csignals_T_275) node _csignals_T_277 = mux(_csignals_T_39, UInt<2>(0h0), _csignals_T_276) node _csignals_T_278 = mux(_csignals_T_37, UInt<2>(0h1), _csignals_T_277) node _csignals_T_279 = mux(_csignals_T_35, UInt<2>(0h1), _csignals_T_278) node _csignals_T_280 = mux(_csignals_T_33, UInt<2>(0h1), _csignals_T_279) node _csignals_T_281 = mux(_csignals_T_31, UInt<2>(0h1), _csignals_T_280) node _csignals_T_282 = mux(_csignals_T_29, UInt<2>(0h1), _csignals_T_281) node _csignals_T_283 = mux(_csignals_T_27, UInt<2>(0h1), _csignals_T_282) node _csignals_T_284 = mux(_csignals_T_25, UInt<2>(0h1), _csignals_T_283) node _csignals_T_285 = mux(_csignals_T_23, UInt<2>(0h1), _csignals_T_284) node _csignals_T_286 = mux(_csignals_T_21, UInt<2>(0h1), _csignals_T_285) node _csignals_T_287 = mux(_csignals_T_19, UInt<2>(0h0), _csignals_T_286) node _csignals_T_288 = mux(_csignals_T_17, UInt<2>(0h3), _csignals_T_287) node _csignals_T_289 = mux(_csignals_T_15, UInt<2>(0h2), _csignals_T_288) node _csignals_T_290 = mux(_csignals_T_13, UInt<2>(0h2), _csignals_T_289) node _csignals_T_291 = mux(_csignals_T_11, UInt<2>(0h2), _csignals_T_290) node _csignals_T_292 = mux(_csignals_T_9, UInt<2>(0h1), _csignals_T_291) node _csignals_T_293 = mux(_csignals_T_7, UInt<2>(0h1), _csignals_T_292) node _csignals_T_294 = mux(_csignals_T_5, UInt<2>(0h1), _csignals_T_293) node _csignals_T_295 = mux(_csignals_T_3, UInt<2>(0h1), _csignals_T_294) node csignals_3 = mux(_csignals_T_1, UInt<2>(0h1), _csignals_T_295) node _csignals_T_296 = mux(_csignals_T_99, UInt<4>(0h0), UInt<4>(0h0)) node _csignals_T_297 = mux(_csignals_T_97, UInt<4>(0h0), _csignals_T_296) node _csignals_T_298 = mux(_csignals_T_95, UInt<4>(0h0), _csignals_T_297) node _csignals_T_299 = mux(_csignals_T_93, UInt<4>(0h0), _csignals_T_298) node _csignals_T_300 = mux(_csignals_T_91, UInt<4>(0h0), _csignals_T_299) node _csignals_T_301 = mux(_csignals_T_89, UInt<4>(0h0), _csignals_T_300) node _csignals_T_302 = mux(_csignals_T_87, UInt<4>(0h0), _csignals_T_301) node _csignals_T_303 = mux(_csignals_T_85, UInt<4>(0hb), _csignals_T_302) node _csignals_T_304 = mux(_csignals_T_83, UInt<4>(0hb), _csignals_T_303) node _csignals_T_305 = mux(_csignals_T_81, UInt<4>(0hb), _csignals_T_304) node _csignals_T_306 = mux(_csignals_T_79, UInt<4>(0hb), _csignals_T_305) node _csignals_T_307 = mux(_csignals_T_77, UInt<4>(0hb), _csignals_T_306) node _csignals_T_308 = mux(_csignals_T_75, UInt<4>(0hb), _csignals_T_307) node _csignals_T_309 = mux(_csignals_T_73, UInt<4>(0h0), _csignals_T_308) node _csignals_T_310 = mux(_csignals_T_71, UInt<4>(0h0), _csignals_T_309) node _csignals_T_311 = mux(_csignals_T_69, UInt<4>(0h0), _csignals_T_310) node _csignals_T_312 = mux(_csignals_T_67, UInt<4>(0h0), _csignals_T_311) node _csignals_T_313 = mux(_csignals_T_65, UInt<4>(0h0), _csignals_T_312) node _csignals_T_314 = mux(_csignals_T_63, UInt<4>(0h0), _csignals_T_313) node _csignals_T_315 = mux(_csignals_T_61, UInt<4>(0h0), _csignals_T_314) node _csignals_T_316 = mux(_csignals_T_59, UInt<4>(0h0), _csignals_T_315) node _csignals_T_317 = mux(_csignals_T_57, UInt<4>(0h4), _csignals_T_316) node _csignals_T_318 = mux(_csignals_T_55, UInt<4>(0h5), _csignals_T_317) node _csignals_T_319 = mux(_csignals_T_53, UInt<4>(0h8), _csignals_T_318) node _csignals_T_320 = mux(_csignals_T_51, UInt<4>(0h7), _csignals_T_319) node _csignals_T_321 = mux(_csignals_T_49, UInt<4>(0h6), _csignals_T_320) node _csignals_T_322 = mux(_csignals_T_47, UInt<4>(0ha), _csignals_T_321) node _csignals_T_323 = mux(_csignals_T_45, UInt<4>(0h9), _csignals_T_322) node _csignals_T_324 = mux(_csignals_T_43, UInt<4>(0h2), _csignals_T_323) node _csignals_T_325 = mux(_csignals_T_41, UInt<4>(0h1), _csignals_T_324) node _csignals_T_326 = mux(_csignals_T_39, UInt<4>(0h3), _csignals_T_325) node _csignals_T_327 = mux(_csignals_T_37, UInt<4>(0h4), _csignals_T_326) node _csignals_T_328 = mux(_csignals_T_35, UInt<4>(0h5), _csignals_T_327) node _csignals_T_329 = mux(_csignals_T_33, UInt<4>(0h3), _csignals_T_328) node _csignals_T_330 = mux(_csignals_T_31, UInt<4>(0ha), _csignals_T_329) node _csignals_T_331 = mux(_csignals_T_29, UInt<4>(0h9), _csignals_T_330) node _csignals_T_332 = mux(_csignals_T_27, UInt<4>(0h8), _csignals_T_331) node _csignals_T_333 = mux(_csignals_T_25, UInt<4>(0h7), _csignals_T_332) node _csignals_T_334 = mux(_csignals_T_23, UInt<4>(0h6), _csignals_T_333) node _csignals_T_335 = mux(_csignals_T_21, UInt<4>(0h1), _csignals_T_334) node _csignals_T_336 = mux(_csignals_T_19, UInt<4>(0hb), _csignals_T_335) node _csignals_T_337 = mux(_csignals_T_17, UInt<4>(0h1), _csignals_T_336) node _csignals_T_338 = mux(_csignals_T_15, UInt<4>(0h1), _csignals_T_337) node _csignals_T_339 = mux(_csignals_T_13, UInt<4>(0h1), _csignals_T_338) node _csignals_T_340 = mux(_csignals_T_11, UInt<4>(0h1), _csignals_T_339) node _csignals_T_341 = mux(_csignals_T_9, UInt<4>(0h1), _csignals_T_340) node _csignals_T_342 = mux(_csignals_T_7, UInt<4>(0h1), _csignals_T_341) node _csignals_T_343 = mux(_csignals_T_5, UInt<4>(0h1), _csignals_T_342) node _csignals_T_344 = mux(_csignals_T_3, UInt<4>(0h1), _csignals_T_343) node csignals_4 = mux(_csignals_T_1, UInt<4>(0h1), _csignals_T_344) node _csignals_T_345 = mux(_csignals_T_99, UInt<2>(0h0), UInt<2>(0h0)) node _csignals_T_346 = mux(_csignals_T_97, UInt<2>(0h0), _csignals_T_345) node _csignals_T_347 = mux(_csignals_T_95, UInt<2>(0h0), _csignals_T_346) node _csignals_T_348 = mux(_csignals_T_93, UInt<2>(0h0), _csignals_T_347) node _csignals_T_349 = mux(_csignals_T_91, UInt<2>(0h0), _csignals_T_348) node _csignals_T_350 = mux(_csignals_T_89, UInt<2>(0h0), _csignals_T_349) node _csignals_T_351 = mux(_csignals_T_87, UInt<2>(0h0), _csignals_T_350) node _csignals_T_352 = mux(_csignals_T_85, UInt<2>(0h3), _csignals_T_351) node _csignals_T_353 = mux(_csignals_T_83, UInt<2>(0h3), _csignals_T_352) node _csignals_T_354 = mux(_csignals_T_81, UInt<2>(0h3), _csignals_T_353) node _csignals_T_355 = mux(_csignals_T_79, UInt<2>(0h3), _csignals_T_354) node _csignals_T_356 = mux(_csignals_T_77, UInt<2>(0h3), _csignals_T_355) node _csignals_T_357 = mux(_csignals_T_75, UInt<2>(0h3), _csignals_T_356) node _csignals_T_358 = mux(_csignals_T_73, UInt<2>(0h0), _csignals_T_357) node _csignals_T_359 = mux(_csignals_T_71, UInt<2>(0h0), _csignals_T_358) node _csignals_T_360 = mux(_csignals_T_69, UInt<2>(0h0), _csignals_T_359) node _csignals_T_361 = mux(_csignals_T_67, UInt<2>(0h0), _csignals_T_360) node _csignals_T_362 = mux(_csignals_T_65, UInt<2>(0h0), _csignals_T_361) node _csignals_T_363 = mux(_csignals_T_63, UInt<2>(0h0), _csignals_T_362) node _csignals_T_364 = mux(_csignals_T_61, UInt<2>(0h2), _csignals_T_363) node _csignals_T_365 = mux(_csignals_T_59, UInt<2>(0h2), _csignals_T_364) node _csignals_T_366 = mux(_csignals_T_57, UInt<2>(0h0), _csignals_T_365) node _csignals_T_367 = mux(_csignals_T_55, UInt<2>(0h0), _csignals_T_366) node _csignals_T_368 = mux(_csignals_T_53, UInt<2>(0h0), _csignals_T_367) node _csignals_T_369 = mux(_csignals_T_51, UInt<2>(0h0), _csignals_T_368) node _csignals_T_370 = mux(_csignals_T_49, UInt<2>(0h0), _csignals_T_369) node _csignals_T_371 = mux(_csignals_T_47, UInt<2>(0h0), _csignals_T_370) node _csignals_T_372 = mux(_csignals_T_45, UInt<2>(0h0), _csignals_T_371) node _csignals_T_373 = mux(_csignals_T_43, UInt<2>(0h0), _csignals_T_372) node _csignals_T_374 = mux(_csignals_T_41, UInt<2>(0h0), _csignals_T_373) node _csignals_T_375 = mux(_csignals_T_39, UInt<2>(0h0), _csignals_T_374) node _csignals_T_376 = mux(_csignals_T_37, UInt<2>(0h0), _csignals_T_375) node _csignals_T_377 = mux(_csignals_T_35, UInt<2>(0h0), _csignals_T_376) node _csignals_T_378 = mux(_csignals_T_33, UInt<2>(0h0), _csignals_T_377) node _csignals_T_379 = mux(_csignals_T_31, UInt<2>(0h0), _csignals_T_378) node _csignals_T_380 = mux(_csignals_T_29, UInt<2>(0h0), _csignals_T_379) node _csignals_T_381 = mux(_csignals_T_27, UInt<2>(0h0), _csignals_T_380) node _csignals_T_382 = mux(_csignals_T_25, UInt<2>(0h0), _csignals_T_381) node _csignals_T_383 = mux(_csignals_T_23, UInt<2>(0h0), _csignals_T_382) node _csignals_T_384 = mux(_csignals_T_21, UInt<2>(0h0), _csignals_T_383) node _csignals_T_385 = mux(_csignals_T_19, UInt<2>(0h0), _csignals_T_384) node _csignals_T_386 = mux(_csignals_T_17, UInt<2>(0h0), _csignals_T_385) node _csignals_T_387 = mux(_csignals_T_15, UInt<2>(0h0), _csignals_T_386) node _csignals_T_388 = mux(_csignals_T_13, UInt<2>(0h0), _csignals_T_387) node _csignals_T_389 = mux(_csignals_T_11, UInt<2>(0h0), _csignals_T_388) node _csignals_T_390 = mux(_csignals_T_9, UInt<2>(0h1), _csignals_T_389) node _csignals_T_391 = mux(_csignals_T_7, UInt<2>(0h1), _csignals_T_390) node _csignals_T_392 = mux(_csignals_T_5, UInt<2>(0h1), _csignals_T_391) node _csignals_T_393 = mux(_csignals_T_3, UInt<2>(0h1), _csignals_T_392) node csignals_5 = mux(_csignals_T_1, UInt<2>(0h1), _csignals_T_393) node _csignals_T_394 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0)) node _csignals_T_395 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_394) node _csignals_T_396 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_395) node _csignals_T_397 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_396) node _csignals_T_398 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_397) node _csignals_T_399 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_398) node _csignals_T_400 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_399) node _csignals_T_401 = mux(_csignals_T_85, UInt<1>(0h1), _csignals_T_400) node _csignals_T_402 = mux(_csignals_T_83, UInt<1>(0h1), _csignals_T_401) node _csignals_T_403 = mux(_csignals_T_81, UInt<1>(0h1), _csignals_T_402) node _csignals_T_404 = mux(_csignals_T_79, UInt<1>(0h1), _csignals_T_403) node _csignals_T_405 = mux(_csignals_T_77, UInt<1>(0h1), _csignals_T_404) node _csignals_T_406 = mux(_csignals_T_75, UInt<1>(0h1), _csignals_T_405) node _csignals_T_407 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_406) node _csignals_T_408 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_407) node _csignals_T_409 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_408) node _csignals_T_410 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_409) node _csignals_T_411 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_410) node _csignals_T_412 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_411) node _csignals_T_413 = mux(_csignals_T_61, UInt<1>(0h1), _csignals_T_412) node _csignals_T_414 = mux(_csignals_T_59, UInt<1>(0h1), _csignals_T_413) node _csignals_T_415 = mux(_csignals_T_57, UInt<1>(0h1), _csignals_T_414) node _csignals_T_416 = mux(_csignals_T_55, UInt<1>(0h1), _csignals_T_415) node _csignals_T_417 = mux(_csignals_T_53, UInt<1>(0h1), _csignals_T_416) node _csignals_T_418 = mux(_csignals_T_51, UInt<1>(0h1), _csignals_T_417) node _csignals_T_419 = mux(_csignals_T_49, UInt<1>(0h1), _csignals_T_418) node _csignals_T_420 = mux(_csignals_T_47, UInt<1>(0h1), _csignals_T_419) node _csignals_T_421 = mux(_csignals_T_45, UInt<1>(0h1), _csignals_T_420) node _csignals_T_422 = mux(_csignals_T_43, UInt<1>(0h1), _csignals_T_421) node _csignals_T_423 = mux(_csignals_T_41, UInt<1>(0h1), _csignals_T_422) node _csignals_T_424 = mux(_csignals_T_39, UInt<1>(0h1), _csignals_T_423) node _csignals_T_425 = mux(_csignals_T_37, UInt<1>(0h1), _csignals_T_424) node _csignals_T_426 = mux(_csignals_T_35, UInt<1>(0h1), _csignals_T_425) node _csignals_T_427 = mux(_csignals_T_33, UInt<1>(0h1), _csignals_T_426) node _csignals_T_428 = mux(_csignals_T_31, UInt<1>(0h1), _csignals_T_427) node _csignals_T_429 = mux(_csignals_T_29, UInt<1>(0h1), _csignals_T_428) node _csignals_T_430 = mux(_csignals_T_27, UInt<1>(0h1), _csignals_T_429) node _csignals_T_431 = mux(_csignals_T_25, UInt<1>(0h1), _csignals_T_430) node _csignals_T_432 = mux(_csignals_T_23, UInt<1>(0h1), _csignals_T_431) node _csignals_T_433 = mux(_csignals_T_21, UInt<1>(0h1), _csignals_T_432) node _csignals_T_434 = mux(_csignals_T_19, UInt<1>(0h1), _csignals_T_433) node _csignals_T_435 = mux(_csignals_T_17, UInt<1>(0h1), _csignals_T_434) node _csignals_T_436 = mux(_csignals_T_15, UInt<1>(0h0), _csignals_T_435) node _csignals_T_437 = mux(_csignals_T_13, UInt<1>(0h0), _csignals_T_436) node _csignals_T_438 = mux(_csignals_T_11, UInt<1>(0h0), _csignals_T_437) node _csignals_T_439 = mux(_csignals_T_9, UInt<1>(0h1), _csignals_T_438) node _csignals_T_440 = mux(_csignals_T_7, UInt<1>(0h1), _csignals_T_439) node _csignals_T_441 = mux(_csignals_T_5, UInt<1>(0h1), _csignals_T_440) node _csignals_T_442 = mux(_csignals_T_3, UInt<1>(0h1), _csignals_T_441) node csignals_6 = mux(_csignals_T_1, UInt<1>(0h1), _csignals_T_442) node _csignals_T_443 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0)) node _csignals_T_444 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_443) node _csignals_T_445 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_444) node _csignals_T_446 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_445) node _csignals_T_447 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_446) node _csignals_T_448 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_447) node _csignals_T_449 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_448) node _csignals_T_450 = mux(_csignals_T_85, UInt<1>(0h0), _csignals_T_449) node _csignals_T_451 = mux(_csignals_T_83, UInt<1>(0h0), _csignals_T_450) node _csignals_T_452 = mux(_csignals_T_81, UInt<1>(0h0), _csignals_T_451) node _csignals_T_453 = mux(_csignals_T_79, UInt<1>(0h0), _csignals_T_452) node _csignals_T_454 = mux(_csignals_T_77, UInt<1>(0h0), _csignals_T_453) node _csignals_T_455 = mux(_csignals_T_75, UInt<1>(0h0), _csignals_T_454) node _csignals_T_456 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_455) node _csignals_T_457 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_456) node _csignals_T_458 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_457) node _csignals_T_459 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_458) node _csignals_T_460 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_459) node _csignals_T_461 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_460) node _csignals_T_462 = mux(_csignals_T_61, UInt<1>(0h0), _csignals_T_461) node _csignals_T_463 = mux(_csignals_T_59, UInt<1>(0h0), _csignals_T_462) node _csignals_T_464 = mux(_csignals_T_57, UInt<1>(0h0), _csignals_T_463) node _csignals_T_465 = mux(_csignals_T_55, UInt<1>(0h0), _csignals_T_464) node _csignals_T_466 = mux(_csignals_T_53, UInt<1>(0h0), _csignals_T_465) node _csignals_T_467 = mux(_csignals_T_51, UInt<1>(0h0), _csignals_T_466) node _csignals_T_468 = mux(_csignals_T_49, UInt<1>(0h0), _csignals_T_467) node _csignals_T_469 = mux(_csignals_T_47, UInt<1>(0h0), _csignals_T_468) node _csignals_T_470 = mux(_csignals_T_45, UInt<1>(0h0), _csignals_T_469) node _csignals_T_471 = mux(_csignals_T_43, UInt<1>(0h0), _csignals_T_470) node _csignals_T_472 = mux(_csignals_T_41, UInt<1>(0h0), _csignals_T_471) node _csignals_T_473 = mux(_csignals_T_39, UInt<1>(0h0), _csignals_T_472) node _csignals_T_474 = mux(_csignals_T_37, UInt<1>(0h0), _csignals_T_473) node _csignals_T_475 = mux(_csignals_T_35, UInt<1>(0h0), _csignals_T_474) node _csignals_T_476 = mux(_csignals_T_33, UInt<1>(0h0), _csignals_T_475) node _csignals_T_477 = mux(_csignals_T_31, UInt<1>(0h0), _csignals_T_476) node _csignals_T_478 = mux(_csignals_T_29, UInt<1>(0h0), _csignals_T_477) node _csignals_T_479 = mux(_csignals_T_27, UInt<1>(0h0), _csignals_T_478) node _csignals_T_480 = mux(_csignals_T_25, UInt<1>(0h0), _csignals_T_479) node _csignals_T_481 = mux(_csignals_T_23, UInt<1>(0h0), _csignals_T_480) node _csignals_T_482 = mux(_csignals_T_21, UInt<1>(0h0), _csignals_T_481) node _csignals_T_483 = mux(_csignals_T_19, UInt<1>(0h0), _csignals_T_482) node _csignals_T_484 = mux(_csignals_T_17, UInt<1>(0h0), _csignals_T_483) node _csignals_T_485 = mux(_csignals_T_15, UInt<1>(0h1), _csignals_T_484) node _csignals_T_486 = mux(_csignals_T_13, UInt<1>(0h1), _csignals_T_485) node _csignals_T_487 = mux(_csignals_T_11, UInt<1>(0h1), _csignals_T_486) node _csignals_T_488 = mux(_csignals_T_9, UInt<1>(0h1), _csignals_T_487) node _csignals_T_489 = mux(_csignals_T_7, UInt<1>(0h1), _csignals_T_488) node _csignals_T_490 = mux(_csignals_T_5, UInt<1>(0h1), _csignals_T_489) node _csignals_T_491 = mux(_csignals_T_3, UInt<1>(0h1), _csignals_T_490) node csignals_7 = mux(_csignals_T_1, UInt<1>(0h1), _csignals_T_491) node _csignals_T_492 = mux(_csignals_T_99, UInt<1>(0h0), UInt<1>(0h0)) node _csignals_T_493 = mux(_csignals_T_97, UInt<1>(0h0), _csignals_T_492) node _csignals_T_494 = mux(_csignals_T_95, UInt<1>(0h0), _csignals_T_493) node _csignals_T_495 = mux(_csignals_T_93, UInt<1>(0h0), _csignals_T_494) node _csignals_T_496 = mux(_csignals_T_91, UInt<1>(0h0), _csignals_T_495) node _csignals_T_497 = mux(_csignals_T_89, UInt<1>(0h0), _csignals_T_496) node _csignals_T_498 = mux(_csignals_T_87, UInt<1>(0h0), _csignals_T_497) node _csignals_T_499 = mux(_csignals_T_85, UInt<1>(0h0), _csignals_T_498) node _csignals_T_500 = mux(_csignals_T_83, UInt<1>(0h0), _csignals_T_499) node _csignals_T_501 = mux(_csignals_T_81, UInt<1>(0h0), _csignals_T_500) node _csignals_T_502 = mux(_csignals_T_79, UInt<1>(0h0), _csignals_T_501) node _csignals_T_503 = mux(_csignals_T_77, UInt<1>(0h0), _csignals_T_502) node _csignals_T_504 = mux(_csignals_T_75, UInt<1>(0h0), _csignals_T_503) node _csignals_T_505 = mux(_csignals_T_73, UInt<1>(0h0), _csignals_T_504) node _csignals_T_506 = mux(_csignals_T_71, UInt<1>(0h0), _csignals_T_505) node _csignals_T_507 = mux(_csignals_T_69, UInt<1>(0h0), _csignals_T_506) node _csignals_T_508 = mux(_csignals_T_67, UInt<1>(0h0), _csignals_T_507) node _csignals_T_509 = mux(_csignals_T_65, UInt<1>(0h0), _csignals_T_508) node _csignals_T_510 = mux(_csignals_T_63, UInt<1>(0h0), _csignals_T_509) node _csignals_T_511 = mux(_csignals_T_61, UInt<1>(0h0), _csignals_T_510) node _csignals_T_512 = mux(_csignals_T_59, UInt<1>(0h0), _csignals_T_511) node _csignals_T_513 = mux(_csignals_T_57, UInt<1>(0h0), _csignals_T_512) node _csignals_T_514 = mux(_csignals_T_55, UInt<1>(0h0), _csignals_T_513) node _csignals_T_515 = mux(_csignals_T_53, UInt<1>(0h0), _csignals_T_514) node _csignals_T_516 = mux(_csignals_T_51, UInt<1>(0h0), _csignals_T_515) node _csignals_T_517 = mux(_csignals_T_49, UInt<1>(0h0), _csignals_T_516) node _csignals_T_518 = mux(_csignals_T_47, UInt<1>(0h0), _csignals_T_517) node _csignals_T_519 = mux(_csignals_T_45, UInt<1>(0h0), _csignals_T_518) node _csignals_T_520 = mux(_csignals_T_43, UInt<1>(0h0), _csignals_T_519) node _csignals_T_521 = mux(_csignals_T_41, UInt<1>(0h0), _csignals_T_520) node _csignals_T_522 = mux(_csignals_T_39, UInt<1>(0h0), _csignals_T_521) node _csignals_T_523 = mux(_csignals_T_37, UInt<1>(0h0), _csignals_T_522) node _csignals_T_524 = mux(_csignals_T_35, UInt<1>(0h0), _csignals_T_523) node _csignals_T_525 = mux(_csignals_T_33, UInt<1>(0h0), _csignals_T_524) node _csignals_T_526 = mux(_csignals_T_31, UInt<1>(0h0), _csignals_T_525) node _csignals_T_527 = mux(_csignals_T_29, UInt<1>(0h0), _csignals_T_526) node _csignals_T_528 = mux(_csignals_T_27, UInt<1>(0h0), _csignals_T_527) node _csignals_T_529 = mux(_csignals_T_25, UInt<1>(0h0), _csignals_T_528) node _csignals_T_530 = mux(_csignals_T_23, UInt<1>(0h0), _csignals_T_529) node _csignals_T_531 = mux(_csignals_T_21, UInt<1>(0h0), _csignals_T_530) node _csignals_T_532 = mux(_csignals_T_19, UInt<1>(0h0), _csignals_T_531) node _csignals_T_533 = mux(_csignals_T_17, UInt<1>(0h0), _csignals_T_532) node _csignals_T_534 = mux(_csignals_T_15, UInt<1>(0h1), _csignals_T_533) node _csignals_T_535 = mux(_csignals_T_13, UInt<1>(0h1), _csignals_T_534) node _csignals_T_536 = mux(_csignals_T_11, UInt<1>(0h1), _csignals_T_535) node _csignals_T_537 = mux(_csignals_T_9, UInt<1>(0h0), _csignals_T_536) node _csignals_T_538 = mux(_csignals_T_7, UInt<1>(0h0), _csignals_T_537) node _csignals_T_539 = mux(_csignals_T_5, UInt<1>(0h0), _csignals_T_538) node _csignals_T_540 = mux(_csignals_T_3, UInt<1>(0h0), _csignals_T_539) node csignals_8 = mux(_csignals_T_1, UInt<1>(0h0), _csignals_T_540) node _csignals_T_541 = mux(_csignals_T_99, UInt<3>(0h0), UInt<3>(0h0)) node _csignals_T_542 = mux(_csignals_T_97, UInt<3>(0h0), _csignals_T_541) node _csignals_T_543 = mux(_csignals_T_95, UInt<3>(0h0), _csignals_T_542) node _csignals_T_544 = mux(_csignals_T_93, UInt<3>(0h0), _csignals_T_543) node _csignals_T_545 = mux(_csignals_T_91, UInt<3>(0h0), _csignals_T_544) node _csignals_T_546 = mux(_csignals_T_89, UInt<3>(0h0), _csignals_T_545) node _csignals_T_547 = mux(_csignals_T_87, UInt<3>(0h0), _csignals_T_546) node _csignals_T_548 = mux(_csignals_T_85, UInt<3>(0h0), _csignals_T_547) node _csignals_T_549 = mux(_csignals_T_83, UInt<3>(0h0), _csignals_T_548) node _csignals_T_550 = mux(_csignals_T_81, UInt<3>(0h0), _csignals_T_549) node _csignals_T_551 = mux(_csignals_T_79, UInt<3>(0h0), _csignals_T_550) node _csignals_T_552 = mux(_csignals_T_77, UInt<3>(0h0), _csignals_T_551) node _csignals_T_553 = mux(_csignals_T_75, UInt<3>(0h0), _csignals_T_552) node _csignals_T_554 = mux(_csignals_T_73, UInt<3>(0h0), _csignals_T_553) node _csignals_T_555 = mux(_csignals_T_71, UInt<3>(0h0), _csignals_T_554) node _csignals_T_556 = mux(_csignals_T_69, UInt<3>(0h0), _csignals_T_555) node _csignals_T_557 = mux(_csignals_T_67, UInt<3>(0h0), _csignals_T_556) node _csignals_T_558 = mux(_csignals_T_65, UInt<3>(0h0), _csignals_T_557) node _csignals_T_559 = mux(_csignals_T_63, UInt<3>(0h0), _csignals_T_558) node _csignals_T_560 = mux(_csignals_T_61, UInt<3>(0h0), _csignals_T_559) node _csignals_T_561 = mux(_csignals_T_59, UInt<3>(0h0), _csignals_T_560) node _csignals_T_562 = mux(_csignals_T_57, UInt<3>(0h0), _csignals_T_561) node _csignals_T_563 = mux(_csignals_T_55, UInt<3>(0h0), _csignals_T_562) node _csignals_T_564 = mux(_csignals_T_53, UInt<3>(0h0), _csignals_T_563) node _csignals_T_565 = mux(_csignals_T_51, UInt<3>(0h0), _csignals_T_564) node _csignals_T_566 = mux(_csignals_T_49, UInt<3>(0h0), _csignals_T_565) node _csignals_T_567 = mux(_csignals_T_47, UInt<3>(0h0), _csignals_T_566) node _csignals_T_568 = mux(_csignals_T_45, UInt<3>(0h0), _csignals_T_567) node _csignals_T_569 = mux(_csignals_T_43, UInt<3>(0h0), _csignals_T_568) node _csignals_T_570 = mux(_csignals_T_41, UInt<3>(0h0), _csignals_T_569) node _csignals_T_571 = mux(_csignals_T_39, UInt<3>(0h0), _csignals_T_570) node _csignals_T_572 = mux(_csignals_T_37, UInt<3>(0h0), _csignals_T_571) node _csignals_T_573 = mux(_csignals_T_35, UInt<3>(0h0), _csignals_T_572) node _csignals_T_574 = mux(_csignals_T_33, UInt<3>(0h0), _csignals_T_573) node _csignals_T_575 = mux(_csignals_T_31, UInt<3>(0h0), _csignals_T_574) node _csignals_T_576 = mux(_csignals_T_29, UInt<3>(0h0), _csignals_T_575) node _csignals_T_577 = mux(_csignals_T_27, UInt<3>(0h0), _csignals_T_576) node _csignals_T_578 = mux(_csignals_T_25, UInt<3>(0h0), _csignals_T_577) node _csignals_T_579 = mux(_csignals_T_23, UInt<3>(0h0), _csignals_T_578) node _csignals_T_580 = mux(_csignals_T_21, UInt<3>(0h0), _csignals_T_579) node _csignals_T_581 = mux(_csignals_T_19, UInt<3>(0h0), _csignals_T_580) node _csignals_T_582 = mux(_csignals_T_17, UInt<3>(0h0), _csignals_T_581) node _csignals_T_583 = mux(_csignals_T_15, UInt<3>(0h2), _csignals_T_582) node _csignals_T_584 = mux(_csignals_T_13, UInt<3>(0h1), _csignals_T_583) node _csignals_T_585 = mux(_csignals_T_11, UInt<3>(0h3), _csignals_T_584) node _csignals_T_586 = mux(_csignals_T_9, UInt<3>(0h6), _csignals_T_585) node _csignals_T_587 = mux(_csignals_T_7, UInt<3>(0h2), _csignals_T_586) node _csignals_T_588 = mux(_csignals_T_5, UInt<3>(0h5), _csignals_T_587) node _csignals_T_589 = mux(_csignals_T_3, UInt<3>(0h1), _csignals_T_588) node csignals_9 = mux(_csignals_T_1, UInt<3>(0h3), _csignals_T_589) node _csignals_T_590 = mux(_csignals_T_99, UInt<3>(0h0), UInt<3>(0h0)) node _csignals_T_591 = mux(_csignals_T_97, UInt<3>(0h0), _csignals_T_590) node _csignals_T_592 = mux(_csignals_T_95, UInt<3>(0h0), _csignals_T_591) node _csignals_T_593 = mux(_csignals_T_93, UInt<3>(0h4), _csignals_T_592) node _csignals_T_594 = mux(_csignals_T_91, UInt<3>(0h4), _csignals_T_593) node _csignals_T_595 = mux(_csignals_T_89, UInt<3>(0h4), _csignals_T_594) node _csignals_T_596 = mux(_csignals_T_87, UInt<3>(0h4), _csignals_T_595) node _csignals_T_597 = mux(_csignals_T_85, UInt<3>(0h7), _csignals_T_596) node _csignals_T_598 = mux(_csignals_T_83, UInt<3>(0h6), _csignals_T_597) node _csignals_T_599 = mux(_csignals_T_81, UInt<3>(0h5), _csignals_T_598) node _csignals_T_600 = mux(_csignals_T_79, UInt<3>(0h7), _csignals_T_599) node _csignals_T_601 = mux(_csignals_T_77, UInt<3>(0h6), _csignals_T_600) node _csignals_T_602 = mux(_csignals_T_75, UInt<3>(0h5), _csignals_T_601) node _csignals_T_603 = mux(_csignals_T_73, UInt<3>(0h0), _csignals_T_602) node _csignals_T_604 = mux(_csignals_T_71, UInt<3>(0h0), _csignals_T_603) node _csignals_T_605 = mux(_csignals_T_69, UInt<3>(0h0), _csignals_T_604) node _csignals_T_606 = mux(_csignals_T_67, UInt<3>(0h0), _csignals_T_605) node _csignals_T_607 = mux(_csignals_T_65, UInt<3>(0h0), _csignals_T_606) node _csignals_T_608 = mux(_csignals_T_63, UInt<3>(0h0), _csignals_T_607) node _csignals_T_609 = mux(_csignals_T_61, UInt<3>(0h0), _csignals_T_608) node _csignals_T_610 = mux(_csignals_T_59, UInt<3>(0h0), _csignals_T_609) node _csignals_T_611 = mux(_csignals_T_57, UInt<3>(0h0), _csignals_T_610) node _csignals_T_612 = mux(_csignals_T_55, UInt<3>(0h0), _csignals_T_611) node _csignals_T_613 = mux(_csignals_T_53, UInt<3>(0h0), _csignals_T_612) node _csignals_T_614 = mux(_csignals_T_51, UInt<3>(0h0), _csignals_T_613) node _csignals_T_615 = mux(_csignals_T_49, UInt<3>(0h0), _csignals_T_614) node _csignals_T_616 = mux(_csignals_T_47, UInt<3>(0h0), _csignals_T_615) node _csignals_T_617 = mux(_csignals_T_45, UInt<3>(0h0), _csignals_T_616) node _csignals_T_618 = mux(_csignals_T_43, UInt<3>(0h0), _csignals_T_617) node _csignals_T_619 = mux(_csignals_T_41, UInt<3>(0h0), _csignals_T_618) node _csignals_T_620 = mux(_csignals_T_39, UInt<3>(0h0), _csignals_T_619) node _csignals_T_621 = mux(_csignals_T_37, UInt<3>(0h0), _csignals_T_620) node _csignals_T_622 = mux(_csignals_T_35, UInt<3>(0h0), _csignals_T_621) node _csignals_T_623 = mux(_csignals_T_33, UInt<3>(0h0), _csignals_T_622) node _csignals_T_624 = mux(_csignals_T_31, UInt<3>(0h0), _csignals_T_623) node _csignals_T_625 = mux(_csignals_T_29, UInt<3>(0h0), _csignals_T_624) node _csignals_T_626 = mux(_csignals_T_27, UInt<3>(0h0), _csignals_T_625) node _csignals_T_627 = mux(_csignals_T_25, UInt<3>(0h0), _csignals_T_626) node _csignals_T_628 = mux(_csignals_T_23, UInt<3>(0h0), _csignals_T_627) node _csignals_T_629 = mux(_csignals_T_21, UInt<3>(0h0), _csignals_T_628) node _csignals_T_630 = mux(_csignals_T_19, UInt<3>(0h0), _csignals_T_629) node _csignals_T_631 = mux(_csignals_T_17, UInt<3>(0h0), _csignals_T_630) node _csignals_T_632 = mux(_csignals_T_15, UInt<3>(0h0), _csignals_T_631) node _csignals_T_633 = mux(_csignals_T_13, UInt<3>(0h0), _csignals_T_632) node _csignals_T_634 = mux(_csignals_T_11, UInt<3>(0h0), _csignals_T_633) node _csignals_T_635 = mux(_csignals_T_9, UInt<3>(0h0), _csignals_T_634) node _csignals_T_636 = mux(_csignals_T_7, UInt<3>(0h0), _csignals_T_635) node _csignals_T_637 = mux(_csignals_T_5, UInt<3>(0h0), _csignals_T_636) node _csignals_T_638 = mux(_csignals_T_3, UInt<3>(0h0), _csignals_T_637) node csignals_10 = mux(_csignals_T_1, UInt<3>(0h0), _csignals_T_638) node _ctrl_pc_sel_no_xept_T = eq(csignals_1, UInt<4>(0h0)) node _ctrl_pc_sel_no_xept_T_1 = eq(csignals_1, UInt<4>(0h1)) node _ctrl_pc_sel_no_xept_T_2 = eq(io.dat.br_eq, UInt<1>(0h0)) node _ctrl_pc_sel_no_xept_T_3 = mux(_ctrl_pc_sel_no_xept_T_2, UInt<3>(0h1), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_4 = eq(csignals_1, UInt<4>(0h2)) node _ctrl_pc_sel_no_xept_T_5 = mux(io.dat.br_eq, UInt<3>(0h1), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_6 = eq(csignals_1, UInt<4>(0h3)) node _ctrl_pc_sel_no_xept_T_7 = eq(io.dat.br_lt, UInt<1>(0h0)) node _ctrl_pc_sel_no_xept_T_8 = mux(_ctrl_pc_sel_no_xept_T_7, UInt<3>(0h1), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_9 = eq(csignals_1, UInt<4>(0h4)) node _ctrl_pc_sel_no_xept_T_10 = eq(io.dat.br_ltu, UInt<1>(0h0)) node _ctrl_pc_sel_no_xept_T_11 = mux(_ctrl_pc_sel_no_xept_T_10, UInt<3>(0h1), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_12 = eq(csignals_1, UInt<4>(0h5)) node _ctrl_pc_sel_no_xept_T_13 = mux(io.dat.br_lt, UInt<3>(0h1), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_14 = eq(csignals_1, UInt<4>(0h6)) node _ctrl_pc_sel_no_xept_T_15 = mux(io.dat.br_ltu, UInt<3>(0h1), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_16 = eq(csignals_1, UInt<4>(0h7)) node _ctrl_pc_sel_no_xept_T_17 = eq(csignals_1, UInt<4>(0h8)) node _ctrl_pc_sel_no_xept_T_18 = mux(_ctrl_pc_sel_no_xept_T_17, UInt<3>(0h3), UInt<3>(0h0)) node _ctrl_pc_sel_no_xept_T_19 = mux(_ctrl_pc_sel_no_xept_T_16, UInt<3>(0h2), _ctrl_pc_sel_no_xept_T_18) node _ctrl_pc_sel_no_xept_T_20 = mux(_ctrl_pc_sel_no_xept_T_14, _ctrl_pc_sel_no_xept_T_15, _ctrl_pc_sel_no_xept_T_19) node _ctrl_pc_sel_no_xept_T_21 = mux(_ctrl_pc_sel_no_xept_T_12, _ctrl_pc_sel_no_xept_T_13, _ctrl_pc_sel_no_xept_T_20) node _ctrl_pc_sel_no_xept_T_22 = mux(_ctrl_pc_sel_no_xept_T_9, _ctrl_pc_sel_no_xept_T_11, _ctrl_pc_sel_no_xept_T_21) node _ctrl_pc_sel_no_xept_T_23 = mux(_ctrl_pc_sel_no_xept_T_6, _ctrl_pc_sel_no_xept_T_8, _ctrl_pc_sel_no_xept_T_22) node _ctrl_pc_sel_no_xept_T_24 = mux(_ctrl_pc_sel_no_xept_T_4, _ctrl_pc_sel_no_xept_T_5, _ctrl_pc_sel_no_xept_T_23) node _ctrl_pc_sel_no_xept_T_25 = mux(_ctrl_pc_sel_no_xept_T_1, _ctrl_pc_sel_no_xept_T_3, _ctrl_pc_sel_no_xept_T_24) node _ctrl_pc_sel_no_xept_T_26 = mux(_ctrl_pc_sel_no_xept_T, UInt<3>(0h0), _ctrl_pc_sel_no_xept_T_25) node ctrl_pc_sel_no_xept = mux(io.dat.csr_interrupt, UInt<3>(0h4), _ctrl_pc_sel_no_xept_T_26) node _ctrl_pc_sel_T = or(io.ctl.exception, io.dat.csr_eret) node ctrl_pc_sel = mux(_ctrl_pc_sel_T, UInt<3>(0h4), ctrl_pc_sel_no_xept) regreset reg_mem_en : UInt<1>, clock, reset, UInt<1>(0h0) when io.dmem.resp.valid : connect reg_mem_en, UInt<1>(0h0) else : when io.imem.resp.valid : connect reg_mem_en, csignals_7 node mem_en = mux(io.imem.resp.valid, csignals_7, reg_mem_en) wire data_misaligned : UInt<1> node _io_ctl_dmiss_T = or(io.dmem.resp.valid, data_misaligned) node _io_ctl_dmiss_T_1 = and(mem_en, _io_ctl_dmiss_T) node _io_ctl_dmiss_T_2 = eq(mem_en, UInt<1>(0h0)) node _io_ctl_dmiss_T_3 = or(_io_ctl_dmiss_T_1, _io_ctl_dmiss_T_2) node _io_ctl_dmiss_T_4 = eq(_io_ctl_dmiss_T_3, UInt<1>(0h0)) connect io.ctl.dmiss, _io_ctl_dmiss_T_4 node stall = or(io.dat.imiss, io.ctl.dmiss) connect io.ctl.stall, stall connect io.ctl.pc_sel, ctrl_pc_sel connect io.ctl.op1_sel, csignals_2 connect io.ctl.op2_sel, csignals_3 connect io.ctl.alu_fun, csignals_4 connect io.ctl.wb_sel, csignals_5 node _io_ctl_rf_wen_T = or(stall, io.ctl.exception) node _io_ctl_rf_wen_T_1 = mux(_io_ctl_rf_wen_T, UInt<1>(0h0), csignals_6) connect io.ctl.rf_wen, _io_ctl_rf_wen_T_1 node rs1_addr = bits(io.dat.inst, 19, 15) node _csr_ren_T = eq(csignals_10, UInt<3>(0h6)) node _csr_ren_T_1 = eq(csignals_10, UInt<3>(0h7)) node _csr_ren_T_2 = or(_csr_ren_T, _csr_ren_T_1) node _csr_ren_T_3 = eq(rs1_addr, UInt<1>(0h0)) node csr_ren = and(_csr_ren_T_2, _csr_ren_T_3) node csr_cmd = mux(csr_ren, UInt<3>(0h2), csignals_10) node _io_ctl_csr_cmd_T = mux(stall, UInt<3>(0h0), csr_cmd) connect io.ctl.csr_cmd, _io_ctl_csr_cmd_T node _io_dmem_req_valid_T = eq(io.ctl.exception, UInt<1>(0h0)) node _io_dmem_req_valid_T_1 = and(mem_en, _io_dmem_req_valid_T) connect io.dmem.req.valid, _io_dmem_req_valid_T_1 connect io.dmem.req.bits.fcn, csignals_8 connect io.dmem.req.bits.typ, csignals_9 connect io.ctl.pc_sel_no_xept, ctrl_pc_sel_no_xept node _illegal_T = eq(csignals_0, UInt<1>(0h0)) node illegal = and(_illegal_T, io.imem.resp.valid) wire misaligned_mask : UInt<3> node _misaligned_mask_T = sub(csignals_9, UInt<1>(0h1)) node _misaligned_mask_T_1 = tail(_misaligned_mask_T, 1) node _misaligned_mask_T_2 = bits(_misaligned_mask_T_1, 1, 0) node _misaligned_mask_T_3 = dshl(UInt<3>(0h7), _misaligned_mask_T_2) node _misaligned_mask_T_4 = not(_misaligned_mask_T_3) connect misaligned_mask, _misaligned_mask_T_4 node _data_misaligned_T = and(misaligned_mask, io.dat.mem_address_low) node _data_misaligned_T_1 = orr(_data_misaligned_T) node _data_misaligned_T_2 = and(_data_misaligned_T_1, mem_en) connect data_misaligned, _data_misaligned_T_2 node mem_store = eq(csignals_8, UInt<1>(0h1)) node _io_ctl_exception_T = or(illegal, io.dat.inst_misaligned) node _io_ctl_exception_T_1 = or(_io_ctl_exception_T, data_misaligned) connect io.ctl.exception, _io_ctl_exception_T_1 node _io_ctl_exception_cause_T = mux(mem_store, UInt<3>(0h6), UInt<3>(0h4)) node _io_ctl_exception_cause_T_1 = mux(io.dat.inst_misaligned, UInt<1>(0h0), _io_ctl_exception_cause_T) node _io_ctl_exception_cause_T_2 = mux(illegal, UInt<2>(0h2), _io_ctl_exception_cause_T_1) connect io.ctl.exception_cause, _io_ctl_exception_cause_T_2
module CtlPath( // @[cpath.scala:44:7] input clock, // @[cpath.scala:44:7] input reset, // @[cpath.scala:44:7] input io_imem_req_ready, // @[cpath.scala:46:14] input io_imem_resp_valid, // @[cpath.scala:46:14] input [31:0] io_imem_resp_bits_data, // @[cpath.scala:46:14] input io_dmem_req_ready, // @[cpath.scala:46:14] output io_dmem_req_valid, // @[cpath.scala:46:14] output io_dmem_req_bits_fcn, // @[cpath.scala:46:14] output [2:0] io_dmem_req_bits_typ, // @[cpath.scala:46:14] input io_dmem_resp_valid, // @[cpath.scala:46:14] input [31:0] io_dmem_resp_bits_data, // @[cpath.scala:46:14] input [31:0] io_dat_inst, // @[cpath.scala:46:14] input io_dat_imiss, // @[cpath.scala:46:14] input io_dat_br_eq, // @[cpath.scala:46:14] input io_dat_br_lt, // @[cpath.scala:46:14] input io_dat_br_ltu, // @[cpath.scala:46:14] input io_dat_csr_eret, // @[cpath.scala:46:14] input io_dat_csr_interrupt, // @[cpath.scala:46:14] input io_dat_inst_misaligned, // @[cpath.scala:46:14] input [2:0] io_dat_mem_address_low, // @[cpath.scala:46:14] output io_ctl_stall, // @[cpath.scala:46:14] output io_ctl_dmiss, // @[cpath.scala:46:14] output [2:0] io_ctl_pc_sel, // @[cpath.scala:46:14] output [1:0] io_ctl_op1_sel, // @[cpath.scala:46:14] output [1:0] io_ctl_op2_sel, // @[cpath.scala:46:14] output [3:0] io_ctl_alu_fun, // @[cpath.scala:46:14] output [1:0] io_ctl_wb_sel, // @[cpath.scala:46:14] output io_ctl_rf_wen, // @[cpath.scala:46:14] output [2:0] io_ctl_csr_cmd, // @[cpath.scala:46:14] output io_ctl_exception, // @[cpath.scala:46:14] output [31:0] io_ctl_exception_cause, // @[cpath.scala:46:14] output [2:0] io_ctl_pc_sel_no_xept // @[cpath.scala:46:14] ); wire io_imem_req_ready_0 = io_imem_req_ready; // @[cpath.scala:44:7] wire io_imem_resp_valid_0 = io_imem_resp_valid; // @[cpath.scala:44:7] wire [31:0] io_imem_resp_bits_data_0 = io_imem_resp_bits_data; // @[cpath.scala:44:7] wire io_dmem_req_ready_0 = io_dmem_req_ready; // @[cpath.scala:44:7] wire io_dmem_resp_valid_0 = io_dmem_resp_valid; // @[cpath.scala:44:7] wire [31:0] io_dmem_resp_bits_data_0 = io_dmem_resp_bits_data; // @[cpath.scala:44:7] wire [31:0] io_dat_inst_0 = io_dat_inst; // @[cpath.scala:44:7] wire io_dat_imiss_0 = io_dat_imiss; // @[cpath.scala:44:7] wire io_dat_br_eq_0 = io_dat_br_eq; // @[cpath.scala:44:7] wire io_dat_br_lt_0 = io_dat_br_lt; // @[cpath.scala:44:7] wire io_dat_br_ltu_0 = io_dat_br_ltu; // @[cpath.scala:44:7] wire io_dat_csr_eret_0 = io_dat_csr_eret; // @[cpath.scala:44:7] wire io_dat_csr_interrupt_0 = io_dat_csr_interrupt; // @[cpath.scala:44:7] wire io_dat_inst_misaligned_0 = io_dat_inst_misaligned; // @[cpath.scala:44:7] wire [2:0] io_dat_mem_address_low_0 = io_dat_mem_address_low; // @[cpath.scala:44:7] wire [3:0] _csignals_T_149 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_150 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_151 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_152 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_153 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_154 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_155 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_156 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_157 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_158 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_159 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_160 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_161 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_296 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_297 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_298 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_299 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_300 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_301 = 4'h0; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_302 = 4'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_198 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_199 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_200 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_201 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_202 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_203 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_204 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_205 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_206 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_207 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_247 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_248 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_249 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_250 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_251 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_252 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_253 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_254 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_255 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_256 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_257 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_258 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_259 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_260 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_261 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_262 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_263 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_264 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_265 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_345 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_346 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_347 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_348 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_349 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_350 = 2'h0; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_351 = 2'h0; // @[Lookup.scala:34:39] wire [2:0] io_imem_req_bits_typ = 3'h0; // @[cpath.scala:44:7] wire [2:0] _csignals_T_541 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_542 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_543 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_544 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_545 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_546 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_547 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_548 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_549 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_550 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_551 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_552 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_553 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_554 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_555 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_556 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_557 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_558 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_559 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_560 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_561 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_562 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_563 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_564 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_565 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_566 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_567 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_568 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_569 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_570 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_571 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_572 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_573 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_574 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_575 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_576 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_577 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_578 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_579 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_580 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_581 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_582 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_590 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_591 = 3'h0; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_592 = 3'h0; // @[Lookup.scala:34:39] wire [31:0] io_imem_req_bits_addr = 32'h0; // @[cpath.scala:44:7] wire [31:0] io_imem_req_bits_data = 32'h0; // @[cpath.scala:44:7] wire [31:0] io_dmem_req_bits_addr = 32'h0; // @[cpath.scala:44:7] wire [31:0] io_dmem_req_bits_data = 32'h0; // @[cpath.scala:44:7] wire io_dcpath_halt = 1'h0; // @[cpath.scala:44:7] wire io_imem_req_valid = 1'h0; // @[cpath.scala:44:7] wire io_imem_req_bits_fcn = 1'h0; // @[cpath.scala:44:7] wire _csignals_T_394 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_395 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_396 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_397 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_398 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_399 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_400 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_443 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_444 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_445 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_446 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_447 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_448 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_449 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_450 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_451 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_452 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_453 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_454 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_455 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_456 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_457 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_458 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_459 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_460 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_461 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_462 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_463 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_464 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_465 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_466 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_467 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_468 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_469 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_470 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_471 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_472 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_473 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_474 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_475 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_476 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_477 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_478 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_479 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_480 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_481 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_482 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_483 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_484 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_492 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_493 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_494 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_495 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_496 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_497 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_498 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_499 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_500 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_501 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_502 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_503 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_504 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_505 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_506 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_507 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_508 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_509 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_510 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_511 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_512 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_513 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_514 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_515 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_516 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_517 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_518 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_519 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_520 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_521 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_522 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_523 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_524 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_525 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_526 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_527 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_528 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_529 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_530 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_531 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_532 = 1'h0; // @[Lookup.scala:34:39] wire _csignals_T_533 = 1'h0; // @[Lookup.scala:34:39] wire _io_dmem_req_valid_T_1; // @[cpath.scala:165:35] wire csignals_8; // @[Lookup.scala:34:39] wire [2:0] csignals_9; // @[Lookup.scala:34:39] wire [31:0] _csignals_T_86 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_88 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_90 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_92 = io_dat_inst_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_94 = io_dat_inst_0; // @[Lookup.scala:31:38] wire stall; // @[cpath.scala:145:30] wire _io_ctl_dmiss_T_4; // @[cpath.scala:144:20] wire [2:0] ctrl_pc_sel; // @[cpath.scala:131:25] wire [1:0] csignals_2; // @[Lookup.scala:34:39] wire [1:0] csignals_3; // @[Lookup.scala:34:39] wire [3:0] csignals_4; // @[Lookup.scala:34:39] wire [1:0] csignals_5; // @[Lookup.scala:34:39] wire _io_ctl_rf_wen_T_1; // @[cpath.scala:155:26] wire [2:0] _io_ctl_csr_cmd_T; // @[cpath.scala:162:26] wire _io_ctl_exception_T_1; // @[cpath.scala:182:58] wire [2:0] ctrl_pc_sel_no_xept; // @[cpath.scala:120:34] wire io_dmem_req_bits_fcn_0; // @[cpath.scala:44:7] wire [2:0] io_dmem_req_bits_typ_0; // @[cpath.scala:44:7] wire io_dmem_req_valid_0; // @[cpath.scala:44:7] wire io_ctl_stall_0; // @[cpath.scala:44:7] wire io_ctl_dmiss_0; // @[cpath.scala:44:7] wire [2:0] io_ctl_pc_sel_0; // @[cpath.scala:44:7] wire [1:0] io_ctl_op1_sel_0; // @[cpath.scala:44:7] wire [1:0] io_ctl_op2_sel_0; // @[cpath.scala:44:7] wire [3:0] io_ctl_alu_fun_0; // @[cpath.scala:44:7] wire [1:0] io_ctl_wb_sel_0; // @[cpath.scala:44:7] wire io_ctl_rf_wen_0; // @[cpath.scala:44:7] wire [2:0] io_ctl_csr_cmd_0; // @[cpath.scala:44:7] wire io_ctl_exception_0; // @[cpath.scala:44:7] wire [31:0] io_ctl_exception_cause_0; // @[cpath.scala:44:7] wire [2:0] io_ctl_pc_sel_no_xept_0; // @[cpath.scala:44:7] wire [31:0] _GEN = {17'h0, io_dat_inst_0[14:0] & 15'h707F}; // @[Lookup.scala:31:38] wire [31:0] _csignals_T; // @[Lookup.scala:31:38] assign _csignals_T = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_2; // @[Lookup.scala:31:38] assign _csignals_T_2 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_4; // @[Lookup.scala:31:38] assign _csignals_T_4 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_6; // @[Lookup.scala:31:38] assign _csignals_T_6 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_8; // @[Lookup.scala:31:38] assign _csignals_T_8 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_10; // @[Lookup.scala:31:38] assign _csignals_T_10 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_12; // @[Lookup.scala:31:38] assign _csignals_T_12 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_14; // @[Lookup.scala:31:38] assign _csignals_T_14 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_20; // @[Lookup.scala:31:38] assign _csignals_T_20 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_22; // @[Lookup.scala:31:38] assign _csignals_T_22 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_24; // @[Lookup.scala:31:38] assign _csignals_T_24 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_26; // @[Lookup.scala:31:38] assign _csignals_T_26 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_28; // @[Lookup.scala:31:38] assign _csignals_T_28 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_30; // @[Lookup.scala:31:38] assign _csignals_T_30 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_60; // @[Lookup.scala:31:38] assign _csignals_T_60 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_62; // @[Lookup.scala:31:38] assign _csignals_T_62 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_64; // @[Lookup.scala:31:38] assign _csignals_T_64 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_66; // @[Lookup.scala:31:38] assign _csignals_T_66 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_68; // @[Lookup.scala:31:38] assign _csignals_T_68 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_70; // @[Lookup.scala:31:38] assign _csignals_T_70 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_72; // @[Lookup.scala:31:38] assign _csignals_T_72 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_74; // @[Lookup.scala:31:38] assign _csignals_T_74 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_76; // @[Lookup.scala:31:38] assign _csignals_T_76 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_78; // @[Lookup.scala:31:38] assign _csignals_T_78 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_80; // @[Lookup.scala:31:38] assign _csignals_T_80 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_82; // @[Lookup.scala:31:38] assign _csignals_T_82 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_84; // @[Lookup.scala:31:38] assign _csignals_T_84 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_96; // @[Lookup.scala:31:38] assign _csignals_T_96 = _GEN; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_98; // @[Lookup.scala:31:38] assign _csignals_T_98 = _GEN; // @[Lookup.scala:31:38] wire _csignals_T_1 = _csignals_T == 32'h2003; // @[Lookup.scala:31:38] wire _csignals_T_3 = _csignals_T_2 == 32'h3; // @[Lookup.scala:31:38] wire _csignals_T_5 = _csignals_T_4 == 32'h4003; // @[Lookup.scala:31:38] wire _csignals_T_7 = _csignals_T_6 == 32'h1003; // @[Lookup.scala:31:38] wire _csignals_T_9 = _csignals_T_8 == 32'h5003; // @[Lookup.scala:31:38] wire _csignals_T_11 = _csignals_T_10 == 32'h2023; // @[Lookup.scala:31:38] wire _csignals_T_13 = _csignals_T_12 == 32'h23; // @[Lookup.scala:31:38] wire _csignals_T_15 = _csignals_T_14 == 32'h1023; // @[Lookup.scala:31:38] wire _csignals_T_485 = _csignals_T_15; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_534 = _csignals_T_15; // @[Lookup.scala:31:38, :34:39] wire [31:0] _GEN_0 = {25'h0, io_dat_inst_0[6:0]}; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_16; // @[Lookup.scala:31:38] assign _csignals_T_16 = _GEN_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_18; // @[Lookup.scala:31:38] assign _csignals_T_18 = _GEN_0; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_58; // @[Lookup.scala:31:38] assign _csignals_T_58 = _GEN_0; // @[Lookup.scala:31:38] wire _csignals_T_17 = _csignals_T_16 == 32'h17; // @[Lookup.scala:31:38] wire _csignals_T_19 = _csignals_T_18 == 32'h37; // @[Lookup.scala:31:38] wire _csignals_T_21 = _csignals_T_20 == 32'h13; // @[Lookup.scala:31:38] wire _csignals_T_23 = _csignals_T_22 == 32'h7013; // @[Lookup.scala:31:38] wire _csignals_T_25 = _csignals_T_24 == 32'h6013; // @[Lookup.scala:31:38] wire _csignals_T_27 = _csignals_T_26 == 32'h4013; // @[Lookup.scala:31:38] wire _csignals_T_29 = _csignals_T_28 == 32'h2013; // @[Lookup.scala:31:38] wire _csignals_T_31 = _csignals_T_30 == 32'h3013; // @[Lookup.scala:31:38] wire [31:0] _GEN_1 = io_dat_inst_0 & 32'hFE00707F; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_32; // @[Lookup.scala:31:38] assign _csignals_T_32 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_34; // @[Lookup.scala:31:38] assign _csignals_T_34 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_36; // @[Lookup.scala:31:38] assign _csignals_T_36 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_38; // @[Lookup.scala:31:38] assign _csignals_T_38 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_40; // @[Lookup.scala:31:38] assign _csignals_T_40 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_42; // @[Lookup.scala:31:38] assign _csignals_T_42 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_44; // @[Lookup.scala:31:38] assign _csignals_T_44 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_46; // @[Lookup.scala:31:38] assign _csignals_T_46 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_48; // @[Lookup.scala:31:38] assign _csignals_T_48 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_50; // @[Lookup.scala:31:38] assign _csignals_T_50 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_52; // @[Lookup.scala:31:38] assign _csignals_T_52 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_54; // @[Lookup.scala:31:38] assign _csignals_T_54 = _GEN_1; // @[Lookup.scala:31:38] wire [31:0] _csignals_T_56; // @[Lookup.scala:31:38] assign _csignals_T_56 = _GEN_1; // @[Lookup.scala:31:38] wire _csignals_T_33 = _csignals_T_32 == 32'h1013; // @[Lookup.scala:31:38] wire _csignals_T_35 = _csignals_T_34 == 32'h40005013; // @[Lookup.scala:31:38] wire _csignals_T_37 = _csignals_T_36 == 32'h5013; // @[Lookup.scala:31:38] wire _csignals_T_39 = _csignals_T_38 == 32'h1033; // @[Lookup.scala:31:38] wire _csignals_T_41 = _csignals_T_40 == 32'h33; // @[Lookup.scala:31:38] wire _csignals_T_43 = _csignals_T_42 == 32'h40000033; // @[Lookup.scala:31:38] wire _csignals_T_45 = _csignals_T_44 == 32'h2033; // @[Lookup.scala:31:38] wire _csignals_T_47 = _csignals_T_46 == 32'h3033; // @[Lookup.scala:31:38] wire _csignals_T_49 = _csignals_T_48 == 32'h7033; // @[Lookup.scala:31:38] wire _csignals_T_51 = _csignals_T_50 == 32'h6033; // @[Lookup.scala:31:38] wire _csignals_T_53 = _csignals_T_52 == 32'h4033; // @[Lookup.scala:31:38] wire _csignals_T_55 = _csignals_T_54 == 32'h40005033; // @[Lookup.scala:31:38] wire _csignals_T_57 = _csignals_T_56 == 32'h5033; // @[Lookup.scala:31:38] wire _csignals_T_59 = _csignals_T_58 == 32'h6F; // @[Lookup.scala:31:38] wire _csignals_T_61 = _csignals_T_60 == 32'h67; // @[Lookup.scala:31:38] wire _csignals_T_63 = _csignals_T_62 == 32'h63; // @[Lookup.scala:31:38] wire _csignals_T_65 = _csignals_T_64 == 32'h1063; // @[Lookup.scala:31:38] wire _csignals_T_67 = _csignals_T_66 == 32'h5063; // @[Lookup.scala:31:38] wire _csignals_T_69 = _csignals_T_68 == 32'h7063; // @[Lookup.scala:31:38] wire _csignals_T_71 = _csignals_T_70 == 32'h4063; // @[Lookup.scala:31:38] wire _csignals_T_73 = _csignals_T_72 == 32'h6063; // @[Lookup.scala:31:38] wire _csignals_T_75 = _csignals_T_74 == 32'h5073; // @[Lookup.scala:31:38] wire _csignals_T_77 = _csignals_T_76 == 32'h6073; // @[Lookup.scala:31:38] wire _csignals_T_79 = _csignals_T_78 == 32'h7073; // @[Lookup.scala:31:38] wire _csignals_T_81 = _csignals_T_80 == 32'h1073; // @[Lookup.scala:31:38] wire _csignals_T_83 = _csignals_T_82 == 32'h2073; // @[Lookup.scala:31:38] wire _csignals_T_85 = _csignals_T_84 == 32'h3073; // @[Lookup.scala:31:38] wire _csignals_T_401 = _csignals_T_85; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_87 = _csignals_T_86 == 32'h73; // @[Lookup.scala:31:38] wire _csignals_T_89 = _csignals_T_88 == 32'h30200073; // @[Lookup.scala:31:38] wire _csignals_T_91 = _csignals_T_90 == 32'h7B200073; // @[Lookup.scala:31:38] wire _csignals_T_93 = _csignals_T_92 == 32'h100073; // @[Lookup.scala:31:38] wire _csignals_T_95 = _csignals_T_94 == 32'h10500073; // @[Lookup.scala:31:38] wire _csignals_T_97 = _csignals_T_96 == 32'h100F; // @[Lookup.scala:31:38] wire _csignals_T_99 = _csignals_T_98 == 32'hF; // @[Lookup.scala:31:38] wire _csignals_T_100 = _csignals_T_99; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_101 = _csignals_T_97 | _csignals_T_100; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_102 = _csignals_T_95 | _csignals_T_101; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_103 = _csignals_T_93 | _csignals_T_102; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_104 = _csignals_T_91 | _csignals_T_103; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_105 = _csignals_T_89 | _csignals_T_104; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_106 = _csignals_T_87 | _csignals_T_105; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_107 = _csignals_T_85 | _csignals_T_106; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_108 = _csignals_T_83 | _csignals_T_107; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_109 = _csignals_T_81 | _csignals_T_108; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_110 = _csignals_T_79 | _csignals_T_109; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_111 = _csignals_T_77 | _csignals_T_110; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_112 = _csignals_T_75 | _csignals_T_111; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_113 = _csignals_T_73 | _csignals_T_112; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_114 = _csignals_T_71 | _csignals_T_113; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_115 = _csignals_T_69 | _csignals_T_114; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_116 = _csignals_T_67 | _csignals_T_115; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_117 = _csignals_T_65 | _csignals_T_116; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_118 = _csignals_T_63 | _csignals_T_117; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_119 = _csignals_T_61 | _csignals_T_118; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_120 = _csignals_T_59 | _csignals_T_119; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_121 = _csignals_T_57 | _csignals_T_120; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_122 = _csignals_T_55 | _csignals_T_121; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_123 = _csignals_T_53 | _csignals_T_122; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_124 = _csignals_T_51 | _csignals_T_123; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_125 = _csignals_T_49 | _csignals_T_124; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_126 = _csignals_T_47 | _csignals_T_125; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_127 = _csignals_T_45 | _csignals_T_126; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_128 = _csignals_T_43 | _csignals_T_127; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_129 = _csignals_T_41 | _csignals_T_128; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_130 = _csignals_T_39 | _csignals_T_129; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_131 = _csignals_T_37 | _csignals_T_130; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_132 = _csignals_T_35 | _csignals_T_131; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_133 = _csignals_T_33 | _csignals_T_132; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_134 = _csignals_T_31 | _csignals_T_133; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_135 = _csignals_T_29 | _csignals_T_134; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_136 = _csignals_T_27 | _csignals_T_135; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_137 = _csignals_T_25 | _csignals_T_136; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_138 = _csignals_T_23 | _csignals_T_137; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_139 = _csignals_T_21 | _csignals_T_138; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_140 = _csignals_T_19 | _csignals_T_139; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_141 = _csignals_T_17 | _csignals_T_140; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_142 = _csignals_T_15 | _csignals_T_141; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_143 = _csignals_T_13 | _csignals_T_142; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_144 = _csignals_T_11 | _csignals_T_143; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_145 = _csignals_T_9 | _csignals_T_144; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_146 = _csignals_T_7 | _csignals_T_145; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_147 = _csignals_T_5 | _csignals_T_146; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_148 = _csignals_T_3 | _csignals_T_147; // @[Lookup.scala:31:38, :34:39] wire csignals_0 = _csignals_T_1 | _csignals_T_148; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_162 = _csignals_T_73 ? 4'h6 : 4'h0; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_163 = _csignals_T_71 ? 4'h5 : _csignals_T_162; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_164 = _csignals_T_69 ? 4'h4 : _csignals_T_163; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_165 = _csignals_T_67 ? 4'h3 : _csignals_T_164; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_166 = _csignals_T_65 ? 4'h1 : _csignals_T_165; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_167 = _csignals_T_63 ? 4'h2 : _csignals_T_166; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_168 = _csignals_T_61 ? 4'h8 : _csignals_T_167; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_169 = _csignals_T_59 ? 4'h7 : _csignals_T_168; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_170 = _csignals_T_57 ? 4'h0 : _csignals_T_169; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_171 = _csignals_T_55 ? 4'h0 : _csignals_T_170; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_172 = _csignals_T_53 ? 4'h0 : _csignals_T_171; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_173 = _csignals_T_51 ? 4'h0 : _csignals_T_172; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_174 = _csignals_T_49 ? 4'h0 : _csignals_T_173; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_175 = _csignals_T_47 ? 4'h0 : _csignals_T_174; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_176 = _csignals_T_45 ? 4'h0 : _csignals_T_175; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_177 = _csignals_T_43 ? 4'h0 : _csignals_T_176; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_178 = _csignals_T_41 ? 4'h0 : _csignals_T_177; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_179 = _csignals_T_39 ? 4'h0 : _csignals_T_178; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_180 = _csignals_T_37 ? 4'h0 : _csignals_T_179; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_181 = _csignals_T_35 ? 4'h0 : _csignals_T_180; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_182 = _csignals_T_33 ? 4'h0 : _csignals_T_181; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_183 = _csignals_T_31 ? 4'h0 : _csignals_T_182; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_184 = _csignals_T_29 ? 4'h0 : _csignals_T_183; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_185 = _csignals_T_27 ? 4'h0 : _csignals_T_184; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_186 = _csignals_T_25 ? 4'h0 : _csignals_T_185; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_187 = _csignals_T_23 ? 4'h0 : _csignals_T_186; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_188 = _csignals_T_21 ? 4'h0 : _csignals_T_187; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_189 = _csignals_T_19 ? 4'h0 : _csignals_T_188; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_190 = _csignals_T_17 ? 4'h0 : _csignals_T_189; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_191 = _csignals_T_15 ? 4'h0 : _csignals_T_190; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_192 = _csignals_T_13 ? 4'h0 : _csignals_T_191; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_193 = _csignals_T_11 ? 4'h0 : _csignals_T_192; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_194 = _csignals_T_9 ? 4'h0 : _csignals_T_193; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_195 = _csignals_T_7 ? 4'h0 : _csignals_T_194; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_196 = _csignals_T_5 ? 4'h0 : _csignals_T_195; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_197 = _csignals_T_3 ? 4'h0 : _csignals_T_196; // @[Lookup.scala:31:38, :34:39] wire [3:0] csignals_1 = _csignals_T_1 ? 4'h0 : _csignals_T_197; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_208 = {_csignals_T_79, 1'h0}; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_209 = _csignals_T_77 ? 2'h2 : _csignals_T_208; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_210 = _csignals_T_75 ? 2'h2 : _csignals_T_209; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_211 = _csignals_T_73 ? 2'h0 : _csignals_T_210; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_212 = _csignals_T_71 ? 2'h0 : _csignals_T_211; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_213 = _csignals_T_69 ? 2'h0 : _csignals_T_212; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_214 = _csignals_T_67 ? 2'h0 : _csignals_T_213; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_215 = _csignals_T_65 ? 2'h0 : _csignals_T_214; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_216 = _csignals_T_63 ? 2'h0 : _csignals_T_215; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_217 = _csignals_T_61 ? 2'h0 : _csignals_T_216; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_218 = _csignals_T_59 ? 2'h0 : _csignals_T_217; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_219 = _csignals_T_57 ? 2'h0 : _csignals_T_218; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_220 = _csignals_T_55 ? 2'h0 : _csignals_T_219; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_221 = _csignals_T_53 ? 2'h0 : _csignals_T_220; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_222 = _csignals_T_51 ? 2'h0 : _csignals_T_221; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_223 = _csignals_T_49 ? 2'h0 : _csignals_T_222; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_224 = _csignals_T_47 ? 2'h0 : _csignals_T_223; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_225 = _csignals_T_45 ? 2'h0 : _csignals_T_224; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_226 = _csignals_T_43 ? 2'h0 : _csignals_T_225; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_227 = _csignals_T_41 ? 2'h0 : _csignals_T_226; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_228 = _csignals_T_39 ? 2'h0 : _csignals_T_227; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_229 = _csignals_T_37 ? 2'h0 : _csignals_T_228; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_230 = _csignals_T_35 ? 2'h0 : _csignals_T_229; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_231 = _csignals_T_33 ? 2'h0 : _csignals_T_230; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_232 = _csignals_T_31 ? 2'h0 : _csignals_T_231; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_233 = _csignals_T_29 ? 2'h0 : _csignals_T_232; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_234 = _csignals_T_27 ? 2'h0 : _csignals_T_233; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_235 = _csignals_T_25 ? 2'h0 : _csignals_T_234; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_236 = _csignals_T_23 ? 2'h0 : _csignals_T_235; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_237 = _csignals_T_21 ? 2'h0 : _csignals_T_236; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_238 = _csignals_T_19 ? 2'h1 : _csignals_T_237; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_239 = _csignals_T_17 ? 2'h1 : _csignals_T_238; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_240 = _csignals_T_15 ? 2'h0 : _csignals_T_239; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_241 = _csignals_T_13 ? 2'h0 : _csignals_T_240; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_242 = _csignals_T_11 ? 2'h0 : _csignals_T_241; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_243 = _csignals_T_9 ? 2'h0 : _csignals_T_242; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_244 = _csignals_T_7 ? 2'h0 : _csignals_T_243; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_245 = _csignals_T_5 ? 2'h0 : _csignals_T_244; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_246 = _csignals_T_3 ? 2'h0 : _csignals_T_245; // @[Lookup.scala:31:38, :34:39] assign csignals_2 = _csignals_T_1 ? 2'h0 : _csignals_T_246; // @[Lookup.scala:31:38, :34:39] assign io_ctl_op1_sel_0 = csignals_2; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_266 = {1'h0, _csignals_T_61}; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_267 = _csignals_T_59 ? 2'h0 : _csignals_T_266; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_268 = _csignals_T_57 ? 2'h0 : _csignals_T_267; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_269 = _csignals_T_55 ? 2'h0 : _csignals_T_268; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_270 = _csignals_T_53 ? 2'h0 : _csignals_T_269; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_271 = _csignals_T_51 ? 2'h0 : _csignals_T_270; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_272 = _csignals_T_49 ? 2'h0 : _csignals_T_271; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_273 = _csignals_T_47 ? 2'h0 : _csignals_T_272; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_274 = _csignals_T_45 ? 2'h0 : _csignals_T_273; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_275 = _csignals_T_43 ? 2'h0 : _csignals_T_274; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_276 = _csignals_T_41 ? 2'h0 : _csignals_T_275; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_277 = _csignals_T_39 ? 2'h0 : _csignals_T_276; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_278 = _csignals_T_37 ? 2'h1 : _csignals_T_277; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_279 = _csignals_T_35 ? 2'h1 : _csignals_T_278; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_280 = _csignals_T_33 ? 2'h1 : _csignals_T_279; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_281 = _csignals_T_31 ? 2'h1 : _csignals_T_280; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_282 = _csignals_T_29 ? 2'h1 : _csignals_T_281; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_283 = _csignals_T_27 ? 2'h1 : _csignals_T_282; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_284 = _csignals_T_25 ? 2'h1 : _csignals_T_283; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_285 = _csignals_T_23 ? 2'h1 : _csignals_T_284; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_286 = _csignals_T_21 ? 2'h1 : _csignals_T_285; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_287 = _csignals_T_19 ? 2'h0 : _csignals_T_286; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_288 = _csignals_T_17 ? 2'h3 : _csignals_T_287; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_289 = _csignals_T_15 ? 2'h2 : _csignals_T_288; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_290 = _csignals_T_13 ? 2'h2 : _csignals_T_289; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_291 = _csignals_T_11 ? 2'h2 : _csignals_T_290; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_292 = _csignals_T_9 ? 2'h1 : _csignals_T_291; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_293 = _csignals_T_7 ? 2'h1 : _csignals_T_292; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_294 = _csignals_T_5 ? 2'h1 : _csignals_T_293; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_295 = _csignals_T_3 ? 2'h1 : _csignals_T_294; // @[Lookup.scala:31:38, :34:39] assign csignals_3 = _csignals_T_1 ? 2'h1 : _csignals_T_295; // @[Lookup.scala:31:38, :34:39] assign io_ctl_op2_sel_0 = csignals_3; // @[Lookup.scala:34:39] wire [3:0] _csignals_T_303 = _csignals_T_85 ? 4'hB : 4'h0; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_304 = _csignals_T_83 ? 4'hB : _csignals_T_303; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_305 = _csignals_T_81 ? 4'hB : _csignals_T_304; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_306 = _csignals_T_79 ? 4'hB : _csignals_T_305; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_307 = _csignals_T_77 ? 4'hB : _csignals_T_306; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_308 = _csignals_T_75 ? 4'hB : _csignals_T_307; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_309 = _csignals_T_73 ? 4'h0 : _csignals_T_308; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_310 = _csignals_T_71 ? 4'h0 : _csignals_T_309; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_311 = _csignals_T_69 ? 4'h0 : _csignals_T_310; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_312 = _csignals_T_67 ? 4'h0 : _csignals_T_311; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_313 = _csignals_T_65 ? 4'h0 : _csignals_T_312; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_314 = _csignals_T_63 ? 4'h0 : _csignals_T_313; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_315 = _csignals_T_61 ? 4'h0 : _csignals_T_314; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_316 = _csignals_T_59 ? 4'h0 : _csignals_T_315; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_317 = _csignals_T_57 ? 4'h4 : _csignals_T_316; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_318 = _csignals_T_55 ? 4'h5 : _csignals_T_317; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_319 = _csignals_T_53 ? 4'h8 : _csignals_T_318; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_320 = _csignals_T_51 ? 4'h7 : _csignals_T_319; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_321 = _csignals_T_49 ? 4'h6 : _csignals_T_320; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_322 = _csignals_T_47 ? 4'hA : _csignals_T_321; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_323 = _csignals_T_45 ? 4'h9 : _csignals_T_322; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_324 = _csignals_T_43 ? 4'h2 : _csignals_T_323; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_325 = _csignals_T_41 ? 4'h1 : _csignals_T_324; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_326 = _csignals_T_39 ? 4'h3 : _csignals_T_325; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_327 = _csignals_T_37 ? 4'h4 : _csignals_T_326; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_328 = _csignals_T_35 ? 4'h5 : _csignals_T_327; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_329 = _csignals_T_33 ? 4'h3 : _csignals_T_328; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_330 = _csignals_T_31 ? 4'hA : _csignals_T_329; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_331 = _csignals_T_29 ? 4'h9 : _csignals_T_330; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_332 = _csignals_T_27 ? 4'h8 : _csignals_T_331; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_333 = _csignals_T_25 ? 4'h7 : _csignals_T_332; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_334 = _csignals_T_23 ? 4'h6 : _csignals_T_333; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_335 = _csignals_T_21 ? 4'h1 : _csignals_T_334; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_336 = _csignals_T_19 ? 4'hB : _csignals_T_335; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_337 = _csignals_T_17 ? 4'h1 : _csignals_T_336; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_338 = _csignals_T_15 ? 4'h1 : _csignals_T_337; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_339 = _csignals_T_13 ? 4'h1 : _csignals_T_338; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_340 = _csignals_T_11 ? 4'h1 : _csignals_T_339; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_341 = _csignals_T_9 ? 4'h1 : _csignals_T_340; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_342 = _csignals_T_7 ? 4'h1 : _csignals_T_341; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_343 = _csignals_T_5 ? 4'h1 : _csignals_T_342; // @[Lookup.scala:31:38, :34:39] wire [3:0] _csignals_T_344 = _csignals_T_3 ? 4'h1 : _csignals_T_343; // @[Lookup.scala:31:38, :34:39] assign csignals_4 = _csignals_T_1 ? 4'h1 : _csignals_T_344; // @[Lookup.scala:31:38, :34:39] assign io_ctl_alu_fun_0 = csignals_4; // @[Lookup.scala:34:39] wire [1:0] _csignals_T_352 = {2{_csignals_T_85}}; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_353 = _csignals_T_83 ? 2'h3 : _csignals_T_352; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_354 = _csignals_T_81 ? 2'h3 : _csignals_T_353; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_355 = _csignals_T_79 ? 2'h3 : _csignals_T_354; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_356 = _csignals_T_77 ? 2'h3 : _csignals_T_355; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_357 = _csignals_T_75 ? 2'h3 : _csignals_T_356; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_358 = _csignals_T_73 ? 2'h0 : _csignals_T_357; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_359 = _csignals_T_71 ? 2'h0 : _csignals_T_358; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_360 = _csignals_T_69 ? 2'h0 : _csignals_T_359; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_361 = _csignals_T_67 ? 2'h0 : _csignals_T_360; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_362 = _csignals_T_65 ? 2'h0 : _csignals_T_361; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_363 = _csignals_T_63 ? 2'h0 : _csignals_T_362; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_364 = _csignals_T_61 ? 2'h2 : _csignals_T_363; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_365 = _csignals_T_59 ? 2'h2 : _csignals_T_364; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_366 = _csignals_T_57 ? 2'h0 : _csignals_T_365; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_367 = _csignals_T_55 ? 2'h0 : _csignals_T_366; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_368 = _csignals_T_53 ? 2'h0 : _csignals_T_367; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_369 = _csignals_T_51 ? 2'h0 : _csignals_T_368; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_370 = _csignals_T_49 ? 2'h0 : _csignals_T_369; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_371 = _csignals_T_47 ? 2'h0 : _csignals_T_370; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_372 = _csignals_T_45 ? 2'h0 : _csignals_T_371; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_373 = _csignals_T_43 ? 2'h0 : _csignals_T_372; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_374 = _csignals_T_41 ? 2'h0 : _csignals_T_373; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_375 = _csignals_T_39 ? 2'h0 : _csignals_T_374; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_376 = _csignals_T_37 ? 2'h0 : _csignals_T_375; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_377 = _csignals_T_35 ? 2'h0 : _csignals_T_376; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_378 = _csignals_T_33 ? 2'h0 : _csignals_T_377; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_379 = _csignals_T_31 ? 2'h0 : _csignals_T_378; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_380 = _csignals_T_29 ? 2'h0 : _csignals_T_379; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_381 = _csignals_T_27 ? 2'h0 : _csignals_T_380; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_382 = _csignals_T_25 ? 2'h0 : _csignals_T_381; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_383 = _csignals_T_23 ? 2'h0 : _csignals_T_382; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_384 = _csignals_T_21 ? 2'h0 : _csignals_T_383; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_385 = _csignals_T_19 ? 2'h0 : _csignals_T_384; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_386 = _csignals_T_17 ? 2'h0 : _csignals_T_385; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_387 = _csignals_T_15 ? 2'h0 : _csignals_T_386; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_388 = _csignals_T_13 ? 2'h0 : _csignals_T_387; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_389 = _csignals_T_11 ? 2'h0 : _csignals_T_388; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_390 = _csignals_T_9 ? 2'h1 : _csignals_T_389; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_391 = _csignals_T_7 ? 2'h1 : _csignals_T_390; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_392 = _csignals_T_5 ? 2'h1 : _csignals_T_391; // @[Lookup.scala:31:38, :34:39] wire [1:0] _csignals_T_393 = _csignals_T_3 ? 2'h1 : _csignals_T_392; // @[Lookup.scala:31:38, :34:39] assign csignals_5 = _csignals_T_1 ? 2'h1 : _csignals_T_393; // @[Lookup.scala:31:38, :34:39] assign io_ctl_wb_sel_0 = csignals_5; // @[Lookup.scala:34:39] wire _csignals_T_402 = _csignals_T_83 | _csignals_T_401; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_403 = _csignals_T_81 | _csignals_T_402; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_404 = _csignals_T_79 | _csignals_T_403; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_405 = _csignals_T_77 | _csignals_T_404; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_406 = _csignals_T_75 | _csignals_T_405; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_407 = ~_csignals_T_73 & _csignals_T_406; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_408 = ~_csignals_T_71 & _csignals_T_407; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_409 = ~_csignals_T_69 & _csignals_T_408; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_410 = ~_csignals_T_67 & _csignals_T_409; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_411 = ~_csignals_T_65 & _csignals_T_410; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_412 = ~_csignals_T_63 & _csignals_T_411; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_413 = _csignals_T_61 | _csignals_T_412; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_414 = _csignals_T_59 | _csignals_T_413; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_415 = _csignals_T_57 | _csignals_T_414; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_416 = _csignals_T_55 | _csignals_T_415; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_417 = _csignals_T_53 | _csignals_T_416; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_418 = _csignals_T_51 | _csignals_T_417; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_419 = _csignals_T_49 | _csignals_T_418; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_420 = _csignals_T_47 | _csignals_T_419; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_421 = _csignals_T_45 | _csignals_T_420; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_422 = _csignals_T_43 | _csignals_T_421; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_423 = _csignals_T_41 | _csignals_T_422; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_424 = _csignals_T_39 | _csignals_T_423; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_425 = _csignals_T_37 | _csignals_T_424; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_426 = _csignals_T_35 | _csignals_T_425; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_427 = _csignals_T_33 | _csignals_T_426; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_428 = _csignals_T_31 | _csignals_T_427; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_429 = _csignals_T_29 | _csignals_T_428; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_430 = _csignals_T_27 | _csignals_T_429; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_431 = _csignals_T_25 | _csignals_T_430; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_432 = _csignals_T_23 | _csignals_T_431; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_433 = _csignals_T_21 | _csignals_T_432; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_434 = _csignals_T_19 | _csignals_T_433; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_435 = _csignals_T_17 | _csignals_T_434; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_436 = ~_csignals_T_15 & _csignals_T_435; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_437 = ~_csignals_T_13 & _csignals_T_436; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_438 = ~_csignals_T_11 & _csignals_T_437; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_439 = _csignals_T_9 | _csignals_T_438; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_440 = _csignals_T_7 | _csignals_T_439; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_441 = _csignals_T_5 | _csignals_T_440; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_442 = _csignals_T_3 | _csignals_T_441; // @[Lookup.scala:31:38, :34:39] wire csignals_6 = _csignals_T_1 | _csignals_T_442; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_486 = _csignals_T_13 | _csignals_T_485; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_487 = _csignals_T_11 | _csignals_T_486; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_488 = _csignals_T_9 | _csignals_T_487; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_489 = _csignals_T_7 | _csignals_T_488; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_490 = _csignals_T_5 | _csignals_T_489; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_491 = _csignals_T_3 | _csignals_T_490; // @[Lookup.scala:31:38, :34:39] wire csignals_7 = _csignals_T_1 | _csignals_T_491; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_535 = _csignals_T_13 | _csignals_T_534; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_536 = _csignals_T_11 | _csignals_T_535; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_537 = ~_csignals_T_9 & _csignals_T_536; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_538 = ~_csignals_T_7 & _csignals_T_537; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_539 = ~_csignals_T_5 & _csignals_T_538; // @[Lookup.scala:31:38, :34:39] wire _csignals_T_540 = ~_csignals_T_3 & _csignals_T_539; // @[Lookup.scala:31:38, :34:39] assign csignals_8 = ~_csignals_T_1 & _csignals_T_540; // @[Lookup.scala:31:38, :34:39] assign io_dmem_req_bits_fcn_0 = csignals_8; // @[Lookup.scala:34:39] wire mem_store = csignals_8; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_583 = {1'h0, _csignals_T_15, 1'h0}; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_584 = _csignals_T_13 ? 3'h1 : _csignals_T_583; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_585 = _csignals_T_11 ? 3'h3 : _csignals_T_584; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_586 = _csignals_T_9 ? 3'h6 : _csignals_T_585; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_587 = _csignals_T_7 ? 3'h2 : _csignals_T_586; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_588 = _csignals_T_5 ? 3'h5 : _csignals_T_587; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_589 = _csignals_T_3 ? 3'h1 : _csignals_T_588; // @[Lookup.scala:31:38, :34:39] assign csignals_9 = _csignals_T_1 ? 3'h3 : _csignals_T_589; // @[Lookup.scala:31:38, :34:39] assign io_dmem_req_bits_typ_0 = csignals_9; // @[Lookup.scala:34:39] wire [2:0] _csignals_T_593 = {_csignals_T_93, 2'h0}; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_594 = _csignals_T_91 ? 3'h4 : _csignals_T_593; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_595 = _csignals_T_89 ? 3'h4 : _csignals_T_594; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_596 = _csignals_T_87 ? 3'h4 : _csignals_T_595; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_597 = _csignals_T_85 ? 3'h7 : _csignals_T_596; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_598 = _csignals_T_83 ? 3'h6 : _csignals_T_597; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_599 = _csignals_T_81 ? 3'h5 : _csignals_T_598; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_600 = _csignals_T_79 ? 3'h7 : _csignals_T_599; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_601 = _csignals_T_77 ? 3'h6 : _csignals_T_600; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_602 = _csignals_T_75 ? 3'h5 : _csignals_T_601; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_603 = _csignals_T_73 ? 3'h0 : _csignals_T_602; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_604 = _csignals_T_71 ? 3'h0 : _csignals_T_603; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_605 = _csignals_T_69 ? 3'h0 : _csignals_T_604; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_606 = _csignals_T_67 ? 3'h0 : _csignals_T_605; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_607 = _csignals_T_65 ? 3'h0 : _csignals_T_606; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_608 = _csignals_T_63 ? 3'h0 : _csignals_T_607; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_609 = _csignals_T_61 ? 3'h0 : _csignals_T_608; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_610 = _csignals_T_59 ? 3'h0 : _csignals_T_609; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_611 = _csignals_T_57 ? 3'h0 : _csignals_T_610; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_612 = _csignals_T_55 ? 3'h0 : _csignals_T_611; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_613 = _csignals_T_53 ? 3'h0 : _csignals_T_612; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_614 = _csignals_T_51 ? 3'h0 : _csignals_T_613; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_615 = _csignals_T_49 ? 3'h0 : _csignals_T_614; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_616 = _csignals_T_47 ? 3'h0 : _csignals_T_615; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_617 = _csignals_T_45 ? 3'h0 : _csignals_T_616; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_618 = _csignals_T_43 ? 3'h0 : _csignals_T_617; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_619 = _csignals_T_41 ? 3'h0 : _csignals_T_618; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_620 = _csignals_T_39 ? 3'h0 : _csignals_T_619; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_621 = _csignals_T_37 ? 3'h0 : _csignals_T_620; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_622 = _csignals_T_35 ? 3'h0 : _csignals_T_621; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_623 = _csignals_T_33 ? 3'h0 : _csignals_T_622; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_624 = _csignals_T_31 ? 3'h0 : _csignals_T_623; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_625 = _csignals_T_29 ? 3'h0 : _csignals_T_624; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_626 = _csignals_T_27 ? 3'h0 : _csignals_T_625; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_627 = _csignals_T_25 ? 3'h0 : _csignals_T_626; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_628 = _csignals_T_23 ? 3'h0 : _csignals_T_627; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_629 = _csignals_T_21 ? 3'h0 : _csignals_T_628; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_630 = _csignals_T_19 ? 3'h0 : _csignals_T_629; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_631 = _csignals_T_17 ? 3'h0 : _csignals_T_630; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_632 = _csignals_T_15 ? 3'h0 : _csignals_T_631; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_633 = _csignals_T_13 ? 3'h0 : _csignals_T_632; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_634 = _csignals_T_11 ? 3'h0 : _csignals_T_633; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_635 = _csignals_T_9 ? 3'h0 : _csignals_T_634; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_636 = _csignals_T_7 ? 3'h0 : _csignals_T_635; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_637 = _csignals_T_5 ? 3'h0 : _csignals_T_636; // @[Lookup.scala:31:38, :34:39] wire [2:0] _csignals_T_638 = _csignals_T_3 ? 3'h0 : _csignals_T_637; // @[Lookup.scala:31:38, :34:39] wire [2:0] csignals_10 = _csignals_T_1 ? 3'h0 : _csignals_T_638; // @[Lookup.scala:31:38, :34:39] wire _ctrl_pc_sel_no_xept_T = csignals_1 == 4'h0; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_1 = csignals_1 == 4'h1; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_2 = ~io_dat_br_eq_0; // @[cpath.scala:44:7, :122:63] wire [2:0] _ctrl_pc_sel_no_xept_T_3 = {2'h0, _ctrl_pc_sel_no_xept_T_2}; // @[cpath.scala:122:{62,63}] wire _ctrl_pc_sel_no_xept_T_4 = csignals_1 == 4'h2; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_5 = {2'h0, io_dat_br_eq_0}; // @[cpath.scala:44:7, :123:62] wire _ctrl_pc_sel_no_xept_T_6 = csignals_1 == 4'h3; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_7 = ~io_dat_br_lt_0; // @[cpath.scala:44:7, :124:63] wire [2:0] _ctrl_pc_sel_no_xept_T_8 = {2'h0, _ctrl_pc_sel_no_xept_T_7}; // @[cpath.scala:124:{62,63}] wire _ctrl_pc_sel_no_xept_T_9 = csignals_1 == 4'h4; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_10 = ~io_dat_br_ltu_0; // @[cpath.scala:44:7, :125:63] wire [2:0] _ctrl_pc_sel_no_xept_T_11 = {2'h0, _ctrl_pc_sel_no_xept_T_10}; // @[cpath.scala:125:{62,63}] wire _ctrl_pc_sel_no_xept_T_12 = csignals_1 == 4'h5; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_13 = {2'h0, io_dat_br_lt_0}; // @[cpath.scala:44:7, :126:62] wire _ctrl_pc_sel_no_xept_T_14 = csignals_1 == 4'h6; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_15 = {2'h0, io_dat_br_ltu_0}; // @[cpath.scala:44:7, :127:62] wire _ctrl_pc_sel_no_xept_T_16 = csignals_1 == 4'h7; // @[Lookup.scala:34:39] wire _ctrl_pc_sel_no_xept_T_17 = csignals_1 == 4'h8; // @[Lookup.scala:34:39] wire [2:0] _ctrl_pc_sel_no_xept_T_18 = _ctrl_pc_sel_no_xept_T_17 ? 3'h3 : 3'h0; // @[cpath.scala:129:{34,46}] wire [2:0] _ctrl_pc_sel_no_xept_T_19 = _ctrl_pc_sel_no_xept_T_16 ? 3'h2 : _ctrl_pc_sel_no_xept_T_18; // @[cpath.scala:128:{34,46}, :129:34] wire [2:0] _ctrl_pc_sel_no_xept_T_20 = _ctrl_pc_sel_no_xept_T_14 ? _ctrl_pc_sel_no_xept_T_15 : _ctrl_pc_sel_no_xept_T_19; // @[cpath.scala:127:{34,46,62}, :128:34] wire [2:0] _ctrl_pc_sel_no_xept_T_21 = _ctrl_pc_sel_no_xept_T_12 ? _ctrl_pc_sel_no_xept_T_13 : _ctrl_pc_sel_no_xept_T_20; // @[cpath.scala:126:{34,46,62}, :127:34] wire [2:0] _ctrl_pc_sel_no_xept_T_22 = _ctrl_pc_sel_no_xept_T_9 ? _ctrl_pc_sel_no_xept_T_11 : _ctrl_pc_sel_no_xept_T_21; // @[cpath.scala:125:{34,46,62}, :126:34] wire [2:0] _ctrl_pc_sel_no_xept_T_23 = _ctrl_pc_sel_no_xept_T_6 ? _ctrl_pc_sel_no_xept_T_8 : _ctrl_pc_sel_no_xept_T_22; // @[cpath.scala:124:{34,46,62}, :125:34] wire [2:0] _ctrl_pc_sel_no_xept_T_24 = _ctrl_pc_sel_no_xept_T_4 ? _ctrl_pc_sel_no_xept_T_5 : _ctrl_pc_sel_no_xept_T_23; // @[cpath.scala:123:{34,46,62}, :124:34] wire [2:0] _ctrl_pc_sel_no_xept_T_25 = _ctrl_pc_sel_no_xept_T_1 ? _ctrl_pc_sel_no_xept_T_3 : _ctrl_pc_sel_no_xept_T_24; // @[cpath.scala:122:{34,46,62}, :123:34] wire [2:0] _ctrl_pc_sel_no_xept_T_26 = _ctrl_pc_sel_no_xept_T ? 3'h0 : _ctrl_pc_sel_no_xept_T_25; // @[cpath.scala:121:{34,46}, :122:34] assign ctrl_pc_sel_no_xept = io_dat_csr_interrupt_0 ? 3'h4 : _ctrl_pc_sel_no_xept_T_26; // @[cpath.scala:44:7, :120:34, :121:34] assign io_ctl_pc_sel_no_xept_0 = ctrl_pc_sel_no_xept; // @[cpath.scala:44:7, :120:34] wire _ctrl_pc_sel_T = io_ctl_exception_0 | io_dat_csr_eret_0; // @[cpath.scala:44:7, :131:43] assign ctrl_pc_sel = _ctrl_pc_sel_T ? 3'h4 : ctrl_pc_sel_no_xept; // @[cpath.scala:120:34, :131:{25,43}] assign io_ctl_pc_sel_0 = ctrl_pc_sel; // @[cpath.scala:44:7, :131:25] reg reg_mem_en; // @[cpath.scala:135:28] wire mem_en = io_imem_resp_valid_0 ? csignals_7 : reg_mem_en; // @[Lookup.scala:34:39] wire _data_misaligned_T_2; // @[cpath.scala:177:70] wire data_misaligned; // @[cpath.scala:143:30] wire _io_ctl_dmiss_T = io_dmem_resp_valid_0 | data_misaligned; // @[cpath.scala:44:7, :143:30, :144:53] wire _io_ctl_dmiss_T_1 = mem_en & _io_ctl_dmiss_T; // @[cpath.scala:141:20, :144:{30,53}] wire _io_ctl_dmiss_T_2 = ~mem_en; // @[cpath.scala:141:20, :144:77] wire _io_ctl_dmiss_T_3 = _io_ctl_dmiss_T_1 | _io_ctl_dmiss_T_2; // @[cpath.scala:144:{30,74,77}] assign _io_ctl_dmiss_T_4 = ~_io_ctl_dmiss_T_3; // @[cpath.scala:144:{20,74}] assign io_ctl_dmiss_0 = _io_ctl_dmiss_T_4; // @[cpath.scala:44:7, :144:20] assign stall = io_dat_imiss_0 | io_ctl_dmiss_0; // @[cpath.scala:44:7, :145:30] assign io_ctl_stall_0 = stall; // @[cpath.scala:44:7, :145:30] wire _io_ctl_rf_wen_T = stall | io_ctl_exception_0; // @[cpath.scala:44:7, :145:30, :155:33] assign _io_ctl_rf_wen_T_1 = ~_io_ctl_rf_wen_T & csignals_6; // @[Lookup.scala:34:39] assign io_ctl_rf_wen_0 = _io_ctl_rf_wen_T_1; // @[cpath.scala:44:7, :155:26] wire [4:0] rs1_addr = io_dat_inst_0[19:15]; // @[cpath.scala:44:7, :158:30] wire _csr_ren_T = csignals_10 == 3'h6; // @[Lookup.scala:34:39] wire _csr_ren_T_1 = &csignals_10; // @[Lookup.scala:34:39] wire _csr_ren_T_2 = _csr_ren_T | _csr_ren_T_1; // @[cpath.scala:159:{30,40,54}] wire _csr_ren_T_3 = rs1_addr == 5'h0; // @[cpath.scala:158:30, :159:77] wire csr_ren = _csr_ren_T_2 & _csr_ren_T_3; // @[cpath.scala:159:{40,65,77}] wire [2:0] csr_cmd = csr_ren ? 3'h2 : csignals_10; // @[Lookup.scala:34:39] assign _io_ctl_csr_cmd_T = stall ? 3'h0 : csr_cmd; // @[cpath.scala:145:30, :160:21, :162:26] assign io_ctl_csr_cmd_0 = _io_ctl_csr_cmd_T; // @[cpath.scala:44:7, :162:26] wire _io_dmem_req_valid_T = ~io_ctl_exception_0; // @[cpath.scala:44:7, :165:38] assign _io_dmem_req_valid_T_1 = mem_en & _io_dmem_req_valid_T; // @[cpath.scala:141:20, :165:{35,38}] assign io_dmem_req_valid_0 = _io_dmem_req_valid_T_1; // @[cpath.scala:44:7, :165:35] wire _illegal_T = ~csignals_0; // @[Lookup.scala:34:39] wire illegal = _illegal_T & io_imem_resp_valid_0; // @[cpath.scala:44:7, :171:{19,32}] wire [2:0] misaligned_mask; // @[cpath.scala:175:30] wire [3:0] _misaligned_mask_T = {1'h0, csignals_9} - 4'h1; // @[Lookup.scala:34:39] wire [2:0] _misaligned_mask_T_1 = _misaligned_mask_T[2:0]; // @[cpath.scala:176:49] wire [1:0] _misaligned_mask_T_2 = _misaligned_mask_T_1[1:0]; // @[cpath.scala:176:{49,55}] wire [5:0] _misaligned_mask_T_3 = 6'h7 << _misaligned_mask_T_2; // @[cpath.scala:176:{34,55}] wire [5:0] _misaligned_mask_T_4 = ~_misaligned_mask_T_3; // @[cpath.scala:176:{23,34}] assign misaligned_mask = _misaligned_mask_T_4[2:0]; // @[cpath.scala:175:30, :176:{20,23}] wire [2:0] _data_misaligned_T = misaligned_mask & io_dat_mem_address_low_0; // @[cpath.scala:44:7, :175:30, :177:40] wire _data_misaligned_T_1 = |_data_misaligned_T; // @[cpath.scala:177:{40,66}] assign _data_misaligned_T_2 = _data_misaligned_T_1 & mem_en; // @[cpath.scala:141:20, :177:{66,70}] assign data_misaligned = _data_misaligned_T_2; // @[cpath.scala:143:30, :177:70] wire _io_ctl_exception_T = illegal | io_dat_inst_misaligned_0; // @[cpath.scala:44:7, :171:32, :182:32] assign _io_ctl_exception_T_1 = _io_ctl_exception_T | data_misaligned; // @[cpath.scala:143:30, :182:{32,58}] assign io_ctl_exception_0 = _io_ctl_exception_T_1; // @[cpath.scala:44:7, :182:58] wire [2:0] _io_ctl_exception_cause_T = {1'h1, mem_store, 1'h0}; // @[cpath.scala:178:31, :185:34] wire [2:0] _io_ctl_exception_cause_T_1 = io_dat_inst_misaligned_0 ? 3'h0 : _io_ctl_exception_cause_T; // @[cpath.scala:44:7, :184:34, :185:34] wire [2:0] _io_ctl_exception_cause_T_2 = illegal ? 3'h2 : _io_ctl_exception_cause_T_1; // @[cpath.scala:171:32, :183:34, :184:34] assign io_ctl_exception_cause_0 = {29'h0, _io_ctl_exception_cause_T_2}; // @[cpath.scala:44:7, :183:{27,34}] always @(posedge clock) begin // @[cpath.scala:44:7] if (reset) // @[cpath.scala:44:7] reg_mem_en <= 1'h0; // @[cpath.scala:135:28] else // @[cpath.scala:44:7] reg_mem_en <= ~io_dmem_resp_valid_0 & mem_en; // @[cpath.scala:44:7, :135:28, :136:30, :137:18, :138:37, :141:20] always @(posedge) assign io_dmem_req_valid = io_dmem_req_valid_0; // @[cpath.scala:44:7] assign io_dmem_req_bits_fcn = io_dmem_req_bits_fcn_0; // @[cpath.scala:44:7] assign io_dmem_req_bits_typ = io_dmem_req_bits_typ_0; // @[cpath.scala:44:7] assign io_ctl_stall = io_ctl_stall_0; // @[cpath.scala:44:7] assign io_ctl_dmiss = io_ctl_dmiss_0; // @[cpath.scala:44:7] assign io_ctl_pc_sel = io_ctl_pc_sel_0; // @[cpath.scala:44:7] assign io_ctl_op1_sel = io_ctl_op1_sel_0; // @[cpath.scala:44:7] assign io_ctl_op2_sel = io_ctl_op2_sel_0; // @[cpath.scala:44:7] assign io_ctl_alu_fun = io_ctl_alu_fun_0; // @[cpath.scala:44:7] assign io_ctl_wb_sel = io_ctl_wb_sel_0; // @[cpath.scala:44:7] assign io_ctl_rf_wen = io_ctl_rf_wen_0; // @[cpath.scala:44:7] assign io_ctl_csr_cmd = io_ctl_csr_cmd_0; // @[cpath.scala:44:7] assign io_ctl_exception = io_ctl_exception_0; // @[cpath.scala:44:7] assign io_ctl_exception_cause = io_ctl_exception_cause_0; // @[cpath.scala:44:7] assign io_ctl_pc_sel_no_xept = io_ctl_pc_sel_no_xept_0; // @[cpath.scala:44:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_22 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = or(UInt<1>(0h0), _T_70) node _T_72 = and(_T_21, _T_71) node _T_73 = asUInt(reset) node _T_74 = eq(_T_73, UInt<1>(0h0)) when _T_74 : node _T_75 = eq(_T_72, UInt<1>(0h0)) when _T_75 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_72, UInt<1>(0h1), "") : assert_2 node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<14>(0h2000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<13>(0h1000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<17>(0h10000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<18>(0h2f000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<17>(0h10000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<13>(0h1000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<13>(0h1000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = or(_T_84, _T_89) node _T_121 = or(_T_120, _T_94) node _T_122 = or(_T_121, _T_99) node _T_123 = or(_T_122, _T_104) node _T_124 = or(_T_123, _T_109) node _T_125 = or(_T_124, _T_114) node _T_126 = or(_T_125, _T_119) node _T_127 = and(_T_79, _T_126) node _T_128 = or(UInt<1>(0h0), _T_127) node _T_129 = and(UInt<1>(0h0), _T_128) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_129, UInt<1>(0h1), "") : assert_3 node _T_133 = asUInt(reset) node _T_134 = eq(_T_133, UInt<1>(0h0)) when _T_134 : node _T_135 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_136 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_136, UInt<1>(0h1), "") : assert_5 node _T_140 = asUInt(reset) node _T_141 = eq(_T_140, UInt<1>(0h0)) when _T_141 : node _T_142 = eq(is_aligned, UInt<1>(0h0)) when _T_142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_143 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_143, UInt<1>(0h1), "") : assert_7 node _T_147 = not(io.in.a.bits.mask) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_148, UInt<1>(0h1), "") : assert_8 node _T_152 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_T_152, UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_152, UInt<1>(0h1), "") : assert_9 node _T_156 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_156 : node _T_157 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_158 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_159 = and(_T_157, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_165 = cvt(_T_164) node _T_166 = and(_T_165, asSInt(UInt<14>(0h2000))) node _T_167 = asSInt(_T_166) node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0))) node _T_169 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_170 = cvt(_T_169) node _T_171 = and(_T_170, asSInt(UInt<13>(0h1000))) node _T_172 = asSInt(_T_171) node _T_173 = eq(_T_172, asSInt(UInt<1>(0h0))) node _T_174 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_175 = cvt(_T_174) node _T_176 = and(_T_175, asSInt(UInt<17>(0h10000))) node _T_177 = asSInt(_T_176) node _T_178 = eq(_T_177, asSInt(UInt<1>(0h0))) node _T_179 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<18>(0h2f000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<17>(0h10000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<13>(0h1000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<27>(0h4000000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<13>(0h1000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = or(_T_168, _T_173) node _T_205 = or(_T_204, _T_178) node _T_206 = or(_T_205, _T_183) node _T_207 = or(_T_206, _T_188) node _T_208 = or(_T_207, _T_193) node _T_209 = or(_T_208, _T_198) node _T_210 = or(_T_209, _T_203) node _T_211 = and(_T_163, _T_210) node _T_212 = or(UInt<1>(0h0), _T_211) node _T_213 = and(_T_162, _T_212) node _T_214 = asUInt(reset) node _T_215 = eq(_T_214, UInt<1>(0h0)) when _T_215 : node _T_216 = eq(_T_213, UInt<1>(0h0)) when _T_216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_213, UInt<1>(0h1), "") : assert_10 node _T_217 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_218 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_219 = and(_T_217, _T_218) node _T_220 = or(UInt<1>(0h0), _T_219) node _T_221 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<14>(0h2000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_232 = cvt(_T_231) node _T_233 = and(_T_232, asSInt(UInt<17>(0h10000))) node _T_234 = asSInt(_T_233) node _T_235 = eq(_T_234, asSInt(UInt<1>(0h0))) node _T_236 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_237 = cvt(_T_236) node _T_238 = and(_T_237, asSInt(UInt<18>(0h2f000))) node _T_239 = asSInt(_T_238) node _T_240 = eq(_T_239, asSInt(UInt<1>(0h0))) node _T_241 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<13>(0h1000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<27>(0h4000000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<13>(0h1000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = or(_T_225, _T_230) node _T_262 = or(_T_261, _T_235) node _T_263 = or(_T_262, _T_240) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_250) node _T_266 = or(_T_265, _T_255) node _T_267 = or(_T_266, _T_260) node _T_268 = and(_T_220, _T_267) node _T_269 = or(UInt<1>(0h0), _T_268) node _T_270 = and(UInt<1>(0h0), _T_269) node _T_271 = asUInt(reset) node _T_272 = eq(_T_271, UInt<1>(0h0)) when _T_272 : node _T_273 = eq(_T_270, UInt<1>(0h0)) when _T_273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_270, UInt<1>(0h1), "") : assert_11 node _T_274 = asUInt(reset) node _T_275 = eq(_T_274, UInt<1>(0h0)) when _T_275 : node _T_276 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_276 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_277 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_278 = asUInt(reset) node _T_279 = eq(_T_278, UInt<1>(0h0)) when _T_279 : node _T_280 = eq(_T_277, UInt<1>(0h0)) when _T_280 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_277, UInt<1>(0h1), "") : assert_13 node _T_281 = asUInt(reset) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(is_aligned, UInt<1>(0h0)) when _T_283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_284 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_284, UInt<1>(0h1), "") : assert_15 node _T_288 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_289 = asUInt(reset) node _T_290 = eq(_T_289, UInt<1>(0h0)) when _T_290 : node _T_291 = eq(_T_288, UInt<1>(0h0)) when _T_291 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_288, UInt<1>(0h1), "") : assert_16 node _T_292 = not(io.in.a.bits.mask) node _T_293 = eq(_T_292, UInt<1>(0h0)) node _T_294 = asUInt(reset) node _T_295 = eq(_T_294, UInt<1>(0h0)) when _T_295 : node _T_296 = eq(_T_293, UInt<1>(0h0)) when _T_296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_293, UInt<1>(0h1), "") : assert_17 node _T_297 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_T_297, UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_297, UInt<1>(0h1), "") : assert_18 node _T_301 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_301 : node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_306 = and(_T_304, _T_305) node _T_307 = or(UInt<1>(0h0), _T_306) node _T_308 = asUInt(reset) node _T_309 = eq(_T_308, UInt<1>(0h0)) when _T_309 : node _T_310 = eq(_T_307, UInt<1>(0h0)) when _T_310 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_307, UInt<1>(0h1), "") : assert_19 node _T_311 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_312 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_313 = and(_T_311, _T_312) node _T_314 = or(UInt<1>(0h0), _T_313) node _T_315 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = and(_T_314, _T_319) node _T_321 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_322 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_323 = and(_T_321, _T_322) node _T_324 = or(UInt<1>(0h0), _T_323) node _T_325 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<14>(0h2000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<17>(0h10000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_336 = cvt(_T_335) node _T_337 = and(_T_336, asSInt(UInt<18>(0h2f000))) node _T_338 = asSInt(_T_337) node _T_339 = eq(_T_338, asSInt(UInt<1>(0h0))) node _T_340 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<13>(0h1000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_351 = cvt(_T_350) node _T_352 = and(_T_351, asSInt(UInt<27>(0h4000000))) node _T_353 = asSInt(_T_352) node _T_354 = eq(_T_353, asSInt(UInt<1>(0h0))) node _T_355 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<13>(0h1000))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = or(_T_329, _T_334) node _T_361 = or(_T_360, _T_339) node _T_362 = or(_T_361, _T_344) node _T_363 = or(_T_362, _T_349) node _T_364 = or(_T_363, _T_354) node _T_365 = or(_T_364, _T_359) node _T_366 = and(_T_324, _T_365) node _T_367 = or(UInt<1>(0h0), _T_320) node _T_368 = or(_T_367, _T_366) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_368, UInt<1>(0h1), "") : assert_20 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_378 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_378, UInt<1>(0h1), "") : assert_23 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_382, UInt<1>(0h1), "") : assert_24 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_386, UInt<1>(0h1), "") : assert_25 node _T_390 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_390 : node _T_391 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_392 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_398 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_399 = and(_T_397, _T_398) node _T_400 = or(UInt<1>(0h0), _T_399) node _T_401 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_402 = cvt(_T_401) node _T_403 = and(_T_402, asSInt(UInt<13>(0h1000))) node _T_404 = asSInt(_T_403) node _T_405 = eq(_T_404, asSInt(UInt<1>(0h0))) node _T_406 = and(_T_400, _T_405) node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_409 = and(_T_407, _T_408) node _T_410 = or(UInt<1>(0h0), _T_409) node _T_411 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_412 = cvt(_T_411) node _T_413 = and(_T_412, asSInt(UInt<14>(0h2000))) node _T_414 = asSInt(_T_413) node _T_415 = eq(_T_414, asSInt(UInt<1>(0h0))) node _T_416 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_417 = cvt(_T_416) node _T_418 = and(_T_417, asSInt(UInt<18>(0h2f000))) node _T_419 = asSInt(_T_418) node _T_420 = eq(_T_419, asSInt(UInt<1>(0h0))) node _T_421 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_422 = cvt(_T_421) node _T_423 = and(_T_422, asSInt(UInt<17>(0h10000))) node _T_424 = asSInt(_T_423) node _T_425 = eq(_T_424, asSInt(UInt<1>(0h0))) node _T_426 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_427 = cvt(_T_426) node _T_428 = and(_T_427, asSInt(UInt<13>(0h1000))) node _T_429 = asSInt(_T_428) node _T_430 = eq(_T_429, asSInt(UInt<1>(0h0))) node _T_431 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<27>(0h4000000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_437 = cvt(_T_436) node _T_438 = and(_T_437, asSInt(UInt<13>(0h1000))) node _T_439 = asSInt(_T_438) node _T_440 = eq(_T_439, asSInt(UInt<1>(0h0))) node _T_441 = or(_T_415, _T_420) node _T_442 = or(_T_441, _T_425) node _T_443 = or(_T_442, _T_430) node _T_444 = or(_T_443, _T_435) node _T_445 = or(_T_444, _T_440) node _T_446 = and(_T_410, _T_445) node _T_447 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_448 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_449 = cvt(_T_448) node _T_450 = and(_T_449, asSInt(UInt<17>(0h10000))) node _T_451 = asSInt(_T_450) node _T_452 = eq(_T_451, asSInt(UInt<1>(0h0))) node _T_453 = and(_T_447, _T_452) node _T_454 = or(UInt<1>(0h0), _T_406) node _T_455 = or(_T_454, _T_446) node _T_456 = or(_T_455, _T_453) node _T_457 = and(_T_396, _T_456) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_457, UInt<1>(0h1), "") : assert_26 node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(is_aligned, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_467 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_467, UInt<1>(0h1), "") : assert_29 node _T_471 = eq(io.in.a.bits.mask, mask) node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_T_471, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_471, UInt<1>(0h1), "") : assert_30 node _T_475 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_475 : node _T_476 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_477 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_478 = and(_T_476, _T_477) node _T_479 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_480 = and(_T_478, _T_479) node _T_481 = or(UInt<1>(0h0), _T_480) node _T_482 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_483 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_484 = and(_T_482, _T_483) node _T_485 = or(UInt<1>(0h0), _T_484) node _T_486 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_487 = cvt(_T_486) node _T_488 = and(_T_487, asSInt(UInt<13>(0h1000))) node _T_489 = asSInt(_T_488) node _T_490 = eq(_T_489, asSInt(UInt<1>(0h0))) node _T_491 = and(_T_485, _T_490) node _T_492 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_493 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_494 = and(_T_492, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_497 = cvt(_T_496) node _T_498 = and(_T_497, asSInt(UInt<14>(0h2000))) node _T_499 = asSInt(_T_498) node _T_500 = eq(_T_499, asSInt(UInt<1>(0h0))) node _T_501 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_502 = cvt(_T_501) node _T_503 = and(_T_502, asSInt(UInt<18>(0h2f000))) node _T_504 = asSInt(_T_503) node _T_505 = eq(_T_504, asSInt(UInt<1>(0h0))) node _T_506 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_507 = cvt(_T_506) node _T_508 = and(_T_507, asSInt(UInt<17>(0h10000))) node _T_509 = asSInt(_T_508) node _T_510 = eq(_T_509, asSInt(UInt<1>(0h0))) node _T_511 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_512 = cvt(_T_511) node _T_513 = and(_T_512, asSInt(UInt<13>(0h1000))) node _T_514 = asSInt(_T_513) node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0))) node _T_516 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_517 = cvt(_T_516) node _T_518 = and(_T_517, asSInt(UInt<27>(0h4000000))) node _T_519 = asSInt(_T_518) node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0))) node _T_521 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_522 = cvt(_T_521) node _T_523 = and(_T_522, asSInt(UInt<13>(0h1000))) node _T_524 = asSInt(_T_523) node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0))) node _T_526 = or(_T_500, _T_505) node _T_527 = or(_T_526, _T_510) node _T_528 = or(_T_527, _T_515) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_525) node _T_531 = and(_T_495, _T_530) node _T_532 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_534 = cvt(_T_533) node _T_535 = and(_T_534, asSInt(UInt<17>(0h10000))) node _T_536 = asSInt(_T_535) node _T_537 = eq(_T_536, asSInt(UInt<1>(0h0))) node _T_538 = and(_T_532, _T_537) node _T_539 = or(UInt<1>(0h0), _T_491) node _T_540 = or(_T_539, _T_531) node _T_541 = or(_T_540, _T_538) node _T_542 = and(_T_481, _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_542, UInt<1>(0h1), "") : assert_31 node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(is_aligned, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_552 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_552, UInt<1>(0h1), "") : assert_34 node _T_556 = not(mask) node _T_557 = and(io.in.a.bits.mask, _T_556) node _T_558 = eq(_T_557, UInt<1>(0h0)) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_558, UInt<1>(0h1), "") : assert_35 node _T_562 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_562 : node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_567 = and(_T_565, _T_566) node _T_568 = or(UInt<1>(0h0), _T_567) node _T_569 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_570 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_571 = and(_T_569, _T_570) node _T_572 = or(UInt<1>(0h0), _T_571) node _T_573 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_574 = cvt(_T_573) node _T_575 = and(_T_574, asSInt(UInt<14>(0h2000))) node _T_576 = asSInt(_T_575) node _T_577 = eq(_T_576, asSInt(UInt<1>(0h0))) node _T_578 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_579 = cvt(_T_578) node _T_580 = and(_T_579, asSInt(UInt<13>(0h1000))) node _T_581 = asSInt(_T_580) node _T_582 = eq(_T_581, asSInt(UInt<1>(0h0))) node _T_583 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_584 = cvt(_T_583) node _T_585 = and(_T_584, asSInt(UInt<18>(0h2f000))) node _T_586 = asSInt(_T_585) node _T_587 = eq(_T_586, asSInt(UInt<1>(0h0))) node _T_588 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_589 = cvt(_T_588) node _T_590 = and(_T_589, asSInt(UInt<17>(0h10000))) node _T_591 = asSInt(_T_590) node _T_592 = eq(_T_591, asSInt(UInt<1>(0h0))) node _T_593 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<13>(0h1000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<27>(0h4000000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_604 = cvt(_T_603) node _T_605 = and(_T_604, asSInt(UInt<13>(0h1000))) node _T_606 = asSInt(_T_605) node _T_607 = eq(_T_606, asSInt(UInt<1>(0h0))) node _T_608 = or(_T_577, _T_582) node _T_609 = or(_T_608, _T_587) node _T_610 = or(_T_609, _T_592) node _T_611 = or(_T_610, _T_597) node _T_612 = or(_T_611, _T_602) node _T_613 = or(_T_612, _T_607) node _T_614 = and(_T_572, _T_613) node _T_615 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_616 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_617 = cvt(_T_616) node _T_618 = and(_T_617, asSInt(UInt<17>(0h10000))) node _T_619 = asSInt(_T_618) node _T_620 = eq(_T_619, asSInt(UInt<1>(0h0))) node _T_621 = and(_T_615, _T_620) node _T_622 = or(UInt<1>(0h0), _T_614) node _T_623 = or(_T_622, _T_621) node _T_624 = and(_T_568, _T_623) node _T_625 = asUInt(reset) node _T_626 = eq(_T_625, UInt<1>(0h0)) when _T_626 : node _T_627 = eq(_T_624, UInt<1>(0h0)) when _T_627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_624, UInt<1>(0h1), "") : assert_36 node _T_628 = asUInt(reset) node _T_629 = eq(_T_628, UInt<1>(0h0)) when _T_629 : node _T_630 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(is_aligned, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_634 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_634, UInt<1>(0h1), "") : assert_39 node _T_638 = eq(io.in.a.bits.mask, mask) node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(_T_638, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_638, UInt<1>(0h1), "") : assert_40 node _T_642 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_642 : node _T_643 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_644 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_645 = and(_T_643, _T_644) node _T_646 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_647 = and(_T_645, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<18>(0h2f000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<13>(0h1000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = or(_T_657, _T_662) node _T_689 = or(_T_688, _T_667) node _T_690 = or(_T_689, _T_672) node _T_691 = or(_T_690, _T_677) node _T_692 = or(_T_691, _T_682) node _T_693 = or(_T_692, _T_687) node _T_694 = and(_T_652, _T_693) node _T_695 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_696 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_697 = cvt(_T_696) node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000))) node _T_699 = asSInt(_T_698) node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0))) node _T_701 = and(_T_695, _T_700) node _T_702 = or(UInt<1>(0h0), _T_694) node _T_703 = or(_T_702, _T_701) node _T_704 = and(_T_648, _T_703) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_704, UInt<1>(0h1), "") : assert_41 node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_711 = asUInt(reset) node _T_712 = eq(_T_711, UInt<1>(0h0)) when _T_712 : node _T_713 = eq(is_aligned, UInt<1>(0h0)) when _T_713 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_714 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_714, UInt<1>(0h1), "") : assert_44 node _T_718 = eq(io.in.a.bits.mask, mask) node _T_719 = asUInt(reset) node _T_720 = eq(_T_719, UInt<1>(0h0)) when _T_720 : node _T_721 = eq(_T_718, UInt<1>(0h0)) when _T_721 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_718, UInt<1>(0h1), "") : assert_45 node _T_722 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_722 : node _T_723 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_724 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_725 = and(_T_723, _T_724) node _T_726 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_727 = and(_T_725, _T_726) node _T_728 = or(UInt<1>(0h0), _T_727) node _T_729 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_730 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(UInt<1>(0h0), _T_731) node _T_733 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_734 = cvt(_T_733) node _T_735 = and(_T_734, asSInt(UInt<13>(0h1000))) node _T_736 = asSInt(_T_735) node _T_737 = eq(_T_736, asSInt(UInt<1>(0h0))) node _T_738 = and(_T_732, _T_737) node _T_739 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_741 = cvt(_T_740) node _T_742 = and(_T_741, asSInt(UInt<14>(0h2000))) node _T_743 = asSInt(_T_742) node _T_744 = eq(_T_743, asSInt(UInt<1>(0h0))) node _T_745 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_746 = cvt(_T_745) node _T_747 = and(_T_746, asSInt(UInt<17>(0h10000))) node _T_748 = asSInt(_T_747) node _T_749 = eq(_T_748, asSInt(UInt<1>(0h0))) node _T_750 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_751 = cvt(_T_750) node _T_752 = and(_T_751, asSInt(UInt<18>(0h2f000))) node _T_753 = asSInt(_T_752) node _T_754 = eq(_T_753, asSInt(UInt<1>(0h0))) node _T_755 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<17>(0h10000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<27>(0h4000000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<13>(0h1000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = or(_T_744, _T_749) node _T_776 = or(_T_775, _T_754) node _T_777 = or(_T_776, _T_759) node _T_778 = or(_T_777, _T_764) node _T_779 = or(_T_778, _T_769) node _T_780 = or(_T_779, _T_774) node _T_781 = and(_T_739, _T_780) node _T_782 = or(UInt<1>(0h0), _T_738) node _T_783 = or(_T_782, _T_781) node _T_784 = and(_T_728, _T_783) node _T_785 = asUInt(reset) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(_T_784, UInt<1>(0h0)) when _T_787 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_784, UInt<1>(0h1), "") : assert_46 node _T_788 = asUInt(reset) node _T_789 = eq(_T_788, UInt<1>(0h0)) when _T_789 : node _T_790 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_790 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_791 = asUInt(reset) node _T_792 = eq(_T_791, UInt<1>(0h0)) when _T_792 : node _T_793 = eq(is_aligned, UInt<1>(0h0)) when _T_793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_794 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(_T_794, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_794, UInt<1>(0h1), "") : assert_49 node _T_798 = eq(io.in.a.bits.mask, mask) node _T_799 = asUInt(reset) node _T_800 = eq(_T_799, UInt<1>(0h0)) when _T_800 : node _T_801 = eq(_T_798, UInt<1>(0h0)) when _T_801 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_798, UInt<1>(0h1), "") : assert_50 node _T_802 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_803 = asUInt(reset) node _T_804 = eq(_T_803, UInt<1>(0h0)) when _T_804 : node _T_805 = eq(_T_802, UInt<1>(0h0)) when _T_805 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_802, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_806 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(_T_806, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_806, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_810 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_810 : node _T_811 = asUInt(reset) node _T_812 = eq(_T_811, UInt<1>(0h0)) when _T_812 : node _T_813 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_813 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_814 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_814, UInt<1>(0h1), "") : assert_54 node _T_818 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_818, UInt<1>(0h1), "") : assert_55 node _T_822 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_822, UInt<1>(0h1), "") : assert_56 node _T_826 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_827 = asUInt(reset) node _T_828 = eq(_T_827, UInt<1>(0h0)) when _T_828 : node _T_829 = eq(_T_826, UInt<1>(0h0)) when _T_829 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_826, UInt<1>(0h1), "") : assert_57 node _T_830 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_830 : node _T_831 = asUInt(reset) node _T_832 = eq(_T_831, UInt<1>(0h0)) when _T_832 : node _T_833 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_833 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_834 = asUInt(reset) node _T_835 = eq(_T_834, UInt<1>(0h0)) when _T_835 : node _T_836 = eq(sink_ok, UInt<1>(0h0)) when _T_836 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_837 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(_T_837, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_837, UInt<1>(0h1), "") : assert_60 node _T_841 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_841, UInt<1>(0h1), "") : assert_61 node _T_845 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_845, UInt<1>(0h1), "") : assert_62 node _T_849 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_849, UInt<1>(0h1), "") : assert_63 node _T_853 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_854 = or(UInt<1>(0h1), _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_854, UInt<1>(0h1), "") : assert_64 node _T_858 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_858 : node _T_859 = asUInt(reset) node _T_860 = eq(_T_859, UInt<1>(0h0)) when _T_860 : node _T_861 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_861 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(sink_ok, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_865, UInt<1>(0h1), "") : assert_67 node _T_869 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_869, UInt<1>(0h1), "") : assert_68 node _T_873 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_873, UInt<1>(0h1), "") : assert_69 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = or(_T_877, io.in.d.bits.corrupt) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_878, UInt<1>(0h1), "") : assert_70 node _T_882 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_883 = or(UInt<1>(0h1), _T_882) node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(_T_883, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_883, UInt<1>(0h1), "") : assert_71 node _T_887 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_887 : node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_891 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_892 = asUInt(reset) node _T_893 = eq(_T_892, UInt<1>(0h0)) when _T_893 : node _T_894 = eq(_T_891, UInt<1>(0h0)) when _T_894 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_891, UInt<1>(0h1), "") : assert_73 node _T_895 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_896 = asUInt(reset) node _T_897 = eq(_T_896, UInt<1>(0h0)) when _T_897 : node _T_898 = eq(_T_895, UInt<1>(0h0)) when _T_898 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_895, UInt<1>(0h1), "") : assert_74 node _T_899 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_900 = or(UInt<1>(0h1), _T_899) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_900, UInt<1>(0h1), "") : assert_75 node _T_904 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_904 : node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_908 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_908, UInt<1>(0h1), "") : assert_77 node _T_912 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_913 = or(_T_912, io.in.d.bits.corrupt) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_913, UInt<1>(0h1), "") : assert_78 node _T_917 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_918 = or(UInt<1>(0h1), _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_918, UInt<1>(0h1), "") : assert_79 node _T_922 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_926 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_926, UInt<1>(0h1), "") : assert_81 node _T_930 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_931 = asUInt(reset) node _T_932 = eq(_T_931, UInt<1>(0h0)) when _T_932 : node _T_933 = eq(_T_930, UInt<1>(0h0)) when _T_933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_930, UInt<1>(0h1), "") : assert_82 node _T_934 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_935 = or(UInt<1>(0h1), _T_934) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_935, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<29>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_939 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_939, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<29>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_943 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_943, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_947 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_947, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_951 = eq(a_first, UInt<1>(0h0)) node _T_952 = and(io.in.a.valid, _T_951) when _T_952 : node _T_953 = eq(io.in.a.bits.opcode, opcode) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_953, UInt<1>(0h1), "") : assert_87 node _T_957 = eq(io.in.a.bits.param, param) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_957, UInt<1>(0h1), "") : assert_88 node _T_961 = eq(io.in.a.bits.size, size) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_961, UInt<1>(0h1), "") : assert_89 node _T_965 = eq(io.in.a.bits.source, source) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_965, UInt<1>(0h1), "") : assert_90 node _T_969 = eq(io.in.a.bits.address, address) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_969, UInt<1>(0h1), "") : assert_91 node _T_973 = and(io.in.a.ready, io.in.a.valid) node _T_974 = and(_T_973, a_first) when _T_974 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_975 = eq(d_first, UInt<1>(0h0)) node _T_976 = and(io.in.d.valid, _T_975) when _T_976 : node _T_977 = eq(io.in.d.bits.opcode, opcode_1) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_977, UInt<1>(0h1), "") : assert_92 node _T_981 = eq(io.in.d.bits.param, param_1) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_981, UInt<1>(0h1), "") : assert_93 node _T_985 = eq(io.in.d.bits.size, size_1) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_985, UInt<1>(0h1), "") : assert_94 node _T_989 = eq(io.in.d.bits.source, source_1) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_989, UInt<1>(0h1), "") : assert_95 node _T_993 = eq(io.in.d.bits.sink, sink) node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(_T_993, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_993, UInt<1>(0h1), "") : assert_96 node _T_997 = eq(io.in.d.bits.denied, denied) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_997, UInt<1>(0h1), "") : assert_97 node _T_1001 = and(io.in.d.ready, io.in.d.valid) node _T_1002 = and(_T_1001, d_first) when _T_1002 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1003 = and(io.in.a.valid, a_first_1) node _T_1004 = and(_T_1003, UInt<1>(0h1)) when _T_1004 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1005 = and(io.in.a.ready, io.in.a.valid) node _T_1006 = and(_T_1005, a_first_1) node _T_1007 = and(_T_1006, UInt<1>(0h1)) when _T_1007 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1008 = dshr(inflight, io.in.a.bits.source) node _T_1009 = bits(_T_1008, 0, 0) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1014 = and(io.in.d.valid, d_first_1) node _T_1015 = and(_T_1014, UInt<1>(0h1)) node _T_1016 = eq(d_release_ack, UInt<1>(0h0)) node _T_1017 = and(_T_1015, _T_1016) when _T_1017 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1018 = and(io.in.d.ready, io.in.d.valid) node _T_1019 = and(_T_1018, d_first_1) node _T_1020 = and(_T_1019, UInt<1>(0h1)) node _T_1021 = eq(d_release_ack, UInt<1>(0h0)) node _T_1022 = and(_T_1020, _T_1021) when _T_1022 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1023 = and(io.in.d.valid, d_first_1) node _T_1024 = and(_T_1023, UInt<1>(0h1)) node _T_1025 = eq(d_release_ack, UInt<1>(0h0)) node _T_1026 = and(_T_1024, _T_1025) when _T_1026 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1027 = dshr(inflight, io.in.d.bits.source) node _T_1028 = bits(_T_1027, 0, 0) node _T_1029 = or(_T_1028, same_cycle_resp) node _T_1030 = asUInt(reset) node _T_1031 = eq(_T_1030, UInt<1>(0h0)) when _T_1031 : node _T_1032 = eq(_T_1029, UInt<1>(0h0)) when _T_1032 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1029, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1033 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1034 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1035 = or(_T_1033, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_100 node _T_1039 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_101 else : node _T_1043 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1044 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1045 = or(_T_1043, _T_1044) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_102 node _T_1049 = eq(io.in.d.bits.size, a_size_lookup) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_103 node _T_1053 = and(io.in.d.valid, d_first_1) node _T_1054 = and(_T_1053, a_first_1) node _T_1055 = and(_T_1054, io.in.a.valid) node _T_1056 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1057 = and(_T_1055, _T_1056) node _T_1058 = eq(d_release_ack, UInt<1>(0h0)) node _T_1059 = and(_T_1057, _T_1058) when _T_1059 : node _T_1060 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1061 = or(_T_1060, io.in.a.ready) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_104 node _T_1065 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1066 = orr(a_set_wo_ready) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) node _T_1068 = or(_T_1065, _T_1067) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_70 node _T_1072 = orr(inflight) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) node _T_1074 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1075 = or(_T_1073, _T_1074) node _T_1076 = lt(watchdog, plusarg_reader.out) node _T_1077 = or(_T_1075, _T_1076) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1081 = and(io.in.a.ready, io.in.a.valid) node _T_1082 = and(io.in.d.ready, io.in.d.valid) node _T_1083 = or(_T_1081, _T_1082) when _T_1083 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1084 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<29>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1085 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1086 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1087 = and(_T_1085, _T_1086) node _T_1088 = and(_T_1084, _T_1087) when _T_1088 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1089 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1090 = and(_T_1089, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1091 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1092 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1093 = and(_T_1091, _T_1092) node _T_1094 = and(_T_1090, _T_1093) when _T_1094 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1095 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1096 = bits(_T_1095, 0, 0) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1101 = and(io.in.d.valid, d_first_2) node _T_1102 = and(_T_1101, UInt<1>(0h1)) node _T_1103 = and(_T_1102, d_release_ack_1) when _T_1103 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1104 = and(io.in.d.ready, io.in.d.valid) node _T_1105 = and(_T_1104, d_first_2) node _T_1106 = and(_T_1105, UInt<1>(0h1)) node _T_1107 = and(_T_1106, d_release_ack_1) when _T_1107 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1108 = and(io.in.d.valid, d_first_2) node _T_1109 = and(_T_1108, UInt<1>(0h1)) node _T_1110 = and(_T_1109, d_release_ack_1) when _T_1110 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1111 = dshr(inflight_1, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp_1) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1117 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(_T_1117, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1117, UInt<1>(0h1), "") : assert_109 else : node _T_1121 = eq(io.in.d.bits.size, c_size_lookup) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_110 node _T_1125 = and(io.in.d.valid, d_first_2) node _T_1126 = and(_T_1125, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1127 = and(_T_1126, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1128 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1129 = and(_T_1127, _T_1128) node _T_1130 = and(_T_1129, d_release_ack_1) node _T_1131 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _T_1133 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1134 = or(_T_1133, _WIRE_23.ready) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_111 node _T_1138 = orr(c_set_wo_ready) when _T_1138 : node _T_1139 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_71 node _T_1143 = orr(inflight_1) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) node _T_1145 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1146 = or(_T_1144, _T_1145) node _T_1147 = lt(watchdog_1, plusarg_reader_1.out) node _T_1148 = or(_T_1146, _T_1147) node _T_1149 = asUInt(reset) node _T_1150 = eq(_T_1149, UInt<1>(0h0)) when _T_1150 : node _T_1151 = eq(_T_1148, UInt<1>(0h0)) when _T_1151 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1148, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1152 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1153 = and(io.in.d.ready, io.in.d.valid) node _T_1154 = or(_T_1152, _T_1153) when _T_1154 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_22( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [28:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire _GEN = io_in_d_valid & d_first_1; // @[Monitor.scala:674:26] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] wire d_clr = _GEN & _GEN_0; // @[Monitor.scala:673:46, :674:{26,71,74}] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire d_clr_1 = io_in_d_valid & d_first_2 & io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46, :784:26, :788:70] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_94 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_94( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_42 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 2, 0) node _source_ok_T = shr(io.in.a.bits.source, 3) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<3>(0h4)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits = bits(_uncommonBits_T, 2, 0) node _T_4 = shr(io.in.a.bits.source, 3) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<3>(0h4)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 2, 0) node _T_42 = shr(io.in.a.bits.source, 3) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<3>(0h4)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_49 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 2, 0) node _T_123 = shr(io.in.a.bits.source, 3) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<3>(0h4)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_130 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 2, 0) node _T_233 = shr(io.in.a.bits.source, 3) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<3>(0h4)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_240 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_314 = shr(io.in.a.bits.source, 3) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<3>(0h4)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_321 = eq(io.in.a.bits.source, UInt<4>(0h8)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0) node _T_428 = shr(io.in.a.bits.source, 3) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<3>(0h4)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_435 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 2, 0) node _T_538 = shr(io.in.a.bits.source, 3) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<3>(0h4)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_545 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 2, 0) node _T_644 = shr(io.in.a.bits.source, 3) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<3>(0h4)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_651 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 2, 0) node _T_752 = shr(io.in.a.bits.source, 3) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<3>(0h4)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_759 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<27>(0h4000000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<13>(0h1000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = or(_T_772, _T_777) node _T_804 = or(_T_803, _T_782) node _T_805 = or(_T_804, _T_787) node _T_806 = or(_T_805, _T_792) node _T_807 = or(_T_806, _T_797) node _T_808 = or(_T_807, _T_802) node _T_809 = and(_T_767, _T_808) node _T_810 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_811 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_812 = cvt(_T_811) node _T_813 = and(_T_812, asSInt(UInt<17>(0h10000))) node _T_814 = asSInt(_T_813) node _T_815 = eq(_T_814, asSInt(UInt<1>(0h0))) node _T_816 = and(_T_810, _T_815) node _T_817 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_818 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_819 = and(_T_817, _T_818) node _T_820 = or(UInt<1>(0h0), _T_819) node _T_821 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_822 = cvt(_T_821) node _T_823 = and(_T_822, asSInt(UInt<17>(0h10000))) node _T_824 = asSInt(_T_823) node _T_825 = eq(_T_824, asSInt(UInt<1>(0h0))) node _T_826 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_827 = cvt(_T_826) node _T_828 = and(_T_827, asSInt(UInt<29>(0h10000000))) node _T_829 = asSInt(_T_828) node _T_830 = eq(_T_829, asSInt(UInt<1>(0h0))) node _T_831 = or(_T_825, _T_830) node _T_832 = and(_T_820, _T_831) node _T_833 = or(UInt<1>(0h0), _T_809) node _T_834 = or(_T_833, _T_816) node _T_835 = or(_T_834, _T_832) node _T_836 = and(_T_763, _T_835) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_836, UInt<1>(0h1), "") : assert_36 node _T_840 = asUInt(reset) node _T_841 = eq(_T_840, UInt<1>(0h0)) when _T_841 : node _T_842 = eq(source_ok, UInt<1>(0h0)) when _T_842 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(is_aligned, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_846 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_847 = asUInt(reset) node _T_848 = eq(_T_847, UInt<1>(0h0)) when _T_848 : node _T_849 = eq(_T_846, UInt<1>(0h0)) when _T_849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_846, UInt<1>(0h1), "") : assert_39 node _T_850 = eq(io.in.a.bits.mask, mask) node _T_851 = asUInt(reset) node _T_852 = eq(_T_851, UInt<1>(0h0)) when _T_852 : node _T_853 = eq(_T_850, UInt<1>(0h0)) when _T_853 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_850, UInt<1>(0h1), "") : assert_40 node _T_854 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_854 : node _T_855 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_856 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_857 = and(_T_855, _T_856) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_858 = shr(io.in.a.bits.source, 3) node _T_859 = eq(_T_858, UInt<1>(0h0)) node _T_860 = leq(UInt<1>(0h0), uncommonBits_9) node _T_861 = and(_T_859, _T_860) node _T_862 = leq(uncommonBits_9, UInt<3>(0h4)) node _T_863 = and(_T_861, _T_862) node _T_864 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_865 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_866 = or(_T_863, _T_864) node _T_867 = or(_T_866, _T_865) node _T_868 = and(_T_857, _T_867) node _T_869 = or(UInt<1>(0h0), _T_868) node _T_870 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_871 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_872 = and(_T_870, _T_871) node _T_873 = or(UInt<1>(0h0), _T_872) node _T_874 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<14>(0h2000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<13>(0h1000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<18>(0h2f000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<17>(0h10000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = or(_T_878, _T_883) node _T_910 = or(_T_909, _T_888) node _T_911 = or(_T_910, _T_893) node _T_912 = or(_T_911, _T_898) node _T_913 = or(_T_912, _T_903) node _T_914 = or(_T_913, _T_908) node _T_915 = and(_T_873, _T_914) node _T_916 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_917 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<17>(0h10000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = and(_T_916, _T_921) node _T_923 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_924 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_925 = and(_T_923, _T_924) node _T_926 = or(UInt<1>(0h0), _T_925) node _T_927 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_928 = cvt(_T_927) node _T_929 = and(_T_928, asSInt(UInt<17>(0h10000))) node _T_930 = asSInt(_T_929) node _T_931 = eq(_T_930, asSInt(UInt<1>(0h0))) node _T_932 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_933 = cvt(_T_932) node _T_934 = and(_T_933, asSInt(UInt<29>(0h10000000))) node _T_935 = asSInt(_T_934) node _T_936 = eq(_T_935, asSInt(UInt<1>(0h0))) node _T_937 = or(_T_931, _T_936) node _T_938 = and(_T_926, _T_937) node _T_939 = or(UInt<1>(0h0), _T_915) node _T_940 = or(_T_939, _T_922) node _T_941 = or(_T_940, _T_938) node _T_942 = and(_T_869, _T_941) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_942, UInt<1>(0h1), "") : assert_41 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(source_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(is_aligned, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_952 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_953 = asUInt(reset) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(_T_952, UInt<1>(0h0)) when _T_955 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_952, UInt<1>(0h1), "") : assert_44 node _T_956 = eq(io.in.a.bits.mask, mask) node _T_957 = asUInt(reset) node _T_958 = eq(_T_957, UInt<1>(0h0)) when _T_958 : node _T_959 = eq(_T_956, UInt<1>(0h0)) when _T_959 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_956, UInt<1>(0h1), "") : assert_45 node _T_960 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_960 : node _T_961 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_962 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_963 = and(_T_961, _T_962) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0) node _T_964 = shr(io.in.a.bits.source, 3) node _T_965 = eq(_T_964, UInt<1>(0h0)) node _T_966 = leq(UInt<1>(0h0), uncommonBits_10) node _T_967 = and(_T_965, _T_966) node _T_968 = leq(uncommonBits_10, UInt<3>(0h4)) node _T_969 = and(_T_967, _T_968) node _T_970 = eq(io.in.a.bits.source, UInt<3>(0h5)) node _T_971 = eq(io.in.a.bits.source, UInt<4>(0h8)) node _T_972 = or(_T_969, _T_970) node _T_973 = or(_T_972, _T_971) node _T_974 = and(_T_963, _T_973) node _T_975 = or(UInt<1>(0h0), _T_974) node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_977 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_978 = and(_T_976, _T_977) node _T_979 = or(UInt<1>(0h0), _T_978) node _T_980 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_981 = cvt(_T_980) node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000))) node _T_983 = asSInt(_T_982) node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0))) node _T_985 = and(_T_979, _T_984) node _T_986 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_987 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<14>(0h2000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_991, _T_996) node _T_1023 = or(_T_1022, _T_1001) node _T_1024 = or(_T_1023, _T_1006) node _T_1025 = or(_T_1024, _T_1011) node _T_1026 = or(_T_1025, _T_1016) node _T_1027 = or(_T_1026, _T_1021) node _T_1028 = and(_T_986, _T_1027) node _T_1029 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1030 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1031 = and(_T_1029, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_1031) node _T_1033 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1034 = cvt(_T_1033) node _T_1035 = and(_T_1034, asSInt(UInt<17>(0h10000))) node _T_1036 = asSInt(_T_1035) node _T_1037 = eq(_T_1036, asSInt(UInt<1>(0h0))) node _T_1038 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1039 = cvt(_T_1038) node _T_1040 = and(_T_1039, asSInt(UInt<29>(0h10000000))) node _T_1041 = asSInt(_T_1040) node _T_1042 = eq(_T_1041, asSInt(UInt<1>(0h0))) node _T_1043 = or(_T_1037, _T_1042) node _T_1044 = and(_T_1032, _T_1043) node _T_1045 = or(UInt<1>(0h0), _T_985) node _T_1046 = or(_T_1045, _T_1028) node _T_1047 = or(_T_1046, _T_1044) node _T_1048 = and(_T_975, _T_1047) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_46 node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(source_ok, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(is_aligned, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1058 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_49 node _T_1062 = eq(io.in.a.bits.mask, mask) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_50 node _T_1066 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1070 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 2, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 3) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<3>(0h4)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<3>(0h5)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1074 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1074 : node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(source_ok_1, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1078 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_54 node _T_1082 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_55 node _T_1086 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_56 node _T_1090 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_57 node _T_1094 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1094 : node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(source_ok_1, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(sink_ok, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1101 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_60 node _T_1105 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_61 node _T_1109 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_62 node _T_1113 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_63 node _T_1117 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1118 = or(UInt<1>(0h1), _T_1117) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_64 node _T_1122 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(source_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(sink_ok, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1129 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_67 node _T_1133 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_68 node _T_1137 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_69 node _T_1141 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1142 = or(_T_1141, io.in.d.bits.corrupt) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_70 node _T_1146 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1147 = or(UInt<1>(0h1), _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_71 node _T_1151 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1151 : node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(source_ok_1, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1155 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_73 node _T_1159 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_74 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(UInt<1>(0h1), _T_1163) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_75 node _T_1168 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1168 : node _T_1169 = asUInt(reset) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(source_ok_1, UInt<1>(0h0)) when _T_1171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1172 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_77 node _T_1176 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1177 = or(_T_1176, io.in.d.bits.corrupt) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_78 node _T_1181 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1182 = or(UInt<1>(0h1), _T_1181) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_79 node _T_1186 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1186 : node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(source_ok_1, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1190 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_81 node _T_1194 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_82 node _T_1198 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1199 = or(UInt<1>(0h1), _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1203 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0) node _T_1207 = shr(io.in.b.bits.source, 3) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_11, UInt<3>(0h4)) node _T_1212 = and(_T_1210, _T_1211) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) node _T_1214 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1215 = cvt(_T_1214) node _T_1216 = and(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = asSInt(_T_1216) node _T_1218 = eq(_T_1217, asSInt(UInt<1>(0h0))) node _T_1219 = or(_T_1213, _T_1218) node _T_1220 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) node _T_1222 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1223 = cvt(_T_1222) node _T_1224 = and(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = asSInt(_T_1224) node _T_1226 = eq(_T_1225, asSInt(UInt<1>(0h0))) node _T_1227 = or(_T_1221, _T_1226) node _T_1228 = eq(io.in.b.bits.source, UInt<4>(0h8)) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) node _T_1230 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1231 = cvt(_T_1230) node _T_1232 = and(_T_1231, asSInt(UInt<1>(0h0))) node _T_1233 = asSInt(_T_1232) node _T_1234 = eq(_T_1233, asSInt(UInt<1>(0h0))) node _T_1235 = or(_T_1229, _T_1234) node _T_1236 = and(_T_1219, _T_1227) node _T_1237 = and(_T_1236, _T_1235) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 3, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size_1 = bits(mask_sizeOH_1, 3, 3) node mask_sub_sub_sub_bit_1 = bits(io.in.b.bits.address, 3, 3) node mask_sub_sub_sub_nbit_1 = eq(mask_sub_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit_1) node _mask_sub_sub_sub_acc_T_2 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_0_2_1) node mask_sub_sub_sub_0_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_2) node mask_sub_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_sub_bit_1) node _mask_sub_sub_sub_acc_T_3 = and(mask_sub_sub_sub_size_1, mask_sub_sub_sub_1_2_1) node mask_sub_sub_sub_1_1_1 = or(mask_sub_sub_sub_sub_0_1_1, _mask_sub_sub_sub_acc_T_3) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_4 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_4) node mask_sub_sub_1_2_1 = and(mask_sub_sub_sub_0_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_5 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_5) node mask_sub_sub_2_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_6 = and(mask_sub_sub_size_1, mask_sub_sub_2_2_1) node mask_sub_sub_2_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_6) node mask_sub_sub_3_2_1 = and(mask_sub_sub_sub_1_2_1, mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_7 = and(mask_sub_sub_size_1, mask_sub_sub_3_2_1) node mask_sub_sub_3_1_1 = or(mask_sub_sub_sub_1_1_1, _mask_sub_sub_acc_T_7) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_8 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_8) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_9 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_9) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_10 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_10) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_11 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_11) node mask_sub_4_2_1 = and(mask_sub_sub_2_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_12 = and(mask_sub_size_1, mask_sub_4_2_1) node mask_sub_4_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_12) node mask_sub_5_2_1 = and(mask_sub_sub_2_2_1, mask_sub_bit_1) node _mask_sub_acc_T_13 = and(mask_sub_size_1, mask_sub_5_2_1) node mask_sub_5_1_1 = or(mask_sub_sub_2_1_1, _mask_sub_acc_T_13) node mask_sub_6_2_1 = and(mask_sub_sub_3_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_14 = and(mask_sub_size_1, mask_sub_6_2_1) node mask_sub_6_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_14) node mask_sub_7_2_1 = and(mask_sub_sub_3_2_1, mask_sub_bit_1) node _mask_sub_acc_T_15 = and(mask_sub_size_1, mask_sub_7_2_1) node mask_sub_7_1_1 = or(mask_sub_sub_3_1_1, _mask_sub_acc_T_15) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_16 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_16 = and(mask_size_1, mask_eq_16) node mask_acc_16 = or(mask_sub_0_1_1, _mask_acc_T_16) node mask_eq_17 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_17 = and(mask_size_1, mask_eq_17) node mask_acc_17 = or(mask_sub_0_1_1, _mask_acc_T_17) node mask_eq_18 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_18 = and(mask_size_1, mask_eq_18) node mask_acc_18 = or(mask_sub_1_1_1, _mask_acc_T_18) node mask_eq_19 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_19 = and(mask_size_1, mask_eq_19) node mask_acc_19 = or(mask_sub_1_1_1, _mask_acc_T_19) node mask_eq_20 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_20 = and(mask_size_1, mask_eq_20) node mask_acc_20 = or(mask_sub_2_1_1, _mask_acc_T_20) node mask_eq_21 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_21 = and(mask_size_1, mask_eq_21) node mask_acc_21 = or(mask_sub_2_1_1, _mask_acc_T_21) node mask_eq_22 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_22 = and(mask_size_1, mask_eq_22) node mask_acc_22 = or(mask_sub_3_1_1, _mask_acc_T_22) node mask_eq_23 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_23 = and(mask_size_1, mask_eq_23) node mask_acc_23 = or(mask_sub_3_1_1, _mask_acc_T_23) node mask_eq_24 = and(mask_sub_4_2_1, mask_nbit_1) node _mask_acc_T_24 = and(mask_size_1, mask_eq_24) node mask_acc_24 = or(mask_sub_4_1_1, _mask_acc_T_24) node mask_eq_25 = and(mask_sub_4_2_1, mask_bit_1) node _mask_acc_T_25 = and(mask_size_1, mask_eq_25) node mask_acc_25 = or(mask_sub_4_1_1, _mask_acc_T_25) node mask_eq_26 = and(mask_sub_5_2_1, mask_nbit_1) node _mask_acc_T_26 = and(mask_size_1, mask_eq_26) node mask_acc_26 = or(mask_sub_5_1_1, _mask_acc_T_26) node mask_eq_27 = and(mask_sub_5_2_1, mask_bit_1) node _mask_acc_T_27 = and(mask_size_1, mask_eq_27) node mask_acc_27 = or(mask_sub_5_1_1, _mask_acc_T_27) node mask_eq_28 = and(mask_sub_6_2_1, mask_nbit_1) node _mask_acc_T_28 = and(mask_size_1, mask_eq_28) node mask_acc_28 = or(mask_sub_6_1_1, _mask_acc_T_28) node mask_eq_29 = and(mask_sub_6_2_1, mask_bit_1) node _mask_acc_T_29 = and(mask_size_1, mask_eq_29) node mask_acc_29 = or(mask_sub_6_1_1, _mask_acc_T_29) node mask_eq_30 = and(mask_sub_7_2_1, mask_nbit_1) node _mask_acc_T_30 = and(mask_size_1, mask_eq_30) node mask_acc_30 = or(mask_sub_7_1_1, _mask_acc_T_30) node mask_eq_31 = and(mask_sub_7_2_1, mask_bit_1) node _mask_acc_T_31 = and(mask_size_1, mask_eq_31) node mask_acc_31 = or(mask_sub_7_1_1, _mask_acc_T_31) node mask_lo_lo_lo_1 = cat(mask_acc_17, mask_acc_16) node mask_lo_lo_hi_1 = cat(mask_acc_19, mask_acc_18) node mask_lo_lo_1 = cat(mask_lo_lo_hi_1, mask_lo_lo_lo_1) node mask_lo_hi_lo_1 = cat(mask_acc_21, mask_acc_20) node mask_lo_hi_hi_1 = cat(mask_acc_23, mask_acc_22) node mask_lo_hi_1 = cat(mask_lo_hi_hi_1, mask_lo_hi_lo_1) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_lo_1 = cat(mask_acc_25, mask_acc_24) node mask_hi_lo_hi_1 = cat(mask_acc_27, mask_acc_26) node mask_hi_lo_1 = cat(mask_hi_lo_hi_1, mask_hi_lo_lo_1) node mask_hi_hi_lo_1 = cat(mask_acc_29, mask_acc_28) node mask_hi_hi_hi_1 = cat(mask_acc_31, mask_acc_30) node mask_hi_hi_1 = cat(mask_hi_hi_hi_1, mask_hi_hi_lo_1) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<3>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 2, 0) node _legal_source_T = shr(io.in.b.bits.source, 3) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<3>(0h4)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<3>(0h5), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<4>(0h8), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<4> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1241 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1241 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<3>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 2, 0) node _T_1242 = shr(io.in.b.bits.source, 3) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) node _T_1244 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1245 = and(_T_1243, _T_1244) node _T_1246 = leq(uncommonBits_12, UInt<3>(0h4)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = eq(io.in.b.bits.source, UInt<3>(0h5)) node _T_1249 = eq(io.in.b.bits.source, UInt<4>(0h8)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1247 connect _WIRE_4[1], _T_1248 connect _WIRE_4[2], _T_1249 node _T_1250 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1251 = mux(_WIRE_4[0], _T_1250, UInt<1>(0h0)) node _T_1252 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1253 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1254 = or(_T_1251, _T_1252) node _T_1255 = or(_T_1254, _T_1253) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1255 node _T_1256 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1257 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1258 = and(_T_1256, _T_1257) node _T_1259 = or(UInt<1>(0h0), _T_1258) node _T_1260 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<14>(0h2000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<13>(0h1000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<18>(0h2f000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<17>(0h10000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<27>(0h4000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1301 = cvt(_T_1300) node _T_1302 = and(_T_1301, asSInt(UInt<13>(0h1000))) node _T_1303 = asSInt(_T_1302) node _T_1304 = eq(_T_1303, asSInt(UInt<1>(0h0))) node _T_1305 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1306 = cvt(_T_1305) node _T_1307 = and(_T_1306, asSInt(UInt<29>(0h10000000))) node _T_1308 = asSInt(_T_1307) node _T_1309 = eq(_T_1308, asSInt(UInt<1>(0h0))) node _T_1310 = or(_T_1264, _T_1269) node _T_1311 = or(_T_1310, _T_1274) node _T_1312 = or(_T_1311, _T_1279) node _T_1313 = or(_T_1312, _T_1284) node _T_1314 = or(_T_1313, _T_1289) node _T_1315 = or(_T_1314, _T_1294) node _T_1316 = or(_T_1315, _T_1299) node _T_1317 = or(_T_1316, _T_1304) node _T_1318 = or(_T_1317, _T_1309) node _T_1319 = and(_T_1259, _T_1318) node _T_1320 = or(UInt<1>(0h0), _T_1319) node _T_1321 = and(_WIRE_5, _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_86 node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(address_ok, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1328 = asUInt(reset) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) when _T_1329 : node _T_1330 = eq(legal_source, UInt<1>(0h0)) when _T_1330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1331 = asUInt(reset) node _T_1332 = eq(_T_1331, UInt<1>(0h0)) when _T_1332 : node _T_1333 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1334 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_90 node _T_1338 = eq(io.in.b.bits.mask, mask_1) node _T_1339 = asUInt(reset) node _T_1340 = eq(_T_1339, UInt<1>(0h0)) when _T_1340 : node _T_1341 = eq(_T_1338, UInt<1>(0h0)) when _T_1341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1338, UInt<1>(0h1), "") : assert_91 node _T_1342 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1343 = asUInt(reset) node _T_1344 = eq(_T_1343, UInt<1>(0h0)) when _T_1344 : node _T_1345 = eq(_T_1342, UInt<1>(0h0)) when _T_1345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1342, UInt<1>(0h1), "") : assert_92 node _T_1346 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1346 : node _T_1347 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1348 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1349 = and(_T_1347, _T_1348) node _T_1350 = or(UInt<1>(0h0), _T_1349) node _T_1351 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<14>(0h2000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<13>(0h1000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<18>(0h2f000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<13>(0h1000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<17>(0h10000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<27>(0h4000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<13>(0h1000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<29>(0h10000000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = or(_T_1355, _T_1360) node _T_1402 = or(_T_1401, _T_1365) node _T_1403 = or(_T_1402, _T_1370) node _T_1404 = or(_T_1403, _T_1375) node _T_1405 = or(_T_1404, _T_1380) node _T_1406 = or(_T_1405, _T_1385) node _T_1407 = or(_T_1406, _T_1390) node _T_1408 = or(_T_1407, _T_1395) node _T_1409 = or(_T_1408, _T_1400) node _T_1410 = and(_T_1350, _T_1409) node _T_1411 = or(UInt<1>(0h0), _T_1410) node _T_1412 = and(UInt<1>(0h0), _T_1411) node _T_1413 = asUInt(reset) node _T_1414 = eq(_T_1413, UInt<1>(0h0)) when _T_1414 : node _T_1415 = eq(_T_1412, UInt<1>(0h0)) when _T_1415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1412, UInt<1>(0h1), "") : assert_93 node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(address_ok, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(legal_source, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1425 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_97 node _T_1429 = eq(io.in.b.bits.mask, mask_1) node _T_1430 = asUInt(reset) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) when _T_1431 : node _T_1432 = eq(_T_1429, UInt<1>(0h0)) when _T_1432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1429, UInt<1>(0h1), "") : assert_98 node _T_1433 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(_T_1433, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1433, UInt<1>(0h1), "") : assert_99 node _T_1437 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1437 : node _T_1438 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1439 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1440 = and(_T_1438, _T_1439) node _T_1441 = or(UInt<1>(0h0), _T_1440) node _T_1442 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<14>(0h2000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<13>(0h1000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<18>(0h2f000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<13>(0h1000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<17>(0h10000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<27>(0h4000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1483 = cvt(_T_1482) node _T_1484 = and(_T_1483, asSInt(UInt<13>(0h1000))) node _T_1485 = asSInt(_T_1484) node _T_1486 = eq(_T_1485, asSInt(UInt<1>(0h0))) node _T_1487 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1488 = cvt(_T_1487) node _T_1489 = and(_T_1488, asSInt(UInt<29>(0h10000000))) node _T_1490 = asSInt(_T_1489) node _T_1491 = eq(_T_1490, asSInt(UInt<1>(0h0))) node _T_1492 = or(_T_1446, _T_1451) node _T_1493 = or(_T_1492, _T_1456) node _T_1494 = or(_T_1493, _T_1461) node _T_1495 = or(_T_1494, _T_1466) node _T_1496 = or(_T_1495, _T_1471) node _T_1497 = or(_T_1496, _T_1476) node _T_1498 = or(_T_1497, _T_1481) node _T_1499 = or(_T_1498, _T_1486) node _T_1500 = or(_T_1499, _T_1491) node _T_1501 = and(_T_1441, _T_1500) node _T_1502 = or(UInt<1>(0h0), _T_1501) node _T_1503 = and(UInt<1>(0h0), _T_1502) node _T_1504 = asUInt(reset) node _T_1505 = eq(_T_1504, UInt<1>(0h0)) when _T_1505 : node _T_1506 = eq(_T_1503, UInt<1>(0h0)) when _T_1506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1503, UInt<1>(0h1), "") : assert_100 node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(address_ok, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(legal_source, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1513 = asUInt(reset) node _T_1514 = eq(_T_1513, UInt<1>(0h0)) when _T_1514 : node _T_1515 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1516 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1517 = asUInt(reset) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(_T_1516, UInt<1>(0h0)) when _T_1519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1516, UInt<1>(0h1), "") : assert_104 node _T_1520 = eq(io.in.b.bits.mask, mask_1) node _T_1521 = asUInt(reset) node _T_1522 = eq(_T_1521, UInt<1>(0h0)) when _T_1522 : node _T_1523 = eq(_T_1520, UInt<1>(0h0)) when _T_1523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1520, UInt<1>(0h1), "") : assert_105 node _T_1524 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1524 : node _T_1525 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1526 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1527 = and(_T_1525, _T_1526) node _T_1528 = or(UInt<1>(0h0), _T_1527) node _T_1529 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<14>(0h2000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<13>(0h1000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<18>(0h2f000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<13>(0h1000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<17>(0h10000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<27>(0h4000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1570 = cvt(_T_1569) node _T_1571 = and(_T_1570, asSInt(UInt<13>(0h1000))) node _T_1572 = asSInt(_T_1571) node _T_1573 = eq(_T_1572, asSInt(UInt<1>(0h0))) node _T_1574 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1575 = cvt(_T_1574) node _T_1576 = and(_T_1575, asSInt(UInt<29>(0h10000000))) node _T_1577 = asSInt(_T_1576) node _T_1578 = eq(_T_1577, asSInt(UInt<1>(0h0))) node _T_1579 = or(_T_1533, _T_1538) node _T_1580 = or(_T_1579, _T_1543) node _T_1581 = or(_T_1580, _T_1548) node _T_1582 = or(_T_1581, _T_1553) node _T_1583 = or(_T_1582, _T_1558) node _T_1584 = or(_T_1583, _T_1563) node _T_1585 = or(_T_1584, _T_1568) node _T_1586 = or(_T_1585, _T_1573) node _T_1587 = or(_T_1586, _T_1578) node _T_1588 = and(_T_1528, _T_1587) node _T_1589 = or(UInt<1>(0h0), _T_1588) node _T_1590 = and(UInt<1>(0h0), _T_1589) node _T_1591 = asUInt(reset) node _T_1592 = eq(_T_1591, UInt<1>(0h0)) when _T_1592 : node _T_1593 = eq(_T_1590, UInt<1>(0h0)) when _T_1593 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1590, UInt<1>(0h1), "") : assert_106 node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(address_ok, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(legal_source, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1603 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_110 node _T_1607 = not(mask_1) node _T_1608 = and(io.in.b.bits.mask, _T_1607) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(_T_1609, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1609, UInt<1>(0h1), "") : assert_111 node _T_1613 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1613 : node _T_1614 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1615 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1616 = and(_T_1614, _T_1615) node _T_1617 = or(UInt<1>(0h0), _T_1616) node _T_1618 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<14>(0h2000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<13>(0h1000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<18>(0h2f000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<13>(0h1000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<17>(0h10000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<27>(0h4000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1659 = cvt(_T_1658) node _T_1660 = and(_T_1659, asSInt(UInt<13>(0h1000))) node _T_1661 = asSInt(_T_1660) node _T_1662 = eq(_T_1661, asSInt(UInt<1>(0h0))) node _T_1663 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1664 = cvt(_T_1663) node _T_1665 = and(_T_1664, asSInt(UInt<29>(0h10000000))) node _T_1666 = asSInt(_T_1665) node _T_1667 = eq(_T_1666, asSInt(UInt<1>(0h0))) node _T_1668 = or(_T_1622, _T_1627) node _T_1669 = or(_T_1668, _T_1632) node _T_1670 = or(_T_1669, _T_1637) node _T_1671 = or(_T_1670, _T_1642) node _T_1672 = or(_T_1671, _T_1647) node _T_1673 = or(_T_1672, _T_1652) node _T_1674 = or(_T_1673, _T_1657) node _T_1675 = or(_T_1674, _T_1662) node _T_1676 = or(_T_1675, _T_1667) node _T_1677 = and(_T_1617, _T_1676) node _T_1678 = or(UInt<1>(0h0), _T_1677) node _T_1679 = and(UInt<1>(0h0), _T_1678) node _T_1680 = asUInt(reset) node _T_1681 = eq(_T_1680, UInt<1>(0h0)) when _T_1681 : node _T_1682 = eq(_T_1679, UInt<1>(0h0)) when _T_1682 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1679, UInt<1>(0h1), "") : assert_112 node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(address_ok, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(legal_source, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1689 = asUInt(reset) node _T_1690 = eq(_T_1689, UInt<1>(0h0)) when _T_1690 : node _T_1691 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1692 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1693 = asUInt(reset) node _T_1694 = eq(_T_1693, UInt<1>(0h0)) when _T_1694 : node _T_1695 = eq(_T_1692, UInt<1>(0h0)) when _T_1695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1692, UInt<1>(0h1), "") : assert_116 node _T_1696 = eq(io.in.b.bits.mask, mask_1) node _T_1697 = asUInt(reset) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) when _T_1698 : node _T_1699 = eq(_T_1696, UInt<1>(0h0)) when _T_1699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1696, UInt<1>(0h1), "") : assert_117 node _T_1700 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1700 : node _T_1701 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1702 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = or(UInt<1>(0h0), _T_1703) node _T_1705 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<14>(0h2000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<13>(0h1000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<18>(0h2f000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<13>(0h1000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<17>(0h10000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<27>(0h4000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1746 = cvt(_T_1745) node _T_1747 = and(_T_1746, asSInt(UInt<13>(0h1000))) node _T_1748 = asSInt(_T_1747) node _T_1749 = eq(_T_1748, asSInt(UInt<1>(0h0))) node _T_1750 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1751 = cvt(_T_1750) node _T_1752 = and(_T_1751, asSInt(UInt<29>(0h10000000))) node _T_1753 = asSInt(_T_1752) node _T_1754 = eq(_T_1753, asSInt(UInt<1>(0h0))) node _T_1755 = or(_T_1709, _T_1714) node _T_1756 = or(_T_1755, _T_1719) node _T_1757 = or(_T_1756, _T_1724) node _T_1758 = or(_T_1757, _T_1729) node _T_1759 = or(_T_1758, _T_1734) node _T_1760 = or(_T_1759, _T_1739) node _T_1761 = or(_T_1760, _T_1744) node _T_1762 = or(_T_1761, _T_1749) node _T_1763 = or(_T_1762, _T_1754) node _T_1764 = and(_T_1704, _T_1763) node _T_1765 = or(UInt<1>(0h0), _T_1764) node _T_1766 = and(UInt<1>(0h0), _T_1765) node _T_1767 = asUInt(reset) node _T_1768 = eq(_T_1767, UInt<1>(0h0)) when _T_1768 : node _T_1769 = eq(_T_1766, UInt<1>(0h0)) when _T_1769 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1766, UInt<1>(0h1), "") : assert_118 node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(address_ok, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1773 = asUInt(reset) node _T_1774 = eq(_T_1773, UInt<1>(0h0)) when _T_1774 : node _T_1775 = eq(legal_source, UInt<1>(0h0)) when _T_1775 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1776 = asUInt(reset) node _T_1777 = eq(_T_1776, UInt<1>(0h0)) when _T_1777 : node _T_1778 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1779 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1780 = asUInt(reset) node _T_1781 = eq(_T_1780, UInt<1>(0h0)) when _T_1781 : node _T_1782 = eq(_T_1779, UInt<1>(0h0)) when _T_1782 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1779, UInt<1>(0h1), "") : assert_122 node _T_1783 = eq(io.in.b.bits.mask, mask_1) node _T_1784 = asUInt(reset) node _T_1785 = eq(_T_1784, UInt<1>(0h0)) when _T_1785 : node _T_1786 = eq(_T_1783, UInt<1>(0h0)) when _T_1786 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1783, UInt<1>(0h1), "") : assert_123 node _T_1787 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1787 : node _T_1788 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1789 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1790 = and(_T_1788, _T_1789) node _T_1791 = or(UInt<1>(0h0), _T_1790) node _T_1792 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<14>(0h2000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<13>(0h1000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<18>(0h2f000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<13>(0h1000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<17>(0h10000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<27>(0h4000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1833 = cvt(_T_1832) node _T_1834 = and(_T_1833, asSInt(UInt<13>(0h1000))) node _T_1835 = asSInt(_T_1834) node _T_1836 = eq(_T_1835, asSInt(UInt<1>(0h0))) node _T_1837 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1838 = cvt(_T_1837) node _T_1839 = and(_T_1838, asSInt(UInt<29>(0h10000000))) node _T_1840 = asSInt(_T_1839) node _T_1841 = eq(_T_1840, asSInt(UInt<1>(0h0))) node _T_1842 = or(_T_1796, _T_1801) node _T_1843 = or(_T_1842, _T_1806) node _T_1844 = or(_T_1843, _T_1811) node _T_1845 = or(_T_1844, _T_1816) node _T_1846 = or(_T_1845, _T_1821) node _T_1847 = or(_T_1846, _T_1826) node _T_1848 = or(_T_1847, _T_1831) node _T_1849 = or(_T_1848, _T_1836) node _T_1850 = or(_T_1849, _T_1841) node _T_1851 = and(_T_1791, _T_1850) node _T_1852 = or(UInt<1>(0h0), _T_1851) node _T_1853 = and(UInt<1>(0h0), _T_1852) node _T_1854 = asUInt(reset) node _T_1855 = eq(_T_1854, UInt<1>(0h0)) when _T_1855 : node _T_1856 = eq(_T_1853, UInt<1>(0h0)) when _T_1856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1853, UInt<1>(0h1), "") : assert_124 node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(address_ok, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1860 = asUInt(reset) node _T_1861 = eq(_T_1860, UInt<1>(0h0)) when _T_1861 : node _T_1862 = eq(legal_source, UInt<1>(0h0)) when _T_1862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1863 = asUInt(reset) node _T_1864 = eq(_T_1863, UInt<1>(0h0)) when _T_1864 : node _T_1865 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1865 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1866 = eq(io.in.b.bits.mask, mask_1) node _T_1867 = asUInt(reset) node _T_1868 = eq(_T_1867, UInt<1>(0h0)) when _T_1868 : node _T_1869 = eq(_T_1866, UInt<1>(0h0)) when _T_1869 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1866, UInt<1>(0h1), "") : assert_128 node _T_1870 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1871 = asUInt(reset) node _T_1872 = eq(_T_1871, UInt<1>(0h0)) when _T_1872 : node _T_1873 = eq(_T_1870, UInt<1>(0h0)) when _T_1873 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1870, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1874 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1875 = asUInt(reset) node _T_1876 = eq(_T_1875, UInt<1>(0h0)) when _T_1876 : node _T_1877 = eq(_T_1874, UInt<1>(0h0)) when _T_1877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1874, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 2, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 3) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<3>(0h4)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 2, 0) node _T_1878 = shr(io.in.c.bits.source, 3) node _T_1879 = eq(_T_1878, UInt<1>(0h0)) node _T_1880 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1881 = and(_T_1879, _T_1880) node _T_1882 = leq(uncommonBits_13, UInt<3>(0h4)) node _T_1883 = and(_T_1881, _T_1882) node _T_1884 = eq(_T_1883, UInt<1>(0h0)) node _T_1885 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1886 = cvt(_T_1885) node _T_1887 = and(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = asSInt(_T_1887) node _T_1889 = eq(_T_1888, asSInt(UInt<1>(0h0))) node _T_1890 = or(_T_1884, _T_1889) node _T_1891 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1892 = eq(_T_1891, UInt<1>(0h0)) node _T_1893 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1894 = cvt(_T_1893) node _T_1895 = and(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = asSInt(_T_1895) node _T_1897 = eq(_T_1896, asSInt(UInt<1>(0h0))) node _T_1898 = or(_T_1892, _T_1897) node _T_1899 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) node _T_1901 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1902 = cvt(_T_1901) node _T_1903 = and(_T_1902, asSInt(UInt<1>(0h0))) node _T_1904 = asSInt(_T_1903) node _T_1905 = eq(_T_1904, asSInt(UInt<1>(0h0))) node _T_1906 = or(_T_1900, _T_1905) node _T_1907 = and(_T_1890, _T_1898) node _T_1908 = and(_T_1907, _T_1906) node _T_1909 = asUInt(reset) node _T_1910 = eq(_T_1909, UInt<1>(0h0)) when _T_1910 : node _T_1911 = eq(_T_1908, UInt<1>(0h0)) when _T_1911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1908, UInt<1>(0h1), "") : assert_131 node _T_1912 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1912 : node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(address_ok_1, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1916 = asUInt(reset) node _T_1917 = eq(_T_1916, UInt<1>(0h0)) when _T_1917 : node _T_1918 = eq(source_ok_2, UInt<1>(0h0)) when _T_1918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1919 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1920 = asUInt(reset) node _T_1921 = eq(_T_1920, UInt<1>(0h0)) when _T_1921 : node _T_1922 = eq(_T_1919, UInt<1>(0h0)) when _T_1922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1919, UInt<1>(0h1), "") : assert_134 node _T_1923 = asUInt(reset) node _T_1924 = eq(_T_1923, UInt<1>(0h0)) when _T_1924 : node _T_1925 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1926 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1927 = asUInt(reset) node _T_1928 = eq(_T_1927, UInt<1>(0h0)) when _T_1928 : node _T_1929 = eq(_T_1926, UInt<1>(0h0)) when _T_1929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1926, UInt<1>(0h1), "") : assert_136 node _T_1930 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1931 = asUInt(reset) node _T_1932 = eq(_T_1931, UInt<1>(0h0)) when _T_1932 : node _T_1933 = eq(_T_1930, UInt<1>(0h0)) when _T_1933 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1930, UInt<1>(0h1), "") : assert_137 node _T_1934 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1934 : node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(address_ok_1, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1938 = asUInt(reset) node _T_1939 = eq(_T_1938, UInt<1>(0h0)) when _T_1939 : node _T_1940 = eq(source_ok_2, UInt<1>(0h0)) when _T_1940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1941 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_1942 = asUInt(reset) node _T_1943 = eq(_T_1942, UInt<1>(0h0)) when _T_1943 : node _T_1944 = eq(_T_1941, UInt<1>(0h0)) when _T_1944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1941, UInt<1>(0h1), "") : assert_140 node _T_1945 = asUInt(reset) node _T_1946 = eq(_T_1945, UInt<1>(0h0)) when _T_1946 : node _T_1947 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1948 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1949 = asUInt(reset) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(_T_1948, UInt<1>(0h0)) when _T_1951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1948, UInt<1>(0h1), "") : assert_142 node _T_1952 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1952 : node _T_1953 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1954 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1955 = and(_T_1953, _T_1954) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_1956 = shr(io.in.c.bits.source, 3) node _T_1957 = eq(_T_1956, UInt<1>(0h0)) node _T_1958 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1959 = and(_T_1957, _T_1958) node _T_1960 = leq(uncommonBits_14, UInt<3>(0h4)) node _T_1961 = and(_T_1959, _T_1960) node _T_1962 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_1963 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_1964 = or(_T_1961, _T_1962) node _T_1965 = or(_T_1964, _T_1963) node _T_1966 = and(_T_1955, _T_1965) node _T_1967 = or(UInt<1>(0h0), _T_1966) node _T_1968 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1969 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<14>(0h2000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<13>(0h1000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<18>(0h2f000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<17>(0h10000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2000 = cvt(_T_1999) node _T_2001 = and(_T_2000, asSInt(UInt<27>(0h4000000))) node _T_2002 = asSInt(_T_2001) node _T_2003 = eq(_T_2002, asSInt(UInt<1>(0h0))) node _T_2004 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2005 = cvt(_T_2004) node _T_2006 = and(_T_2005, asSInt(UInt<13>(0h1000))) node _T_2007 = asSInt(_T_2006) node _T_2008 = eq(_T_2007, asSInt(UInt<1>(0h0))) node _T_2009 = or(_T_1973, _T_1978) node _T_2010 = or(_T_2009, _T_1983) node _T_2011 = or(_T_2010, _T_1988) node _T_2012 = or(_T_2011, _T_1993) node _T_2013 = or(_T_2012, _T_1998) node _T_2014 = or(_T_2013, _T_2003) node _T_2015 = or(_T_2014, _T_2008) node _T_2016 = and(_T_1968, _T_2015) node _T_2017 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2018 = or(UInt<1>(0h0), _T_2017) node _T_2019 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2020 = cvt(_T_2019) node _T_2021 = and(_T_2020, asSInt(UInt<17>(0h10000))) node _T_2022 = asSInt(_T_2021) node _T_2023 = eq(_T_2022, asSInt(UInt<1>(0h0))) node _T_2024 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2025 = cvt(_T_2024) node _T_2026 = and(_T_2025, asSInt(UInt<29>(0h10000000))) node _T_2027 = asSInt(_T_2026) node _T_2028 = eq(_T_2027, asSInt(UInt<1>(0h0))) node _T_2029 = or(_T_2023, _T_2028) node _T_2030 = and(_T_2018, _T_2029) node _T_2031 = or(UInt<1>(0h0), _T_2016) node _T_2032 = or(_T_2031, _T_2030) node _T_2033 = and(_T_1967, _T_2032) node _T_2034 = asUInt(reset) node _T_2035 = eq(_T_2034, UInt<1>(0h0)) when _T_2035 : node _T_2036 = eq(_T_2033, UInt<1>(0h0)) when _T_2036 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2033, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 2, 0) node _T_2037 = shr(io.in.c.bits.source, 3) node _T_2038 = eq(_T_2037, UInt<1>(0h0)) node _T_2039 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2040 = and(_T_2038, _T_2039) node _T_2041 = leq(uncommonBits_15, UInt<3>(0h4)) node _T_2042 = and(_T_2040, _T_2041) node _T_2043 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2044 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2042 connect _WIRE_6[1], _T_2043 connect _WIRE_6[2], _T_2044 node _T_2045 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2046 = mux(_WIRE_6[0], _T_2045, UInt<1>(0h0)) node _T_2047 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2048 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2049 = or(_T_2046, _T_2047) node _T_2050 = or(_T_2049, _T_2048) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2050 node _T_2051 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2052 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2053 = and(_T_2051, _T_2052) node _T_2054 = or(UInt<1>(0h0), _T_2053) node _T_2055 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<14>(0h2000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<13>(0h1000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<18>(0h2f000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<13>(0h1000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<17>(0h10000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<27>(0h4000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2096 = cvt(_T_2095) node _T_2097 = and(_T_2096, asSInt(UInt<13>(0h1000))) node _T_2098 = asSInt(_T_2097) node _T_2099 = eq(_T_2098, asSInt(UInt<1>(0h0))) node _T_2100 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2101 = cvt(_T_2100) node _T_2102 = and(_T_2101, asSInt(UInt<29>(0h10000000))) node _T_2103 = asSInt(_T_2102) node _T_2104 = eq(_T_2103, asSInt(UInt<1>(0h0))) node _T_2105 = or(_T_2059, _T_2064) node _T_2106 = or(_T_2105, _T_2069) node _T_2107 = or(_T_2106, _T_2074) node _T_2108 = or(_T_2107, _T_2079) node _T_2109 = or(_T_2108, _T_2084) node _T_2110 = or(_T_2109, _T_2089) node _T_2111 = or(_T_2110, _T_2094) node _T_2112 = or(_T_2111, _T_2099) node _T_2113 = or(_T_2112, _T_2104) node _T_2114 = and(_T_2054, _T_2113) node _T_2115 = or(UInt<1>(0h0), _T_2114) node _T_2116 = and(_WIRE_7, _T_2115) node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(_T_2116, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2116, UInt<1>(0h1), "") : assert_144 node _T_2120 = asUInt(reset) node _T_2121 = eq(_T_2120, UInt<1>(0h0)) when _T_2121 : node _T_2122 = eq(source_ok_2, UInt<1>(0h0)) when _T_2122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2123 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2124 = asUInt(reset) node _T_2125 = eq(_T_2124, UInt<1>(0h0)) when _T_2125 : node _T_2126 = eq(_T_2123, UInt<1>(0h0)) when _T_2126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2123, UInt<1>(0h1), "") : assert_146 node _T_2127 = asUInt(reset) node _T_2128 = eq(_T_2127, UInt<1>(0h0)) when _T_2128 : node _T_2129 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2130 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2131 = asUInt(reset) node _T_2132 = eq(_T_2131, UInt<1>(0h0)) when _T_2132 : node _T_2133 = eq(_T_2130, UInt<1>(0h0)) when _T_2133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2130, UInt<1>(0h1), "") : assert_148 node _T_2134 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2135 = asUInt(reset) node _T_2136 = eq(_T_2135, UInt<1>(0h0)) when _T_2136 : node _T_2137 = eq(_T_2134, UInt<1>(0h0)) when _T_2137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2134, UInt<1>(0h1), "") : assert_149 node _T_2138 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2138 : node _T_2139 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2140 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2141 = and(_T_2139, _T_2140) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0) node _T_2142 = shr(io.in.c.bits.source, 3) node _T_2143 = eq(_T_2142, UInt<1>(0h0)) node _T_2144 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2145 = and(_T_2143, _T_2144) node _T_2146 = leq(uncommonBits_16, UInt<3>(0h4)) node _T_2147 = and(_T_2145, _T_2146) node _T_2148 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2149 = eq(io.in.c.bits.source, UInt<4>(0h8)) node _T_2150 = or(_T_2147, _T_2148) node _T_2151 = or(_T_2150, _T_2149) node _T_2152 = and(_T_2141, _T_2151) node _T_2153 = or(UInt<1>(0h0), _T_2152) node _T_2154 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2155 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<14>(0h2000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<13>(0h1000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<18>(0h2f000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<17>(0h10000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2186 = cvt(_T_2185) node _T_2187 = and(_T_2186, asSInt(UInt<27>(0h4000000))) node _T_2188 = asSInt(_T_2187) node _T_2189 = eq(_T_2188, asSInt(UInt<1>(0h0))) node _T_2190 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2191 = cvt(_T_2190) node _T_2192 = and(_T_2191, asSInt(UInt<13>(0h1000))) node _T_2193 = asSInt(_T_2192) node _T_2194 = eq(_T_2193, asSInt(UInt<1>(0h0))) node _T_2195 = or(_T_2159, _T_2164) node _T_2196 = or(_T_2195, _T_2169) node _T_2197 = or(_T_2196, _T_2174) node _T_2198 = or(_T_2197, _T_2179) node _T_2199 = or(_T_2198, _T_2184) node _T_2200 = or(_T_2199, _T_2189) node _T_2201 = or(_T_2200, _T_2194) node _T_2202 = and(_T_2154, _T_2201) node _T_2203 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2204 = or(UInt<1>(0h0), _T_2203) node _T_2205 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2206 = cvt(_T_2205) node _T_2207 = and(_T_2206, asSInt(UInt<17>(0h10000))) node _T_2208 = asSInt(_T_2207) node _T_2209 = eq(_T_2208, asSInt(UInt<1>(0h0))) node _T_2210 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2211 = cvt(_T_2210) node _T_2212 = and(_T_2211, asSInt(UInt<29>(0h10000000))) node _T_2213 = asSInt(_T_2212) node _T_2214 = eq(_T_2213, asSInt(UInt<1>(0h0))) node _T_2215 = or(_T_2209, _T_2214) node _T_2216 = and(_T_2204, _T_2215) node _T_2217 = or(UInt<1>(0h0), _T_2202) node _T_2218 = or(_T_2217, _T_2216) node _T_2219 = and(_T_2153, _T_2218) node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : node _T_2222 = eq(_T_2219, UInt<1>(0h0)) when _T_2222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2219, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<3>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0) node _T_2223 = shr(io.in.c.bits.source, 3) node _T_2224 = eq(_T_2223, UInt<1>(0h0)) node _T_2225 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2226 = and(_T_2224, _T_2225) node _T_2227 = leq(uncommonBits_17, UInt<3>(0h4)) node _T_2228 = and(_T_2226, _T_2227) node _T_2229 = eq(io.in.c.bits.source, UInt<3>(0h5)) node _T_2230 = eq(io.in.c.bits.source, UInt<4>(0h8)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2228 connect _WIRE_8[1], _T_2229 connect _WIRE_8[2], _T_2230 node _T_2231 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2232 = mux(_WIRE_8[0], _T_2231, UInt<1>(0h0)) node _T_2233 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2234 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2235 = or(_T_2232, _T_2233) node _T_2236 = or(_T_2235, _T_2234) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2236 node _T_2237 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2238 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2239 = and(_T_2237, _T_2238) node _T_2240 = or(UInt<1>(0h0), _T_2239) node _T_2241 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<14>(0h2000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<13>(0h1000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<18>(0h2f000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<13>(0h1000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<17>(0h10000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<27>(0h4000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2282 = cvt(_T_2281) node _T_2283 = and(_T_2282, asSInt(UInt<13>(0h1000))) node _T_2284 = asSInt(_T_2283) node _T_2285 = eq(_T_2284, asSInt(UInt<1>(0h0))) node _T_2286 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2287 = cvt(_T_2286) node _T_2288 = and(_T_2287, asSInt(UInt<29>(0h10000000))) node _T_2289 = asSInt(_T_2288) node _T_2290 = eq(_T_2289, asSInt(UInt<1>(0h0))) node _T_2291 = or(_T_2245, _T_2250) node _T_2292 = or(_T_2291, _T_2255) node _T_2293 = or(_T_2292, _T_2260) node _T_2294 = or(_T_2293, _T_2265) node _T_2295 = or(_T_2294, _T_2270) node _T_2296 = or(_T_2295, _T_2275) node _T_2297 = or(_T_2296, _T_2280) node _T_2298 = or(_T_2297, _T_2285) node _T_2299 = or(_T_2298, _T_2290) node _T_2300 = and(_T_2240, _T_2299) node _T_2301 = or(UInt<1>(0h0), _T_2300) node _T_2302 = and(_WIRE_9, _T_2301) node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(_T_2302, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2302, UInt<1>(0h1), "") : assert_151 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : node _T_2308 = eq(source_ok_2, UInt<1>(0h0)) when _T_2308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2309 = geq(io.in.c.bits.size, UInt<3>(0h4)) node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : node _T_2312 = eq(_T_2309, UInt<1>(0h0)) when _T_2312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2309, UInt<1>(0h1), "") : assert_153 node _T_2313 = asUInt(reset) node _T_2314 = eq(_T_2313, UInt<1>(0h0)) when _T_2314 : node _T_2315 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2316 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(_T_2316, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2316, UInt<1>(0h1), "") : assert_155 node _T_2320 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2320 : node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(address_ok_1, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : node _T_2326 = eq(source_ok_2, UInt<1>(0h0)) when _T_2326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2327 = asUInt(reset) node _T_2328 = eq(_T_2327, UInt<1>(0h0)) when _T_2328 : node _T_2329 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2330 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2331 = asUInt(reset) node _T_2332 = eq(_T_2331, UInt<1>(0h0)) when _T_2332 : node _T_2333 = eq(_T_2330, UInt<1>(0h0)) when _T_2333 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2330, UInt<1>(0h1), "") : assert_159 node _T_2334 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(_T_2334, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2334, UInt<1>(0h1), "") : assert_160 node _T_2338 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2338 : node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(address_ok_1, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2342 = asUInt(reset) node _T_2343 = eq(_T_2342, UInt<1>(0h0)) when _T_2343 : node _T_2344 = eq(source_ok_2, UInt<1>(0h0)) when _T_2344 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2345 = asUInt(reset) node _T_2346 = eq(_T_2345, UInt<1>(0h0)) when _T_2346 : node _T_2347 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2347 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2348 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(_T_2348, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2348, UInt<1>(0h1), "") : assert_164 node _T_2352 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2352 : node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(address_ok_1, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2356 = asUInt(reset) node _T_2357 = eq(_T_2356, UInt<1>(0h0)) when _T_2357 : node _T_2358 = eq(source_ok_2, UInt<1>(0h0)) when _T_2358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2359 = asUInt(reset) node _T_2360 = eq(_T_2359, UInt<1>(0h0)) when _T_2360 : node _T_2361 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2362 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2363 = asUInt(reset) node _T_2364 = eq(_T_2363, UInt<1>(0h0)) when _T_2364 : node _T_2365 = eq(_T_2362, UInt<1>(0h0)) when _T_2365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2362, UInt<1>(0h1), "") : assert_168 node _T_2366 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2367 = asUInt(reset) node _T_2368 = eq(_T_2367, UInt<1>(0h0)) when _T_2368 : node _T_2369 = eq(_T_2366, UInt<1>(0h0)) when _T_2369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2366, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<5>(0h10)) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2373 = eq(a_first, UInt<1>(0h0)) node _T_2374 = and(io.in.a.valid, _T_2373) when _T_2374 : node _T_2375 = eq(io.in.a.bits.opcode, opcode) node _T_2376 = asUInt(reset) node _T_2377 = eq(_T_2376, UInt<1>(0h0)) when _T_2377 : node _T_2378 = eq(_T_2375, UInt<1>(0h0)) when _T_2378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2375, UInt<1>(0h1), "") : assert_171 node _T_2379 = eq(io.in.a.bits.param, param) node _T_2380 = asUInt(reset) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) when _T_2381 : node _T_2382 = eq(_T_2379, UInt<1>(0h0)) when _T_2382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2379, UInt<1>(0h1), "") : assert_172 node _T_2383 = eq(io.in.a.bits.size, size) node _T_2384 = asUInt(reset) node _T_2385 = eq(_T_2384, UInt<1>(0h0)) when _T_2385 : node _T_2386 = eq(_T_2383, UInt<1>(0h0)) when _T_2386 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2383, UInt<1>(0h1), "") : assert_173 node _T_2387 = eq(io.in.a.bits.source, source) node _T_2388 = asUInt(reset) node _T_2389 = eq(_T_2388, UInt<1>(0h0)) when _T_2389 : node _T_2390 = eq(_T_2387, UInt<1>(0h0)) when _T_2390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2387, UInt<1>(0h1), "") : assert_174 node _T_2391 = eq(io.in.a.bits.address, address) node _T_2392 = asUInt(reset) node _T_2393 = eq(_T_2392, UInt<1>(0h0)) when _T_2393 : node _T_2394 = eq(_T_2391, UInt<1>(0h0)) when _T_2394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2391, UInt<1>(0h1), "") : assert_175 node _T_2395 = and(io.in.a.ready, io.in.a.valid) node _T_2396 = and(_T_2395, a_first) when _T_2396 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2397 = eq(d_first, UInt<1>(0h0)) node _T_2398 = and(io.in.d.valid, _T_2397) when _T_2398 : node _T_2399 = eq(io.in.d.bits.opcode, opcode_1) node _T_2400 = asUInt(reset) node _T_2401 = eq(_T_2400, UInt<1>(0h0)) when _T_2401 : node _T_2402 = eq(_T_2399, UInt<1>(0h0)) when _T_2402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2399, UInt<1>(0h1), "") : assert_176 node _T_2403 = eq(io.in.d.bits.param, param_1) node _T_2404 = asUInt(reset) node _T_2405 = eq(_T_2404, UInt<1>(0h0)) when _T_2405 : node _T_2406 = eq(_T_2403, UInt<1>(0h0)) when _T_2406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2403, UInt<1>(0h1), "") : assert_177 node _T_2407 = eq(io.in.d.bits.size, size_1) node _T_2408 = asUInt(reset) node _T_2409 = eq(_T_2408, UInt<1>(0h0)) when _T_2409 : node _T_2410 = eq(_T_2407, UInt<1>(0h0)) when _T_2410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2407, UInt<1>(0h1), "") : assert_178 node _T_2411 = eq(io.in.d.bits.source, source_1) node _T_2412 = asUInt(reset) node _T_2413 = eq(_T_2412, UInt<1>(0h0)) when _T_2413 : node _T_2414 = eq(_T_2411, UInt<1>(0h0)) when _T_2414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2411, UInt<1>(0h1), "") : assert_179 node _T_2415 = eq(io.in.d.bits.sink, sink) node _T_2416 = asUInt(reset) node _T_2417 = eq(_T_2416, UInt<1>(0h0)) when _T_2417 : node _T_2418 = eq(_T_2415, UInt<1>(0h0)) when _T_2418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2415, UInt<1>(0h1), "") : assert_180 node _T_2419 = eq(io.in.d.bits.denied, denied) node _T_2420 = asUInt(reset) node _T_2421 = eq(_T_2420, UInt<1>(0h0)) when _T_2421 : node _T_2422 = eq(_T_2419, UInt<1>(0h0)) when _T_2422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2419, UInt<1>(0h1), "") : assert_181 node _T_2423 = and(io.in.d.ready, io.in.d.valid) node _T_2424 = and(_T_2423, d_first) when _T_2424 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 4) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2425 = eq(b_first, UInt<1>(0h0)) node _T_2426 = and(io.in.b.valid, _T_2425) when _T_2426 : node _T_2427 = eq(io.in.b.bits.opcode, opcode_2) node _T_2428 = asUInt(reset) node _T_2429 = eq(_T_2428, UInt<1>(0h0)) when _T_2429 : node _T_2430 = eq(_T_2427, UInt<1>(0h0)) when _T_2430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2427, UInt<1>(0h1), "") : assert_182 node _T_2431 = eq(io.in.b.bits.param, param_2) node _T_2432 = asUInt(reset) node _T_2433 = eq(_T_2432, UInt<1>(0h0)) when _T_2433 : node _T_2434 = eq(_T_2431, UInt<1>(0h0)) when _T_2434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2431, UInt<1>(0h1), "") : assert_183 node _T_2435 = eq(io.in.b.bits.size, size_2) node _T_2436 = asUInt(reset) node _T_2437 = eq(_T_2436, UInt<1>(0h0)) when _T_2437 : node _T_2438 = eq(_T_2435, UInt<1>(0h0)) when _T_2438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2435, UInt<1>(0h1), "") : assert_184 node _T_2439 = eq(io.in.b.bits.source, source_2) node _T_2440 = asUInt(reset) node _T_2441 = eq(_T_2440, UInt<1>(0h0)) when _T_2441 : node _T_2442 = eq(_T_2439, UInt<1>(0h0)) when _T_2442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2439, UInt<1>(0h1), "") : assert_185 node _T_2443 = eq(io.in.b.bits.address, address_1) node _T_2444 = asUInt(reset) node _T_2445 = eq(_T_2444, UInt<1>(0h0)) when _T_2445 : node _T_2446 = eq(_T_2443, UInt<1>(0h0)) when _T_2446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2443, UInt<1>(0h1), "") : assert_186 node _T_2447 = and(io.in.b.ready, io.in.b.valid) node _T_2448 = and(_T_2447, b_first) when _T_2448 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2449 = eq(c_first, UInt<1>(0h0)) node _T_2450 = and(io.in.c.valid, _T_2449) when _T_2450 : node _T_2451 = eq(io.in.c.bits.opcode, opcode_3) node _T_2452 = asUInt(reset) node _T_2453 = eq(_T_2452, UInt<1>(0h0)) when _T_2453 : node _T_2454 = eq(_T_2451, UInt<1>(0h0)) when _T_2454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2451, UInt<1>(0h1), "") : assert_187 node _T_2455 = eq(io.in.c.bits.param, param_3) node _T_2456 = asUInt(reset) node _T_2457 = eq(_T_2456, UInt<1>(0h0)) when _T_2457 : node _T_2458 = eq(_T_2455, UInt<1>(0h0)) when _T_2458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2455, UInt<1>(0h1), "") : assert_188 node _T_2459 = eq(io.in.c.bits.size, size_3) node _T_2460 = asUInt(reset) node _T_2461 = eq(_T_2460, UInt<1>(0h0)) when _T_2461 : node _T_2462 = eq(_T_2459, UInt<1>(0h0)) when _T_2462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2459, UInt<1>(0h1), "") : assert_189 node _T_2463 = eq(io.in.c.bits.source, source_3) node _T_2464 = asUInt(reset) node _T_2465 = eq(_T_2464, UInt<1>(0h0)) when _T_2465 : node _T_2466 = eq(_T_2463, UInt<1>(0h0)) when _T_2466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2463, UInt<1>(0h1), "") : assert_190 node _T_2467 = eq(io.in.c.bits.address, address_2) node _T_2468 = asUInt(reset) node _T_2469 = eq(_T_2468, UInt<1>(0h0)) when _T_2469 : node _T_2470 = eq(_T_2467, UInt<1>(0h0)) when _T_2470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2467, UInt<1>(0h1), "") : assert_191 node _T_2471 = and(io.in.c.ready, io.in.c.valid) node _T_2472 = and(_T_2471, c_first) when _T_2472 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes : UInt<72>, clock, reset, UInt<72>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<9> connect a_set, UInt<9>(0h0) wire a_set_wo_ready : UInt<9> connect a_set_wo_ready, UInt<9>(0h0) wire a_opcodes_set : UInt<36> connect a_opcodes_set, UInt<36>(0h0) wire a_sizes_set : UInt<72> connect a_sizes_set, UInt<72>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2473 = and(io.in.a.valid, a_first_1) node _T_2474 = and(_T_2473, UInt<1>(0h1)) when _T_2474 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2475 = and(io.in.a.ready, io.in.a.valid) node _T_2476 = and(_T_2475, a_first_1) node _T_2477 = and(_T_2476, UInt<1>(0h1)) when _T_2477 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2478 = dshr(inflight, io.in.a.bits.source) node _T_2479 = bits(_T_2478, 0, 0) node _T_2480 = eq(_T_2479, UInt<1>(0h0)) node _T_2481 = asUInt(reset) node _T_2482 = eq(_T_2481, UInt<1>(0h0)) when _T_2482 : node _T_2483 = eq(_T_2480, UInt<1>(0h0)) when _T_2483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2480, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<9> connect d_clr, UInt<9>(0h0) wire d_clr_wo_ready : UInt<9> connect d_clr_wo_ready, UInt<9>(0h0) wire d_opcodes_clr : UInt<36> connect d_opcodes_clr, UInt<36>(0h0) wire d_sizes_clr : UInt<72> connect d_sizes_clr, UInt<72>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2484 = and(io.in.d.valid, d_first_1) node _T_2485 = and(_T_2484, UInt<1>(0h1)) node _T_2486 = eq(d_release_ack, UInt<1>(0h0)) node _T_2487 = and(_T_2485, _T_2486) when _T_2487 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2488 = and(io.in.d.ready, io.in.d.valid) node _T_2489 = and(_T_2488, d_first_1) node _T_2490 = and(_T_2489, UInt<1>(0h1)) node _T_2491 = eq(d_release_ack, UInt<1>(0h0)) node _T_2492 = and(_T_2490, _T_2491) when _T_2492 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2493 = and(io.in.d.valid, d_first_1) node _T_2494 = and(_T_2493, UInt<1>(0h1)) node _T_2495 = eq(d_release_ack, UInt<1>(0h0)) node _T_2496 = and(_T_2494, _T_2495) when _T_2496 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2497 = dshr(inflight, io.in.d.bits.source) node _T_2498 = bits(_T_2497, 0, 0) node _T_2499 = or(_T_2498, same_cycle_resp) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_194 node _T_2509 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_195 else : node _T_2513 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2514 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2515 = or(_T_2513, _T_2514) node _T_2516 = asUInt(reset) node _T_2517 = eq(_T_2516, UInt<1>(0h0)) when _T_2517 : node _T_2518 = eq(_T_2515, UInt<1>(0h0)) when _T_2518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2515, UInt<1>(0h1), "") : assert_196 node _T_2519 = eq(io.in.d.bits.size, a_size_lookup) node _T_2520 = asUInt(reset) node _T_2521 = eq(_T_2520, UInt<1>(0h0)) when _T_2521 : node _T_2522 = eq(_T_2519, UInt<1>(0h0)) when _T_2522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2519, UInt<1>(0h1), "") : assert_197 node _T_2523 = and(io.in.d.valid, d_first_1) node _T_2524 = and(_T_2523, a_first_1) node _T_2525 = and(_T_2524, io.in.a.valid) node _T_2526 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2527 = and(_T_2525, _T_2526) node _T_2528 = eq(d_release_ack, UInt<1>(0h0)) node _T_2529 = and(_T_2527, _T_2528) when _T_2529 : node _T_2530 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2531 = or(_T_2530, io.in.a.ready) node _T_2532 = asUInt(reset) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) when _T_2533 : node _T_2534 = eq(_T_2531, UInt<1>(0h0)) when _T_2534 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2531, UInt<1>(0h1), "") : assert_198 node _T_2535 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2536 = orr(a_set_wo_ready) node _T_2537 = eq(_T_2536, UInt<1>(0h0)) node _T_2538 = or(_T_2535, _T_2537) node _T_2539 = asUInt(reset) node _T_2540 = eq(_T_2539, UInt<1>(0h0)) when _T_2540 : node _T_2541 = eq(_T_2538, UInt<1>(0h0)) when _T_2541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2538, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_84 node _T_2542 = orr(inflight) node _T_2543 = eq(_T_2542, UInt<1>(0h0)) node _T_2544 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2545 = or(_T_2543, _T_2544) node _T_2546 = lt(watchdog, plusarg_reader.out) node _T_2547 = or(_T_2545, _T_2546) node _T_2548 = asUInt(reset) node _T_2549 = eq(_T_2548, UInt<1>(0h0)) when _T_2549 : node _T_2550 = eq(_T_2547, UInt<1>(0h0)) when _T_2550 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2547, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2551 = and(io.in.a.ready, io.in.a.valid) node _T_2552 = and(io.in.d.ready, io.in.d.valid) node _T_2553 = or(_T_2551, _T_2552) when _T_2553 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<9>, clock, reset, UInt<9>(0h0) regreset inflight_opcodes_1 : UInt<36>, clock, reset, UInt<36>(0h0) regreset inflight_sizes_1 : UInt<72>, clock, reset, UInt<72>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 4) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<9> connect c_set, UInt<9>(0h0) wire c_set_wo_ready : UInt<9> connect c_set_wo_ready, UInt<9>(0h0) wire c_opcodes_set : UInt<36> connect c_opcodes_set, UInt<36>(0h0) wire c_sizes_set : UInt<72> connect c_sizes_set, UInt<72>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2554 = and(io.in.c.valid, c_first_1) node _T_2555 = bits(io.in.c.bits.opcode, 2, 2) node _T_2556 = bits(io.in.c.bits.opcode, 1, 1) node _T_2557 = and(_T_2555, _T_2556) node _T_2558 = and(_T_2554, _T_2557) when _T_2558 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2559 = and(io.in.c.ready, io.in.c.valid) node _T_2560 = and(_T_2559, c_first_1) node _T_2561 = bits(io.in.c.bits.opcode, 2, 2) node _T_2562 = bits(io.in.c.bits.opcode, 1, 1) node _T_2563 = and(_T_2561, _T_2562) node _T_2564 = and(_T_2560, _T_2563) when _T_2564 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2565 = dshr(inflight_1, io.in.c.bits.source) node _T_2566 = bits(_T_2565, 0, 0) node _T_2567 = eq(_T_2566, UInt<1>(0h0)) node _T_2568 = asUInt(reset) node _T_2569 = eq(_T_2568, UInt<1>(0h0)) when _T_2569 : node _T_2570 = eq(_T_2567, UInt<1>(0h0)) when _T_2570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2567, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<9> connect d_clr_1, UInt<9>(0h0) wire d_clr_wo_ready_1 : UInt<9> connect d_clr_wo_ready_1, UInt<9>(0h0) wire d_opcodes_clr_1 : UInt<36> connect d_opcodes_clr_1, UInt<36>(0h0) wire d_sizes_clr_1 : UInt<72> connect d_sizes_clr_1, UInt<72>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2571 = and(io.in.d.valid, d_first_2) node _T_2572 = and(_T_2571, UInt<1>(0h1)) node _T_2573 = and(_T_2572, d_release_ack_1) when _T_2573 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2574 = and(io.in.d.ready, io.in.d.valid) node _T_2575 = and(_T_2574, d_first_2) node _T_2576 = and(_T_2575, UInt<1>(0h1)) node _T_2577 = and(_T_2576, d_release_ack_1) when _T_2577 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2578 = and(io.in.d.valid, d_first_2) node _T_2579 = and(_T_2578, UInt<1>(0h1)) node _T_2580 = and(_T_2579, d_release_ack_1) when _T_2580 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2581 = dshr(inflight_1, io.in.d.bits.source) node _T_2582 = bits(_T_2581, 0, 0) node _T_2583 = or(_T_2582, same_cycle_resp_1) node _T_2584 = asUInt(reset) node _T_2585 = eq(_T_2584, UInt<1>(0h0)) when _T_2585 : node _T_2586 = eq(_T_2583, UInt<1>(0h0)) when _T_2586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2583, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2587 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2588 = asUInt(reset) node _T_2589 = eq(_T_2588, UInt<1>(0h0)) when _T_2589 : node _T_2590 = eq(_T_2587, UInt<1>(0h0)) when _T_2590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2587, UInt<1>(0h1), "") : assert_203 else : node _T_2591 = eq(io.in.d.bits.size, c_size_lookup) node _T_2592 = asUInt(reset) node _T_2593 = eq(_T_2592, UInt<1>(0h0)) when _T_2593 : node _T_2594 = eq(_T_2591, UInt<1>(0h0)) when _T_2594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2591, UInt<1>(0h1), "") : assert_204 node _T_2595 = and(io.in.d.valid, d_first_2) node _T_2596 = and(_T_2595, c_first_1) node _T_2597 = and(_T_2596, io.in.c.valid) node _T_2598 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2599 = and(_T_2597, _T_2598) node _T_2600 = and(_T_2599, d_release_ack_1) node _T_2601 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2602 = and(_T_2600, _T_2601) when _T_2602 : node _T_2603 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2604 = or(_T_2603, io.in.c.ready) node _T_2605 = asUInt(reset) node _T_2606 = eq(_T_2605, UInt<1>(0h0)) when _T_2606 : node _T_2607 = eq(_T_2604, UInt<1>(0h0)) when _T_2607 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2604, UInt<1>(0h1), "") : assert_205 node _T_2608 = orr(c_set_wo_ready) when _T_2608 : node _T_2609 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2610 = asUInt(reset) node _T_2611 = eq(_T_2610, UInt<1>(0h0)) when _T_2611 : node _T_2612 = eq(_T_2609, UInt<1>(0h0)) when _T_2612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2609, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_85 node _T_2613 = orr(inflight_1) node _T_2614 = eq(_T_2613, UInt<1>(0h0)) node _T_2615 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2616 = or(_T_2614, _T_2615) node _T_2617 = lt(watchdog_1, plusarg_reader_1.out) node _T_2618 = or(_T_2616, _T_2617) node _T_2619 = asUInt(reset) node _T_2620 = eq(_T_2619, UInt<1>(0h0)) when _T_2620 : node _T_2621 = eq(_T_2618, UInt<1>(0h0)) when _T_2621 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2618, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2622 = and(io.in.c.ready, io.in.c.valid) node _T_2623 = and(io.in.d.ready, io.in.d.valid) node _T_2624 = or(_T_2622, _T_2623) when _T_2624 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<16>, clock, reset, UInt<16>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 4) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<16> connect d_set, UInt<16>(0h0) node _T_2625 = and(io.in.d.ready, io.in.d.valid) node _T_2626 = and(_T_2625, d_first_3) node _T_2627 = bits(io.in.d.bits.opcode, 2, 2) node _T_2628 = bits(io.in.d.bits.opcode, 1, 1) node _T_2629 = eq(_T_2628, UInt<1>(0h0)) node _T_2630 = and(_T_2627, _T_2629) node _T_2631 = and(_T_2626, _T_2630) when _T_2631 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2632 = dshr(inflight_2, io.in.d.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = eq(_T_2633, UInt<1>(0h0)) node _T_2635 = asUInt(reset) node _T_2636 = eq(_T_2635, UInt<1>(0h0)) when _T_2636 : node _T_2637 = eq(_T_2634, UInt<1>(0h0)) when _T_2637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2634, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<16> connect e_clr, UInt<16>(0h0) node _T_2638 = and(io.in.e.ready, io.in.e.valid) node _T_2639 = and(_T_2638, UInt<1>(0h1)) node _T_2640 = and(_T_2639, UInt<1>(0h1)) when _T_2640 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2641 = or(d_set, inflight_2) node _T_2642 = dshr(_T_2641, io.in.e.bits.sink) node _T_2643 = bits(_T_2642, 0, 0) node _T_2644 = asUInt(reset) node _T_2645 = eq(_T_2644, UInt<1>(0h0)) when _T_2645 : node _T_2646 = eq(_T_2643, UInt<1>(0h0)) when _T_2646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/CrossingHelper.scala:65:80)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2643, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_42( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [127:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [3:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [7:0] b_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] b_first_count = 8'h0; // @[Edges.scala:234:25] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [2:0] uncommonBits = _uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_1 = _uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_2 = _uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_3 = _uncommonBits_T_3[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_6 = _uncommonBits_T_6[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_7 = _uncommonBits_T_7[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_8 = _uncommonBits_T_8[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[3]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1_1 = |(io_in_b_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size_1 = mask_sizeOH_1[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit_1 = io_in_b_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2_1 = mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit_1 = ~mask_sub_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2_1 = mask_sub_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T_2 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_3 = mask_sub_sub_sub_size_1 & mask_sub_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1_1 = mask_sub_sub_sub_sub_0_1_1 | _mask_sub_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_4 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2_1 = mask_sub_sub_sub_0_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_5 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_6 = mask_sub_sub_size_1 & mask_sub_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2_1 = mask_sub_sub_sub_1_2_1 & mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_7 = mask_sub_sub_size_1 & mask_sub_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1_1 = mask_sub_sub_sub_1_1_1 | _mask_sub_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_8 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_9 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_10 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_11 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2_1 = mask_sub_sub_2_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_12 = mask_sub_size_1 & mask_sub_4_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2_1 = mask_sub_sub_2_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_13 = mask_sub_size_1 & mask_sub_5_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1_1 = mask_sub_sub_2_1_1 | _mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2_1 = mask_sub_sub_3_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_14 = mask_sub_size_1 & mask_sub_6_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2_1 = mask_sub_sub_3_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_15 = mask_sub_size_1 & mask_sub_7_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1_1 = mask_sub_sub_3_1_1 | _mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_16 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_16 = mask_size_1 & mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_16 = mask_sub_0_1_1 | _mask_acc_T_16; // @[Misc.scala:215:{29,38}] wire mask_eq_17 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_17 = mask_size_1 & mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_17 = mask_sub_0_1_1 | _mask_acc_T_17; // @[Misc.scala:215:{29,38}] wire mask_eq_18 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_18 = mask_size_1 & mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_18 = mask_sub_1_1_1 | _mask_acc_T_18; // @[Misc.scala:215:{29,38}] wire mask_eq_19 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_19 = mask_size_1 & mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_19 = mask_sub_1_1_1 | _mask_acc_T_19; // @[Misc.scala:215:{29,38}] wire mask_eq_20 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_20 = mask_size_1 & mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_20 = mask_sub_2_1_1 | _mask_acc_T_20; // @[Misc.scala:215:{29,38}] wire mask_eq_21 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_21 = mask_size_1 & mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_21 = mask_sub_2_1_1 | _mask_acc_T_21; // @[Misc.scala:215:{29,38}] wire mask_eq_22 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_22 = mask_size_1 & mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_22 = mask_sub_3_1_1 | _mask_acc_T_22; // @[Misc.scala:215:{29,38}] wire mask_eq_23 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_23 = mask_size_1 & mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_23 = mask_sub_3_1_1 | _mask_acc_T_23; // @[Misc.scala:215:{29,38}] wire mask_eq_24 = mask_sub_4_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_24 = mask_size_1 & mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_24 = mask_sub_4_1_1 | _mask_acc_T_24; // @[Misc.scala:215:{29,38}] wire mask_eq_25 = mask_sub_4_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_25 = mask_size_1 & mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_25 = mask_sub_4_1_1 | _mask_acc_T_25; // @[Misc.scala:215:{29,38}] wire mask_eq_26 = mask_sub_5_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_26 = mask_size_1 & mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_26 = mask_sub_5_1_1 | _mask_acc_T_26; // @[Misc.scala:215:{29,38}] wire mask_eq_27 = mask_sub_5_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_27 = mask_size_1 & mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_27 = mask_sub_5_1_1 | _mask_acc_T_27; // @[Misc.scala:215:{29,38}] wire mask_eq_28 = mask_sub_6_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_28 = mask_size_1 & mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_28 = mask_sub_6_1_1 | _mask_acc_T_28; // @[Misc.scala:215:{29,38}] wire mask_eq_29 = mask_sub_6_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_29 = mask_size_1 & mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_29 = mask_sub_6_1_1 | _mask_acc_T_29; // @[Misc.scala:215:{29,38}] wire mask_eq_30 = mask_sub_7_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_30 = mask_size_1 & mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_30 = mask_sub_7_1_1 | _mask_acc_T_30; // @[Misc.scala:215:{29,38}] wire mask_eq_31 = mask_sub_7_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_31 = mask_size_1 & mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_31 = mask_sub_7_1_1 | _mask_acc_T_31; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo_1 = {mask_acc_17, mask_acc_16}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi_1 = {mask_acc_19, mask_acc_18}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo_1 = {mask_lo_lo_hi_1, mask_lo_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo_1 = {mask_acc_21, mask_acc_20}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi_1 = {mask_acc_23, mask_acc_22}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi_1 = {mask_lo_hi_hi_1, mask_lo_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo_1 = {mask_acc_25, mask_acc_24}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi_1 = {mask_acc_27, mask_acc_26}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo_1 = {mask_hi_lo_hi_1, mask_hi_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo_1 = {mask_acc_29, mask_acc_28}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi_1 = {mask_acc_31, mask_acc_30}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi_1 = {mask_hi_hi_hi_1, mask_hi_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [15:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [2:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [2:0] _legal_source_T_9 = _legal_source_WIRE_1 ? 3'h5 : 3'h0; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_10 = {_legal_source_WIRE_2, 3'h0}; // @[Mux.scala:30:73] wire [3:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} | _legal_source_T_10; // @[Mux.scala:30:73] wire [3:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [2:0] uncommonBits_12 = _uncommonBits_T_12[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[3]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 4'h5; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 4'h8; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [2:0] uncommonBits_13 = _uncommonBits_T_13[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_15 = _uncommonBits_T_15[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}] wire _T_2551 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2551; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2551; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2625 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2625; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2625; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [7:0] b_first_counter; // @[Edges.scala:229:27] wire [8:0] _b_first_counter1_T = {1'h0, b_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] b_first_counter1 = _b_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _b_first_counter_T = b_first ? 8'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [3:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2622 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2622; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2622; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T = {1'h0, c_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1 = _c_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [8:0] inflight; // @[Monitor.scala:614:27] reg [35:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [71:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] a_set; // @[Monitor.scala:626:34] wire [8:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [35:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [71:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [35:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [35:0] _a_opcode_lookup_T_6 = {32'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [35:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [71:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [71:0] _a_size_lookup_T_6 = {64'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [71:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[71:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_21 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2477 = _T_2551 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2477 ? _a_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2477 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2477 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2477 ? _a_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2477 ? _a_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [8:0] d_clr; // @[Monitor.scala:664:34] wire [8:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [35:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [71:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2523 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_23 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2523 & ~d_release_ack ? _d_clr_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2492 = _T_2625 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2492 ? _d_clr_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2492 ? _d_opcodes_clr_T_5[35:0] : 36'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2492 ? _d_sizes_clr_T_5[71:0] : 72'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [8:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [8:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [8:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [35:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [35:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [35:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [71:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [71:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [71:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [8:0] inflight_1; // @[Monitor.scala:726:35] reg [35:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [71:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 8'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [7:0] c_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] c_first_counter1_1 = _c_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [8:0] c_set; // @[Monitor.scala:738:34] wire [8:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [35:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [71:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [35:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [35:0] _c_opcode_lookup_T_6 = {32'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [35:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[35:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [71:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [71:0] _c_size_lookup_T_6 = {64'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [71:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[71:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_24 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2564 = _T_2622 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2564 ? _c_set_T[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2564 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2564 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2564 ? _c_opcodes_set_T_1[35:0] : 36'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [6:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [131:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2564 ? _c_sizes_set_T_1[71:0] : 72'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [8:0] d_clr_1; // @[Monitor.scala:774:34] wire [8:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [35:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [71:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2595 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2595 & d_release_ack_1 ? _d_clr_wo_ready_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire _T_2577 = _T_2625 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2577 ? _d_clr_T_1[8:0] : 9'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2577 ? _d_opcodes_clr_T_11[35:0] : 36'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2577 ? _d_sizes_clr_T_11[71:0] : 72'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [8:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [8:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [8:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [35:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [35:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [35:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [71:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [71:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [71:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [15:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_3; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_3 = _d_first_counter1_T_3[7:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] d_set; // @[Monitor.scala:833:25] wire _T_2631 = _T_2625 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [15:0] _GEN_25 = {12'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _d_set_T = 16'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2631 ? _d_set_T : 16'h0; // @[OneHot.scala:58:35] wire [15:0] e_clr; // @[Monitor.scala:839:25] wire _T_2640 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [15:0] _GEN_26 = {12'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [15:0] _e_clr_T = 16'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2640 ? _e_clr_T : 16'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_170 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_170( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_18 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_274 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_18( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_274 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLAsyncCrossingSource_a9d32s1k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, out : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_61 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip b : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, c : { mem : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, flip d : { mem : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}, e : { mem : { sink : UInt<1>}[1], flip ridx : UInt<1>, widx : UInt<1>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}} invalidate nodeOut.e.safe.sink_reset_n invalidate nodeOut.e.safe.source_reset_n invalidate nodeOut.e.safe.widx_valid invalidate nodeOut.e.safe.ridx_valid invalidate nodeOut.e.widx invalidate nodeOut.e.ridx invalidate nodeOut.e.mem[0].sink invalidate nodeOut.d.safe.sink_reset_n invalidate nodeOut.d.safe.source_reset_n invalidate nodeOut.d.safe.widx_valid invalidate nodeOut.d.safe.ridx_valid invalidate nodeOut.d.widx invalidate nodeOut.d.ridx invalidate nodeOut.d.mem[0].corrupt invalidate nodeOut.d.mem[0].data invalidate nodeOut.d.mem[0].denied invalidate nodeOut.d.mem[0].sink invalidate nodeOut.d.mem[0].source invalidate nodeOut.d.mem[0].size invalidate nodeOut.d.mem[0].param invalidate nodeOut.d.mem[0].opcode invalidate nodeOut.c.safe.sink_reset_n invalidate nodeOut.c.safe.source_reset_n invalidate nodeOut.c.safe.widx_valid invalidate nodeOut.c.safe.ridx_valid invalidate nodeOut.c.widx invalidate nodeOut.c.ridx invalidate nodeOut.c.mem[0].corrupt invalidate nodeOut.c.mem[0].data invalidate nodeOut.c.mem[0].address invalidate nodeOut.c.mem[0].source invalidate nodeOut.c.mem[0].size invalidate nodeOut.c.mem[0].param invalidate nodeOut.c.mem[0].opcode invalidate nodeOut.b.safe.sink_reset_n invalidate nodeOut.b.safe.source_reset_n invalidate nodeOut.b.safe.widx_valid invalidate nodeOut.b.safe.ridx_valid invalidate nodeOut.b.widx invalidate nodeOut.b.ridx invalidate nodeOut.b.mem[0].corrupt invalidate nodeOut.b.mem[0].data invalidate nodeOut.b.mem[0].mask invalidate nodeOut.b.mem[0].address invalidate nodeOut.b.mem[0].source invalidate nodeOut.b.mem[0].size invalidate nodeOut.b.mem[0].param invalidate nodeOut.b.mem[0].opcode invalidate nodeOut.a.safe.sink_reset_n invalidate nodeOut.a.safe.source_reset_n invalidate nodeOut.a.safe.widx_valid invalidate nodeOut.a.safe.ridx_valid invalidate nodeOut.a.widx invalidate nodeOut.a.ridx invalidate nodeOut.a.mem[0].corrupt invalidate nodeOut.a.mem[0].data invalidate nodeOut.a.mem[0].mask invalidate nodeOut.a.mem[0].address invalidate nodeOut.a.mem[0].source invalidate nodeOut.a.mem[0].size invalidate nodeOut.a.mem[0].param invalidate nodeOut.a.mem[0].opcode connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_source of AsyncQueueSource_TLBundleA_a9d32s1k1z2u connect nodeOut_a_source.clock, clock connect nodeOut_a_source.reset, reset connect nodeOut_a_source.io.enq, nodeIn.a connect nodeOut_a_source.io.async.safe.sink_reset_n, nodeOut.a.safe.sink_reset_n connect nodeOut.a.safe.source_reset_n, nodeOut_a_source.io.async.safe.source_reset_n connect nodeOut.a.safe.widx_valid, nodeOut_a_source.io.async.safe.widx_valid connect nodeOut_a_source.io.async.safe.ridx_valid, nodeOut.a.safe.ridx_valid connect nodeOut.a.widx, nodeOut_a_source.io.async.widx connect nodeOut_a_source.io.async.ridx, nodeOut.a.ridx connect nodeOut.a.mem, nodeOut_a_source.io.async.mem inst nodeIn_d_sink of AsyncQueueSink_TLBundleD_a9d32s1k1z2u connect nodeIn_d_sink.clock, clock connect nodeIn_d_sink.reset, reset connect nodeIn_d_sink.io.async, nodeOut.d connect nodeIn.d.bits, nodeIn_d_sink.io.deq.bits connect nodeIn.d.valid, nodeIn_d_sink.io.deq.valid connect nodeIn_d_sink.io.deq.ready, nodeIn.d.ready node _T = and(nodeIn.a.valid, nodeIn.a.ready) node _T_1 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_2 = and(nodeIn.a.valid, _T_1) node _T_3 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_4 = and(_T_3, nodeIn.a.ready) node _T_5 = eq(nodeIn.a.valid, UInt<1>(0h0)) node _T_6 = eq(nodeIn.a.ready, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) node _T_8 = and(nodeIn.d.valid, nodeIn.d.ready) node _T_9 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_10 = and(nodeIn.d.valid, _T_9) node _T_11 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_12 = and(_T_11, nodeIn.d.ready) node _T_13 = eq(nodeIn.d.valid, UInt<1>(0h0)) node _T_14 = eq(nodeIn.d.ready, UInt<1>(0h0)) node _T_15 = and(_T_13, _T_14) wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<9>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<9>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) connect nodeOut.b.ridx, UInt<1>(0h0) connect nodeOut.c.widx, UInt<1>(0h0) connect nodeOut.e.widx, UInt<1>(0h0)
module TLAsyncCrossingSource_a9d32s1k1z2u( // @[AsyncCrossing.scala:23:9] input clock, // @[AsyncCrossing.scala:23:9] input reset, // @[AsyncCrossing.scala:23:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [8:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_mem_0_opcode, // @[LazyModuleImp.scala:107:25] output [8:0] auto_out_a_mem_0_address, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_mem_0_data, // @[LazyModuleImp.scala:107:25] input auto_out_a_ridx, // @[LazyModuleImp.scala:107:25] output auto_out_a_widx, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_widx_valid, // @[LazyModuleImp.scala:107:25] output auto_out_a_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] input auto_out_a_safe_sink_reset_n, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_mem_0_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_mem_0_size, // @[LazyModuleImp.scala:107:25] input auto_out_d_mem_0_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_d_mem_0_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ridx, // @[LazyModuleImp.scala:107:25] input auto_out_d_widx, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_ridx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_widx_valid, // @[LazyModuleImp.scala:107:25] input auto_out_d_safe_source_reset_n, // @[LazyModuleImp.scala:107:25] output auto_out_d_safe_sink_reset_n // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[AsyncCrossing.scala:23:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[AsyncCrossing.scala:23:9] wire auto_out_a_ridx_0 = auto_out_a_ridx; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_ridx_valid_0 = auto_out_a_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_sink_reset_n_0 = auto_out_a_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_d_mem_0_opcode_0 = auto_out_d_mem_0_opcode; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_size_0 = auto_out_d_mem_0_size; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_source_0 = auto_out_d_mem_0_source; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_d_mem_0_data_0 = auto_out_d_mem_0_data; // @[AsyncCrossing.scala:23:9] wire auto_out_d_widx_0 = auto_out_d_widx; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_widx_valid_0 = auto_out_d_safe_widx_valid; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_source_reset_n_0 = auto_out_d_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_b_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_c_mem_0_data = 32'h0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_b_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_c_mem_0_data = 32'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_out_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeOut_b_mem_0_mask = 4'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_b_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_c_mem_0_address = 9'h0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeOut_b_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_c_mem_0_address = 9'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_out_b_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_b_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_c_mem_0_size = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_d_mem_0_param = 2'h0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_b_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_b_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_c_mem_0_size = 2'h0; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_d_mem_0_param = 2'h0; // @[MixedNode.scala:542:17] wire [3:0] auto_in_a_bits_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] auto_out_a_mem_0_mask = 4'hF; // @[AsyncCrossing.scala:23:9] wire [3:0] nodeIn_a_bits_mask = 4'hF; // @[MixedNode.scala:551:17] wire [3:0] nodeOut_a_mem_0_mask = 4'hF; // @[MixedNode.scala:542:17] wire auto_in_a_bits_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_in_a_bits_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_b_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_source = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_c_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_denied = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_mem_0_corrupt = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_mem_0_sink = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_ridx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_widx = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_ridx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_widx_valid = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_source_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire auto_out_e_safe_sink_reset_n = 1'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_bits_source = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeOut_a_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_a_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_b_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_source = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_c_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_denied = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_d_mem_0_corrupt = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_mem_0_sink = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_ridx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_widx = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_ridx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_widx_valid = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_source_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire nodeOut_e_safe_sink_reset_n = 1'h0; // @[MixedNode.scala:542:17] wire [1:0] auto_in_a_bits_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_out_a_mem_0_size = 2'h2; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeIn_a_bits_size = 2'h2; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_a_mem_0_size = 2'h2; // @[MixedNode.scala:542:17] wire [2:0] auto_in_a_bits_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_b_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_opcode = 3'h0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_c_mem_0_param = 3'h0; // @[AsyncCrossing.scala:23:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_a_bits_param = 3'h0; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_b_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_opcode = 3'h0; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_c_mem_0_param = 3'h0; // @[MixedNode.scala:542:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[AsyncCrossing.scala:23:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire [2:0] nodeOut_a_mem_0_opcode; // @[MixedNode.scala:542:17] wire [8:0] nodeOut_a_mem_0_address; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_mem_0_data; // @[MixedNode.scala:542:17] wire nodeOut_a_ridx = auto_out_a_ridx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_widx; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_ridx_valid = auto_out_a_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_a_safe_widx_valid; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_source_reset_n; // @[MixedNode.scala:542:17] wire nodeOut_a_safe_sink_reset_n = auto_out_a_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire [2:0] nodeOut_d_mem_0_opcode = auto_out_d_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] nodeOut_d_mem_0_size = auto_out_d_mem_0_size_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_mem_0_source = auto_out_d_mem_0_source_0; // @[AsyncCrossing.scala:23:9] wire [31:0] nodeOut_d_mem_0_data = auto_out_d_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_ridx; // @[MixedNode.scala:542:17] wire nodeOut_d_widx = auto_out_d_widx_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_ridx_valid; // @[MixedNode.scala:542:17] wire nodeOut_d_safe_widx_valid = auto_out_d_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_source_reset_n = auto_out_d_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire nodeOut_d_safe_sink_reset_n; // @[MixedNode.scala:542:17] wire auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] wire [1:0] auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] wire auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] wire [2:0] auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] wire [8:0] auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] wire [31:0] auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] wire auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode_0 = nodeOut_a_mem_0_opcode; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address_0 = nodeOut_a_mem_0_address; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data_0 = nodeOut_a_mem_0_data; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx_0 = nodeOut_a_widx; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid_0 = nodeOut_a_safe_widx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n_0 = nodeOut_a_safe_source_reset_n; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx_0 = nodeOut_d_ridx; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid_0 = nodeOut_d_safe_ridx_valid; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n_0 = nodeOut_d_safe_sink_reset_n; // @[AsyncCrossing.scala:23:9] TLMonitor_61 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] AsyncQueueSource_TLBundleA_a9d32s1k1z2u nodeOut_a_source ( // @[AsyncQueue.scala:220:24] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_async_mem_0_opcode (nodeOut_a_mem_0_opcode), .io_async_mem_0_address (nodeOut_a_mem_0_address), .io_async_mem_0_data (nodeOut_a_mem_0_data), .io_async_ridx (nodeOut_a_ridx), // @[MixedNode.scala:542:17] .io_async_widx (nodeOut_a_widx), .io_async_safe_ridx_valid (nodeOut_a_safe_ridx_valid), // @[MixedNode.scala:542:17] .io_async_safe_widx_valid (nodeOut_a_safe_widx_valid), .io_async_safe_source_reset_n (nodeOut_a_safe_source_reset_n), .io_async_safe_sink_reset_n (nodeOut_a_safe_sink_reset_n) // @[MixedNode.scala:542:17] ); // @[AsyncQueue.scala:220:24] AsyncQueueSink_TLBundleD_a9d32s1k1z2u nodeIn_d_sink ( // @[AsyncQueue.scala:211:22] .clock (clock), .reset (reset), .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt), .io_async_mem_0_opcode (nodeOut_d_mem_0_opcode), // @[MixedNode.scala:542:17] .io_async_mem_0_size (nodeOut_d_mem_0_size), // @[MixedNode.scala:542:17] .io_async_mem_0_source (nodeOut_d_mem_0_source), // @[MixedNode.scala:542:17] .io_async_mem_0_data (nodeOut_d_mem_0_data), // @[MixedNode.scala:542:17] .io_async_ridx (nodeOut_d_ridx), .io_async_widx (nodeOut_d_widx), // @[MixedNode.scala:542:17] .io_async_safe_ridx_valid (nodeOut_d_safe_ridx_valid), .io_async_safe_widx_valid (nodeOut_d_safe_widx_valid), // @[MixedNode.scala:542:17] .io_async_safe_source_reset_n (nodeOut_d_safe_source_reset_n), // @[MixedNode.scala:542:17] .io_async_safe_sink_reset_n (nodeOut_d_safe_sink_reset_n) ); // @[AsyncQueue.scala:211:22] assign auto_in_a_ready = auto_in_a_ready_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[AsyncCrossing.scala:23:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_opcode = auto_out_a_mem_0_opcode_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_address = auto_out_a_mem_0_address_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_mem_0_data = auto_out_a_mem_0_data_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_widx = auto_out_a_widx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_widx_valid = auto_out_a_safe_widx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_a_safe_source_reset_n = auto_out_a_safe_source_reset_n_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_ridx = auto_out_d_ridx_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_ridx_valid = auto_out_d_safe_ridx_valid_0; // @[AsyncCrossing.scala:23:9] assign auto_out_d_safe_sink_reset_n = auto_out_d_safe_sink_reset_n_0; // @[AsyncCrossing.scala:23:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_32 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_32 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h9), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h6), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h5), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0ha), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h22), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_16 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h20), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_17 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0h1e), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_18 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0h1c), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_19 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h24), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_20 = or(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_21 = or(_q_io_enq_bits_ingress_id_T_20, _q_io_enq_bits_ingress_id_T_17) node _q_io_enq_bits_ingress_id_T_22 = or(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_18) node _q_io_enq_bits_ingress_id_T_23 = or(_q_io_enq_bits_ingress_id_T_22, _q_io_enq_bits_ingress_id_T_19) wire _q_io_enq_bits_ingress_id_WIRE : UInt<6> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_23 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_32( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_13 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_85 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_85( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_59 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_83 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_59( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_83 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_40 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h2)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_T_6 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _source_ok_T_7 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE : UInt<1>[3] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_7 node _source_ok_T_8 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node source_ok = or(_source_ok_T_8, _source_ok_WIRE[2]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h2)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _T_25 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_26 = eq(_T_25, UInt<1>(0h0)) node _T_27 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_28 = cvt(_T_27) node _T_29 = and(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = asSInt(_T_29) node _T_31 = eq(_T_30, asSInt(UInt<1>(0h0))) node _T_32 = or(_T_26, _T_31) node _T_33 = and(_T_16, _T_24) node _T_34 = and(_T_33, _T_32) node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : node _T_37 = eq(_T_34, UInt<1>(0h0)) when _T_37 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_34, UInt<1>(0h1), "") : assert_1 node _T_38 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_38 : node _T_39 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_40 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_41 = and(_T_39, _T_40) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_42 = shr(io.in.a.bits.source, 2) node _T_43 = eq(_T_42, UInt<1>(0h0)) node _T_44 = leq(UInt<1>(0h0), uncommonBits_1) node _T_45 = and(_T_43, _T_44) node _T_46 = leq(uncommonBits_1, UInt<2>(0h2)) node _T_47 = and(_T_45, _T_46) node _T_48 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_49 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_50 = or(_T_47, _T_48) node _T_51 = or(_T_50, _T_49) node _T_52 = and(_T_41, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_55 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_56 = cvt(_T_55) node _T_57 = and(_T_56, asSInt(UInt<14>(0h2000))) node _T_58 = asSInt(_T_57) node _T_59 = eq(_T_58, asSInt(UInt<1>(0h0))) node _T_60 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_61 = cvt(_T_60) node _T_62 = and(_T_61, asSInt(UInt<13>(0h1000))) node _T_63 = asSInt(_T_62) node _T_64 = eq(_T_63, asSInt(UInt<1>(0h0))) node _T_65 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_66 = cvt(_T_65) node _T_67 = and(_T_66, asSInt(UInt<17>(0h10000))) node _T_68 = asSInt(_T_67) node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0))) node _T_70 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_71 = cvt(_T_70) node _T_72 = and(_T_71, asSInt(UInt<18>(0h2f000))) node _T_73 = asSInt(_T_72) node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0))) node _T_75 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_76 = cvt(_T_75) node _T_77 = and(_T_76, asSInt(UInt<17>(0h10000))) node _T_78 = asSInt(_T_77) node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0))) node _T_80 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<13>(0h1000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<27>(0h4000000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<13>(0h1000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_59, _T_64) node _T_96 = or(_T_95, _T_69) node _T_97 = or(_T_96, _T_74) node _T_98 = or(_T_97, _T_79) node _T_99 = or(_T_98, _T_84) node _T_100 = or(_T_99, _T_89) node _T_101 = or(_T_100, _T_94) node _T_102 = and(_T_54, _T_101) node _T_103 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_104 = or(UInt<1>(0h0), _T_103) node _T_105 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = or(_T_109, _T_114) node _T_116 = and(_T_104, _T_115) node _T_117 = or(UInt<1>(0h0), _T_102) node _T_118 = or(_T_117, _T_116) node _T_119 = and(_T_53, _T_118) node _T_120 = asUInt(reset) node _T_121 = eq(_T_120, UInt<1>(0h0)) when _T_121 : node _T_122 = eq(_T_119, UInt<1>(0h0)) when _T_122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_119, UInt<1>(0h1), "") : assert_2 node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_2) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_2, UInt<2>(0h2)) node _T_128 = and(_T_126, _T_127) node _T_129 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_130 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _WIRE : UInt<1>[3] connect _WIRE[0], _T_128 connect _WIRE[1], _T_129 connect _WIRE[2], _T_130 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = mux(_WIRE[0], _T_131, UInt<1>(0h0)) node _T_133 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_134 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_135 = or(_T_132, _T_133) node _T_136 = or(_T_135, _T_134) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_136 node _T_137 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_138 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_139 = and(_T_137, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<14>(0h2000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<13>(0h1000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<17>(0h10000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<18>(0h2f000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<17>(0h10000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<17>(0h10000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<27>(0h4000000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<29>(0h10000000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_145, _T_150) node _T_192 = or(_T_191, _T_155) node _T_193 = or(_T_192, _T_160) node _T_194 = or(_T_193, _T_165) node _T_195 = or(_T_194, _T_170) node _T_196 = or(_T_195, _T_175) node _T_197 = or(_T_196, _T_180) node _T_198 = or(_T_197, _T_185) node _T_199 = or(_T_198, _T_190) node _T_200 = and(_T_140, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = and(_WIRE_1, _T_201) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_202, UInt<1>(0h1), "") : assert_3 node _T_206 = asUInt(reset) node _T_207 = eq(_T_206, UInt<1>(0h0)) when _T_207 : node _T_208 = eq(source_ok, UInt<1>(0h0)) when _T_208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_209 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_210 = asUInt(reset) node _T_211 = eq(_T_210, UInt<1>(0h0)) when _T_211 : node _T_212 = eq(_T_209, UInt<1>(0h0)) when _T_212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_209, UInt<1>(0h1), "") : assert_5 node _T_213 = asUInt(reset) node _T_214 = eq(_T_213, UInt<1>(0h0)) when _T_214 : node _T_215 = eq(is_aligned, UInt<1>(0h0)) when _T_215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_216 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_217 = asUInt(reset) node _T_218 = eq(_T_217, UInt<1>(0h0)) when _T_218 : node _T_219 = eq(_T_216, UInt<1>(0h0)) when _T_219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_216, UInt<1>(0h1), "") : assert_7 node _T_220 = not(io.in.a.bits.mask) node _T_221 = eq(_T_220, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_221, UInt<1>(0h1), "") : assert_8 node _T_225 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_225, UInt<1>(0h1), "") : assert_9 node _T_229 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_229 : node _T_230 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_231 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_232 = and(_T_230, _T_231) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_233 = shr(io.in.a.bits.source, 2) node _T_234 = eq(_T_233, UInt<1>(0h0)) node _T_235 = leq(UInt<1>(0h0), uncommonBits_3) node _T_236 = and(_T_234, _T_235) node _T_237 = leq(uncommonBits_3, UInt<2>(0h2)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_240 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_241 = or(_T_238, _T_239) node _T_242 = or(_T_241, _T_240) node _T_243 = and(_T_232, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_246 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<14>(0h2000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_252 = cvt(_T_251) node _T_253 = and(_T_252, asSInt(UInt<13>(0h1000))) node _T_254 = asSInt(_T_253) node _T_255 = eq(_T_254, asSInt(UInt<1>(0h0))) node _T_256 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_257 = cvt(_T_256) node _T_258 = and(_T_257, asSInt(UInt<17>(0h10000))) node _T_259 = asSInt(_T_258) node _T_260 = eq(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_262 = cvt(_T_261) node _T_263 = and(_T_262, asSInt(UInt<18>(0h2f000))) node _T_264 = asSInt(_T_263) node _T_265 = eq(_T_264, asSInt(UInt<1>(0h0))) node _T_266 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_267 = cvt(_T_266) node _T_268 = and(_T_267, asSInt(UInt<17>(0h10000))) node _T_269 = asSInt(_T_268) node _T_270 = eq(_T_269, asSInt(UInt<1>(0h0))) node _T_271 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_272 = cvt(_T_271) node _T_273 = and(_T_272, asSInt(UInt<13>(0h1000))) node _T_274 = asSInt(_T_273) node _T_275 = eq(_T_274, asSInt(UInt<1>(0h0))) node _T_276 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_277 = cvt(_T_276) node _T_278 = and(_T_277, asSInt(UInt<27>(0h4000000))) node _T_279 = asSInt(_T_278) node _T_280 = eq(_T_279, asSInt(UInt<1>(0h0))) node _T_281 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_282 = cvt(_T_281) node _T_283 = and(_T_282, asSInt(UInt<13>(0h1000))) node _T_284 = asSInt(_T_283) node _T_285 = eq(_T_284, asSInt(UInt<1>(0h0))) node _T_286 = or(_T_250, _T_255) node _T_287 = or(_T_286, _T_260) node _T_288 = or(_T_287, _T_265) node _T_289 = or(_T_288, _T_270) node _T_290 = or(_T_289, _T_275) node _T_291 = or(_T_290, _T_280) node _T_292 = or(_T_291, _T_285) node _T_293 = and(_T_245, _T_292) node _T_294 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_293) node _T_309 = or(_T_308, _T_307) node _T_310 = and(_T_244, _T_309) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_310, UInt<1>(0h1), "") : assert_10 node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_314 = shr(io.in.a.bits.source, 2) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = leq(UInt<1>(0h0), uncommonBits_4) node _T_317 = and(_T_315, _T_316) node _T_318 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_319 = and(_T_317, _T_318) node _T_320 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_321 = eq(io.in.a.bits.source, UInt<3>(0h4)) wire _WIRE_2 : UInt<1>[3] connect _WIRE_2[0], _T_319 connect _WIRE_2[1], _T_320 connect _WIRE_2[2], _T_321 node _T_322 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_323 = mux(_WIRE_2[0], _T_322, UInt<1>(0h0)) node _T_324 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_325 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_326 = or(_T_323, _T_324) node _T_327 = or(_T_326, _T_325) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_327 node _T_328 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_329 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_333 = cvt(_T_332) node _T_334 = and(_T_333, asSInt(UInt<14>(0h2000))) node _T_335 = asSInt(_T_334) node _T_336 = eq(_T_335, asSInt(UInt<1>(0h0))) node _T_337 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_338 = cvt(_T_337) node _T_339 = and(_T_338, asSInt(UInt<13>(0h1000))) node _T_340 = asSInt(_T_339) node _T_341 = eq(_T_340, asSInt(UInt<1>(0h0))) node _T_342 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<18>(0h2f000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_353 = cvt(_T_352) node _T_354 = and(_T_353, asSInt(UInt<17>(0h10000))) node _T_355 = asSInt(_T_354) node _T_356 = eq(_T_355, asSInt(UInt<1>(0h0))) node _T_357 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_358 = cvt(_T_357) node _T_359 = and(_T_358, asSInt(UInt<13>(0h1000))) node _T_360 = asSInt(_T_359) node _T_361 = eq(_T_360, asSInt(UInt<1>(0h0))) node _T_362 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<17>(0h10000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<27>(0h4000000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<29>(0h10000000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = or(_T_336, _T_341) node _T_383 = or(_T_382, _T_346) node _T_384 = or(_T_383, _T_351) node _T_385 = or(_T_384, _T_356) node _T_386 = or(_T_385, _T_361) node _T_387 = or(_T_386, _T_366) node _T_388 = or(_T_387, _T_371) node _T_389 = or(_T_388, _T_376) node _T_390 = or(_T_389, _T_381) node _T_391 = and(_T_331, _T_390) node _T_392 = or(UInt<1>(0h0), _T_391) node _T_393 = and(_WIRE_3, _T_392) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_393, UInt<1>(0h1), "") : assert_11 node _T_397 = asUInt(reset) node _T_398 = eq(_T_397, UInt<1>(0h0)) when _T_398 : node _T_399 = eq(source_ok, UInt<1>(0h0)) when _T_399 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_400 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_401 = asUInt(reset) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(_T_400, UInt<1>(0h0)) when _T_403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_400, UInt<1>(0h1), "") : assert_13 node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(is_aligned, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_407 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(_T_407, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_407, UInt<1>(0h1), "") : assert_15 node _T_411 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_411, UInt<1>(0h1), "") : assert_16 node _T_415 = not(io.in.a.bits.mask) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_416, UInt<1>(0h1), "") : assert_17 node _T_420 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_T_420, UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_420, UInt<1>(0h1), "") : assert_18 node _T_424 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_424 : node _T_425 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_426 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_427 = and(_T_425, _T_426) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_428 = shr(io.in.a.bits.source, 2) node _T_429 = eq(_T_428, UInt<1>(0h0)) node _T_430 = leq(UInt<1>(0h0), uncommonBits_5) node _T_431 = and(_T_429, _T_430) node _T_432 = leq(uncommonBits_5, UInt<2>(0h2)) node _T_433 = and(_T_431, _T_432) node _T_434 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_435 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_436 = or(_T_433, _T_434) node _T_437 = or(_T_436, _T_435) node _T_438 = and(_T_427, _T_437) node _T_439 = or(UInt<1>(0h0), _T_438) node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(_T_439, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_439, UInt<1>(0h1), "") : assert_19 node _T_443 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_444 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_445 = and(_T_443, _T_444) node _T_446 = or(UInt<1>(0h0), _T_445) node _T_447 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<13>(0h1000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = and(_T_446, _T_451) node _T_453 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_454 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_455 = and(_T_453, _T_454) node _T_456 = or(UInt<1>(0h0), _T_455) node _T_457 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<14>(0h2000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<18>(0h2f000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<13>(0h1000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<17>(0h10000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<27>(0h4000000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<29>(0h10000000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = or(_T_461, _T_466) node _T_503 = or(_T_502, _T_471) node _T_504 = or(_T_503, _T_476) node _T_505 = or(_T_504, _T_481) node _T_506 = or(_T_505, _T_486) node _T_507 = or(_T_506, _T_491) node _T_508 = or(_T_507, _T_496) node _T_509 = or(_T_508, _T_501) node _T_510 = and(_T_456, _T_509) node _T_511 = or(UInt<1>(0h0), _T_452) node _T_512 = or(_T_511, _T_510) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_512, UInt<1>(0h1), "") : assert_20 node _T_516 = asUInt(reset) node _T_517 = eq(_T_516, UInt<1>(0h0)) when _T_517 : node _T_518 = eq(source_ok, UInt<1>(0h0)) when _T_518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(is_aligned, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_522 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_522, UInt<1>(0h1), "") : assert_23 node _T_526 = eq(io.in.a.bits.mask, mask) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_526, UInt<1>(0h1), "") : assert_24 node _T_530 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_530, UInt<1>(0h1), "") : assert_25 node _T_534 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_534 : node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_537 = and(_T_535, _T_536) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_538 = shr(io.in.a.bits.source, 2) node _T_539 = eq(_T_538, UInt<1>(0h0)) node _T_540 = leq(UInt<1>(0h0), uncommonBits_6) node _T_541 = and(_T_539, _T_540) node _T_542 = leq(uncommonBits_6, UInt<2>(0h2)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_545 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_546 = or(_T_543, _T_544) node _T_547 = or(_T_546, _T_545) node _T_548 = and(_T_537, _T_547) node _T_549 = or(UInt<1>(0h0), _T_548) node _T_550 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_551 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_552 = and(_T_550, _T_551) node _T_553 = or(UInt<1>(0h0), _T_552) node _T_554 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = and(_T_553, _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<14>(0h2000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<18>(0h2f000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<27>(0h4000000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<13>(0h1000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<29>(0h10000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = or(_T_568, _T_573) node _T_605 = or(_T_604, _T_578) node _T_606 = or(_T_605, _T_583) node _T_607 = or(_T_606, _T_588) node _T_608 = or(_T_607, _T_593) node _T_609 = or(_T_608, _T_598) node _T_610 = or(_T_609, _T_603) node _T_611 = and(_T_563, _T_610) node _T_612 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_613 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<17>(0h10000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_559) node _T_620 = or(_T_619, _T_611) node _T_621 = or(_T_620, _T_618) node _T_622 = and(_T_549, _T_621) node _T_623 = asUInt(reset) node _T_624 = eq(_T_623, UInt<1>(0h0)) when _T_624 : node _T_625 = eq(_T_622, UInt<1>(0h0)) when _T_625 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_622, UInt<1>(0h1), "") : assert_26 node _T_626 = asUInt(reset) node _T_627 = eq(_T_626, UInt<1>(0h0)) when _T_627 : node _T_628 = eq(source_ok, UInt<1>(0h0)) when _T_628 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_629 = asUInt(reset) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(is_aligned, UInt<1>(0h0)) when _T_631 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_632 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_632, UInt<1>(0h1), "") : assert_29 node _T_636 = eq(io.in.a.bits.mask, mask) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_636, UInt<1>(0h1), "") : assert_30 node _T_640 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_644 = shr(io.in.a.bits.source, 2) node _T_645 = eq(_T_644, UInt<1>(0h0)) node _T_646 = leq(UInt<1>(0h0), uncommonBits_7) node _T_647 = and(_T_645, _T_646) node _T_648 = leq(uncommonBits_7, UInt<2>(0h2)) node _T_649 = and(_T_647, _T_648) node _T_650 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_651 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_652 = or(_T_649, _T_650) node _T_653 = or(_T_652, _T_651) node _T_654 = and(_T_643, _T_653) node _T_655 = or(UInt<1>(0h0), _T_654) node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = and(_T_659, _T_664) node _T_666 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_667 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_668 = and(_T_666, _T_667) node _T_669 = or(UInt<1>(0h0), _T_668) node _T_670 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<14>(0h2000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<18>(0h2f000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<17>(0h10000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_686 = cvt(_T_685) node _T_687 = and(_T_686, asSInt(UInt<13>(0h1000))) node _T_688 = asSInt(_T_687) node _T_689 = eq(_T_688, asSInt(UInt<1>(0h0))) node _T_690 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_691 = cvt(_T_690) node _T_692 = and(_T_691, asSInt(UInt<17>(0h10000))) node _T_693 = asSInt(_T_692) node _T_694 = eq(_T_693, asSInt(UInt<1>(0h0))) node _T_695 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_696 = cvt(_T_695) node _T_697 = and(_T_696, asSInt(UInt<27>(0h4000000))) node _T_698 = asSInt(_T_697) node _T_699 = eq(_T_698, asSInt(UInt<1>(0h0))) node _T_700 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_701 = cvt(_T_700) node _T_702 = and(_T_701, asSInt(UInt<13>(0h1000))) node _T_703 = asSInt(_T_702) node _T_704 = eq(_T_703, asSInt(UInt<1>(0h0))) node _T_705 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_706 = cvt(_T_705) node _T_707 = and(_T_706, asSInt(UInt<29>(0h10000000))) node _T_708 = asSInt(_T_707) node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0))) node _T_710 = or(_T_674, _T_679) node _T_711 = or(_T_710, _T_684) node _T_712 = or(_T_711, _T_689) node _T_713 = or(_T_712, _T_694) node _T_714 = or(_T_713, _T_699) node _T_715 = or(_T_714, _T_704) node _T_716 = or(_T_715, _T_709) node _T_717 = and(_T_669, _T_716) node _T_718 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_719 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_720 = cvt(_T_719) node _T_721 = and(_T_720, asSInt(UInt<17>(0h10000))) node _T_722 = asSInt(_T_721) node _T_723 = eq(_T_722, asSInt(UInt<1>(0h0))) node _T_724 = and(_T_718, _T_723) node _T_725 = or(UInt<1>(0h0), _T_665) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_724) node _T_728 = and(_T_655, _T_727) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_728, UInt<1>(0h1), "") : assert_31 node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(source_ok, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(is_aligned, UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_738 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_738, UInt<1>(0h1), "") : assert_34 node _T_742 = not(mask) node _T_743 = and(io.in.a.bits.mask, _T_742) node _T_744 = eq(_T_743, UInt<1>(0h0)) node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(_T_744, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_744, UInt<1>(0h1), "") : assert_35 node _T_748 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_748 : node _T_749 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_750 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_751 = and(_T_749, _T_750) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_752 = shr(io.in.a.bits.source, 2) node _T_753 = eq(_T_752, UInt<1>(0h0)) node _T_754 = leq(UInt<1>(0h0), uncommonBits_8) node _T_755 = and(_T_753, _T_754) node _T_756 = leq(uncommonBits_8, UInt<2>(0h2)) node _T_757 = and(_T_755, _T_756) node _T_758 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_759 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_760 = or(_T_757, _T_758) node _T_761 = or(_T_760, _T_759) node _T_762 = and(_T_751, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_765 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _T_767 = or(UInt<1>(0h0), _T_766) node _T_768 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_769 = cvt(_T_768) node _T_770 = and(_T_769, asSInt(UInt<14>(0h2000))) node _T_771 = asSInt(_T_770) node _T_772 = eq(_T_771, asSInt(UInt<1>(0h0))) node _T_773 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_774 = cvt(_T_773) node _T_775 = and(_T_774, asSInt(UInt<13>(0h1000))) node _T_776 = asSInt(_T_775) node _T_777 = eq(_T_776, asSInt(UInt<1>(0h0))) node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_779 = cvt(_T_778) node _T_780 = and(_T_779, asSInt(UInt<18>(0h2f000))) node _T_781 = asSInt(_T_780) node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0))) node _T_783 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_784 = cvt(_T_783) node _T_785 = and(_T_784, asSInt(UInt<17>(0h10000))) node _T_786 = asSInt(_T_785) node _T_787 = eq(_T_786, asSInt(UInt<1>(0h0))) node _T_788 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_789 = cvt(_T_788) node _T_790 = and(_T_789, asSInt(UInt<13>(0h1000))) node _T_791 = asSInt(_T_790) node _T_792 = eq(_T_791, asSInt(UInt<1>(0h0))) node _T_793 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_794 = cvt(_T_793) node _T_795 = and(_T_794, asSInt(UInt<17>(0h10000))) node _T_796 = asSInt(_T_795) node _T_797 = eq(_T_796, asSInt(UInt<1>(0h0))) node _T_798 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_799 = cvt(_T_798) node _T_800 = and(_T_799, asSInt(UInt<27>(0h4000000))) node _T_801 = asSInt(_T_800) node _T_802 = eq(_T_801, asSInt(UInt<1>(0h0))) node _T_803 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<13>(0h1000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_809 = cvt(_T_808) node _T_810 = and(_T_809, asSInt(UInt<29>(0h10000000))) node _T_811 = asSInt(_T_810) node _T_812 = eq(_T_811, asSInt(UInt<1>(0h0))) node _T_813 = or(_T_772, _T_777) node _T_814 = or(_T_813, _T_782) node _T_815 = or(_T_814, _T_787) node _T_816 = or(_T_815, _T_792) node _T_817 = or(_T_816, _T_797) node _T_818 = or(_T_817, _T_802) node _T_819 = or(_T_818, _T_807) node _T_820 = or(_T_819, _T_812) node _T_821 = and(_T_767, _T_820) node _T_822 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_823 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_824 = cvt(_T_823) node _T_825 = and(_T_824, asSInt(UInt<17>(0h10000))) node _T_826 = asSInt(_T_825) node _T_827 = eq(_T_826, asSInt(UInt<1>(0h0))) node _T_828 = and(_T_822, _T_827) node _T_829 = or(UInt<1>(0h0), _T_821) node _T_830 = or(_T_829, _T_828) node _T_831 = and(_T_763, _T_830) node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_T_831, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_831, UInt<1>(0h1), "") : assert_36 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(source_ok, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_838 = asUInt(reset) node _T_839 = eq(_T_838, UInt<1>(0h0)) when _T_839 : node _T_840 = eq(is_aligned, UInt<1>(0h0)) when _T_840 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_841 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(_T_841, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_841, UInt<1>(0h1), "") : assert_39 node _T_845 = eq(io.in.a.bits.mask, mask) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_845, UInt<1>(0h1), "") : assert_40 node _T_849 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_849 : node _T_850 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_851 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_852 = and(_T_850, _T_851) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_9) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_858 = and(_T_856, _T_857) node _T_859 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_860 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_861 = or(_T_858, _T_859) node _T_862 = or(_T_861, _T_860) node _T_863 = and(_T_852, _T_862) node _T_864 = or(UInt<1>(0h0), _T_863) node _T_865 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_866 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_867 = and(_T_865, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<14>(0h2000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<18>(0h2f000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<17>(0h10000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<13>(0h1000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_900 = cvt(_T_899) node _T_901 = and(_T_900, asSInt(UInt<27>(0h4000000))) node _T_902 = asSInt(_T_901) node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0))) node _T_904 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_905 = cvt(_T_904) node _T_906 = and(_T_905, asSInt(UInt<13>(0h1000))) node _T_907 = asSInt(_T_906) node _T_908 = eq(_T_907, asSInt(UInt<1>(0h0))) node _T_909 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<29>(0h10000000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = or(_T_873, _T_878) node _T_915 = or(_T_914, _T_883) node _T_916 = or(_T_915, _T_888) node _T_917 = or(_T_916, _T_893) node _T_918 = or(_T_917, _T_898) node _T_919 = or(_T_918, _T_903) node _T_920 = or(_T_919, _T_908) node _T_921 = or(_T_920, _T_913) node _T_922 = and(_T_868, _T_921) node _T_923 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_924 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<17>(0h10000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = and(_T_923, _T_928) node _T_930 = or(UInt<1>(0h0), _T_922) node _T_931 = or(_T_930, _T_929) node _T_932 = and(_T_864, _T_931) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_932, UInt<1>(0h1), "") : assert_41 node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(source_ok, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(is_aligned, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_942 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_942, UInt<1>(0h1), "") : assert_44 node _T_946 = eq(io.in.a.bits.mask, mask) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_946, UInt<1>(0h1), "") : assert_45 node _T_950 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_950 : node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_953 = and(_T_951, _T_952) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_954 = shr(io.in.a.bits.source, 2) node _T_955 = eq(_T_954, UInt<1>(0h0)) node _T_956 = leq(UInt<1>(0h0), uncommonBits_10) node _T_957 = and(_T_955, _T_956) node _T_958 = leq(uncommonBits_10, UInt<2>(0h2)) node _T_959 = and(_T_957, _T_958) node _T_960 = eq(io.in.a.bits.source, UInt<2>(0h3)) node _T_961 = eq(io.in.a.bits.source, UInt<3>(0h4)) node _T_962 = or(_T_959, _T_960) node _T_963 = or(_T_962, _T_961) node _T_964 = and(_T_953, _T_963) node _T_965 = or(UInt<1>(0h0), _T_964) node _T_966 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_967 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_968 = and(_T_966, _T_967) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_971 = cvt(_T_970) node _T_972 = and(_T_971, asSInt(UInt<13>(0h1000))) node _T_973 = asSInt(_T_972) node _T_974 = eq(_T_973, asSInt(UInt<1>(0h0))) node _T_975 = and(_T_969, _T_974) node _T_976 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_977 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<14>(0h2000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<17>(0h10000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<18>(0h2f000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<17>(0h10000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<13>(0h1000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<27>(0h4000000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = or(_T_981, _T_986) node _T_1013 = or(_T_1012, _T_991) node _T_1014 = or(_T_1013, _T_996) node _T_1015 = or(_T_1014, _T_1001) node _T_1016 = or(_T_1015, _T_1006) node _T_1017 = or(_T_1016, _T_1011) node _T_1018 = and(_T_976, _T_1017) node _T_1019 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1020 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1021 = and(_T_1019, _T_1020) node _T_1022 = or(UInt<1>(0h0), _T_1021) node _T_1023 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1024 = cvt(_T_1023) node _T_1025 = and(_T_1024, asSInt(UInt<17>(0h10000))) node _T_1026 = asSInt(_T_1025) node _T_1027 = eq(_T_1026, asSInt(UInt<1>(0h0))) node _T_1028 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1029 = cvt(_T_1028) node _T_1030 = and(_T_1029, asSInt(UInt<29>(0h10000000))) node _T_1031 = asSInt(_T_1030) node _T_1032 = eq(_T_1031, asSInt(UInt<1>(0h0))) node _T_1033 = or(_T_1027, _T_1032) node _T_1034 = and(_T_1022, _T_1033) node _T_1035 = or(UInt<1>(0h0), _T_975) node _T_1036 = or(_T_1035, _T_1018) node _T_1037 = or(_T_1036, _T_1034) node _T_1038 = and(_T_965, _T_1037) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_46 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(source_ok, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(is_aligned, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1048 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_49 node _T_1052 = eq(io.in.a.bits.mask, mask) node _T_1053 = asUInt(reset) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) when _T_1054 : node _T_1055 = eq(_T_1052, UInt<1>(0h0)) when _T_1055 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1052, UInt<1>(0h1), "") : assert_50 node _T_1056 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1060 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(_T_1060, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1060, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_9 = shr(io.in.d.bits.source, 2) node _source_ok_T_10 = eq(_source_ok_T_9, UInt<1>(0h0)) node _source_ok_T_11 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_T_13 = leq(source_ok_uncommonBits_1, UInt<2>(0h2)) node _source_ok_T_14 = and(_source_ok_T_12, _source_ok_T_13) node _source_ok_T_15 = eq(io.in.d.bits.source, UInt<2>(0h3)) node _source_ok_T_16 = eq(io.in.d.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE_1 : UInt<1>[3] connect _source_ok_WIRE_1[0], _source_ok_T_14 connect _source_ok_WIRE_1[1], _source_ok_T_15 connect _source_ok_WIRE_1[2], _source_ok_T_16 node _source_ok_T_17 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node source_ok_1 = or(_source_ok_T_17, _source_ok_WIRE_1[2]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1064 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1064 : node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(source_ok_1, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1068 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1069 = asUInt(reset) node _T_1070 = eq(_T_1069, UInt<1>(0h0)) when _T_1070 : node _T_1071 = eq(_T_1068, UInt<1>(0h0)) when _T_1071 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1068, UInt<1>(0h1), "") : assert_54 node _T_1072 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1073 = asUInt(reset) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(_T_1072, UInt<1>(0h0)) when _T_1075 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1072, UInt<1>(0h1), "") : assert_55 node _T_1076 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_56 node _T_1080 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_57 node _T_1084 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1084 : node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(source_ok_1, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(sink_ok, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1091 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_60 node _T_1095 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_61 node _T_1099 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_62 node _T_1103 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_63 node _T_1107 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1108 = or(UInt<1>(0h1), _T_1107) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_64 node _T_1112 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1112 : node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(source_ok_1, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(sink_ok, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1119 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_67 node _T_1123 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_68 node _T_1127 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1128 = asUInt(reset) node _T_1129 = eq(_T_1128, UInt<1>(0h0)) when _T_1129 : node _T_1130 = eq(_T_1127, UInt<1>(0h0)) when _T_1130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1127, UInt<1>(0h1), "") : assert_69 node _T_1131 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1132 = or(_T_1131, io.in.d.bits.corrupt) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_70 node _T_1136 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1137 = or(UInt<1>(0h1), _T_1136) node _T_1138 = asUInt(reset) node _T_1139 = eq(_T_1138, UInt<1>(0h0)) when _T_1139 : node _T_1140 = eq(_T_1137, UInt<1>(0h0)) when _T_1140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1137, UInt<1>(0h1), "") : assert_71 node _T_1141 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1141 : node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(source_ok_1, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1145 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_73 node _T_1149 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1150 = asUInt(reset) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) when _T_1151 : node _T_1152 = eq(_T_1149, UInt<1>(0h0)) when _T_1152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1149, UInt<1>(0h1), "") : assert_74 node _T_1153 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1154 = or(UInt<1>(0h1), _T_1153) node _T_1155 = asUInt(reset) node _T_1156 = eq(_T_1155, UInt<1>(0h0)) when _T_1156 : node _T_1157 = eq(_T_1154, UInt<1>(0h0)) when _T_1157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1154, UInt<1>(0h1), "") : assert_75 node _T_1158 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1158 : node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok_1, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1162 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1163 = asUInt(reset) node _T_1164 = eq(_T_1163, UInt<1>(0h0)) when _T_1164 : node _T_1165 = eq(_T_1162, UInt<1>(0h0)) when _T_1165 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1162, UInt<1>(0h1), "") : assert_77 node _T_1166 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1167 = or(_T_1166, io.in.d.bits.corrupt) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_78 node _T_1171 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1172 = or(UInt<1>(0h1), _T_1171) node _T_1173 = asUInt(reset) node _T_1174 = eq(_T_1173, UInt<1>(0h0)) when _T_1174 : node _T_1175 = eq(_T_1172, UInt<1>(0h0)) when _T_1175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1172, UInt<1>(0h1), "") : assert_79 node _T_1176 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1176 : node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(source_ok_1, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1180 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_81 node _T_1184 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_82 node _T_1188 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1189 = or(UInt<1>(0h1), _T_1188) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_1193 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_11 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_1197 = shr(io.in.b.bits.source, 2) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = leq(UInt<1>(0h0), uncommonBits_11) node _T_1200 = and(_T_1198, _T_1199) node _T_1201 = leq(uncommonBits_11, UInt<2>(0h2)) node _T_1202 = and(_T_1200, _T_1201) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) node _T_1204 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1205 = cvt(_T_1204) node _T_1206 = and(_T_1205, asSInt(UInt<1>(0h0))) node _T_1207 = asSInt(_T_1206) node _T_1208 = eq(_T_1207, asSInt(UInt<1>(0h0))) node _T_1209 = or(_T_1203, _T_1208) node _T_1210 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) node _T_1212 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1213 = cvt(_T_1212) node _T_1214 = and(_T_1213, asSInt(UInt<1>(0h0))) node _T_1215 = asSInt(_T_1214) node _T_1216 = eq(_T_1215, asSInt(UInt<1>(0h0))) node _T_1217 = or(_T_1211, _T_1216) node _T_1218 = eq(io.in.b.bits.source, UInt<3>(0h4)) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) node _T_1220 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1221 = cvt(_T_1220) node _T_1222 = and(_T_1221, asSInt(UInt<1>(0h0))) node _T_1223 = asSInt(_T_1222) node _T_1224 = eq(_T_1223, asSInt(UInt<1>(0h0))) node _T_1225 = or(_T_1219, _T_1224) node _T_1226 = and(_T_1209, _T_1217) node _T_1227 = and(_T_1226, _T_1225) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<1>(0h0)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<13>(0h1000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<13>(0h1000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<13>(0h1000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) node _address_ok_T_10 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<13>(0h1000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<17>(0h10000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) node _address_ok_T_20 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _address_ok_T_21 = cvt(_address_ok_T_20) node _address_ok_T_22 = and(_address_ok_T_21, asSInt(UInt<13>(0h1000))) node _address_ok_T_23 = asSInt(_address_ok_T_22) node _address_ok_T_24 = eq(_address_ok_T_23, asSInt(UInt<1>(0h0))) node _address_ok_T_25 = xor(io.in.b.bits.address, UInt<21>(0h110000)) node _address_ok_T_26 = cvt(_address_ok_T_25) node _address_ok_T_27 = and(_address_ok_T_26, asSInt(UInt<13>(0h1000))) node _address_ok_T_28 = asSInt(_address_ok_T_27) node _address_ok_T_29 = eq(_address_ok_T_28, asSInt(UInt<1>(0h0))) node _address_ok_T_30 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _address_ok_T_31 = cvt(_address_ok_T_30) node _address_ok_T_32 = and(_address_ok_T_31, asSInt(UInt<17>(0h10000))) node _address_ok_T_33 = asSInt(_address_ok_T_32) node _address_ok_T_34 = eq(_address_ok_T_33, asSInt(UInt<1>(0h0))) node _address_ok_T_35 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _address_ok_T_36 = cvt(_address_ok_T_35) node _address_ok_T_37 = and(_address_ok_T_36, asSInt(UInt<13>(0h1000))) node _address_ok_T_38 = asSInt(_address_ok_T_37) node _address_ok_T_39 = eq(_address_ok_T_38, asSInt(UInt<1>(0h0))) node _address_ok_T_40 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_41 = cvt(_address_ok_T_40) node _address_ok_T_42 = and(_address_ok_T_41, asSInt(UInt<17>(0h10000))) node _address_ok_T_43 = asSInt(_address_ok_T_42) node _address_ok_T_44 = eq(_address_ok_T_43, asSInt(UInt<1>(0h0))) node _address_ok_T_45 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _address_ok_T_46 = cvt(_address_ok_T_45) node _address_ok_T_47 = and(_address_ok_T_46, asSInt(UInt<27>(0h4000000))) node _address_ok_T_48 = asSInt(_address_ok_T_47) node _address_ok_T_49 = eq(_address_ok_T_48, asSInt(UInt<1>(0h0))) node _address_ok_T_50 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _address_ok_T_51 = cvt(_address_ok_T_50) node _address_ok_T_52 = and(_address_ok_T_51, asSInt(UInt<13>(0h1000))) node _address_ok_T_53 = asSInt(_address_ok_T_52) node _address_ok_T_54 = eq(_address_ok_T_53, asSInt(UInt<1>(0h0))) node _address_ok_T_55 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_56 = cvt(_address_ok_T_55) node _address_ok_T_57 = and(_address_ok_T_56, asSInt(UInt<29>(0h10000000))) node _address_ok_T_58 = asSInt(_address_ok_T_57) node _address_ok_T_59 = eq(_address_ok_T_58, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[12] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 connect _address_ok_WIRE[2], _address_ok_T_14 connect _address_ok_WIRE[3], _address_ok_T_19 connect _address_ok_WIRE[4], _address_ok_T_24 connect _address_ok_WIRE[5], _address_ok_T_29 connect _address_ok_WIRE[6], _address_ok_T_34 connect _address_ok_WIRE[7], _address_ok_T_39 connect _address_ok_WIRE[8], _address_ok_T_44 connect _address_ok_WIRE[9], _address_ok_T_49 connect _address_ok_WIRE[10], _address_ok_T_54 connect _address_ok_WIRE[11], _address_ok_T_59 node _address_ok_T_60 = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _address_ok_T_61 = or(_address_ok_T_60, _address_ok_WIRE[2]) node _address_ok_T_62 = or(_address_ok_T_61, _address_ok_WIRE[3]) node _address_ok_T_63 = or(_address_ok_T_62, _address_ok_WIRE[4]) node _address_ok_T_64 = or(_address_ok_T_63, _address_ok_WIRE[5]) node _address_ok_T_65 = or(_address_ok_T_64, _address_ok_WIRE[6]) node _address_ok_T_66 = or(_address_ok_T_65, _address_ok_WIRE[7]) node _address_ok_T_67 = or(_address_ok_T_66, _address_ok_WIRE[8]) node _address_ok_T_68 = or(_address_ok_T_67, _address_ok_WIRE[9]) node _address_ok_T_69 = or(_address_ok_T_68, _address_ok_WIRE[10]) node address_ok = or(_address_ok_T_69, _address_ok_WIRE[11]) node _is_aligned_mask_T_2 = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 11, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<2>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 1, 0) node _legal_source_T = shr(io.in.b.bits.source, 2) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<2>(0h2)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) node _legal_source_T_6 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _legal_source_T_7 = eq(io.in.b.bits.source, UInt<3>(0h4)) wire _legal_source_WIRE : UInt<1>[3] connect _legal_source_WIRE[0], _legal_source_T_5 connect _legal_source_WIRE[1], _legal_source_T_6 connect _legal_source_WIRE[2], _legal_source_T_7 node _legal_source_T_8 = mux(_legal_source_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _legal_source_T_9 = mux(_legal_source_WIRE[1], UInt<2>(0h3), UInt<1>(0h0)) node _legal_source_T_10 = mux(_legal_source_WIRE[2], UInt<3>(0h4), UInt<1>(0h0)) node _legal_source_T_11 = or(_legal_source_T_8, _legal_source_T_9) node _legal_source_T_12 = or(_legal_source_T_11, _legal_source_T_10) wire _legal_source_WIRE_1 : UInt<3> connect _legal_source_WIRE_1, _legal_source_T_12 node legal_source = eq(_legal_source_WIRE_1, io.in.b.bits.source) node _T_1231 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _uncommonBits_T_12 = or(io.in.b.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_1232 = shr(io.in.b.bits.source, 2) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) node _T_1234 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1235 = and(_T_1233, _T_1234) node _T_1236 = leq(uncommonBits_12, UInt<2>(0h2)) node _T_1237 = and(_T_1235, _T_1236) node _T_1238 = eq(io.in.b.bits.source, UInt<2>(0h3)) node _T_1239 = eq(io.in.b.bits.source, UInt<3>(0h4)) wire _WIRE_4 : UInt<1>[3] connect _WIRE_4[0], _T_1237 connect _WIRE_4[1], _T_1238 connect _WIRE_4[2], _T_1239 node _T_1240 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_1241 = mux(_WIRE_4[0], _T_1240, UInt<1>(0h0)) node _T_1242 = mux(_WIRE_4[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_1243 = mux(_WIRE_4[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_1244 = or(_T_1241, _T_1242) node _T_1245 = or(_T_1244, _T_1243) wire _WIRE_5 : UInt<1> connect _WIRE_5, _T_1245 node _T_1246 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1247 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1248 = and(_T_1246, _T_1247) node _T_1249 = or(UInt<1>(0h0), _T_1248) node _T_1250 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1251 = cvt(_T_1250) node _T_1252 = and(_T_1251, asSInt(UInt<14>(0h2000))) node _T_1253 = asSInt(_T_1252) node _T_1254 = eq(_T_1253, asSInt(UInt<1>(0h0))) node _T_1255 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1256 = cvt(_T_1255) node _T_1257 = and(_T_1256, asSInt(UInt<13>(0h1000))) node _T_1258 = asSInt(_T_1257) node _T_1259 = eq(_T_1258, asSInt(UInt<1>(0h0))) node _T_1260 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1261 = cvt(_T_1260) node _T_1262 = and(_T_1261, asSInt(UInt<17>(0h10000))) node _T_1263 = asSInt(_T_1262) node _T_1264 = eq(_T_1263, asSInt(UInt<1>(0h0))) node _T_1265 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1266 = cvt(_T_1265) node _T_1267 = and(_T_1266, asSInt(UInt<18>(0h2f000))) node _T_1268 = asSInt(_T_1267) node _T_1269 = eq(_T_1268, asSInt(UInt<1>(0h0))) node _T_1270 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1271 = cvt(_T_1270) node _T_1272 = and(_T_1271, asSInt(UInt<17>(0h10000))) node _T_1273 = asSInt(_T_1272) node _T_1274 = eq(_T_1273, asSInt(UInt<1>(0h0))) node _T_1275 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1276 = cvt(_T_1275) node _T_1277 = and(_T_1276, asSInt(UInt<13>(0h1000))) node _T_1278 = asSInt(_T_1277) node _T_1279 = eq(_T_1278, asSInt(UInt<1>(0h0))) node _T_1280 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1281 = cvt(_T_1280) node _T_1282 = and(_T_1281, asSInt(UInt<17>(0h10000))) node _T_1283 = asSInt(_T_1282) node _T_1284 = eq(_T_1283, asSInt(UInt<1>(0h0))) node _T_1285 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<27>(0h4000000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1296 = cvt(_T_1295) node _T_1297 = and(_T_1296, asSInt(UInt<29>(0h10000000))) node _T_1298 = asSInt(_T_1297) node _T_1299 = eq(_T_1298, asSInt(UInt<1>(0h0))) node _T_1300 = or(_T_1254, _T_1259) node _T_1301 = or(_T_1300, _T_1264) node _T_1302 = or(_T_1301, _T_1269) node _T_1303 = or(_T_1302, _T_1274) node _T_1304 = or(_T_1303, _T_1279) node _T_1305 = or(_T_1304, _T_1284) node _T_1306 = or(_T_1305, _T_1289) node _T_1307 = or(_T_1306, _T_1294) node _T_1308 = or(_T_1307, _T_1299) node _T_1309 = and(_T_1249, _T_1308) node _T_1310 = or(UInt<1>(0h0), _T_1309) node _T_1311 = and(_WIRE_5, _T_1310) node _T_1312 = asUInt(reset) node _T_1313 = eq(_T_1312, UInt<1>(0h0)) when _T_1313 : node _T_1314 = eq(_T_1311, UInt<1>(0h0)) when _T_1314 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_1311, UInt<1>(0h1), "") : assert_86 node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(address_ok, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(legal_source, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_1321 = asUInt(reset) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) when _T_1322 : node _T_1323 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_1324 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_90 node _T_1328 = eq(io.in.b.bits.mask, mask_1) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_91 node _T_1332 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_92 node _T_1336 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_1336 : node _T_1337 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1338 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1339 = and(_T_1337, _T_1338) node _T_1340 = or(UInt<1>(0h0), _T_1339) node _T_1341 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1342 = cvt(_T_1341) node _T_1343 = and(_T_1342, asSInt(UInt<14>(0h2000))) node _T_1344 = asSInt(_T_1343) node _T_1345 = eq(_T_1344, asSInt(UInt<1>(0h0))) node _T_1346 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1347 = cvt(_T_1346) node _T_1348 = and(_T_1347, asSInt(UInt<13>(0h1000))) node _T_1349 = asSInt(_T_1348) node _T_1350 = eq(_T_1349, asSInt(UInt<1>(0h0))) node _T_1351 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1352 = cvt(_T_1351) node _T_1353 = and(_T_1352, asSInt(UInt<17>(0h10000))) node _T_1354 = asSInt(_T_1353) node _T_1355 = eq(_T_1354, asSInt(UInt<1>(0h0))) node _T_1356 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1357 = cvt(_T_1356) node _T_1358 = and(_T_1357, asSInt(UInt<18>(0h2f000))) node _T_1359 = asSInt(_T_1358) node _T_1360 = eq(_T_1359, asSInt(UInt<1>(0h0))) node _T_1361 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1362 = cvt(_T_1361) node _T_1363 = and(_T_1362, asSInt(UInt<17>(0h10000))) node _T_1364 = asSInt(_T_1363) node _T_1365 = eq(_T_1364, asSInt(UInt<1>(0h0))) node _T_1366 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1367 = cvt(_T_1366) node _T_1368 = and(_T_1367, asSInt(UInt<13>(0h1000))) node _T_1369 = asSInt(_T_1368) node _T_1370 = eq(_T_1369, asSInt(UInt<1>(0h0))) node _T_1371 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1372 = cvt(_T_1371) node _T_1373 = and(_T_1372, asSInt(UInt<17>(0h10000))) node _T_1374 = asSInt(_T_1373) node _T_1375 = eq(_T_1374, asSInt(UInt<1>(0h0))) node _T_1376 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1377 = cvt(_T_1376) node _T_1378 = and(_T_1377, asSInt(UInt<27>(0h4000000))) node _T_1379 = asSInt(_T_1378) node _T_1380 = eq(_T_1379, asSInt(UInt<1>(0h0))) node _T_1381 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1382 = cvt(_T_1381) node _T_1383 = and(_T_1382, asSInt(UInt<13>(0h1000))) node _T_1384 = asSInt(_T_1383) node _T_1385 = eq(_T_1384, asSInt(UInt<1>(0h0))) node _T_1386 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<29>(0h10000000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = or(_T_1345, _T_1350) node _T_1392 = or(_T_1391, _T_1355) node _T_1393 = or(_T_1392, _T_1360) node _T_1394 = or(_T_1393, _T_1365) node _T_1395 = or(_T_1394, _T_1370) node _T_1396 = or(_T_1395, _T_1375) node _T_1397 = or(_T_1396, _T_1380) node _T_1398 = or(_T_1397, _T_1385) node _T_1399 = or(_T_1398, _T_1390) node _T_1400 = and(_T_1340, _T_1399) node _T_1401 = or(UInt<1>(0h0), _T_1400) node _T_1402 = and(UInt<1>(0h0), _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = asUInt(reset) node _T_1407 = eq(_T_1406, UInt<1>(0h0)) when _T_1407 : node _T_1408 = eq(address_ok, UInt<1>(0h0)) when _T_1408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_1409 = asUInt(reset) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(legal_source, UInt<1>(0h0)) when _T_1411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_1412 = asUInt(reset) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) when _T_1413 : node _T_1414 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_1415 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1416 = asUInt(reset) node _T_1417 = eq(_T_1416, UInt<1>(0h0)) when _T_1417 : node _T_1418 = eq(_T_1415, UInt<1>(0h0)) when _T_1418 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_1415, UInt<1>(0h1), "") : assert_97 node _T_1419 = eq(io.in.b.bits.mask, mask_1) node _T_1420 = asUInt(reset) node _T_1421 = eq(_T_1420, UInt<1>(0h0)) when _T_1421 : node _T_1422 = eq(_T_1419, UInt<1>(0h0)) when _T_1422 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1419, UInt<1>(0h1), "") : assert_98 node _T_1423 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1424 = asUInt(reset) node _T_1425 = eq(_T_1424, UInt<1>(0h0)) when _T_1425 : node _T_1426 = eq(_T_1423, UInt<1>(0h0)) when _T_1426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_1423, UInt<1>(0h1), "") : assert_99 node _T_1427 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_1427 : node _T_1428 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1429 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1430 = and(_T_1428, _T_1429) node _T_1431 = or(UInt<1>(0h0), _T_1430) node _T_1432 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1433 = cvt(_T_1432) node _T_1434 = and(_T_1433, asSInt(UInt<14>(0h2000))) node _T_1435 = asSInt(_T_1434) node _T_1436 = eq(_T_1435, asSInt(UInt<1>(0h0))) node _T_1437 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1438 = cvt(_T_1437) node _T_1439 = and(_T_1438, asSInt(UInt<13>(0h1000))) node _T_1440 = asSInt(_T_1439) node _T_1441 = eq(_T_1440, asSInt(UInt<1>(0h0))) node _T_1442 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1443 = cvt(_T_1442) node _T_1444 = and(_T_1443, asSInt(UInt<17>(0h10000))) node _T_1445 = asSInt(_T_1444) node _T_1446 = eq(_T_1445, asSInt(UInt<1>(0h0))) node _T_1447 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1448 = cvt(_T_1447) node _T_1449 = and(_T_1448, asSInt(UInt<18>(0h2f000))) node _T_1450 = asSInt(_T_1449) node _T_1451 = eq(_T_1450, asSInt(UInt<1>(0h0))) node _T_1452 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1453 = cvt(_T_1452) node _T_1454 = and(_T_1453, asSInt(UInt<17>(0h10000))) node _T_1455 = asSInt(_T_1454) node _T_1456 = eq(_T_1455, asSInt(UInt<1>(0h0))) node _T_1457 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1458 = cvt(_T_1457) node _T_1459 = and(_T_1458, asSInt(UInt<13>(0h1000))) node _T_1460 = asSInt(_T_1459) node _T_1461 = eq(_T_1460, asSInt(UInt<1>(0h0))) node _T_1462 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1463 = cvt(_T_1462) node _T_1464 = and(_T_1463, asSInt(UInt<17>(0h10000))) node _T_1465 = asSInt(_T_1464) node _T_1466 = eq(_T_1465, asSInt(UInt<1>(0h0))) node _T_1467 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1468 = cvt(_T_1467) node _T_1469 = and(_T_1468, asSInt(UInt<27>(0h4000000))) node _T_1470 = asSInt(_T_1469) node _T_1471 = eq(_T_1470, asSInt(UInt<1>(0h0))) node _T_1472 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1473 = cvt(_T_1472) node _T_1474 = and(_T_1473, asSInt(UInt<13>(0h1000))) node _T_1475 = asSInt(_T_1474) node _T_1476 = eq(_T_1475, asSInt(UInt<1>(0h0))) node _T_1477 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1478 = cvt(_T_1477) node _T_1479 = and(_T_1478, asSInt(UInt<29>(0h10000000))) node _T_1480 = asSInt(_T_1479) node _T_1481 = eq(_T_1480, asSInt(UInt<1>(0h0))) node _T_1482 = or(_T_1436, _T_1441) node _T_1483 = or(_T_1482, _T_1446) node _T_1484 = or(_T_1483, _T_1451) node _T_1485 = or(_T_1484, _T_1456) node _T_1486 = or(_T_1485, _T_1461) node _T_1487 = or(_T_1486, _T_1466) node _T_1488 = or(_T_1487, _T_1471) node _T_1489 = or(_T_1488, _T_1476) node _T_1490 = or(_T_1489, _T_1481) node _T_1491 = and(_T_1431, _T_1490) node _T_1492 = or(UInt<1>(0h0), _T_1491) node _T_1493 = and(UInt<1>(0h0), _T_1492) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_100 node _T_1497 = asUInt(reset) node _T_1498 = eq(_T_1497, UInt<1>(0h0)) when _T_1498 : node _T_1499 = eq(address_ok, UInt<1>(0h0)) when _T_1499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_1500 = asUInt(reset) node _T_1501 = eq(_T_1500, UInt<1>(0h0)) when _T_1501 : node _T_1502 = eq(legal_source, UInt<1>(0h0)) when _T_1502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_1503 = asUInt(reset) node _T_1504 = eq(_T_1503, UInt<1>(0h0)) when _T_1504 : node _T_1505 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_1506 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1507 = asUInt(reset) node _T_1508 = eq(_T_1507, UInt<1>(0h0)) when _T_1508 : node _T_1509 = eq(_T_1506, UInt<1>(0h0)) when _T_1509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_1506, UInt<1>(0h1), "") : assert_104 node _T_1510 = eq(io.in.b.bits.mask, mask_1) node _T_1511 = asUInt(reset) node _T_1512 = eq(_T_1511, UInt<1>(0h0)) when _T_1512 : node _T_1513 = eq(_T_1510, UInt<1>(0h0)) when _T_1513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1510, UInt<1>(0h1), "") : assert_105 node _T_1514 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_1514 : node _T_1515 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1516 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1517 = and(_T_1515, _T_1516) node _T_1518 = or(UInt<1>(0h0), _T_1517) node _T_1519 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1520 = cvt(_T_1519) node _T_1521 = and(_T_1520, asSInt(UInt<14>(0h2000))) node _T_1522 = asSInt(_T_1521) node _T_1523 = eq(_T_1522, asSInt(UInt<1>(0h0))) node _T_1524 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1525 = cvt(_T_1524) node _T_1526 = and(_T_1525, asSInt(UInt<13>(0h1000))) node _T_1527 = asSInt(_T_1526) node _T_1528 = eq(_T_1527, asSInt(UInt<1>(0h0))) node _T_1529 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1530 = cvt(_T_1529) node _T_1531 = and(_T_1530, asSInt(UInt<17>(0h10000))) node _T_1532 = asSInt(_T_1531) node _T_1533 = eq(_T_1532, asSInt(UInt<1>(0h0))) node _T_1534 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1535 = cvt(_T_1534) node _T_1536 = and(_T_1535, asSInt(UInt<18>(0h2f000))) node _T_1537 = asSInt(_T_1536) node _T_1538 = eq(_T_1537, asSInt(UInt<1>(0h0))) node _T_1539 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1540 = cvt(_T_1539) node _T_1541 = and(_T_1540, asSInt(UInt<17>(0h10000))) node _T_1542 = asSInt(_T_1541) node _T_1543 = eq(_T_1542, asSInt(UInt<1>(0h0))) node _T_1544 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1545 = cvt(_T_1544) node _T_1546 = and(_T_1545, asSInt(UInt<13>(0h1000))) node _T_1547 = asSInt(_T_1546) node _T_1548 = eq(_T_1547, asSInt(UInt<1>(0h0))) node _T_1549 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1550 = cvt(_T_1549) node _T_1551 = and(_T_1550, asSInt(UInt<17>(0h10000))) node _T_1552 = asSInt(_T_1551) node _T_1553 = eq(_T_1552, asSInt(UInt<1>(0h0))) node _T_1554 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1555 = cvt(_T_1554) node _T_1556 = and(_T_1555, asSInt(UInt<27>(0h4000000))) node _T_1557 = asSInt(_T_1556) node _T_1558 = eq(_T_1557, asSInt(UInt<1>(0h0))) node _T_1559 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1560 = cvt(_T_1559) node _T_1561 = and(_T_1560, asSInt(UInt<13>(0h1000))) node _T_1562 = asSInt(_T_1561) node _T_1563 = eq(_T_1562, asSInt(UInt<1>(0h0))) node _T_1564 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1565 = cvt(_T_1564) node _T_1566 = and(_T_1565, asSInt(UInt<29>(0h10000000))) node _T_1567 = asSInt(_T_1566) node _T_1568 = eq(_T_1567, asSInt(UInt<1>(0h0))) node _T_1569 = or(_T_1523, _T_1528) node _T_1570 = or(_T_1569, _T_1533) node _T_1571 = or(_T_1570, _T_1538) node _T_1572 = or(_T_1571, _T_1543) node _T_1573 = or(_T_1572, _T_1548) node _T_1574 = or(_T_1573, _T_1553) node _T_1575 = or(_T_1574, _T_1558) node _T_1576 = or(_T_1575, _T_1563) node _T_1577 = or(_T_1576, _T_1568) node _T_1578 = and(_T_1518, _T_1577) node _T_1579 = or(UInt<1>(0h0), _T_1578) node _T_1580 = and(UInt<1>(0h0), _T_1579) node _T_1581 = asUInt(reset) node _T_1582 = eq(_T_1581, UInt<1>(0h0)) when _T_1582 : node _T_1583 = eq(_T_1580, UInt<1>(0h0)) when _T_1583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1580, UInt<1>(0h1), "") : assert_106 node _T_1584 = asUInt(reset) node _T_1585 = eq(_T_1584, UInt<1>(0h0)) when _T_1585 : node _T_1586 = eq(address_ok, UInt<1>(0h0)) when _T_1586 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_1587 = asUInt(reset) node _T_1588 = eq(_T_1587, UInt<1>(0h0)) when _T_1588 : node _T_1589 = eq(legal_source, UInt<1>(0h0)) when _T_1589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_1593 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_110 node _T_1597 = not(mask_1) node _T_1598 = and(io.in.b.bits.mask, _T_1597) node _T_1599 = eq(_T_1598, UInt<1>(0h0)) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_111 node _T_1603 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_1603 : node _T_1604 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1605 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1606 = and(_T_1604, _T_1605) node _T_1607 = or(UInt<1>(0h0), _T_1606) node _T_1608 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1609 = cvt(_T_1608) node _T_1610 = and(_T_1609, asSInt(UInt<14>(0h2000))) node _T_1611 = asSInt(_T_1610) node _T_1612 = eq(_T_1611, asSInt(UInt<1>(0h0))) node _T_1613 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1614 = cvt(_T_1613) node _T_1615 = and(_T_1614, asSInt(UInt<13>(0h1000))) node _T_1616 = asSInt(_T_1615) node _T_1617 = eq(_T_1616, asSInt(UInt<1>(0h0))) node _T_1618 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1619 = cvt(_T_1618) node _T_1620 = and(_T_1619, asSInt(UInt<17>(0h10000))) node _T_1621 = asSInt(_T_1620) node _T_1622 = eq(_T_1621, asSInt(UInt<1>(0h0))) node _T_1623 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1624 = cvt(_T_1623) node _T_1625 = and(_T_1624, asSInt(UInt<18>(0h2f000))) node _T_1626 = asSInt(_T_1625) node _T_1627 = eq(_T_1626, asSInt(UInt<1>(0h0))) node _T_1628 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1629 = cvt(_T_1628) node _T_1630 = and(_T_1629, asSInt(UInt<17>(0h10000))) node _T_1631 = asSInt(_T_1630) node _T_1632 = eq(_T_1631, asSInt(UInt<1>(0h0))) node _T_1633 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1634 = cvt(_T_1633) node _T_1635 = and(_T_1634, asSInt(UInt<13>(0h1000))) node _T_1636 = asSInt(_T_1635) node _T_1637 = eq(_T_1636, asSInt(UInt<1>(0h0))) node _T_1638 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1639 = cvt(_T_1638) node _T_1640 = and(_T_1639, asSInt(UInt<17>(0h10000))) node _T_1641 = asSInt(_T_1640) node _T_1642 = eq(_T_1641, asSInt(UInt<1>(0h0))) node _T_1643 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1644 = cvt(_T_1643) node _T_1645 = and(_T_1644, asSInt(UInt<27>(0h4000000))) node _T_1646 = asSInt(_T_1645) node _T_1647 = eq(_T_1646, asSInt(UInt<1>(0h0))) node _T_1648 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1649 = cvt(_T_1648) node _T_1650 = and(_T_1649, asSInt(UInt<13>(0h1000))) node _T_1651 = asSInt(_T_1650) node _T_1652 = eq(_T_1651, asSInt(UInt<1>(0h0))) node _T_1653 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1654 = cvt(_T_1653) node _T_1655 = and(_T_1654, asSInt(UInt<29>(0h10000000))) node _T_1656 = asSInt(_T_1655) node _T_1657 = eq(_T_1656, asSInt(UInt<1>(0h0))) node _T_1658 = or(_T_1612, _T_1617) node _T_1659 = or(_T_1658, _T_1622) node _T_1660 = or(_T_1659, _T_1627) node _T_1661 = or(_T_1660, _T_1632) node _T_1662 = or(_T_1661, _T_1637) node _T_1663 = or(_T_1662, _T_1642) node _T_1664 = or(_T_1663, _T_1647) node _T_1665 = or(_T_1664, _T_1652) node _T_1666 = or(_T_1665, _T_1657) node _T_1667 = and(_T_1607, _T_1666) node _T_1668 = or(UInt<1>(0h0), _T_1667) node _T_1669 = and(UInt<1>(0h0), _T_1668) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_112 node _T_1673 = asUInt(reset) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(address_ok, UInt<1>(0h0)) when _T_1675 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(legal_source, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_1679 = asUInt(reset) node _T_1680 = eq(_T_1679, UInt<1>(0h0)) when _T_1680 : node _T_1681 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1681 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_1682 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_1683 = asUInt(reset) node _T_1684 = eq(_T_1683, UInt<1>(0h0)) when _T_1684 : node _T_1685 = eq(_T_1682, UInt<1>(0h0)) when _T_1685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_1682, UInt<1>(0h1), "") : assert_116 node _T_1686 = eq(io.in.b.bits.mask, mask_1) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_117 node _T_1690 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_1690 : node _T_1691 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1692 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1693 = and(_T_1691, _T_1692) node _T_1694 = or(UInt<1>(0h0), _T_1693) node _T_1695 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1696 = cvt(_T_1695) node _T_1697 = and(_T_1696, asSInt(UInt<14>(0h2000))) node _T_1698 = asSInt(_T_1697) node _T_1699 = eq(_T_1698, asSInt(UInt<1>(0h0))) node _T_1700 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1701 = cvt(_T_1700) node _T_1702 = and(_T_1701, asSInt(UInt<13>(0h1000))) node _T_1703 = asSInt(_T_1702) node _T_1704 = eq(_T_1703, asSInt(UInt<1>(0h0))) node _T_1705 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1706 = cvt(_T_1705) node _T_1707 = and(_T_1706, asSInt(UInt<17>(0h10000))) node _T_1708 = asSInt(_T_1707) node _T_1709 = eq(_T_1708, asSInt(UInt<1>(0h0))) node _T_1710 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1711 = cvt(_T_1710) node _T_1712 = and(_T_1711, asSInt(UInt<18>(0h2f000))) node _T_1713 = asSInt(_T_1712) node _T_1714 = eq(_T_1713, asSInt(UInt<1>(0h0))) node _T_1715 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1716 = cvt(_T_1715) node _T_1717 = and(_T_1716, asSInt(UInt<17>(0h10000))) node _T_1718 = asSInt(_T_1717) node _T_1719 = eq(_T_1718, asSInt(UInt<1>(0h0))) node _T_1720 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1721 = cvt(_T_1720) node _T_1722 = and(_T_1721, asSInt(UInt<13>(0h1000))) node _T_1723 = asSInt(_T_1722) node _T_1724 = eq(_T_1723, asSInt(UInt<1>(0h0))) node _T_1725 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1726 = cvt(_T_1725) node _T_1727 = and(_T_1726, asSInt(UInt<17>(0h10000))) node _T_1728 = asSInt(_T_1727) node _T_1729 = eq(_T_1728, asSInt(UInt<1>(0h0))) node _T_1730 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1731 = cvt(_T_1730) node _T_1732 = and(_T_1731, asSInt(UInt<27>(0h4000000))) node _T_1733 = asSInt(_T_1732) node _T_1734 = eq(_T_1733, asSInt(UInt<1>(0h0))) node _T_1735 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1736 = cvt(_T_1735) node _T_1737 = and(_T_1736, asSInt(UInt<13>(0h1000))) node _T_1738 = asSInt(_T_1737) node _T_1739 = eq(_T_1738, asSInt(UInt<1>(0h0))) node _T_1740 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1741 = cvt(_T_1740) node _T_1742 = and(_T_1741, asSInt(UInt<29>(0h10000000))) node _T_1743 = asSInt(_T_1742) node _T_1744 = eq(_T_1743, asSInt(UInt<1>(0h0))) node _T_1745 = or(_T_1699, _T_1704) node _T_1746 = or(_T_1745, _T_1709) node _T_1747 = or(_T_1746, _T_1714) node _T_1748 = or(_T_1747, _T_1719) node _T_1749 = or(_T_1748, _T_1724) node _T_1750 = or(_T_1749, _T_1729) node _T_1751 = or(_T_1750, _T_1734) node _T_1752 = or(_T_1751, _T_1739) node _T_1753 = or(_T_1752, _T_1744) node _T_1754 = and(_T_1694, _T_1753) node _T_1755 = or(UInt<1>(0h0), _T_1754) node _T_1756 = and(UInt<1>(0h0), _T_1755) node _T_1757 = asUInt(reset) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(_T_1756, UInt<1>(0h0)) when _T_1759 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_1756, UInt<1>(0h1), "") : assert_118 node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(address_ok, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_1763 = asUInt(reset) node _T_1764 = eq(_T_1763, UInt<1>(0h0)) when _T_1764 : node _T_1765 = eq(legal_source, UInt<1>(0h0)) when _T_1765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_1766 = asUInt(reset) node _T_1767 = eq(_T_1766, UInt<1>(0h0)) when _T_1767 : node _T_1768 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_1769 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_1770 = asUInt(reset) node _T_1771 = eq(_T_1770, UInt<1>(0h0)) when _T_1771 : node _T_1772 = eq(_T_1769, UInt<1>(0h0)) when _T_1772 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_1769, UInt<1>(0h1), "") : assert_122 node _T_1773 = eq(io.in.b.bits.mask, mask_1) node _T_1774 = asUInt(reset) node _T_1775 = eq(_T_1774, UInt<1>(0h0)) when _T_1775 : node _T_1776 = eq(_T_1773, UInt<1>(0h0)) when _T_1776 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_1773, UInt<1>(0h1), "") : assert_123 node _T_1777 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_1777 : node _T_1778 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_1779 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = or(UInt<1>(0h0), _T_1780) node _T_1782 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_1783 = cvt(_T_1782) node _T_1784 = and(_T_1783, asSInt(UInt<14>(0h2000))) node _T_1785 = asSInt(_T_1784) node _T_1786 = eq(_T_1785, asSInt(UInt<1>(0h0))) node _T_1787 = xor(io.in.b.bits.address, UInt<14>(0h3000)) node _T_1788 = cvt(_T_1787) node _T_1789 = and(_T_1788, asSInt(UInt<13>(0h1000))) node _T_1790 = asSInt(_T_1789) node _T_1791 = eq(_T_1790, asSInt(UInt<1>(0h0))) node _T_1792 = xor(io.in.b.bits.address, UInt<17>(0h10000)) node _T_1793 = cvt(_T_1792) node _T_1794 = and(_T_1793, asSInt(UInt<17>(0h10000))) node _T_1795 = asSInt(_T_1794) node _T_1796 = eq(_T_1795, asSInt(UInt<1>(0h0))) node _T_1797 = xor(io.in.b.bits.address, UInt<21>(0h100000)) node _T_1798 = cvt(_T_1797) node _T_1799 = and(_T_1798, asSInt(UInt<18>(0h2f000))) node _T_1800 = asSInt(_T_1799) node _T_1801 = eq(_T_1800, asSInt(UInt<1>(0h0))) node _T_1802 = xor(io.in.b.bits.address, UInt<26>(0h2000000)) node _T_1803 = cvt(_T_1802) node _T_1804 = and(_T_1803, asSInt(UInt<17>(0h10000))) node _T_1805 = asSInt(_T_1804) node _T_1806 = eq(_T_1805, asSInt(UInt<1>(0h0))) node _T_1807 = xor(io.in.b.bits.address, UInt<26>(0h2010000)) node _T_1808 = cvt(_T_1807) node _T_1809 = and(_T_1808, asSInt(UInt<13>(0h1000))) node _T_1810 = asSInt(_T_1809) node _T_1811 = eq(_T_1810, asSInt(UInt<1>(0h0))) node _T_1812 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_1813 = cvt(_T_1812) node _T_1814 = and(_T_1813, asSInt(UInt<17>(0h10000))) node _T_1815 = asSInt(_T_1814) node _T_1816 = eq(_T_1815, asSInt(UInt<1>(0h0))) node _T_1817 = xor(io.in.b.bits.address, UInt<28>(0hc000000)) node _T_1818 = cvt(_T_1817) node _T_1819 = and(_T_1818, asSInt(UInt<27>(0h4000000))) node _T_1820 = asSInt(_T_1819) node _T_1821 = eq(_T_1820, asSInt(UInt<1>(0h0))) node _T_1822 = xor(io.in.b.bits.address, UInt<29>(0h10020000)) node _T_1823 = cvt(_T_1822) node _T_1824 = and(_T_1823, asSInt(UInt<13>(0h1000))) node _T_1825 = asSInt(_T_1824) node _T_1826 = eq(_T_1825, asSInt(UInt<1>(0h0))) node _T_1827 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_1828 = cvt(_T_1827) node _T_1829 = and(_T_1828, asSInt(UInt<29>(0h10000000))) node _T_1830 = asSInt(_T_1829) node _T_1831 = eq(_T_1830, asSInt(UInt<1>(0h0))) node _T_1832 = or(_T_1786, _T_1791) node _T_1833 = or(_T_1832, _T_1796) node _T_1834 = or(_T_1833, _T_1801) node _T_1835 = or(_T_1834, _T_1806) node _T_1836 = or(_T_1835, _T_1811) node _T_1837 = or(_T_1836, _T_1816) node _T_1838 = or(_T_1837, _T_1821) node _T_1839 = or(_T_1838, _T_1826) node _T_1840 = or(_T_1839, _T_1831) node _T_1841 = and(_T_1781, _T_1840) node _T_1842 = or(UInt<1>(0h0), _T_1841) node _T_1843 = and(UInt<1>(0h0), _T_1842) node _T_1844 = asUInt(reset) node _T_1845 = eq(_T_1844, UInt<1>(0h0)) when _T_1845 : node _T_1846 = eq(_T_1843, UInt<1>(0h0)) when _T_1846 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_1843, UInt<1>(0h1), "") : assert_124 node _T_1847 = asUInt(reset) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) when _T_1848 : node _T_1849 = eq(address_ok, UInt<1>(0h0)) when _T_1849 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_1850 = asUInt(reset) node _T_1851 = eq(_T_1850, UInt<1>(0h0)) when _T_1851 : node _T_1852 = eq(legal_source, UInt<1>(0h0)) when _T_1852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_1853 = asUInt(reset) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(is_aligned_1, UInt<1>(0h0)) when _T_1855 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_1856 = eq(io.in.b.bits.mask, mask_1) node _T_1857 = asUInt(reset) node _T_1858 = eq(_T_1857, UInt<1>(0h0)) when _T_1858 : node _T_1859 = eq(_T_1856, UInt<1>(0h0)) when _T_1859 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_1856, UInt<1>(0h1), "") : assert_128 node _T_1860 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_1861 = asUInt(reset) node _T_1862 = eq(_T_1861, UInt<1>(0h0)) when _T_1862 : node _T_1863 = eq(_T_1860, UInt<1>(0h0)) when _T_1863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_1860, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_1864 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_18 = shr(io.in.c.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_2, UInt<2>(0h2)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) node _source_ok_T_24 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _source_ok_T_25 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _source_ok_WIRE_2 : UInt<1>[3] connect _source_ok_WIRE_2[0], _source_ok_T_23 connect _source_ok_WIRE_2[1], _source_ok_T_24 connect _source_ok_WIRE_2[2], _source_ok_T_25 node _source_ok_T_26 = or(_source_ok_WIRE_2[0], _source_ok_WIRE_2[1]) node source_ok_2 = or(_source_ok_T_26, _source_ok_WIRE_2[2]) node _is_aligned_mask_T_4 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 11, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_70 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _address_ok_T_71 = cvt(_address_ok_T_70) node _address_ok_T_72 = and(_address_ok_T_71, asSInt(UInt<13>(0h1000))) node _address_ok_T_73 = asSInt(_address_ok_T_72) node _address_ok_T_74 = eq(_address_ok_T_73, asSInt(UInt<1>(0h0))) node _address_ok_T_75 = xor(io.in.c.bits.address, UInt<13>(0h1000)) node _address_ok_T_76 = cvt(_address_ok_T_75) node _address_ok_T_77 = and(_address_ok_T_76, asSInt(UInt<13>(0h1000))) node _address_ok_T_78 = asSInt(_address_ok_T_77) node _address_ok_T_79 = eq(_address_ok_T_78, asSInt(UInt<1>(0h0))) node _address_ok_T_80 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _address_ok_T_81 = cvt(_address_ok_T_80) node _address_ok_T_82 = and(_address_ok_T_81, asSInt(UInt<13>(0h1000))) node _address_ok_T_83 = asSInt(_address_ok_T_82) node _address_ok_T_84 = eq(_address_ok_T_83, asSInt(UInt<1>(0h0))) node _address_ok_T_85 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _address_ok_T_86 = cvt(_address_ok_T_85) node _address_ok_T_87 = and(_address_ok_T_86, asSInt(UInt<17>(0h10000))) node _address_ok_T_88 = asSInt(_address_ok_T_87) node _address_ok_T_89 = eq(_address_ok_T_88, asSInt(UInt<1>(0h0))) node _address_ok_T_90 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _address_ok_T_91 = cvt(_address_ok_T_90) node _address_ok_T_92 = and(_address_ok_T_91, asSInt(UInt<13>(0h1000))) node _address_ok_T_93 = asSInt(_address_ok_T_92) node _address_ok_T_94 = eq(_address_ok_T_93, asSInt(UInt<1>(0h0))) node _address_ok_T_95 = xor(io.in.c.bits.address, UInt<21>(0h110000)) node _address_ok_T_96 = cvt(_address_ok_T_95) node _address_ok_T_97 = and(_address_ok_T_96, asSInt(UInt<13>(0h1000))) node _address_ok_T_98 = asSInt(_address_ok_T_97) node _address_ok_T_99 = eq(_address_ok_T_98, asSInt(UInt<1>(0h0))) node _address_ok_T_100 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _address_ok_T_101 = cvt(_address_ok_T_100) node _address_ok_T_102 = and(_address_ok_T_101, asSInt(UInt<17>(0h10000))) node _address_ok_T_103 = asSInt(_address_ok_T_102) node _address_ok_T_104 = eq(_address_ok_T_103, asSInt(UInt<1>(0h0))) node _address_ok_T_105 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _address_ok_T_106 = cvt(_address_ok_T_105) node _address_ok_T_107 = and(_address_ok_T_106, asSInt(UInt<13>(0h1000))) node _address_ok_T_108 = asSInt(_address_ok_T_107) node _address_ok_T_109 = eq(_address_ok_T_108, asSInt(UInt<1>(0h0))) node _address_ok_T_110 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_111 = cvt(_address_ok_T_110) node _address_ok_T_112 = and(_address_ok_T_111, asSInt(UInt<17>(0h10000))) node _address_ok_T_113 = asSInt(_address_ok_T_112) node _address_ok_T_114 = eq(_address_ok_T_113, asSInt(UInt<1>(0h0))) node _address_ok_T_115 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _address_ok_T_116 = cvt(_address_ok_T_115) node _address_ok_T_117 = and(_address_ok_T_116, asSInt(UInt<27>(0h4000000))) node _address_ok_T_118 = asSInt(_address_ok_T_117) node _address_ok_T_119 = eq(_address_ok_T_118, asSInt(UInt<1>(0h0))) node _address_ok_T_120 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _address_ok_T_121 = cvt(_address_ok_T_120) node _address_ok_T_122 = and(_address_ok_T_121, asSInt(UInt<13>(0h1000))) node _address_ok_T_123 = asSInt(_address_ok_T_122) node _address_ok_T_124 = eq(_address_ok_T_123, asSInt(UInt<1>(0h0))) node _address_ok_T_125 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_126 = cvt(_address_ok_T_125) node _address_ok_T_127 = and(_address_ok_T_126, asSInt(UInt<29>(0h10000000))) node _address_ok_T_128 = asSInt(_address_ok_T_127) node _address_ok_T_129 = eq(_address_ok_T_128, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[12] connect _address_ok_WIRE_1[0], _address_ok_T_74 connect _address_ok_WIRE_1[1], _address_ok_T_79 connect _address_ok_WIRE_1[2], _address_ok_T_84 connect _address_ok_WIRE_1[3], _address_ok_T_89 connect _address_ok_WIRE_1[4], _address_ok_T_94 connect _address_ok_WIRE_1[5], _address_ok_T_99 connect _address_ok_WIRE_1[6], _address_ok_T_104 connect _address_ok_WIRE_1[7], _address_ok_T_109 connect _address_ok_WIRE_1[8], _address_ok_T_114 connect _address_ok_WIRE_1[9], _address_ok_T_119 connect _address_ok_WIRE_1[10], _address_ok_T_124 connect _address_ok_WIRE_1[11], _address_ok_T_129 node _address_ok_T_130 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _address_ok_T_131 = or(_address_ok_T_130, _address_ok_WIRE_1[2]) node _address_ok_T_132 = or(_address_ok_T_131, _address_ok_WIRE_1[3]) node _address_ok_T_133 = or(_address_ok_T_132, _address_ok_WIRE_1[4]) node _address_ok_T_134 = or(_address_ok_T_133, _address_ok_WIRE_1[5]) node _address_ok_T_135 = or(_address_ok_T_134, _address_ok_WIRE_1[6]) node _address_ok_T_136 = or(_address_ok_T_135, _address_ok_WIRE_1[7]) node _address_ok_T_137 = or(_address_ok_T_136, _address_ok_WIRE_1[8]) node _address_ok_T_138 = or(_address_ok_T_137, _address_ok_WIRE_1[9]) node _address_ok_T_139 = or(_address_ok_T_138, _address_ok_WIRE_1[10]) node address_ok_1 = or(_address_ok_T_139, _address_ok_WIRE_1[11]) node _uncommonBits_T_13 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_1868 = shr(io.in.c.bits.source, 2) node _T_1869 = eq(_T_1868, UInt<1>(0h0)) node _T_1870 = leq(UInt<1>(0h0), uncommonBits_13) node _T_1871 = and(_T_1869, _T_1870) node _T_1872 = leq(uncommonBits_13, UInt<2>(0h2)) node _T_1873 = and(_T_1871, _T_1872) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) node _T_1875 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1876 = cvt(_T_1875) node _T_1877 = and(_T_1876, asSInt(UInt<1>(0h0))) node _T_1878 = asSInt(_T_1877) node _T_1879 = eq(_T_1878, asSInt(UInt<1>(0h0))) node _T_1880 = or(_T_1874, _T_1879) node _T_1881 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1882 = eq(_T_1881, UInt<1>(0h0)) node _T_1883 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1884 = cvt(_T_1883) node _T_1885 = and(_T_1884, asSInt(UInt<1>(0h0))) node _T_1886 = asSInt(_T_1885) node _T_1887 = eq(_T_1886, asSInt(UInt<1>(0h0))) node _T_1888 = or(_T_1882, _T_1887) node _T_1889 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_1890 = eq(_T_1889, UInt<1>(0h0)) node _T_1891 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1892 = cvt(_T_1891) node _T_1893 = and(_T_1892, asSInt(UInt<1>(0h0))) node _T_1894 = asSInt(_T_1893) node _T_1895 = eq(_T_1894, asSInt(UInt<1>(0h0))) node _T_1896 = or(_T_1890, _T_1895) node _T_1897 = and(_T_1880, _T_1888) node _T_1898 = and(_T_1897, _T_1896) node _T_1899 = asUInt(reset) node _T_1900 = eq(_T_1899, UInt<1>(0h0)) when _T_1900 : node _T_1901 = eq(_T_1898, UInt<1>(0h0)) when _T_1901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_1898, UInt<1>(0h1), "") : assert_131 node _T_1902 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_1902 : node _T_1903 = asUInt(reset) node _T_1904 = eq(_T_1903, UInt<1>(0h0)) when _T_1904 : node _T_1905 = eq(address_ok_1, UInt<1>(0h0)) when _T_1905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_1906 = asUInt(reset) node _T_1907 = eq(_T_1906, UInt<1>(0h0)) when _T_1907 : node _T_1908 = eq(source_ok_2, UInt<1>(0h0)) when _T_1908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_133 node _T_1909 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1910 = asUInt(reset) node _T_1911 = eq(_T_1910, UInt<1>(0h0)) when _T_1911 : node _T_1912 = eq(_T_1909, UInt<1>(0h0)) when _T_1912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_1909, UInt<1>(0h1), "") : assert_134 node _T_1913 = asUInt(reset) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_1916 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1917 = asUInt(reset) node _T_1918 = eq(_T_1917, UInt<1>(0h0)) when _T_1918 : node _T_1919 = eq(_T_1916, UInt<1>(0h0)) when _T_1919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_1916, UInt<1>(0h1), "") : assert_136 node _T_1920 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1921 = asUInt(reset) node _T_1922 = eq(_T_1921, UInt<1>(0h0)) when _T_1922 : node _T_1923 = eq(_T_1920, UInt<1>(0h0)) when _T_1923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_1920, UInt<1>(0h1), "") : assert_137 node _T_1924 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_1924 : node _T_1925 = asUInt(reset) node _T_1926 = eq(_T_1925, UInt<1>(0h0)) when _T_1926 : node _T_1927 = eq(address_ok_1, UInt<1>(0h0)) when _T_1927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_1928 = asUInt(reset) node _T_1929 = eq(_T_1928, UInt<1>(0h0)) when _T_1929 : node _T_1930 = eq(source_ok_2, UInt<1>(0h0)) when _T_1930 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_139 node _T_1931 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1932 = asUInt(reset) node _T_1933 = eq(_T_1932, UInt<1>(0h0)) when _T_1933 : node _T_1934 = eq(_T_1931, UInt<1>(0h0)) when _T_1934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_1931, UInt<1>(0h1), "") : assert_140 node _T_1935 = asUInt(reset) node _T_1936 = eq(_T_1935, UInt<1>(0h0)) when _T_1936 : node _T_1937 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_1938 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1939 = asUInt(reset) node _T_1940 = eq(_T_1939, UInt<1>(0h0)) when _T_1940 : node _T_1941 = eq(_T_1938, UInt<1>(0h0)) when _T_1941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_1938, UInt<1>(0h1), "") : assert_142 node _T_1942 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_1942 : node _T_1943 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1944 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1945 = and(_T_1943, _T_1944) node _uncommonBits_T_14 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_1946 = shr(io.in.c.bits.source, 2) node _T_1947 = eq(_T_1946, UInt<1>(0h0)) node _T_1948 = leq(UInt<1>(0h0), uncommonBits_14) node _T_1949 = and(_T_1947, _T_1948) node _T_1950 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_1951 = and(_T_1949, _T_1950) node _T_1952 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_1953 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_1954 = or(_T_1951, _T_1952) node _T_1955 = or(_T_1954, _T_1953) node _T_1956 = and(_T_1945, _T_1955) node _T_1957 = or(UInt<1>(0h0), _T_1956) node _T_1958 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1959 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_1960 = cvt(_T_1959) node _T_1961 = and(_T_1960, asSInt(UInt<14>(0h2000))) node _T_1962 = asSInt(_T_1961) node _T_1963 = eq(_T_1962, asSInt(UInt<1>(0h0))) node _T_1964 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_1965 = cvt(_T_1964) node _T_1966 = and(_T_1965, asSInt(UInt<13>(0h1000))) node _T_1967 = asSInt(_T_1966) node _T_1968 = eq(_T_1967, asSInt(UInt<1>(0h0))) node _T_1969 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_1970 = cvt(_T_1969) node _T_1971 = and(_T_1970, asSInt(UInt<17>(0h10000))) node _T_1972 = asSInt(_T_1971) node _T_1973 = eq(_T_1972, asSInt(UInt<1>(0h0))) node _T_1974 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_1975 = cvt(_T_1974) node _T_1976 = and(_T_1975, asSInt(UInt<18>(0h2f000))) node _T_1977 = asSInt(_T_1976) node _T_1978 = eq(_T_1977, asSInt(UInt<1>(0h0))) node _T_1979 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_1980 = cvt(_T_1979) node _T_1981 = and(_T_1980, asSInt(UInt<17>(0h10000))) node _T_1982 = asSInt(_T_1981) node _T_1983 = eq(_T_1982, asSInt(UInt<1>(0h0))) node _T_1984 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_1985 = cvt(_T_1984) node _T_1986 = and(_T_1985, asSInt(UInt<13>(0h1000))) node _T_1987 = asSInt(_T_1986) node _T_1988 = eq(_T_1987, asSInt(UInt<1>(0h0))) node _T_1989 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_1990 = cvt(_T_1989) node _T_1991 = and(_T_1990, asSInt(UInt<27>(0h4000000))) node _T_1992 = asSInt(_T_1991) node _T_1993 = eq(_T_1992, asSInt(UInt<1>(0h0))) node _T_1994 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_1995 = cvt(_T_1994) node _T_1996 = and(_T_1995, asSInt(UInt<13>(0h1000))) node _T_1997 = asSInt(_T_1996) node _T_1998 = eq(_T_1997, asSInt(UInt<1>(0h0))) node _T_1999 = or(_T_1963, _T_1968) node _T_2000 = or(_T_1999, _T_1973) node _T_2001 = or(_T_2000, _T_1978) node _T_2002 = or(_T_2001, _T_1983) node _T_2003 = or(_T_2002, _T_1988) node _T_2004 = or(_T_2003, _T_1993) node _T_2005 = or(_T_2004, _T_1998) node _T_2006 = and(_T_1958, _T_2005) node _T_2007 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2008 = or(UInt<1>(0h0), _T_2007) node _T_2009 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2010 = cvt(_T_2009) node _T_2011 = and(_T_2010, asSInt(UInt<17>(0h10000))) node _T_2012 = asSInt(_T_2011) node _T_2013 = eq(_T_2012, asSInt(UInt<1>(0h0))) node _T_2014 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2015 = cvt(_T_2014) node _T_2016 = and(_T_2015, asSInt(UInt<29>(0h10000000))) node _T_2017 = asSInt(_T_2016) node _T_2018 = eq(_T_2017, asSInt(UInt<1>(0h0))) node _T_2019 = or(_T_2013, _T_2018) node _T_2020 = and(_T_2008, _T_2019) node _T_2021 = or(UInt<1>(0h0), _T_2006) node _T_2022 = or(_T_2021, _T_2020) node _T_2023 = and(_T_1957, _T_2022) node _T_2024 = asUInt(reset) node _T_2025 = eq(_T_2024, UInt<1>(0h0)) when _T_2025 : node _T_2026 = eq(_T_2023, UInt<1>(0h0)) when _T_2026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_2023, UInt<1>(0h1), "") : assert_143 node _uncommonBits_T_15 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_2027 = shr(io.in.c.bits.source, 2) node _T_2028 = eq(_T_2027, UInt<1>(0h0)) node _T_2029 = leq(UInt<1>(0h0), uncommonBits_15) node _T_2030 = and(_T_2028, _T_2029) node _T_2031 = leq(uncommonBits_15, UInt<2>(0h2)) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2034 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _WIRE_6 : UInt<1>[3] connect _WIRE_6[0], _T_2032 connect _WIRE_6[1], _T_2033 connect _WIRE_6[2], _T_2034 node _T_2035 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2036 = mux(_WIRE_6[0], _T_2035, UInt<1>(0h0)) node _T_2037 = mux(_WIRE_6[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2038 = mux(_WIRE_6[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2039 = or(_T_2036, _T_2037) node _T_2040 = or(_T_2039, _T_2038) wire _WIRE_7 : UInt<1> connect _WIRE_7, _T_2040 node _T_2041 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2042 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2043 = and(_T_2041, _T_2042) node _T_2044 = or(UInt<1>(0h0), _T_2043) node _T_2045 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2046 = cvt(_T_2045) node _T_2047 = and(_T_2046, asSInt(UInt<14>(0h2000))) node _T_2048 = asSInt(_T_2047) node _T_2049 = eq(_T_2048, asSInt(UInt<1>(0h0))) node _T_2050 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2051 = cvt(_T_2050) node _T_2052 = and(_T_2051, asSInt(UInt<13>(0h1000))) node _T_2053 = asSInt(_T_2052) node _T_2054 = eq(_T_2053, asSInt(UInt<1>(0h0))) node _T_2055 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2056 = cvt(_T_2055) node _T_2057 = and(_T_2056, asSInt(UInt<17>(0h10000))) node _T_2058 = asSInt(_T_2057) node _T_2059 = eq(_T_2058, asSInt(UInt<1>(0h0))) node _T_2060 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2061 = cvt(_T_2060) node _T_2062 = and(_T_2061, asSInt(UInt<18>(0h2f000))) node _T_2063 = asSInt(_T_2062) node _T_2064 = eq(_T_2063, asSInt(UInt<1>(0h0))) node _T_2065 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2066 = cvt(_T_2065) node _T_2067 = and(_T_2066, asSInt(UInt<17>(0h10000))) node _T_2068 = asSInt(_T_2067) node _T_2069 = eq(_T_2068, asSInt(UInt<1>(0h0))) node _T_2070 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2071 = cvt(_T_2070) node _T_2072 = and(_T_2071, asSInt(UInt<13>(0h1000))) node _T_2073 = asSInt(_T_2072) node _T_2074 = eq(_T_2073, asSInt(UInt<1>(0h0))) node _T_2075 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2076 = cvt(_T_2075) node _T_2077 = and(_T_2076, asSInt(UInt<17>(0h10000))) node _T_2078 = asSInt(_T_2077) node _T_2079 = eq(_T_2078, asSInt(UInt<1>(0h0))) node _T_2080 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2081 = cvt(_T_2080) node _T_2082 = and(_T_2081, asSInt(UInt<27>(0h4000000))) node _T_2083 = asSInt(_T_2082) node _T_2084 = eq(_T_2083, asSInt(UInt<1>(0h0))) node _T_2085 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2086 = cvt(_T_2085) node _T_2087 = and(_T_2086, asSInt(UInt<13>(0h1000))) node _T_2088 = asSInt(_T_2087) node _T_2089 = eq(_T_2088, asSInt(UInt<1>(0h0))) node _T_2090 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2091 = cvt(_T_2090) node _T_2092 = and(_T_2091, asSInt(UInt<29>(0h10000000))) node _T_2093 = asSInt(_T_2092) node _T_2094 = eq(_T_2093, asSInt(UInt<1>(0h0))) node _T_2095 = or(_T_2049, _T_2054) node _T_2096 = or(_T_2095, _T_2059) node _T_2097 = or(_T_2096, _T_2064) node _T_2098 = or(_T_2097, _T_2069) node _T_2099 = or(_T_2098, _T_2074) node _T_2100 = or(_T_2099, _T_2079) node _T_2101 = or(_T_2100, _T_2084) node _T_2102 = or(_T_2101, _T_2089) node _T_2103 = or(_T_2102, _T_2094) node _T_2104 = and(_T_2044, _T_2103) node _T_2105 = or(UInt<1>(0h0), _T_2104) node _T_2106 = and(_WIRE_7, _T_2105) node _T_2107 = asUInt(reset) node _T_2108 = eq(_T_2107, UInt<1>(0h0)) when _T_2108 : node _T_2109 = eq(_T_2106, UInt<1>(0h0)) when _T_2109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_2106, UInt<1>(0h1), "") : assert_144 node _T_2110 = asUInt(reset) node _T_2111 = eq(_T_2110, UInt<1>(0h0)) when _T_2111 : node _T_2112 = eq(source_ok_2, UInt<1>(0h0)) when _T_2112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_145 node _T_2113 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2114 = asUInt(reset) node _T_2115 = eq(_T_2114, UInt<1>(0h0)) when _T_2115 : node _T_2116 = eq(_T_2113, UInt<1>(0h0)) when _T_2116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_2113, UInt<1>(0h1), "") : assert_146 node _T_2117 = asUInt(reset) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_2120 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2121 = asUInt(reset) node _T_2122 = eq(_T_2121, UInt<1>(0h0)) when _T_2122 : node _T_2123 = eq(_T_2120, UInt<1>(0h0)) when _T_2123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_2120, UInt<1>(0h1), "") : assert_148 node _T_2124 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2125 = asUInt(reset) node _T_2126 = eq(_T_2125, UInt<1>(0h0)) when _T_2126 : node _T_2127 = eq(_T_2124, UInt<1>(0h0)) when _T_2127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_2124, UInt<1>(0h1), "") : assert_149 node _T_2128 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_2128 : node _T_2129 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2130 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2131 = and(_T_2129, _T_2130) node _uncommonBits_T_16 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_2132 = shr(io.in.c.bits.source, 2) node _T_2133 = eq(_T_2132, UInt<1>(0h0)) node _T_2134 = leq(UInt<1>(0h0), uncommonBits_16) node _T_2135 = and(_T_2133, _T_2134) node _T_2136 = leq(uncommonBits_16, UInt<2>(0h2)) node _T_2137 = and(_T_2135, _T_2136) node _T_2138 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2139 = eq(io.in.c.bits.source, UInt<3>(0h4)) node _T_2140 = or(_T_2137, _T_2138) node _T_2141 = or(_T_2140, _T_2139) node _T_2142 = and(_T_2131, _T_2141) node _T_2143 = or(UInt<1>(0h0), _T_2142) node _T_2144 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_2145 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2146 = cvt(_T_2145) node _T_2147 = and(_T_2146, asSInt(UInt<14>(0h2000))) node _T_2148 = asSInt(_T_2147) node _T_2149 = eq(_T_2148, asSInt(UInt<1>(0h0))) node _T_2150 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2151 = cvt(_T_2150) node _T_2152 = and(_T_2151, asSInt(UInt<13>(0h1000))) node _T_2153 = asSInt(_T_2152) node _T_2154 = eq(_T_2153, asSInt(UInt<1>(0h0))) node _T_2155 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2156 = cvt(_T_2155) node _T_2157 = and(_T_2156, asSInt(UInt<17>(0h10000))) node _T_2158 = asSInt(_T_2157) node _T_2159 = eq(_T_2158, asSInt(UInt<1>(0h0))) node _T_2160 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2161 = cvt(_T_2160) node _T_2162 = and(_T_2161, asSInt(UInt<18>(0h2f000))) node _T_2163 = asSInt(_T_2162) node _T_2164 = eq(_T_2163, asSInt(UInt<1>(0h0))) node _T_2165 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2166 = cvt(_T_2165) node _T_2167 = and(_T_2166, asSInt(UInt<17>(0h10000))) node _T_2168 = asSInt(_T_2167) node _T_2169 = eq(_T_2168, asSInt(UInt<1>(0h0))) node _T_2170 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2171 = cvt(_T_2170) node _T_2172 = and(_T_2171, asSInt(UInt<13>(0h1000))) node _T_2173 = asSInt(_T_2172) node _T_2174 = eq(_T_2173, asSInt(UInt<1>(0h0))) node _T_2175 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2176 = cvt(_T_2175) node _T_2177 = and(_T_2176, asSInt(UInt<27>(0h4000000))) node _T_2178 = asSInt(_T_2177) node _T_2179 = eq(_T_2178, asSInt(UInt<1>(0h0))) node _T_2180 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2181 = cvt(_T_2180) node _T_2182 = and(_T_2181, asSInt(UInt<13>(0h1000))) node _T_2183 = asSInt(_T_2182) node _T_2184 = eq(_T_2183, asSInt(UInt<1>(0h0))) node _T_2185 = or(_T_2149, _T_2154) node _T_2186 = or(_T_2185, _T_2159) node _T_2187 = or(_T_2186, _T_2164) node _T_2188 = or(_T_2187, _T_2169) node _T_2189 = or(_T_2188, _T_2174) node _T_2190 = or(_T_2189, _T_2179) node _T_2191 = or(_T_2190, _T_2184) node _T_2192 = and(_T_2144, _T_2191) node _T_2193 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2194 = or(UInt<1>(0h0), _T_2193) node _T_2195 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2196 = cvt(_T_2195) node _T_2197 = and(_T_2196, asSInt(UInt<17>(0h10000))) node _T_2198 = asSInt(_T_2197) node _T_2199 = eq(_T_2198, asSInt(UInt<1>(0h0))) node _T_2200 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2201 = cvt(_T_2200) node _T_2202 = and(_T_2201, asSInt(UInt<29>(0h10000000))) node _T_2203 = asSInt(_T_2202) node _T_2204 = eq(_T_2203, asSInt(UInt<1>(0h0))) node _T_2205 = or(_T_2199, _T_2204) node _T_2206 = and(_T_2194, _T_2205) node _T_2207 = or(UInt<1>(0h0), _T_2192) node _T_2208 = or(_T_2207, _T_2206) node _T_2209 = and(_T_2143, _T_2208) node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : node _T_2212 = eq(_T_2209, UInt<1>(0h0)) when _T_2212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_2209, UInt<1>(0h1), "") : assert_150 node _uncommonBits_T_17 = or(io.in.c.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_2213 = shr(io.in.c.bits.source, 2) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) node _T_2215 = leq(UInt<1>(0h0), uncommonBits_17) node _T_2216 = and(_T_2214, _T_2215) node _T_2217 = leq(uncommonBits_17, UInt<2>(0h2)) node _T_2218 = and(_T_2216, _T_2217) node _T_2219 = eq(io.in.c.bits.source, UInt<2>(0h3)) node _T_2220 = eq(io.in.c.bits.source, UInt<3>(0h4)) wire _WIRE_8 : UInt<1>[3] connect _WIRE_8[0], _T_2218 connect _WIRE_8[1], _T_2219 connect _WIRE_8[2], _T_2220 node _T_2221 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_2222 = mux(_WIRE_8[0], _T_2221, UInt<1>(0h0)) node _T_2223 = mux(_WIRE_8[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_2224 = mux(_WIRE_8[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_2225 = or(_T_2222, _T_2223) node _T_2226 = or(_T_2225, _T_2224) wire _WIRE_9 : UInt<1> connect _WIRE_9, _T_2226 node _T_2227 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_2228 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_2229 = and(_T_2227, _T_2228) node _T_2230 = or(UInt<1>(0h0), _T_2229) node _T_2231 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_2232 = cvt(_T_2231) node _T_2233 = and(_T_2232, asSInt(UInt<14>(0h2000))) node _T_2234 = asSInt(_T_2233) node _T_2235 = eq(_T_2234, asSInt(UInt<1>(0h0))) node _T_2236 = xor(io.in.c.bits.address, UInt<14>(0h3000)) node _T_2237 = cvt(_T_2236) node _T_2238 = and(_T_2237, asSInt(UInt<13>(0h1000))) node _T_2239 = asSInt(_T_2238) node _T_2240 = eq(_T_2239, asSInt(UInt<1>(0h0))) node _T_2241 = xor(io.in.c.bits.address, UInt<17>(0h10000)) node _T_2242 = cvt(_T_2241) node _T_2243 = and(_T_2242, asSInt(UInt<17>(0h10000))) node _T_2244 = asSInt(_T_2243) node _T_2245 = eq(_T_2244, asSInt(UInt<1>(0h0))) node _T_2246 = xor(io.in.c.bits.address, UInt<21>(0h100000)) node _T_2247 = cvt(_T_2246) node _T_2248 = and(_T_2247, asSInt(UInt<18>(0h2f000))) node _T_2249 = asSInt(_T_2248) node _T_2250 = eq(_T_2249, asSInt(UInt<1>(0h0))) node _T_2251 = xor(io.in.c.bits.address, UInt<26>(0h2000000)) node _T_2252 = cvt(_T_2251) node _T_2253 = and(_T_2252, asSInt(UInt<17>(0h10000))) node _T_2254 = asSInt(_T_2253) node _T_2255 = eq(_T_2254, asSInt(UInt<1>(0h0))) node _T_2256 = xor(io.in.c.bits.address, UInt<26>(0h2010000)) node _T_2257 = cvt(_T_2256) node _T_2258 = and(_T_2257, asSInt(UInt<13>(0h1000))) node _T_2259 = asSInt(_T_2258) node _T_2260 = eq(_T_2259, asSInt(UInt<1>(0h0))) node _T_2261 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_2262 = cvt(_T_2261) node _T_2263 = and(_T_2262, asSInt(UInt<17>(0h10000))) node _T_2264 = asSInt(_T_2263) node _T_2265 = eq(_T_2264, asSInt(UInt<1>(0h0))) node _T_2266 = xor(io.in.c.bits.address, UInt<28>(0hc000000)) node _T_2267 = cvt(_T_2266) node _T_2268 = and(_T_2267, asSInt(UInt<27>(0h4000000))) node _T_2269 = asSInt(_T_2268) node _T_2270 = eq(_T_2269, asSInt(UInt<1>(0h0))) node _T_2271 = xor(io.in.c.bits.address, UInt<29>(0h10020000)) node _T_2272 = cvt(_T_2271) node _T_2273 = and(_T_2272, asSInt(UInt<13>(0h1000))) node _T_2274 = asSInt(_T_2273) node _T_2275 = eq(_T_2274, asSInt(UInt<1>(0h0))) node _T_2276 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_2277 = cvt(_T_2276) node _T_2278 = and(_T_2277, asSInt(UInt<29>(0h10000000))) node _T_2279 = asSInt(_T_2278) node _T_2280 = eq(_T_2279, asSInt(UInt<1>(0h0))) node _T_2281 = or(_T_2235, _T_2240) node _T_2282 = or(_T_2281, _T_2245) node _T_2283 = or(_T_2282, _T_2250) node _T_2284 = or(_T_2283, _T_2255) node _T_2285 = or(_T_2284, _T_2260) node _T_2286 = or(_T_2285, _T_2265) node _T_2287 = or(_T_2286, _T_2270) node _T_2288 = or(_T_2287, _T_2275) node _T_2289 = or(_T_2288, _T_2280) node _T_2290 = and(_T_2230, _T_2289) node _T_2291 = or(UInt<1>(0h0), _T_2290) node _T_2292 = and(_WIRE_9, _T_2291) node _T_2293 = asUInt(reset) node _T_2294 = eq(_T_2293, UInt<1>(0h0)) when _T_2294 : node _T_2295 = eq(_T_2292, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_2292, UInt<1>(0h1), "") : assert_151 node _T_2296 = asUInt(reset) node _T_2297 = eq(_T_2296, UInt<1>(0h0)) when _T_2297 : node _T_2298 = eq(source_ok_2, UInt<1>(0h0)) when _T_2298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_152 node _T_2299 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : node _T_2302 = eq(_T_2299, UInt<1>(0h0)) when _T_2302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_2299, UInt<1>(0h1), "") : assert_153 node _T_2303 = asUInt(reset) node _T_2304 = eq(_T_2303, UInt<1>(0h0)) when _T_2304 : node _T_2305 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_2306 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_2307 = asUInt(reset) node _T_2308 = eq(_T_2307, UInt<1>(0h0)) when _T_2308 : node _T_2309 = eq(_T_2306, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_2306, UInt<1>(0h1), "") : assert_155 node _T_2310 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_2310 : node _T_2311 = asUInt(reset) node _T_2312 = eq(_T_2311, UInt<1>(0h0)) when _T_2312 : node _T_2313 = eq(address_ok_1, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : node _T_2316 = eq(source_ok_2, UInt<1>(0h0)) when _T_2316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_157 node _T_2317 = asUInt(reset) node _T_2318 = eq(_T_2317, UInt<1>(0h0)) when _T_2318 : node _T_2319 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_2320 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2321 = asUInt(reset) node _T_2322 = eq(_T_2321, UInt<1>(0h0)) when _T_2322 : node _T_2323 = eq(_T_2320, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_2320, UInt<1>(0h1), "") : assert_159 node _T_2324 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2325 = asUInt(reset) node _T_2326 = eq(_T_2325, UInt<1>(0h0)) when _T_2326 : node _T_2327 = eq(_T_2324, UInt<1>(0h0)) when _T_2327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_2324, UInt<1>(0h1), "") : assert_160 node _T_2328 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_2328 : node _T_2329 = asUInt(reset) node _T_2330 = eq(_T_2329, UInt<1>(0h0)) when _T_2330 : node _T_2331 = eq(address_ok_1, UInt<1>(0h0)) when _T_2331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_2332 = asUInt(reset) node _T_2333 = eq(_T_2332, UInt<1>(0h0)) when _T_2333 : node _T_2334 = eq(source_ok_2, UInt<1>(0h0)) when _T_2334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_162 node _T_2335 = asUInt(reset) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) when _T_2336 : node _T_2337 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_2338 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2339 = asUInt(reset) node _T_2340 = eq(_T_2339, UInt<1>(0h0)) when _T_2340 : node _T_2341 = eq(_T_2338, UInt<1>(0h0)) when _T_2341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_2338, UInt<1>(0h1), "") : assert_164 node _T_2342 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_2342 : node _T_2343 = asUInt(reset) node _T_2344 = eq(_T_2343, UInt<1>(0h0)) when _T_2344 : node _T_2345 = eq(address_ok_1, UInt<1>(0h0)) when _T_2345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_2346 = asUInt(reset) node _T_2347 = eq(_T_2346, UInt<1>(0h0)) when _T_2347 : node _T_2348 = eq(source_ok_2, UInt<1>(0h0)) when _T_2348 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, source_ok_2, UInt<1>(0h1), "") : assert_166 node _T_2349 = asUInt(reset) node _T_2350 = eq(_T_2349, UInt<1>(0h0)) when _T_2350 : node _T_2351 = eq(is_aligned_2, UInt<1>(0h0)) when _T_2351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_2352 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_2353 = asUInt(reset) node _T_2354 = eq(_T_2353, UInt<1>(0h0)) when _T_2354 : node _T_2355 = eq(_T_2352, UInt<1>(0h0)) when _T_2355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_2352, UInt<1>(0h1), "") : assert_168 node _T_2356 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_2357 = asUInt(reset) node _T_2358 = eq(_T_2357, UInt<1>(0h0)) when _T_2358 : node _T_2359 = eq(_T_2356, UInt<1>(0h0)) when _T_2359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_2356, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_2360 = asUInt(reset) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) when _T_2361 : node _T_2362 = eq(sink_ok_1, UInt<1>(0h0)) when _T_2362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_2363 = eq(a_first, UInt<1>(0h0)) node _T_2364 = and(io.in.a.valid, _T_2363) when _T_2364 : node _T_2365 = eq(io.in.a.bits.opcode, opcode) node _T_2366 = asUInt(reset) node _T_2367 = eq(_T_2366, UInt<1>(0h0)) when _T_2367 : node _T_2368 = eq(_T_2365, UInt<1>(0h0)) when _T_2368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_2365, UInt<1>(0h1), "") : assert_171 node _T_2369 = eq(io.in.a.bits.param, param) node _T_2370 = asUInt(reset) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) when _T_2371 : node _T_2372 = eq(_T_2369, UInt<1>(0h0)) when _T_2372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_2369, UInt<1>(0h1), "") : assert_172 node _T_2373 = eq(io.in.a.bits.size, size) node _T_2374 = asUInt(reset) node _T_2375 = eq(_T_2374, UInt<1>(0h0)) when _T_2375 : node _T_2376 = eq(_T_2373, UInt<1>(0h0)) when _T_2376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_2373, UInt<1>(0h1), "") : assert_173 node _T_2377 = eq(io.in.a.bits.source, source) node _T_2378 = asUInt(reset) node _T_2379 = eq(_T_2378, UInt<1>(0h0)) when _T_2379 : node _T_2380 = eq(_T_2377, UInt<1>(0h0)) when _T_2380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_2377, UInt<1>(0h1), "") : assert_174 node _T_2381 = eq(io.in.a.bits.address, address) node _T_2382 = asUInt(reset) node _T_2383 = eq(_T_2382, UInt<1>(0h0)) when _T_2383 : node _T_2384 = eq(_T_2381, UInt<1>(0h0)) when _T_2384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_2381, UInt<1>(0h1), "") : assert_175 node _T_2385 = and(io.in.a.ready, io.in.a.valid) node _T_2386 = and(_T_2385, a_first) when _T_2386 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_2387 = eq(d_first, UInt<1>(0h0)) node _T_2388 = and(io.in.d.valid, _T_2387) when _T_2388 : node _T_2389 = eq(io.in.d.bits.opcode, opcode_1) node _T_2390 = asUInt(reset) node _T_2391 = eq(_T_2390, UInt<1>(0h0)) when _T_2391 : node _T_2392 = eq(_T_2389, UInt<1>(0h0)) when _T_2392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_2389, UInt<1>(0h1), "") : assert_176 node _T_2393 = eq(io.in.d.bits.param, param_1) node _T_2394 = asUInt(reset) node _T_2395 = eq(_T_2394, UInt<1>(0h0)) when _T_2395 : node _T_2396 = eq(_T_2393, UInt<1>(0h0)) when _T_2396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_2393, UInt<1>(0h1), "") : assert_177 node _T_2397 = eq(io.in.d.bits.size, size_1) node _T_2398 = asUInt(reset) node _T_2399 = eq(_T_2398, UInt<1>(0h0)) when _T_2399 : node _T_2400 = eq(_T_2397, UInt<1>(0h0)) when _T_2400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_2397, UInt<1>(0h1), "") : assert_178 node _T_2401 = eq(io.in.d.bits.source, source_1) node _T_2402 = asUInt(reset) node _T_2403 = eq(_T_2402, UInt<1>(0h0)) when _T_2403 : node _T_2404 = eq(_T_2401, UInt<1>(0h0)) when _T_2404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_2401, UInt<1>(0h1), "") : assert_179 node _T_2405 = eq(io.in.d.bits.sink, sink) node _T_2406 = asUInt(reset) node _T_2407 = eq(_T_2406, UInt<1>(0h0)) when _T_2407 : node _T_2408 = eq(_T_2405, UInt<1>(0h0)) when _T_2408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_2405, UInt<1>(0h1), "") : assert_180 node _T_2409 = eq(io.in.d.bits.denied, denied) node _T_2410 = asUInt(reset) node _T_2411 = eq(_T_2410, UInt<1>(0h0)) when _T_2411 : node _T_2412 = eq(_T_2409, UInt<1>(0h0)) when _T_2412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_2409, UInt<1>(0h1), "") : assert_181 node _T_2413 = and(io.in.d.ready, io.in.d.valid) node _T_2414 = and(_T_2413, d_first) when _T_2414 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 11, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_2415 = eq(b_first, UInt<1>(0h0)) node _T_2416 = and(io.in.b.valid, _T_2415) when _T_2416 : node _T_2417 = eq(io.in.b.bits.opcode, opcode_2) node _T_2418 = asUInt(reset) node _T_2419 = eq(_T_2418, UInt<1>(0h0)) when _T_2419 : node _T_2420 = eq(_T_2417, UInt<1>(0h0)) when _T_2420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_2417, UInt<1>(0h1), "") : assert_182 node _T_2421 = eq(io.in.b.bits.param, param_2) node _T_2422 = asUInt(reset) node _T_2423 = eq(_T_2422, UInt<1>(0h0)) when _T_2423 : node _T_2424 = eq(_T_2421, UInt<1>(0h0)) when _T_2424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_2421, UInt<1>(0h1), "") : assert_183 node _T_2425 = eq(io.in.b.bits.size, size_2) node _T_2426 = asUInt(reset) node _T_2427 = eq(_T_2426, UInt<1>(0h0)) when _T_2427 : node _T_2428 = eq(_T_2425, UInt<1>(0h0)) when _T_2428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_2425, UInt<1>(0h1), "") : assert_184 node _T_2429 = eq(io.in.b.bits.source, source_2) node _T_2430 = asUInt(reset) node _T_2431 = eq(_T_2430, UInt<1>(0h0)) when _T_2431 : node _T_2432 = eq(_T_2429, UInt<1>(0h0)) when _T_2432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_2429, UInt<1>(0h1), "") : assert_185 node _T_2433 = eq(io.in.b.bits.address, address_1) node _T_2434 = asUInt(reset) node _T_2435 = eq(_T_2434, UInt<1>(0h0)) when _T_2435 : node _T_2436 = eq(_T_2433, UInt<1>(0h0)) when _T_2436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_2433, UInt<1>(0h1), "") : assert_186 node _T_2437 = and(io.in.b.ready, io.in.b.valid) node _T_2438 = and(_T_2437, b_first) when _T_2438 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_2439 = eq(c_first, UInt<1>(0h0)) node _T_2440 = and(io.in.c.valid, _T_2439) when _T_2440 : node _T_2441 = eq(io.in.c.bits.opcode, opcode_3) node _T_2442 = asUInt(reset) node _T_2443 = eq(_T_2442, UInt<1>(0h0)) when _T_2443 : node _T_2444 = eq(_T_2441, UInt<1>(0h0)) when _T_2444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_2441, UInt<1>(0h1), "") : assert_187 node _T_2445 = eq(io.in.c.bits.param, param_3) node _T_2446 = asUInt(reset) node _T_2447 = eq(_T_2446, UInt<1>(0h0)) when _T_2447 : node _T_2448 = eq(_T_2445, UInt<1>(0h0)) when _T_2448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_2445, UInt<1>(0h1), "") : assert_188 node _T_2449 = eq(io.in.c.bits.size, size_3) node _T_2450 = asUInt(reset) node _T_2451 = eq(_T_2450, UInt<1>(0h0)) when _T_2451 : node _T_2452 = eq(_T_2449, UInt<1>(0h0)) when _T_2452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_2449, UInt<1>(0h1), "") : assert_189 node _T_2453 = eq(io.in.c.bits.source, source_3) node _T_2454 = asUInt(reset) node _T_2455 = eq(_T_2454, UInt<1>(0h0)) when _T_2455 : node _T_2456 = eq(_T_2453, UInt<1>(0h0)) when _T_2456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_2453, UInt<1>(0h1), "") : assert_190 node _T_2457 = eq(io.in.c.bits.address, address_2) node _T_2458 = asUInt(reset) node _T_2459 = eq(_T_2458, UInt<1>(0h0)) when _T_2459 : node _T_2460 = eq(_T_2457, UInt<1>(0h0)) when _T_2460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_2457, UInt<1>(0h1), "") : assert_191 node _T_2461 = and(io.in.c.ready, io.in.c.valid) node _T_2462 = and(_T_2461, c_first) when _T_2462 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<5> connect a_set, UInt<5>(0h0) wire a_set_wo_ready : UInt<5> connect a_set_wo_ready, UInt<5>(0h0) wire a_opcodes_set : UInt<20> connect a_opcodes_set, UInt<20>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_2463 = and(io.in.a.valid, a_first_1) node _T_2464 = and(_T_2463, UInt<1>(0h1)) when _T_2464 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_2465 = and(io.in.a.ready, io.in.a.valid) node _T_2466 = and(_T_2465, a_first_1) node _T_2467 = and(_T_2466, UInt<1>(0h1)) when _T_2467 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_2468 = dshr(inflight, io.in.a.bits.source) node _T_2469 = bits(_T_2468, 0, 0) node _T_2470 = eq(_T_2469, UInt<1>(0h0)) node _T_2471 = asUInt(reset) node _T_2472 = eq(_T_2471, UInt<1>(0h0)) when _T_2472 : node _T_2473 = eq(_T_2470, UInt<1>(0h0)) when _T_2473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_2470, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<5> connect d_clr, UInt<5>(0h0) wire d_clr_wo_ready : UInt<5> connect d_clr_wo_ready, UInt<5>(0h0) wire d_opcodes_clr : UInt<20> connect d_opcodes_clr, UInt<20>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2474 = and(io.in.d.valid, d_first_1) node _T_2475 = and(_T_2474, UInt<1>(0h1)) node _T_2476 = eq(d_release_ack, UInt<1>(0h0)) node _T_2477 = and(_T_2475, _T_2476) when _T_2477 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_2478 = and(io.in.d.ready, io.in.d.valid) node _T_2479 = and(_T_2478, d_first_1) node _T_2480 = and(_T_2479, UInt<1>(0h1)) node _T_2481 = eq(d_release_ack, UInt<1>(0h0)) node _T_2482 = and(_T_2480, _T_2481) when _T_2482 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_2483 = and(io.in.d.valid, d_first_1) node _T_2484 = and(_T_2483, UInt<1>(0h1)) node _T_2485 = eq(d_release_ack, UInt<1>(0h0)) node _T_2486 = and(_T_2484, _T_2485) when _T_2486 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_2487 = dshr(inflight, io.in.d.bits.source) node _T_2488 = bits(_T_2487, 0, 0) node _T_2489 = or(_T_2488, same_cycle_resp) node _T_2490 = asUInt(reset) node _T_2491 = eq(_T_2490, UInt<1>(0h0)) when _T_2491 : node _T_2492 = eq(_T_2489, UInt<1>(0h0)) when _T_2492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_2489, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_2493 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_2494 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_2495 = or(_T_2493, _T_2494) node _T_2496 = asUInt(reset) node _T_2497 = eq(_T_2496, UInt<1>(0h0)) when _T_2497 : node _T_2498 = eq(_T_2495, UInt<1>(0h0)) when _T_2498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_2495, UInt<1>(0h1), "") : assert_194 node _T_2499 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_2500 = asUInt(reset) node _T_2501 = eq(_T_2500, UInt<1>(0h0)) when _T_2501 : node _T_2502 = eq(_T_2499, UInt<1>(0h0)) when _T_2502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_2499, UInt<1>(0h1), "") : assert_195 else : node _T_2503 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_2504 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_2505 = or(_T_2503, _T_2504) node _T_2506 = asUInt(reset) node _T_2507 = eq(_T_2506, UInt<1>(0h0)) when _T_2507 : node _T_2508 = eq(_T_2505, UInt<1>(0h0)) when _T_2508 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_2505, UInt<1>(0h1), "") : assert_196 node _T_2509 = eq(io.in.d.bits.size, a_size_lookup) node _T_2510 = asUInt(reset) node _T_2511 = eq(_T_2510, UInt<1>(0h0)) when _T_2511 : node _T_2512 = eq(_T_2509, UInt<1>(0h0)) when _T_2512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_2509, UInt<1>(0h1), "") : assert_197 node _T_2513 = and(io.in.d.valid, d_first_1) node _T_2514 = and(_T_2513, a_first_1) node _T_2515 = and(_T_2514, io.in.a.valid) node _T_2516 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_2517 = and(_T_2515, _T_2516) node _T_2518 = eq(d_release_ack, UInt<1>(0h0)) node _T_2519 = and(_T_2517, _T_2518) when _T_2519 : node _T_2520 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2521 = or(_T_2520, io.in.a.ready) node _T_2522 = asUInt(reset) node _T_2523 = eq(_T_2522, UInt<1>(0h0)) when _T_2523 : node _T_2524 = eq(_T_2521, UInt<1>(0h0)) when _T_2524 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_2521, UInt<1>(0h1), "") : assert_198 node _T_2525 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_2526 = orr(a_set_wo_ready) node _T_2527 = eq(_T_2526, UInt<1>(0h0)) node _T_2528 = or(_T_2525, _T_2527) node _T_2529 = asUInt(reset) node _T_2530 = eq(_T_2529, UInt<1>(0h0)) when _T_2530 : node _T_2531 = eq(_T_2528, UInt<1>(0h0)) when _T_2531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_2528, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_80 node _T_2532 = orr(inflight) node _T_2533 = eq(_T_2532, UInt<1>(0h0)) node _T_2534 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_2535 = or(_T_2533, _T_2534) node _T_2536 = lt(watchdog, plusarg_reader.out) node _T_2537 = or(_T_2535, _T_2536) node _T_2538 = asUInt(reset) node _T_2539 = eq(_T_2538, UInt<1>(0h0)) when _T_2539 : node _T_2540 = eq(_T_2537, UInt<1>(0h0)) when _T_2540 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_2537, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_2541 = and(io.in.a.ready, io.in.a.valid) node _T_2542 = and(io.in.d.ready, io.in.d.valid) node _T_2543 = or(_T_2541, _T_2542) when _T_2543 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<5>, clock, reset, UInt<5>(0h0) regreset inflight_opcodes_1 : UInt<20>, clock, reset, UInt<20>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 11, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<5> connect c_set, UInt<5>(0h0) wire c_set_wo_ready : UInt<5> connect c_set_wo_ready, UInt<5>(0h0) wire c_opcodes_set : UInt<20> connect c_opcodes_set, UInt<20>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) node _T_2544 = and(io.in.c.valid, c_first_1) node _T_2545 = bits(io.in.c.bits.opcode, 2, 2) node _T_2546 = bits(io.in.c.bits.opcode, 1, 1) node _T_2547 = and(_T_2545, _T_2546) node _T_2548 = and(_T_2544, _T_2547) when _T_2548 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_2549 = and(io.in.c.ready, io.in.c.valid) node _T_2550 = and(_T_2549, c_first_1) node _T_2551 = bits(io.in.c.bits.opcode, 2, 2) node _T_2552 = bits(io.in.c.bits.opcode, 1, 1) node _T_2553 = and(_T_2551, _T_2552) node _T_2554 = and(_T_2550, _T_2553) when _T_2554 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_2555 = dshr(inflight_1, io.in.c.bits.source) node _T_2556 = bits(_T_2555, 0, 0) node _T_2557 = eq(_T_2556, UInt<1>(0h0)) node _T_2558 = asUInt(reset) node _T_2559 = eq(_T_2558, UInt<1>(0h0)) when _T_2559 : node _T_2560 = eq(_T_2557, UInt<1>(0h0)) when _T_2560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_2557, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<5> connect d_clr_1, UInt<5>(0h0) wire d_clr_wo_ready_1 : UInt<5> connect d_clr_wo_ready_1, UInt<5>(0h0) wire d_opcodes_clr_1 : UInt<20> connect d_opcodes_clr_1, UInt<20>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_2561 = and(io.in.d.valid, d_first_2) node _T_2562 = and(_T_2561, UInt<1>(0h1)) node _T_2563 = and(_T_2562, d_release_ack_1) when _T_2563 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_2564 = and(io.in.d.ready, io.in.d.valid) node _T_2565 = and(_T_2564, d_first_2) node _T_2566 = and(_T_2565, UInt<1>(0h1)) node _T_2567 = and(_T_2566, d_release_ack_1) when _T_2567 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_2568 = and(io.in.d.valid, d_first_2) node _T_2569 = and(_T_2568, UInt<1>(0h1)) node _T_2570 = and(_T_2569, d_release_ack_1) when _T_2570 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_2571 = dshr(inflight_1, io.in.d.bits.source) node _T_2572 = bits(_T_2571, 0, 0) node _T_2573 = or(_T_2572, same_cycle_resp_1) node _T_2574 = asUInt(reset) node _T_2575 = eq(_T_2574, UInt<1>(0h0)) when _T_2575 : node _T_2576 = eq(_T_2573, UInt<1>(0h0)) when _T_2576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_2573, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_2577 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_2578 = asUInt(reset) node _T_2579 = eq(_T_2578, UInt<1>(0h0)) when _T_2579 : node _T_2580 = eq(_T_2577, UInt<1>(0h0)) when _T_2580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_2577, UInt<1>(0h1), "") : assert_203 else : node _T_2581 = eq(io.in.d.bits.size, c_size_lookup) node _T_2582 = asUInt(reset) node _T_2583 = eq(_T_2582, UInt<1>(0h0)) when _T_2583 : node _T_2584 = eq(_T_2581, UInt<1>(0h0)) when _T_2584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_2581, UInt<1>(0h1), "") : assert_204 node _T_2585 = and(io.in.d.valid, d_first_2) node _T_2586 = and(_T_2585, c_first_1) node _T_2587 = and(_T_2586, io.in.c.valid) node _T_2588 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_2589 = and(_T_2587, _T_2588) node _T_2590 = and(_T_2589, d_release_ack_1) node _T_2591 = eq(c_probe_ack, UInt<1>(0h0)) node _T_2592 = and(_T_2590, _T_2591) when _T_2592 : node _T_2593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_2594 = or(_T_2593, io.in.c.ready) node _T_2595 = asUInt(reset) node _T_2596 = eq(_T_2595, UInt<1>(0h0)) when _T_2596 : node _T_2597 = eq(_T_2594, UInt<1>(0h0)) when _T_2597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_2594, UInt<1>(0h1), "") : assert_205 node _T_2598 = orr(c_set_wo_ready) when _T_2598 : node _T_2599 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_2600 = asUInt(reset) node _T_2601 = eq(_T_2600, UInt<1>(0h0)) when _T_2601 : node _T_2602 = eq(_T_2599, UInt<1>(0h0)) when _T_2602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_2599, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_81 node _T_2603 = orr(inflight_1) node _T_2604 = eq(_T_2603, UInt<1>(0h0)) node _T_2605 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_2606 = or(_T_2604, _T_2605) node _T_2607 = lt(watchdog_1, plusarg_reader_1.out) node _T_2608 = or(_T_2606, _T_2607) node _T_2609 = asUInt(reset) node _T_2610 = eq(_T_2609, UInt<1>(0h0)) when _T_2610 : node _T_2611 = eq(_T_2608, UInt<1>(0h0)) when _T_2611 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_2608, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_2612 = and(io.in.c.ready, io.in.c.valid) node _T_2613 = and(io.in.d.ready, io.in.d.valid) node _T_2614 = or(_T_2612, _T_2613) when _T_2614 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 11, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_2615 = and(io.in.d.ready, io.in.d.valid) node _T_2616 = and(_T_2615, d_first_3) node _T_2617 = bits(io.in.d.bits.opcode, 2, 2) node _T_2618 = bits(io.in.d.bits.opcode, 1, 1) node _T_2619 = eq(_T_2618, UInt<1>(0h0)) node _T_2620 = and(_T_2617, _T_2619) node _T_2621 = and(_T_2616, _T_2620) when _T_2621 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_2622 = dshr(inflight_2, io.in.d.bits.sink) node _T_2623 = bits(_T_2622, 0, 0) node _T_2624 = eq(_T_2623, UInt<1>(0h0)) node _T_2625 = asUInt(reset) node _T_2626 = eq(_T_2625, UInt<1>(0h0)) when _T_2626 : node _T_2627 = eq(_T_2624, UInt<1>(0h0)) when _T_2627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_2624, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_2628 = and(io.in.e.ready, io.in.e.valid) node _T_2629 = and(_T_2628, UInt<1>(0h1)) node _T_2630 = and(_T_2629, UInt<1>(0h1)) when _T_2630 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_2631 = or(d_set, inflight_2) node _T_2632 = dshr(_T_2631, io.in.e.bits.sink) node _T_2633 = bits(_T_2632, 0, 0) node _T_2634 = asUInt(reset) node _T_2635 = eq(_T_2634, UInt<1>(0h0)) when _T_2635 : node _T_2636 = eq(_T_2633, UInt<1>(0h0)) when _T_2636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/boom/src/main/scala/v4/common/tile.scala:97:36)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_2633, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_40( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_b_ready, // @[Monitor.scala:20:14] input io_in_b_valid, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_b_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_b_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_b_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_b_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_b_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_b_bits_data, // @[Monitor.scala:20:14] input io_in_b_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_ready, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Monitor.scala:36:7] wire io_in_b_valid_0 = io_in_b_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode_0 = io_in_b_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_b_bits_param_0 = io_in_b_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_b_bits_size_0 = io_in_b_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_source_0 = io_in_b_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_b_bits_address_0 = io_in_b_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_b_bits_mask_0 = io_in_b_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data_0 = io_in_b_bits_data; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt_0 = io_in_b_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_ready_0 = io_in_e_ready; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [8:0] b_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] b_first_count = 9'h0; // @[Edges.scala:234:25] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire _legal_source_T_8 = 1'h0; // @[Mux.scala:30:73] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T_3 = io_in_b_bits_size_0; // @[Misc.scala:202:34] wire [2:0] _uncommonBits_T_11 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _legal_source_uncommonBits_T = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_12 = io_in_b_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T = io_in_b_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_13 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_14 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_15 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_16 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [2:0] _uncommonBits_T_17 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_70 = io_in_c_bits_address_0; // @[Monitor.scala:36:7] wire [2:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = ~_source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_4 = source_ok_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_3 & _source_ok_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire _source_ok_T_6 = io_in_a_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire _source_ok_T_7 = io_in_a_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2 = _source_ok_T_7; // @[Parameters.scala:1138:31] wire _source_ok_T_8 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_8 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_9 = io_in_d_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_10 = ~_source_ok_T_9; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_13 = source_ok_uncommonBits_1 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_14 = _source_ok_T_12 & _source_ok_T_13; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_14; // @[Parameters.scala:1138:31] wire _source_ok_T_15 = io_in_d_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_1 = _source_ok_T_15; // @[Parameters.scala:1138:31] wire _source_ok_T_16 = io_in_d_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_2 = _source_ok_T_16; // @[Parameters.scala:1138:31] wire _source_ok_T_17 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_17 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T = io_in_b_bits_source_0[2]; // @[Monitor.scala:36:7] wire _legal_source_T_6 = io_in_b_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _legal_source_T_7 = io_in_b_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_1 = {1'h0, _address_ok_T}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_2 = _address_ok_T_1 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_3 = _address_ok_T_2; // @[Parameters.scala:137:46] wire _address_ok_T_4 = _address_ok_T_3 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_0 = _address_ok_T_4; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_5 = {io_in_b_bits_address_0[31:13], io_in_b_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_6 = {1'h0, _address_ok_T_5}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_7 = _address_ok_T_6 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_8 = _address_ok_T_7; // @[Parameters.scala:137:46] wire _address_ok_T_9 = _address_ok_T_8 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1 = _address_ok_T_9; // @[Parameters.scala:612:40] wire [13:0] _GEN_0 = io_in_b_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_b_bits_address_0[31:14], _GEN_0}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_2 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [16:0] _GEN_1 = io_in_b_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_15 = {io_in_b_bits_address_0[31:17], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_3 = _address_ok_T_19; // @[Parameters.scala:612:40] wire [20:0] _GEN_2 = io_in_b_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_20 = {io_in_b_bits_address_0[31:21], _GEN_2}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_21 = {1'h0, _address_ok_T_20}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_22 = _address_ok_T_21 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_23 = _address_ok_T_22; // @[Parameters.scala:137:46] wire _address_ok_T_24 = _address_ok_T_23 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_4 = _address_ok_T_24; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_25 = {io_in_b_bits_address_0[31:21], io_in_b_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_26 = {1'h0, _address_ok_T_25}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_27 = _address_ok_T_26 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_28 = _address_ok_T_27; // @[Parameters.scala:137:46] wire _address_ok_T_29 = _address_ok_T_28 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_5 = _address_ok_T_29; // @[Parameters.scala:612:40] wire [25:0] _GEN_3 = io_in_b_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_30 = {io_in_b_bits_address_0[31:26], _GEN_3}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_31 = {1'h0, _address_ok_T_30}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_32 = _address_ok_T_31 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_33 = _address_ok_T_32; // @[Parameters.scala:137:46] wire _address_ok_T_34 = _address_ok_T_33 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_6 = _address_ok_T_34; // @[Parameters.scala:612:40] wire [25:0] _GEN_4 = io_in_b_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_35 = {io_in_b_bits_address_0[31:26], _GEN_4}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_36 = {1'h0, _address_ok_T_35}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_37 = _address_ok_T_36 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_38 = _address_ok_T_37; // @[Parameters.scala:137:46] wire _address_ok_T_39 = _address_ok_T_38 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_7 = _address_ok_T_39; // @[Parameters.scala:612:40] wire [27:0] _GEN_5 = io_in_b_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_40 = {io_in_b_bits_address_0[31:28], _GEN_5}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_41 = {1'h0, _address_ok_T_40}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_42 = _address_ok_T_41 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_43 = _address_ok_T_42; // @[Parameters.scala:137:46] wire _address_ok_T_44 = _address_ok_T_43 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_8 = _address_ok_T_44; // @[Parameters.scala:612:40] wire [27:0] _GEN_6 = io_in_b_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_45 = {io_in_b_bits_address_0[31:28], _GEN_6}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_46 = {1'h0, _address_ok_T_45}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_47 = _address_ok_T_46 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_48 = _address_ok_T_47; // @[Parameters.scala:137:46] wire _address_ok_T_49 = _address_ok_T_48 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_9 = _address_ok_T_49; // @[Parameters.scala:612:40] wire [28:0] _GEN_7 = io_in_b_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_50 = {io_in_b_bits_address_0[31:29], _GEN_7}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_51 = {1'h0, _address_ok_T_50}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_52 = _address_ok_T_51 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_53 = _address_ok_T_52; // @[Parameters.scala:137:46] wire _address_ok_T_54 = _address_ok_T_53 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_10 = _address_ok_T_54; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_55 = io_in_b_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_56 = {1'h0, _address_ok_T_55}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_57 = _address_ok_T_56 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_58 = _address_ok_T_57; // @[Parameters.scala:137:46] wire _address_ok_T_59 = _address_ok_T_58 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_11 = _address_ok_T_59; // @[Parameters.scala:612:40] wire _address_ok_T_60 = _address_ok_WIRE_0 | _address_ok_WIRE_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_61 = _address_ok_T_60 | _address_ok_WIRE_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_62 = _address_ok_T_61 | _address_ok_WIRE_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_63 = _address_ok_T_62 | _address_ok_WIRE_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_64 = _address_ok_T_63 | _address_ok_WIRE_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_65 = _address_ok_T_64 | _address_ok_WIRE_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_66 = _address_ok_T_65 | _address_ok_WIRE_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_67 = _address_ok_T_66 | _address_ok_WIRE_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_68 = _address_ok_T_67 | _address_ok_WIRE_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_69 = _address_ok_T_68 | _address_ok_WIRE_10; // @[Parameters.scala:612:40, :636:64] wire address_ok = _address_ok_T_69 | _address_ok_WIRE_11; // @[Parameters.scala:612:40, :636:64] wire [26:0] _GEN_8 = 27'hFFF << io_in_b_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_2; // @[package.scala:243:71] assign _is_aligned_mask_T_2 = _GEN_8; // @[package.scala:243:71] wire [26:0] _b_first_beats1_decode_T; // @[package.scala:243:71] assign _b_first_beats1_decode_T = _GEN_8; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_3 = _is_aligned_mask_T_2[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_1 = ~_is_aligned_mask_T_3; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_1 = {20'h0, io_in_b_bits_address_0[11:0] & is_aligned_mask_1}; // @[package.scala:243:46] wire is_aligned_1 = _is_aligned_T_1 == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount_1 = _mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_4 = 4'h1 << mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_5 = _mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH_1 = {_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1_1 = io_in_b_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit_1 = io_in_b_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2_1 = mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit_1 = ~mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2_1 = mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size_1 & mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size_1 & mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1_1 = mask_sub_sub_sub_0_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size_1 = mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit_1 = io_in_b_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit_1 = ~mask_sub_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2_1 = mask_sub_sub_0_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size_1 & mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2_1 = mask_sub_sub_0_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size_1 & mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1_1 = mask_sub_sub_0_1_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2_1 = mask_sub_sub_1_2_1 & mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size_1 & mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2_1 = mask_sub_sub_1_2_1 & mask_sub_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size_1 & mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1_1 = mask_sub_sub_1_1_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size_1 = mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit_1 = io_in_b_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit_1 = ~mask_bit_1; // @[Misc.scala:210:26, :211:20] wire mask_eq_8 = mask_sub_0_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size_1 & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_0_1_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_0_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size_1 & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_0_1_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_1_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size_1 & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_1_1_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_1_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size_1 & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_1_1_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_2_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size_1 & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_2_1_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_2_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size_1 & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_2_1_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_3_2_1 & mask_nbit_1; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size_1 & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_3_1_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_3_2_1 & mask_bit_1; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size_1 & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_3_1_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_1 = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_1 = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_1 = {mask_lo_hi_1, mask_lo_lo_1}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_1 = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_1 = {mask_hi_hi_1, mask_hi_lo_1}; // @[Misc.scala:222:10] wire [7:0] mask_1 = {mask_hi_1, mask_lo_1}; // @[Misc.scala:222:10] wire [1:0] legal_source_uncommonBits = _legal_source_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire _legal_source_T_1 = ~_legal_source_T; // @[Parameters.scala:54:{10,32}] wire _legal_source_T_3 = _legal_source_T_1; // @[Parameters.scala:54:{32,67}] wire _legal_source_T_4 = legal_source_uncommonBits != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _legal_source_T_5 = _legal_source_T_3 & _legal_source_T_4; // @[Parameters.scala:54:67, :56:48, :57:20] wire _legal_source_WIRE_0 = _legal_source_T_5; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_1 = _legal_source_T_6; // @[Parameters.scala:1138:31] wire _legal_source_WIRE_2 = _legal_source_T_7; // @[Parameters.scala:1138:31] wire [1:0] _legal_source_T_9 = {2{_legal_source_WIRE_1}}; // @[Mux.scala:30:73] wire [1:0] _legal_source_T_11 = _legal_source_T_9; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_10 = {_legal_source_WIRE_2, 2'h0}; // @[Mux.scala:30:73] wire [2:0] _legal_source_T_12 = {1'h0, _legal_source_T_11} | _legal_source_T_10; // @[Mux.scala:30:73] wire [2:0] _legal_source_WIRE_1_0 = _legal_source_T_12; // @[Mux.scala:30:73] wire legal_source = _legal_source_WIRE_1_0 == io_in_b_bits_source_0; // @[Mux.scala:30:73] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_18 = io_in_c_bits_source_0[2]; // @[Monitor.scala:36:7] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_22 = source_ok_uncommonBits_2 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_23 = _source_ok_T_21 & _source_ok_T_22; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = io_in_c_bits_source_0 == 3'h3; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_1 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_c_bits_source_0 == 3'h4; // @[Monitor.scala:36:7] wire _source_ok_WIRE_2_2 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = _source_ok_WIRE_2_0 | _source_ok_WIRE_2_1; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_2 = _source_ok_T_26 | _source_ok_WIRE_2_2; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN_9 = 27'hFFF << io_in_c_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_9; // @[package.scala:243:71] wire [26:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_9; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {20'h0, io_in_c_bits_address_0[11:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [32:0] _address_ok_T_71 = {1'h0, _address_ok_T_70}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_72 = _address_ok_T_71 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_73 = _address_ok_T_72; // @[Parameters.scala:137:46] wire _address_ok_T_74 = _address_ok_T_73 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_74; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_75 = {io_in_c_bits_address_0[31:13], io_in_c_bits_address_0[12:0] ^ 13'h1000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_76 = {1'h0, _address_ok_T_75}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_77 = _address_ok_T_76 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_78 = _address_ok_T_77; // @[Parameters.scala:137:46] wire _address_ok_T_79 = _address_ok_T_78 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_79; // @[Parameters.scala:612:40] wire [13:0] _GEN_10 = io_in_c_bits_address_0[13:0] ^ 14'h3000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_80 = {io_in_c_bits_address_0[31:14], _GEN_10}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_81 = {1'h0, _address_ok_T_80}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_82 = _address_ok_T_81 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_83 = _address_ok_T_82; // @[Parameters.scala:137:46] wire _address_ok_T_84 = _address_ok_T_83 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_2 = _address_ok_T_84; // @[Parameters.scala:612:40] wire [16:0] _GEN_11 = io_in_c_bits_address_0[16:0] ^ 17'h10000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_85 = {io_in_c_bits_address_0[31:17], _GEN_11}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_86 = {1'h0, _address_ok_T_85}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_87 = _address_ok_T_86 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_88 = _address_ok_T_87; // @[Parameters.scala:137:46] wire _address_ok_T_89 = _address_ok_T_88 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_3 = _address_ok_T_89; // @[Parameters.scala:612:40] wire [20:0] _GEN_12 = io_in_c_bits_address_0[20:0] ^ 21'h100000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_90 = {io_in_c_bits_address_0[31:21], _GEN_12}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_91 = {1'h0, _address_ok_T_90}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_92 = _address_ok_T_91 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_93 = _address_ok_T_92; // @[Parameters.scala:137:46] wire _address_ok_T_94 = _address_ok_T_93 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_4 = _address_ok_T_94; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_95 = {io_in_c_bits_address_0[31:21], io_in_c_bits_address_0[20:0] ^ 21'h110000}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_96 = {1'h0, _address_ok_T_95}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_97 = _address_ok_T_96 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_98 = _address_ok_T_97; // @[Parameters.scala:137:46] wire _address_ok_T_99 = _address_ok_T_98 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_5 = _address_ok_T_99; // @[Parameters.scala:612:40] wire [25:0] _GEN_13 = io_in_c_bits_address_0[25:0] ^ 26'h2000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_100 = {io_in_c_bits_address_0[31:26], _GEN_13}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_101 = {1'h0, _address_ok_T_100}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_102 = _address_ok_T_101 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_103 = _address_ok_T_102; // @[Parameters.scala:137:46] wire _address_ok_T_104 = _address_ok_T_103 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_6 = _address_ok_T_104; // @[Parameters.scala:612:40] wire [25:0] _GEN_14 = io_in_c_bits_address_0[25:0] ^ 26'h2010000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_105 = {io_in_c_bits_address_0[31:26], _GEN_14}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_106 = {1'h0, _address_ok_T_105}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_107 = _address_ok_T_106 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_108 = _address_ok_T_107; // @[Parameters.scala:137:46] wire _address_ok_T_109 = _address_ok_T_108 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_7 = _address_ok_T_109; // @[Parameters.scala:612:40] wire [27:0] _GEN_15 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_110 = {io_in_c_bits_address_0[31:28], _GEN_15}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_111 = {1'h0, _address_ok_T_110}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_112 = _address_ok_T_111 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_113 = _address_ok_T_112; // @[Parameters.scala:137:46] wire _address_ok_T_114 = _address_ok_T_113 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_8 = _address_ok_T_114; // @[Parameters.scala:612:40] wire [27:0] _GEN_16 = io_in_c_bits_address_0[27:0] ^ 28'hC000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_115 = {io_in_c_bits_address_0[31:28], _GEN_16}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_116 = {1'h0, _address_ok_T_115}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_117 = _address_ok_T_116 & 33'h1FC000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_118 = _address_ok_T_117; // @[Parameters.scala:137:46] wire _address_ok_T_119 = _address_ok_T_118 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_9 = _address_ok_T_119; // @[Parameters.scala:612:40] wire [28:0] _GEN_17 = io_in_c_bits_address_0[28:0] ^ 29'h10020000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_120 = {io_in_c_bits_address_0[31:29], _GEN_17}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_121 = {1'h0, _address_ok_T_120}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_122 = _address_ok_T_121 & 33'h1FFFFF000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_123 = _address_ok_T_122; // @[Parameters.scala:137:46] wire _address_ok_T_124 = _address_ok_T_123 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_10 = _address_ok_T_124; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_125 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_126 = {1'h0, _address_ok_T_125}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_127 = _address_ok_T_126 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_128 = _address_ok_T_127; // @[Parameters.scala:137:46] wire _address_ok_T_129 = _address_ok_T_128 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_11 = _address_ok_T_129; // @[Parameters.scala:612:40] wire _address_ok_T_130 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_131 = _address_ok_T_130 | _address_ok_WIRE_1_2; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_132 = _address_ok_T_131 | _address_ok_WIRE_1_3; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_133 = _address_ok_T_132 | _address_ok_WIRE_1_4; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_134 = _address_ok_T_133 | _address_ok_WIRE_1_5; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_135 = _address_ok_T_134 | _address_ok_WIRE_1_6; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_136 = _address_ok_T_135 | _address_ok_WIRE_1_7; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_137 = _address_ok_T_136 | _address_ok_WIRE_1_8; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_138 = _address_ok_T_137 | _address_ok_WIRE_1_9; // @[Parameters.scala:612:40, :636:64] wire _address_ok_T_139 = _address_ok_T_138 | _address_ok_WIRE_1_10; // @[Parameters.scala:612:40, :636:64] wire address_ok_1 = _address_ok_T_139 | _address_ok_WIRE_1_11; // @[Parameters.scala:612:40, :636:64] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire _T_2541 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_2541; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_2541; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [2:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_2615 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_2615; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_2615; // @[Decoupled.scala:51:35] wire [26:0] _GEN_18 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_18; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_18; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _b_first_T = io_in_b_ready_0 & io_in_b_valid_0; // @[Decoupled.scala:51:35] wire b_first_done = _b_first_T; // @[Decoupled.scala:51:35] wire [11:0] _b_first_beats1_decode_T_1 = _b_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _b_first_beats1_decode_T_2 = ~_b_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] b_first_beats1_decode = _b_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _b_first_beats1_opdata_T = io_in_b_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire b_first_beats1_opdata = ~_b_first_beats1_opdata_T; // @[Edges.scala:97:{28,37}] reg [8:0] b_first_counter; // @[Edges.scala:229:27] wire [9:0] _b_first_counter1_T = {1'h0, b_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] b_first_counter1 = _b_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire b_first = b_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _b_first_last_T = b_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire [8:0] _b_first_count_T = ~b_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] _b_first_counter_T = b_first ? 9'h0 : b_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_2; // @[Monitor.scala:410:22] reg [1:0] param_2; // @[Monitor.scala:411:22] reg [3:0] size_2; // @[Monitor.scala:412:22] reg [2:0] source_2; // @[Monitor.scala:413:22] reg [31:0] address_1; // @[Monitor.scala:414:22] wire _T_2612 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_2612; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_2612; // @[Decoupled.scala:51:35] wire [11:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T = {1'h0, c_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1 = _c_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [3:0] size_3; // @[Monitor.scala:517:22] reg [2:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [4:0] inflight; // @[Monitor.scala:614:27] reg [19:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] a_set; // @[Monitor.scala:626:34] wire [4:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [19:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [5:0] _GEN_19 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [5:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69] wire [5:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_19; // @[Monitor.scala:637:69, :680:101] wire [5:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_19; // @[Monitor.scala:637:69, :749:69] wire [5:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_19; // @[Monitor.scala:637:69, :790:101] wire [19:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [19:0] _a_opcode_lookup_T_6 = {16'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [19:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [5:0] _GEN_20 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [5:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65] wire [5:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_20; // @[Monitor.scala:641:65, :681:99] wire [5:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_20; // @[Monitor.scala:641:65, :750:67] wire [5:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_20; // @[Monitor.scala:641:65, :791:99] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {32'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [7:0] _GEN_21 = 8'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_21; // @[OneHot.scala:58:35] wire [7:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_21; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2467 = _T_2541 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_2467 ? _a_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_2467 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_2467 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [5:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [66:0] _a_opcodes_set_T_1 = {63'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_2467 ? _a_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [5:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [67:0] _a_sizes_set_T_1 = {63'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_2467 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [4:0] d_clr; // @[Monitor.scala:664:34] wire [4:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [19:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_22 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_22; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_22; // @[Monitor.scala:673:46, :783:46] wire _T_2513 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [7:0] _GEN_23 = 8'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_23; // @[OneHot.scala:58:35] wire [7:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_23; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_2513 & ~d_release_ack ? _d_clr_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2482 = _T_2615 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_2482 ? _d_clr_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_5 = 79'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_2482 ? _d_opcodes_clr_T_5[19:0] : 20'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [78:0] _d_sizes_clr_T_5 = 79'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_2482 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [4:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [4:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [4:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [19:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [19:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [19:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [4:0] inflight_1; // @[Monitor.scala:726:35] reg [19:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [11:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [8:0] c_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] c_first_counter1_1 = _c_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [4:0] c_set; // @[Monitor.scala:738:34] wire [4:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [19:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [19:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [19:0] _c_opcode_lookup_T_6 = {16'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [19:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[19:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {32'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [4:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [7:0] _GEN_24 = 8'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [7:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_24; // @[OneHot.scala:58:35] wire [7:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_24; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2554 = _T_2612 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_2554 ? _c_set_T[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_2554 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [4:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [4:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_2554 ? _c_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [5:0] _c_opcodes_set_T = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [66:0] _c_opcodes_set_T_1 = {63'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_2554 ? _c_opcodes_set_T_1[19:0] : 20'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [5:0] _c_sizes_set_T = {io_in_c_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :768:77] wire [67:0] _c_sizes_set_T_1 = {63'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_2554 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [4:0] d_clr_1; // @[Monitor.scala:774:34] wire [4:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [19:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_2585 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_2585 & d_release_ack_1 ? _d_clr_wo_ready_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire _T_2567 = _T_2615 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_2567 ? _d_clr_T_1[4:0] : 5'h0; // @[OneHot.scala:58:35] wire [78:0] _d_opcodes_clr_T_11 = 79'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_2567 ? _d_opcodes_clr_T_11[19:0] : 20'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [78:0] _d_sizes_clr_T_11 = 79'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_2567 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [4:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [4:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [4:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [19:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [19:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [19:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [11:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_3; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_3 = _d_first_counter1_T_3[8:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_2621 = _T_2615 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_25 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_25; // @[OneHot.scala:58:35] assign d_set = _T_2621 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire _T_2630 = io_in_e_ready_0 & io_in_e_valid_0; // @[Decoupled.scala:51:35] wire [7:0] _GEN_26 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_26; // @[OneHot.scala:58:35] assign e_clr = _T_2630 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_15 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_28 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_15( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_28 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a28d64s4k1z3u_1 : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_57 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a28d64s4k1z3u_1 connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a28d64s4k1z3u_1 connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a28d64s4k1z3u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [27:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [27:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [27:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_57 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a28d64s4k1z3u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a28d64s4k1z3u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_236 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_492 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_236( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_492 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n8x1_Registered : output auto : { flip in_7 : UInt<1>[1], flip in_6 : UInt<1>[1], flip in_5 : UInt<1>[1], flip in_4 : UInt<1>[1], flip in_3 : UInt<1>[1], flip in_2 : UInt<1>[1], flip in_1 : UInt<1>[1], flip in_0 : UInt<1>[1], out_7 : { sync : UInt<1>[1]}, out_6 : { sync : UInt<1>[1]}, out_5 : { sync : UInt<1>[1]}, out_4 : { sync : UInt<1>[1]}, out_3 : { sync : UInt<1>[1]}, out_2 : { sync : UInt<1>[1]}, out_1 : { sync : UInt<1>[1]}, out_0 : { sync : UInt<1>[1]}} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeIn_1 : UInt<1>[1] invalidate nodeIn_1[0] wire nodeIn_2 : UInt<1>[1] invalidate nodeIn_2[0] wire nodeIn_3 : UInt<1>[1] invalidate nodeIn_3[0] wire nodeIn_4 : UInt<1>[1] invalidate nodeIn_4[0] wire nodeIn_5 : UInt<1>[1] invalidate nodeIn_5[0] wire nodeIn_6 : UInt<1>[1] invalidate nodeIn_6[0] wire nodeIn_7 : UInt<1>[1] invalidate nodeIn_7[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] wire x1_nodeOut : { sync : UInt<1>[1]} invalidate x1_nodeOut.sync[0] wire x1_nodeOut_1 : { sync : UInt<1>[1]} invalidate x1_nodeOut_1.sync[0] wire x1_nodeOut_2 : { sync : UInt<1>[1]} invalidate x1_nodeOut_2.sync[0] wire x1_nodeOut_3 : { sync : UInt<1>[1]} invalidate x1_nodeOut_3.sync[0] wire x1_nodeOut_4 : { sync : UInt<1>[1]} invalidate x1_nodeOut_4.sync[0] wire x1_nodeOut_5 : { sync : UInt<1>[1]} invalidate x1_nodeOut_5.sync[0] wire x1_nodeOut_6 : { sync : UInt<1>[1]} invalidate x1_nodeOut_6.sync[0] connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 connect auto.out_4, x1_nodeOut_3 connect auto.out_5, x1_nodeOut_4 connect auto.out_6, x1_nodeOut_5 connect auto.out_7, x1_nodeOut_6 connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeIn_2, auto.in_2 connect nodeIn_3, auto.in_3 connect nodeIn_4, auto.in_4 connect nodeIn_5, auto.in_5 connect nodeIn_6, auto.in_6 connect nodeIn_7, auto.in_7 connect nodeOut.sync, nodeIn connect x1_nodeOut.sync, nodeIn_1 connect x1_nodeOut_1.sync, nodeIn_2 connect x1_nodeOut_2.sync, nodeIn_3 connect x1_nodeOut_3.sync, nodeIn_4 connect x1_nodeOut_4.sync, nodeIn_5 connect x1_nodeOut_5.sync, nodeIn_6 connect x1_nodeOut_6.sync, nodeIn_7 extmodule plusarg_reader_162 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_163 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module IntSyncCrossingSource_n8x1_Registered( // @[Crossing.scala:48:9] input auto_in_7_0, // @[LazyModuleImp.scala:107:25] input auto_in_6_0, // @[LazyModuleImp.scala:107:25] input auto_in_5_0, // @[LazyModuleImp.scala:107:25] input auto_in_4_0, // @[LazyModuleImp.scala:107:25] input auto_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_out_7_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_6_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_5_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_4_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0_sync_0 // @[LazyModuleImp.scala:107:25] ); wire auto_in_7_0_0 = auto_in_7_0; // @[Crossing.scala:48:9] wire auto_in_6_0_0 = auto_in_6_0; // @[Crossing.scala:48:9] wire auto_in_5_0_0 = auto_in_5_0; // @[Crossing.scala:48:9] wire auto_in_4_0_0 = auto_in_4_0; // @[Crossing.scala:48:9] wire auto_in_3_0_0 = auto_in_3_0; // @[Crossing.scala:48:9] wire auto_in_2_0_0 = auto_in_2_0; // @[Crossing.scala:48:9] wire auto_in_1_0_0 = auto_in_1_0; // @[Crossing.scala:48:9] wire auto_in_0_0_0 = auto_in_0_0; // @[Crossing.scala:48:9] wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeIn_7_0 = auto_in_7_0_0; // @[Crossing.scala:48:9] wire nodeIn_6_0 = auto_in_6_0_0; // @[Crossing.scala:48:9] wire nodeIn_5_0 = auto_in_5_0_0; // @[Crossing.scala:48:9] wire nodeIn_4_0 = auto_in_4_0_0; // @[Crossing.scala:48:9] wire nodeIn_3_0 = auto_in_3_0_0; // @[Crossing.scala:48:9] wire nodeIn_2_0 = auto_in_2_0_0; // @[Crossing.scala:48:9] wire nodeIn_1_0 = auto_in_1_0_0; // @[Crossing.scala:48:9] wire nodeIn_0 = auto_in_0_0_0; // @[Crossing.scala:48:9] wire x1_nodeOut_6_sync_0; // @[MixedNode.scala:542:17] wire x1_nodeOut_5_sync_0; // @[MixedNode.scala:542:17] wire x1_nodeOut_4_sync_0; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_sync_0; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_sync_0; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_sync_0; // @[MixedNode.scala:542:17] wire x1_nodeOut_sync_0; // @[MixedNode.scala:542:17] wire nodeOut_sync_0; // @[MixedNode.scala:542:17] wire auto_out_7_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_6_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_5_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_4_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_3_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_2_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_1_sync_0_0; // @[Crossing.scala:48:9] wire auto_out_0_sync_0_0; // @[Crossing.scala:48:9] assign nodeOut_sync_0 = nodeIn_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_sync_0 = nodeIn_1_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_1_sync_0 = nodeIn_2_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_2_sync_0 = nodeIn_3_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_3_sync_0 = nodeIn_4_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_4_sync_0 = nodeIn_5_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_5_sync_0 = nodeIn_6_0; // @[MixedNode.scala:542:17, :551:17] assign x1_nodeOut_6_sync_0 = nodeIn_7_0; // @[MixedNode.scala:542:17, :551:17] assign auto_out_0_sync_0_0 = nodeOut_sync_0; // @[Crossing.scala:48:9] assign auto_out_1_sync_0_0 = x1_nodeOut_sync_0; // @[Crossing.scala:48:9] assign auto_out_2_sync_0_0 = x1_nodeOut_1_sync_0; // @[Crossing.scala:48:9] assign auto_out_3_sync_0_0 = x1_nodeOut_2_sync_0; // @[Crossing.scala:48:9] assign auto_out_4_sync_0_0 = x1_nodeOut_3_sync_0; // @[Crossing.scala:48:9] assign auto_out_5_sync_0_0 = x1_nodeOut_4_sync_0; // @[Crossing.scala:48:9] assign auto_out_6_sync_0_0 = x1_nodeOut_5_sync_0; // @[Crossing.scala:48:9] assign auto_out_7_sync_0_0 = x1_nodeOut_6_sync_0; // @[Crossing.scala:48:9] assign auto_out_7_sync_0 = auto_out_7_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_6_sync_0 = auto_out_6_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_5_sync_0 = auto_out_5_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_4_sync_0 = auto_out_4_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_3_sync_0 = auto_out_3_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_2_sync_0 = auto_out_2_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_1_sync_0 = auto_out_1_sync_0_0; // @[Crossing.scala:48:9] assign auto_out_0_sync_0 = auto_out_0_sync_0_0; // @[Crossing.scala:48:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s11k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_20 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s11k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s11k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<11>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<11>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_42 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_43 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLBuffer_a26d64s11k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [10:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [10:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [10:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_20 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s11k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s11k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_73 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}} wire _in_flight_WIRE : UInt<1>[2] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_8 = and(_T_6, _T_7) node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_10 = and(_T_8, _T_9) node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_12 = and(_T_10, _T_11) node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8)) node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_19 = and(_T_17, _T_18) node _T_20 = or(_T_12, _T_19) node _T_21 = or(_T_5, _T_20) node _T_22 = asUInt(reset) node _T_23 = eq(_T_22, UInt<1>(0h0)) when _T_23 : node _T_24 = eq(_T_21, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_21, UInt<1>(0h1), "") : assert_1 node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf)) node _T_28 = and(_T_26, _T_27) node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_32 = and(_T_30, _T_31) node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_37 = and(_T_35, _T_36) node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb)) node _T_42 = and(_T_40, _T_41) node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_44 = and(_T_42, _T_43) node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_46 = and(_T_44, _T_45) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = or(_T_32, _T_39) node _T_69 = or(_T_68, _T_46) node _T_70 = or(_T_69, _T_53) node _T_71 = or(_T_70, _T_60) node _T_72 = or(_T_71, _T_67) node _T_73 = or(_T_25, _T_72) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_73, UInt<1>(0h1), "") : assert_2
module NoCMonitor_73( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_262 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_262( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFN_e8_s24_6 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} inst mulAddRecFNToRaw_preMul of MulAddRecFNToRaw_preMul_e8_s24_6 inst mulAddRecFNToRaw_postMul of MulAddRecFNToRaw_postMul_e8_s24_6 connect mulAddRecFNToRaw_preMul.io.op, io.op connect mulAddRecFNToRaw_preMul.io.a, io.a connect mulAddRecFNToRaw_preMul.io.b, io.b connect mulAddRecFNToRaw_preMul.io.c, io.c node _mulAddResult_T = mul(mulAddRecFNToRaw_preMul.io.mulAddA, mulAddRecFNToRaw_preMul.io.mulAddB) node mulAddResult = add(_mulAddResult_T, mulAddRecFNToRaw_preMul.io.mulAddC) connect mulAddRecFNToRaw_postMul.io.fromPreMul.bit0AlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.bit0AlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.highAlignedSigC, mulAddRecFNToRaw_preMul.io.toPostMul.highAlignedSigC connect mulAddRecFNToRaw_postMul.io.fromPreMul.CDom_CAlignDist, mulAddRecFNToRaw_preMul.io.toPostMul.CDom_CAlignDist connect mulAddRecFNToRaw_postMul.io.fromPreMul.CIsDominant, mulAddRecFNToRaw_preMul.io.toPostMul.CIsDominant connect mulAddRecFNToRaw_postMul.io.fromPreMul.doSubMags, mulAddRecFNToRaw_preMul.io.toPostMul.doSubMags connect mulAddRecFNToRaw_postMul.io.fromPreMul.sExpSum, mulAddRecFNToRaw_preMul.io.toPostMul.sExpSum connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroC, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfC, mulAddRecFNToRaw_preMul.io.toPostMul.isInfC connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNC, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNC connect mulAddRecFNToRaw_postMul.io.fromPreMul.signProd, mulAddRecFNToRaw_preMul.io.toPostMul.signProd connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroB, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfB, mulAddRecFNToRaw_preMul.io.toPostMul.isInfB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isZeroA, mulAddRecFNToRaw_preMul.io.toPostMul.isZeroA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isInfA, mulAddRecFNToRaw_preMul.io.toPostMul.isInfA connect mulAddRecFNToRaw_postMul.io.fromPreMul.isNaNAOrB, mulAddRecFNToRaw_preMul.io.toPostMul.isNaNAOrB connect mulAddRecFNToRaw_postMul.io.fromPreMul.isSigNaNAny, mulAddRecFNToRaw_preMul.io.toPostMul.isSigNaNAny connect mulAddRecFNToRaw_postMul.io.mulAddResult, mulAddResult connect mulAddRecFNToRaw_postMul.io.roundingMode, io.roundingMode inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_14 connect roundRawFNToRecFN.io.invalidExc, mulAddRecFNToRaw_postMul.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundRawFNToRecFN.io.in.sig, mulAddRecFNToRaw_postMul.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, mulAddRecFNToRaw_postMul.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, mulAddRecFNToRaw_postMul.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, mulAddRecFNToRaw_postMul.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, mulAddRecFNToRaw_postMul.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, mulAddRecFNToRaw_postMul.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, io.roundingMode connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module MulAddRecFN_e8_s24_6( // @[MulAddRecFN.scala:300:7] input [32:0] io_a, // @[MulAddRecFN.scala:303:16] input [32:0] io_c, // @[MulAddRecFN.scala:303:16] output [32:0] io_out // @[MulAddRecFN.scala:303:16] ); wire _mulAddRecFNToRaw_postMul_io_invalidExc; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isNaN; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isInf; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_isZero; // @[MulAddRecFN.scala:319:15] wire _mulAddRecFNToRaw_postMul_io_rawOut_sign; // @[MulAddRecFN.scala:319:15] wire [9:0] _mulAddRecFNToRaw_postMul_io_rawOut_sExp; // @[MulAddRecFN.scala:319:15] wire [26:0] _mulAddRecFNToRaw_postMul_io_rawOut_sig; // @[MulAddRecFN.scala:319:15] wire [23:0] _mulAddRecFNToRaw_preMul_io_mulAddA; // @[MulAddRecFN.scala:317:15] wire [47:0] _mulAddRecFNToRaw_preMul_io_mulAddC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_signProd; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isInfC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC; // @[MulAddRecFN.scala:317:15] wire [9:0] _mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant; // @[MulAddRecFN.scala:317:15] wire [4:0] _mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist; // @[MulAddRecFN.scala:317:15] wire [25:0] _mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC; // @[MulAddRecFN.scala:317:15] wire _mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC; // @[MulAddRecFN.scala:317:15] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:300:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:300:7] wire io_detectTininess = 1'h1; // @[MulAddRecFN.scala:300:7, :303:16, :339:15] wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:300:7, :303:16, :319:15, :339:15] wire [32:0] io_b = 33'h80000000; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [1:0] io_op = 2'h0; // @[MulAddRecFN.scala:300:7, :303:16, :317:15] wire [32:0] io_out_0; // @[MulAddRecFN.scala:300:7] wire [4:0] io_exceptionFlags; // @[MulAddRecFN.scala:300:7] wire [47:0] _mulAddResult_T = {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddA, 23'h0}; // @[MulAddRecFN.scala:317:15, :327:45] wire [48:0] mulAddResult = {1'h0, _mulAddResult_T} + {1'h0, _mulAddRecFNToRaw_preMul_io_mulAddC}; // @[MulAddRecFN.scala:317:15, :327:45, :328:50] MulAddRecFNToRaw_preMul_e8_s24_6 mulAddRecFNToRaw_preMul ( // @[MulAddRecFN.scala:317:15] .io_a (io_a_0), // @[MulAddRecFN.scala:300:7] .io_c (io_c_0), // @[MulAddRecFN.scala:300:7] .io_mulAddA (_mulAddRecFNToRaw_preMul_io_mulAddA), .io_mulAddC (_mulAddRecFNToRaw_preMul_io_mulAddC), .io_toPostMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), .io_toPostMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), .io_toPostMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), .io_toPostMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), .io_toPostMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), .io_toPostMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), .io_toPostMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), .io_toPostMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), .io_toPostMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), .io_toPostMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), .io_toPostMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), .io_toPostMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), .io_toPostMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), .io_toPostMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC) ); // @[MulAddRecFN.scala:317:15] MulAddRecFNToRaw_postMul_e8_s24_6 mulAddRecFNToRaw_postMul ( // @[MulAddRecFN.scala:319:15] .io_fromPreMul_isSigNaNAny (_mulAddRecFNToRaw_preMul_io_toPostMul_isSigNaNAny), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNAOrB (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNAOrB), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfA (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroA (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroA), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_signProd (_mulAddRecFNToRaw_preMul_io_toPostMul_signProd), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isNaNC (_mulAddRecFNToRaw_preMul_io_toPostMul_isNaNC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isInfC (_mulAddRecFNToRaw_preMul_io_toPostMul_isInfC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_isZeroC (_mulAddRecFNToRaw_preMul_io_toPostMul_isZeroC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_sExpSum (_mulAddRecFNToRaw_preMul_io_toPostMul_sExpSum), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_doSubMags (_mulAddRecFNToRaw_preMul_io_toPostMul_doSubMags), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CIsDominant (_mulAddRecFNToRaw_preMul_io_toPostMul_CIsDominant), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_CDom_CAlignDist (_mulAddRecFNToRaw_preMul_io_toPostMul_CDom_CAlignDist), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_highAlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_highAlignedSigC), // @[MulAddRecFN.scala:317:15] .io_fromPreMul_bit0AlignedSigC (_mulAddRecFNToRaw_preMul_io_toPostMul_bit0AlignedSigC), // @[MulAddRecFN.scala:317:15] .io_mulAddResult (mulAddResult), // @[MulAddRecFN.scala:328:50] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), .io_rawOut_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), .io_rawOut_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), .io_rawOut_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), .io_rawOut_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), .io_rawOut_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), .io_rawOut_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig) ); // @[MulAddRecFN.scala:319:15] RoundRawFNToRecFN_e8_s24_14 roundRawFNToRecFN ( // @[MulAddRecFN.scala:339:15] .io_invalidExc (_mulAddRecFNToRaw_postMul_io_invalidExc), // @[MulAddRecFN.scala:319:15] .io_in_isNaN (_mulAddRecFNToRaw_postMul_io_rawOut_isNaN), // @[MulAddRecFN.scala:319:15] .io_in_isInf (_mulAddRecFNToRaw_postMul_io_rawOut_isInf), // @[MulAddRecFN.scala:319:15] .io_in_isZero (_mulAddRecFNToRaw_postMul_io_rawOut_isZero), // @[MulAddRecFN.scala:319:15] .io_in_sign (_mulAddRecFNToRaw_postMul_io_rawOut_sign), // @[MulAddRecFN.scala:319:15] .io_in_sExp (_mulAddRecFNToRaw_postMul_io_rawOut_sExp), // @[MulAddRecFN.scala:319:15] .io_in_sig (_mulAddRecFNToRaw_postMul_io_rawOut_sig), // @[MulAddRecFN.scala:319:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags) ); // @[MulAddRecFN.scala:339:15] assign io_out = io_out_0; // @[MulAddRecFN.scala:300:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_178 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_178( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Frontend : input clock : Clock input reset : Reset output auto : { flip icache_slave_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<13>, address : UInt<22>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<13>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}, icache_master_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip icache_mmio_address_prefix_sink_in : UInt<1>, flip icache_hart_id_sink_in : UInt<1>, flip reset_vector_sink_in : UInt<32>} output io : { flip cpu : { might_request : UInt<1>, flip clock_enabled : UInt<1>, req : { valid : UInt<1>, bits : { pc : UInt<40>, speculative : UInt<1>}}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { btb : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<40>, data : UInt<32>, mask : UInt<2>, xcpt : { pf : { inst : UInt<1>}, gf : { inst : UInt<1>}, ae : { inst : UInt<1>}}, replay : UInt<1>}}, flip gpa : { valid : UInt<1>, bits : UInt<40>}, flip gpa_is_pte : UInt<1>, btb_update : { valid : UInt<1>, bits : { prediction : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isValid : UInt<1>, br_pc : UInt<39>, cfiType : UInt<2>}}, bht_update : { valid : UInt<1>, bits : { prediction : { history : UInt<8>, value : UInt<1>}, pc : UInt<39>, branch : UInt<1>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : { valid : UInt<1>, bits : { cfiType : UInt<2>, returnAddr : UInt<39>}}, flush_icache : UInt<1>, flip npc : UInt<40>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}, progress : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}} inst icache of ICache connect icache.clock, clock connect icache.reset, reset wire resetVectorSinkNodeIn : UInt<32> invalidate resetVectorSinkNodeIn connect resetVectorSinkNodeIn, auto.reset_vector_sink_in connect icache.auto.hart_id_sink_in, auto.icache_hart_id_sink_in connect icache.auto.mmio_address_prefix_sink_in, auto.icache_mmio_address_prefix_sink_in connect icache.auto.master_out.d, auto.icache_master_out.d connect auto.icache_master_out.a.bits, icache.auto.master_out.a.bits connect auto.icache_master_out.a.valid, icache.auto.master_out.a.valid connect icache.auto.master_out.a.ready, auto.icache_master_out.a.ready connect icache.auto.slave_in, auto.icache_slave_in node _T = asUInt(reset) node _T_1 = or(_T, io.cpu.req.valid) inst fq of ShiftQueue connect fq.clock, clock connect fq.reset, _T_1 reg clock_en_reg : UInt<1>, clock node clock_en = or(clock_en_reg, io.cpu.might_request) connect io.cpu.clock_enabled, clock_en node _T_2 = or(io.cpu.req.valid, io.cpu.sfence.valid) node _T_3 = or(_T_2, io.cpu.flush_icache) node _T_4 = or(_T_3, io.cpu.bht_update.valid) node _T_5 = or(_T_4, io.cpu.btb_update.valid) node _T_6 = eq(_T_5, UInt<1>(0h0)) node _T_7 = or(_T_6, io.cpu.might_request) node _T_8 = asUInt(reset) node _T_9 = eq(_T_8, UInt<1>(0h0)) when _T_9 : node _T_10 = eq(_T_7, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:96 assert(!(io.cpu.req.valid || io.cpu.sfence.valid || io.cpu.flush_icache || io.cpu.bht_update.valid || io.cpu.btb_update.valid) || io.cpu.might_request)\n") : printf assert(clock, _T_7, UInt<1>(0h1), "") : assert connect icache.clock, clock connect icache.io.clock_enabled, clock_en inst tlb of ITLB connect tlb.clock, clock connect tlb.reset, reset reg s1_valid : UInt<1>, clock regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0) node _s0_fq_has_space_T = bits(fq.io.mask, 2, 2) node _s0_fq_has_space_T_1 = eq(_s0_fq_has_space_T, UInt<1>(0h0)) node _s0_fq_has_space_T_2 = bits(fq.io.mask, 3, 3) node _s0_fq_has_space_T_3 = eq(_s0_fq_has_space_T_2, UInt<1>(0h0)) node _s0_fq_has_space_T_4 = eq(s1_valid, UInt<1>(0h0)) node _s0_fq_has_space_T_5 = eq(s2_valid, UInt<1>(0h0)) node _s0_fq_has_space_T_6 = or(_s0_fq_has_space_T_4, _s0_fq_has_space_T_5) node _s0_fq_has_space_T_7 = and(_s0_fq_has_space_T_3, _s0_fq_has_space_T_6) node _s0_fq_has_space_T_8 = or(_s0_fq_has_space_T_1, _s0_fq_has_space_T_7) node _s0_fq_has_space_T_9 = bits(fq.io.mask, 4, 4) node _s0_fq_has_space_T_10 = eq(_s0_fq_has_space_T_9, UInt<1>(0h0)) node _s0_fq_has_space_T_11 = eq(s1_valid, UInt<1>(0h0)) node _s0_fq_has_space_T_12 = eq(s2_valid, UInt<1>(0h0)) node _s0_fq_has_space_T_13 = and(_s0_fq_has_space_T_11, _s0_fq_has_space_T_12) node _s0_fq_has_space_T_14 = and(_s0_fq_has_space_T_10, _s0_fq_has_space_T_13) node s0_fq_has_space = or(_s0_fq_has_space_T_8, _s0_fq_has_space_T_14) node s0_valid = or(io.cpu.req.valid, s0_fq_has_space) connect s1_valid, s0_valid reg s1_pc : UInt<40>, clock reg s1_speculative : UInt<1>, clock node _s2_pc_T = not(resetVectorSinkNodeIn) node _s2_pc_T_1 = or(_s2_pc_T, UInt<1>(0h1)) node _s2_pc_T_2 = not(_s2_pc_T_1) regreset s2_pc : UInt<40>, clock, reset, _s2_pc_T_2 reg s2_btb_resp_valid : UInt<1>, clock reg s2_btb_resp_bits : { cfiType : UInt<2>, taken : UInt<1>, mask : UInt<2>, bridx : UInt<1>, target : UInt<39>, entry : UInt<5>, bht : { history : UInt<8>, value : UInt<1>}}, clock node s2_btb_taken = and(s2_btb_resp_valid, s2_btb_resp_bits.taken) reg s2_tlb_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock node _s2_xcpt_T = or(s2_tlb_resp.ae.inst, s2_tlb_resp.pf.inst) node s2_xcpt = or(_s2_xcpt_T, s2_tlb_resp.gf.inst) regreset s2_speculative : UInt<1>, clock, reset, UInt<1>(0h0) regreset s2_partial_insn_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg s2_partial_insn : UInt<16>, clock regreset wrong_path : UInt<1>, clock, reset, UInt<1>(0h0) node _s1_base_pc_T = not(s1_pc) node _s1_base_pc_T_1 = or(_s1_base_pc_T, UInt<2>(0h3)) node s1_base_pc = not(_s1_base_pc_T_1) node _ntpc_T = add(s1_base_pc, UInt<3>(0h4)) node ntpc = tail(_ntpc_T, 1) wire predicted_npc : UInt connect predicted_npc, ntpc wire predicted_taken : UInt<1> connect predicted_taken, UInt<1>(0h0) wire s2_replay : UInt<1> node _s2_replay_T = and(fq.io.enq.ready, fq.io.enq.valid) node _s2_replay_T_1 = eq(_s2_replay_T, UInt<1>(0h0)) node _s2_replay_T_2 = and(s2_valid, _s2_replay_T_1) node _s2_replay_T_3 = eq(s0_valid, UInt<1>(0h0)) node _s2_replay_T_4 = and(s2_replay, _s2_replay_T_3) regreset s2_replay_REG : UInt<1>, clock, reset, UInt<1>(0h1) connect s2_replay_REG, _s2_replay_T_4 node _s2_replay_T_5 = or(_s2_replay_T_2, s2_replay_REG) connect s2_replay, _s2_replay_T_5 node npc = mux(s2_replay, s2_pc, predicted_npc) connect s1_pc, io.cpu.npc node _s0_speculative_T = eq(s2_speculative, UInt<1>(0h0)) node _s0_speculative_T_1 = and(s2_valid, _s0_speculative_T) node _s0_speculative_T_2 = or(s1_speculative, _s0_speculative_T_1) node s0_speculative = or(_s0_speculative_T_2, predicted_taken) node _s1_speculative_T = mux(s2_replay, s2_speculative, s0_speculative) node _s1_speculative_T_1 = mux(io.cpu.req.valid, io.cpu.req.bits.speculative, _s1_speculative_T) connect s1_speculative, _s1_speculative_T_1 wire s2_redirect : UInt<1> connect s2_redirect, io.cpu.req.valid connect s2_valid, UInt<1>(0h0) node _T_11 = eq(s2_replay, UInt<1>(0h0)) when _T_11 : node _s2_valid_T = eq(s2_redirect, UInt<1>(0h0)) connect s2_valid, _s2_valid_T connect s2_pc, s1_pc connect s2_speculative, s1_speculative connect s2_tlb_resp, tlb.io.resp regreset recent_progress_counter : UInt, clock, reset, UInt<2>(0h3) node recent_progress = gt(recent_progress_counter, UInt<1>(0h0)) node _T_12 = and(io.ptw.req.ready, io.ptw.req.valid) node _T_13 = and(_T_12, recent_progress) when _T_13 : node _recent_progress_counter_T = sub(recent_progress_counter, UInt<1>(0h1)) node _recent_progress_counter_T_1 = tail(_recent_progress_counter_T, 1) connect recent_progress_counter, _recent_progress_counter_T_1 when io.cpu.progress : connect recent_progress_counter, UInt<2>(0h3) node _s2_kill_speculative_tlb_refill_T = eq(recent_progress, UInt<1>(0h0)) node s2_kill_speculative_tlb_refill = and(s2_speculative, _s2_kill_speculative_tlb_refill_T) connect tlb.io.ptw.customCSRs, io.ptw.customCSRs connect tlb.io.ptw.pmp[0], io.ptw.pmp[0] connect tlb.io.ptw.pmp[1], io.ptw.pmp[1] connect tlb.io.ptw.pmp[2], io.ptw.pmp[2] connect tlb.io.ptw.pmp[3], io.ptw.pmp[3] connect tlb.io.ptw.pmp[4], io.ptw.pmp[4] connect tlb.io.ptw.pmp[5], io.ptw.pmp[5] connect tlb.io.ptw.pmp[6], io.ptw.pmp[6] connect tlb.io.ptw.pmp[7], io.ptw.pmp[7] connect tlb.io.ptw.gstatus, io.ptw.gstatus connect tlb.io.ptw.hstatus, io.ptw.hstatus connect tlb.io.ptw.status, io.ptw.status connect tlb.io.ptw.vsatp, io.ptw.vsatp connect tlb.io.ptw.hgatp, io.ptw.hgatp connect tlb.io.ptw.ptbr, io.ptw.ptbr connect tlb.io.ptw.resp, io.ptw.resp connect io.ptw.req.bits, tlb.io.ptw.req.bits connect io.ptw.req.valid, tlb.io.ptw.req.valid connect tlb.io.ptw.req.ready, io.ptw.req.ready node _tlb_io_req_valid_T = eq(s2_replay, UInt<1>(0h0)) node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T) connect tlb.io.req.valid, _tlb_io_req_valid_T_1 connect tlb.io.req.bits.cmd, UInt<1>(0h0) connect tlb.io.req.bits.vaddr, s1_pc connect tlb.io.req.bits.passthrough, UInt<1>(0h0) connect tlb.io.req.bits.size, UInt<2>(0h2) connect tlb.io.req.bits.prv, io.ptw.status.prv connect tlb.io.req.bits.v, io.ptw.status.v connect tlb.io.sfence.bits.hg, io.cpu.sfence.bits.hg connect tlb.io.sfence.bits.hv, io.cpu.sfence.bits.hv connect tlb.io.sfence.bits.asid, io.cpu.sfence.bits.asid connect tlb.io.sfence.bits.addr, io.cpu.sfence.bits.addr connect tlb.io.sfence.bits.rs2, io.cpu.sfence.bits.rs2 connect tlb.io.sfence.bits.rs1, io.cpu.sfence.bits.rs1 connect tlb.io.sfence.valid, io.cpu.sfence.valid node _tlb_io_kill_T = eq(s2_valid, UInt<1>(0h0)) node _tlb_io_kill_T_1 = or(_tlb_io_kill_T, s2_kill_speculative_tlb_refill) connect tlb.io.kill, _tlb_io_kill_T_1 connect icache.io.req.valid, s0_valid connect icache.io.req.bits.addr, io.cpu.npc connect icache.io.invalidate, io.cpu.flush_icache connect icache.io.s1_paddr, tlb.io.resp.paddr connect icache.io.s2_vaddr, s2_pc node _icache_io_s1_kill_T = or(s2_redirect, tlb.io.resp.miss) node _icache_io_s1_kill_T_1 = or(_icache_io_s1_kill_T, s2_replay) connect icache.io.s1_kill, _icache_io_s1_kill_T_1 node _s2_can_speculatively_refill_T = bits(io.ptw.customCSRs.csrs[0].value, 3, 3) node _s2_can_speculatively_refill_T_1 = eq(_s2_can_speculatively_refill_T, UInt<1>(0h0)) node s2_can_speculatively_refill = and(s2_tlb_resp.cacheable, _s2_can_speculatively_refill_T_1) node _icache_io_s2_kill_T = eq(s2_can_speculatively_refill, UInt<1>(0h0)) node _icache_io_s2_kill_T_1 = and(s2_speculative, _icache_io_s2_kill_T) node _icache_io_s2_kill_T_2 = or(_icache_io_s2_kill_T_1, s2_xcpt) connect icache.io.s2_kill, _icache_io_s2_kill_T_2 connect icache.io.s2_cacheable, s2_tlb_resp.cacheable node _icache_io_s2_prefetch_T = bits(io.ptw.customCSRs.csrs[0].value, 17, 17) node _icache_io_s2_prefetch_T_1 = eq(_icache_io_s2_prefetch_T, UInt<1>(0h0)) node _icache_io_s2_prefetch_T_2 = and(s2_tlb_resp.prefetchable, _icache_io_s2_prefetch_T_1) connect icache.io.s2_prefetch, _icache_io_s2_prefetch_T_2 reg fq_io_enq_valid_REG : UInt<1>, clock connect fq_io_enq_valid_REG, s1_valid node _fq_io_enq_valid_T = and(fq_io_enq_valid_REG, s2_valid) node _fq_io_enq_valid_T_1 = and(s2_kill_speculative_tlb_refill, s2_tlb_resp.miss) node _fq_io_enq_valid_T_2 = or(icache.io.resp.valid, _fq_io_enq_valid_T_1) node _fq_io_enq_valid_T_3 = eq(s2_tlb_resp.miss, UInt<1>(0h0)) node _fq_io_enq_valid_T_4 = and(_fq_io_enq_valid_T_3, icache.io.s2_kill) node _fq_io_enq_valid_T_5 = or(_fq_io_enq_valid_T_2, _fq_io_enq_valid_T_4) node _fq_io_enq_valid_T_6 = and(_fq_io_enq_valid_T, _fq_io_enq_valid_T_5) connect fq.io.enq.valid, _fq_io_enq_valid_T_6 connect fq.io.enq.bits.pc, s2_pc node _io_cpu_npc_T = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) node _io_cpu_npc_T_1 = not(_io_cpu_npc_T) node _io_cpu_npc_T_2 = or(_io_cpu_npc_T_1, UInt<1>(0h1)) node _io_cpu_npc_T_3 = not(_io_cpu_npc_T_2) connect io.cpu.npc, _io_cpu_npc_T_3 connect fq.io.enq.bits.data, icache.io.resp.bits.data node _fq_io_enq_bits_mask_T = bits(s2_pc, 1, 1) node _fq_io_enq_bits_mask_T_1 = dshl(UInt<2>(0h3), _fq_io_enq_bits_mask_T) connect fq.io.enq.bits.mask, _fq_io_enq_bits_mask_T_1 node _fq_io_enq_bits_replay_T = eq(icache.io.resp.valid, UInt<1>(0h0)) node _fq_io_enq_bits_replay_T_1 = and(icache.io.s2_kill, _fq_io_enq_bits_replay_T) node _fq_io_enq_bits_replay_T_2 = eq(s2_xcpt, UInt<1>(0h0)) node _fq_io_enq_bits_replay_T_3 = and(_fq_io_enq_bits_replay_T_1, _fq_io_enq_bits_replay_T_2) node _fq_io_enq_bits_replay_T_4 = or(icache.io.resp.bits.replay, _fq_io_enq_bits_replay_T_3) node _fq_io_enq_bits_replay_T_5 = and(s2_kill_speculative_tlb_refill, s2_tlb_resp.miss) node _fq_io_enq_bits_replay_T_6 = or(_fq_io_enq_bits_replay_T_4, _fq_io_enq_bits_replay_T_5) connect fq.io.enq.bits.replay, _fq_io_enq_bits_replay_T_6 connect fq.io.enq.bits.btb.bht.value, s2_btb_resp_bits.bht.value connect fq.io.enq.bits.btb.bht.history, s2_btb_resp_bits.bht.history connect fq.io.enq.bits.btb.entry, s2_btb_resp_bits.entry connect fq.io.enq.bits.btb.target, s2_btb_resp_bits.target connect fq.io.enq.bits.btb.bridx, s2_btb_resp_bits.bridx connect fq.io.enq.bits.btb.mask, s2_btb_resp_bits.mask connect fq.io.enq.bits.btb.taken, s2_btb_resp_bits.taken connect fq.io.enq.bits.btb.cfiType, s2_btb_resp_bits.cfiType connect fq.io.enq.bits.btb.taken, s2_btb_taken connect fq.io.enq.bits.xcpt.ae.inst, s2_tlb_resp.ae.inst connect fq.io.enq.bits.xcpt.gf.inst, s2_tlb_resp.gf.inst connect fq.io.enq.bits.xcpt.pf.inst, s2_tlb_resp.pf.inst node _T_14 = bits(io.ptw.customCSRs.csrs[0].value, 3, 3) node _T_15 = and(s2_speculative, _T_14) node _T_16 = eq(icache.io.s2_kill, UInt<1>(0h0)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:194 assert(!(s2_speculative && io.ptw.customCSRs.asInstanceOf[RocketCustomCSRs].disableSpeculativeICacheRefill && !icache.io.s2_kill))\n") : printf_1 assert(clock, _T_18, UInt<1>(0h1), "") : assert_1 node _T_22 = and(icache.io.resp.valid, icache.io.resp.bits.ae) when _T_22 : connect fq.io.enq.bits.xcpt.ae.inst, UInt<1>(0h1) inst btb of BTB connect btb.clock, clock connect btb.reset, reset connect btb.io.flush, UInt<1>(0h0) connect btb.io.req.valid, UInt<1>(0h0) connect btb.io.req.bits.addr, s1_pc connect btb.io.btb_update.bits.cfiType, io.cpu.btb_update.bits.cfiType connect btb.io.btb_update.bits.br_pc, io.cpu.btb_update.bits.br_pc connect btb.io.btb_update.bits.isValid, io.cpu.btb_update.bits.isValid connect btb.io.btb_update.bits.taken, io.cpu.btb_update.bits.taken connect btb.io.btb_update.bits.target, io.cpu.btb_update.bits.target connect btb.io.btb_update.bits.pc, io.cpu.btb_update.bits.pc connect btb.io.btb_update.bits.prediction.bht.value, io.cpu.btb_update.bits.prediction.bht.value connect btb.io.btb_update.bits.prediction.bht.history, io.cpu.btb_update.bits.prediction.bht.history connect btb.io.btb_update.bits.prediction.entry, io.cpu.btb_update.bits.prediction.entry connect btb.io.btb_update.bits.prediction.target, io.cpu.btb_update.bits.prediction.target connect btb.io.btb_update.bits.prediction.bridx, io.cpu.btb_update.bits.prediction.bridx connect btb.io.btb_update.bits.prediction.mask, io.cpu.btb_update.bits.prediction.mask connect btb.io.btb_update.bits.prediction.taken, io.cpu.btb_update.bits.prediction.taken connect btb.io.btb_update.bits.prediction.cfiType, io.cpu.btb_update.bits.prediction.cfiType connect btb.io.btb_update.valid, io.cpu.btb_update.valid connect btb.io.bht_update.bits.mispredict, io.cpu.bht_update.bits.mispredict connect btb.io.bht_update.bits.taken, io.cpu.bht_update.bits.taken connect btb.io.bht_update.bits.branch, io.cpu.bht_update.bits.branch connect btb.io.bht_update.bits.pc, io.cpu.bht_update.bits.pc connect btb.io.bht_update.bits.prediction.value, io.cpu.bht_update.bits.prediction.value connect btb.io.bht_update.bits.prediction.history, io.cpu.bht_update.bits.prediction.history connect btb.io.bht_update.valid, io.cpu.bht_update.valid connect btb.io.ras_update.valid, UInt<1>(0h0) invalidate btb.io.ras_update.bits.returnAddr invalidate btb.io.ras_update.bits.cfiType connect btb.io.bht_advance.valid, UInt<1>(0h0) invalidate btb.io.bht_advance.bits.bht.value invalidate btb.io.bht_advance.bits.bht.history invalidate btb.io.bht_advance.bits.entry invalidate btb.io.bht_advance.bits.target invalidate btb.io.bht_advance.bits.bridx invalidate btb.io.bht_advance.bits.mask invalidate btb.io.bht_advance.bits.taken invalidate btb.io.bht_advance.bits.cfiType node _T_23 = eq(s2_replay, UInt<1>(0h0)) when _T_23 : node _btb_io_req_valid_T = eq(s2_redirect, UInt<1>(0h0)) connect btb.io.req.valid, _btb_io_req_valid_T connect s2_btb_resp_valid, btb.io.resp.valid connect s2_btb_resp_bits, btb.io.resp.bits node _T_24 = and(btb.io.resp.valid, btb.io.resp.bits.taken) when _T_24 : node _predicted_npc_T = bits(btb.io.resp.bits.target, 38, 38) node _predicted_npc_T_1 = cat(_predicted_npc_T, btb.io.resp.bits.target) connect predicted_npc, _predicted_npc_T_1 connect predicted_taken, UInt<1>(0h1) when UInt<1>(0h0) : connect btb.io.flush, UInt<1>(0h1) when UInt<1>(0h0) : connect btb.io.bht_update.valid, UInt<1>(0h0) node _s2_base_pc_T = not(s2_pc) node _s2_base_pc_T_1 = or(_s2_base_pc_T, UInt<2>(0h3)) node s2_base_pc = not(_s2_base_pc_T_1) wire taken_idx : UInt wire after_idx : UInt wire useRAS : UInt<1> connect useRAS, UInt<1>(0h0) wire updateBTB : UInt<1> connect updateBTB, UInt<1>(0h0) invalidate taken_idx invalidate after_idx node _T_25 = eq(io.cpu.btb_update.valid, UInt<1>(0h0)) when _T_25 : node _fetch_bubble_likely_T = bits(fq.io.mask, 1, 1) node fetch_bubble_likely = eq(_fetch_bubble_likely_T, UInt<1>(0h0)) node _btb_io_btb_update_valid_T = and(fq.io.enq.ready, fq.io.enq.valid) node _btb_io_btb_update_valid_T_1 = eq(wrong_path, UInt<1>(0h0)) node _btb_io_btb_update_valid_T_2 = and(_btb_io_btb_update_valid_T, _btb_io_btb_update_valid_T_1) node _btb_io_btb_update_valid_T_3 = and(_btb_io_btb_update_valid_T_2, fetch_bubble_likely) node _btb_io_btb_update_valid_T_4 = and(_btb_io_btb_update_valid_T_3, updateBTB) connect btb.io.btb_update.valid, _btb_io_btb_update_valid_T_4 connect btb.io.btb_update.bits.prediction.entry, UInt<5>(0h1c) connect btb.io.btb_update.bits.isValid, UInt<1>(0h1) connect btb.io.btb_update.bits.cfiType, btb.io.ras_update.bits.cfiType node _btb_io_btb_update_bits_br_pc_T = shl(taken_idx, 1) node _btb_io_btb_update_bits_br_pc_T_1 = or(s2_base_pc, _btb_io_btb_update_bits_br_pc_T) connect btb.io.btb_update.bits.br_pc, _btb_io_btb_update_bits_br_pc_T_1 connect btb.io.btb_update.bits.pc, s2_base_pc node _btb_io_ras_update_bits_returnAddr_T = shl(after_idx, 1) node _btb_io_ras_update_bits_returnAddr_T_1 = add(s2_base_pc, _btb_io_ras_update_bits_returnAddr_T) node _btb_io_ras_update_bits_returnAddr_T_2 = tail(_btb_io_ras_update_bits_returnAddr_T_1, 1) connect btb.io.ras_update.bits.returnAddr, _btb_io_ras_update_bits_returnAddr_T_2 node _taken_prevRVI_T = bits(s2_partial_insn, 1, 0) node _taken_prevRVI_T_1 = neq(_taken_prevRVI_T, UInt<2>(0h3)) node _taken_prevRVI_T_2 = eq(_taken_prevRVI_T_1, UInt<1>(0h0)) node taken_prevRVI = and(s2_partial_insn_valid, _taken_prevRVI_T_2) node _taken_valid_T = bits(fq.io.enq.bits.mask, 0, 0) node _taken_valid_T_1 = eq(taken_prevRVI, UInt<1>(0h0)) node taken_valid = and(_taken_valid_T, _taken_valid_T_1) node taken_bits = bits(fq.io.enq.bits.data, 15, 0) node _taken_rvc_T = bits(taken_bits, 1, 0) node taken_rvc = neq(_taken_rvc_T, UInt<2>(0h3)) node taken_rviBits = cat(taken_bits, s2_partial_insn) node _taken_rviBranch_T = bits(taken_rviBits, 6, 0) node taken_rviBranch = eq(_taken_rviBranch_T, UInt<7>(0h63)) node _taken_rviJump_T = bits(taken_rviBits, 6, 0) node taken_rviJump = eq(_taken_rviJump_T, UInt<7>(0h6f)) node _taken_rviJALR_T = bits(taken_rviBits, 6, 0) node taken_rviJALR = eq(_taken_rviJALR_T, UInt<7>(0h67)) node _taken_rviReturn_T = bits(taken_rviBits, 7, 7) node _taken_rviReturn_T_1 = eq(_taken_rviReturn_T, UInt<1>(0h0)) node _taken_rviReturn_T_2 = and(taken_rviJALR, _taken_rviReturn_T_1) node _taken_rviReturn_T_3 = bits(taken_rviBits, 19, 15) node _taken_rviReturn_T_4 = and(_taken_rviReturn_T_3, UInt<5>(0h1b)) node _taken_rviReturn_T_5 = eq(UInt<1>(0h1), _taken_rviReturn_T_4) node taken_rviReturn = and(_taken_rviReturn_T_2, _taken_rviReturn_T_5) node _taken_rviCall_T = or(taken_rviJALR, taken_rviJump) node _taken_rviCall_T_1 = bits(taken_rviBits, 7, 7) node taken_rviCall = and(_taken_rviCall_T, _taken_rviCall_T_1) node _taken_rvcBranch_T = and(taken_bits, UInt<16>(0he003)) node _taken_rvcBranch_T_1 = eq(UInt<16>(0hc001), _taken_rvcBranch_T) node _taken_rvcBranch_T_2 = and(taken_bits, UInt<16>(0he003)) node _taken_rvcBranch_T_3 = eq(UInt<16>(0he001), _taken_rvcBranch_T_2) node taken_rvcBranch = or(_taken_rvcBranch_T_1, _taken_rvcBranch_T_3) node _taken_rvcJAL_T = and(taken_bits, UInt<16>(0he003)) node _taken_rvcJAL_T_1 = eq(UInt<14>(0h2001), _taken_rvcJAL_T) node taken_rvcJAL = and(UInt<1>(0h0), _taken_rvcJAL_T_1) node _taken_rvcJump_T = and(taken_bits, UInt<16>(0he003)) node _taken_rvcJump_T_1 = eq(UInt<16>(0ha001), _taken_rvcJump_T) node taken_rvcJump = or(_taken_rvcJump_T_1, taken_rvcJAL) node _taken_rvcImm_T = bits(taken_bits, 14, 14) node _taken_rvcImm_T_1 = bits(taken_bits, 12, 12) node _taken_rvcImm_T_2 = mux(_taken_rvcImm_T_1, UInt<5>(0h1f), UInt<5>(0h0)) node _taken_rvcImm_T_3 = bits(taken_bits, 6, 5) node _taken_rvcImm_T_4 = bits(taken_bits, 2, 2) node _taken_rvcImm_T_5 = bits(taken_bits, 11, 10) node _taken_rvcImm_T_6 = bits(taken_bits, 4, 3) node taken_rvcImm_lo_hi = cat(_taken_rvcImm_T_5, _taken_rvcImm_T_6) node taken_rvcImm_lo = cat(taken_rvcImm_lo_hi, UInt<1>(0h0)) node taken_rvcImm_hi_hi = cat(_taken_rvcImm_T_2, _taken_rvcImm_T_3) node taken_rvcImm_hi = cat(taken_rvcImm_hi_hi, _taken_rvcImm_T_4) node _taken_rvcImm_T_7 = cat(taken_rvcImm_hi, taken_rvcImm_lo) node _taken_rvcImm_T_8 = asSInt(_taken_rvcImm_T_7) node _taken_rvcImm_T_9 = bits(taken_bits, 12, 12) node _taken_rvcImm_T_10 = mux(_taken_rvcImm_T_9, UInt<10>(0h3ff), UInt<10>(0h0)) node _taken_rvcImm_T_11 = bits(taken_bits, 8, 8) node _taken_rvcImm_T_12 = bits(taken_bits, 10, 9) node _taken_rvcImm_T_13 = bits(taken_bits, 6, 6) node _taken_rvcImm_T_14 = bits(taken_bits, 7, 7) node _taken_rvcImm_T_15 = bits(taken_bits, 2, 2) node _taken_rvcImm_T_16 = bits(taken_bits, 11, 11) node _taken_rvcImm_T_17 = bits(taken_bits, 5, 3) node taken_rvcImm_lo_lo = cat(_taken_rvcImm_T_17, UInt<1>(0h0)) node taken_rvcImm_lo_hi_1 = cat(_taken_rvcImm_T_15, _taken_rvcImm_T_16) node taken_rvcImm_lo_1 = cat(taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo) node taken_rvcImm_hi_lo = cat(_taken_rvcImm_T_13, _taken_rvcImm_T_14) node taken_rvcImm_hi_hi_hi = cat(_taken_rvcImm_T_10, _taken_rvcImm_T_11) node taken_rvcImm_hi_hi_1 = cat(taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12) node taken_rvcImm_hi_1 = cat(taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo) node _taken_rvcImm_T_18 = cat(taken_rvcImm_hi_1, taken_rvcImm_lo_1) node _taken_rvcImm_T_19 = asSInt(_taken_rvcImm_T_18) node taken_rvcImm = mux(_taken_rvcImm_T, _taken_rvcImm_T_8, _taken_rvcImm_T_19) node _taken_rvcJR_T = and(taken_bits, UInt<16>(0hf003)) node _taken_rvcJR_T_1 = eq(UInt<16>(0h8002), _taken_rvcJR_T) node _taken_rvcJR_T_2 = bits(taken_bits, 6, 2) node _taken_rvcJR_T_3 = eq(_taken_rvcJR_T_2, UInt<1>(0h0)) node taken_rvcJR = and(_taken_rvcJR_T_1, _taken_rvcJR_T_3) node _taken_rvcReturn_T = bits(taken_bits, 11, 7) node _taken_rvcReturn_T_1 = and(_taken_rvcReturn_T, UInt<5>(0h1b)) node _taken_rvcReturn_T_2 = eq(UInt<1>(0h1), _taken_rvcReturn_T_1) node taken_rvcReturn = and(taken_rvcJR, _taken_rvcReturn_T_2) node _taken_rvcJALR_T = and(taken_bits, UInt<16>(0hf003)) node _taken_rvcJALR_T_1 = eq(UInt<16>(0h9002), _taken_rvcJALR_T) node _taken_rvcJALR_T_2 = bits(taken_bits, 6, 2) node _taken_rvcJALR_T_3 = eq(_taken_rvcJALR_T_2, UInt<1>(0h0)) node taken_rvcJALR = and(_taken_rvcJALR_T_1, _taken_rvcJALR_T_3) node taken_rvcCall = or(taken_rvcJAL, taken_rvcJALR) node _taken_rviImm_T = bits(taken_rviBits, 3, 3) node _taken_rviImm_sign_T = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_sign_T_1 = bits(taken_rviBits, 31, 31) node _taken_rviImm_sign_T_2 = asSInt(_taken_rviImm_sign_T_1) node taken_rviImm_sign = mux(_taken_rviImm_sign_T, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_2) node _taken_rviImm_b30_20_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b30_20_T_1 = bits(taken_rviBits, 30, 20) node _taken_rviImm_b30_20_T_2 = asSInt(_taken_rviImm_b30_20_T_1) node taken_rviImm_b30_20 = mux(_taken_rviImm_b30_20_T, _taken_rviImm_b30_20_T_2, taken_rviImm_sign) node _taken_rviImm_b19_12_T = neq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b19_12_T_1 = neq(UInt<3>(0h3), UInt<3>(0h3)) node _taken_rviImm_b19_12_T_2 = and(_taken_rviImm_b19_12_T, _taken_rviImm_b19_12_T_1) node _taken_rviImm_b19_12_T_3 = bits(taken_rviBits, 19, 12) node _taken_rviImm_b19_12_T_4 = asSInt(_taken_rviImm_b19_12_T_3) node taken_rviImm_b19_12 = mux(_taken_rviImm_b19_12_T_2, taken_rviImm_sign, _taken_rviImm_b19_12_T_4) node _taken_rviImm_b11_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b11_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b11_T_2 = or(_taken_rviImm_b11_T, _taken_rviImm_b11_T_1) node _taken_rviImm_b11_T_3 = eq(UInt<3>(0h3), UInt<3>(0h3)) node _taken_rviImm_b11_T_4 = bits(taken_rviBits, 20, 20) node _taken_rviImm_b11_T_5 = asSInt(_taken_rviImm_b11_T_4) node _taken_rviImm_b11_T_6 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _taken_rviImm_b11_T_7 = bits(taken_rviBits, 7, 7) node _taken_rviImm_b11_T_8 = asSInt(_taken_rviImm_b11_T_7) node _taken_rviImm_b11_T_9 = mux(_taken_rviImm_b11_T_6, _taken_rviImm_b11_T_8, taken_rviImm_sign) node _taken_rviImm_b11_T_10 = mux(_taken_rviImm_b11_T_3, _taken_rviImm_b11_T_5, _taken_rviImm_b11_T_9) node taken_rviImm_b11 = mux(_taken_rviImm_b11_T_2, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_10) node _taken_rviImm_b10_5_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b10_5_T_1 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b10_5_T_2 = or(_taken_rviImm_b10_5_T, _taken_rviImm_b10_5_T_1) node _taken_rviImm_b10_5_T_3 = bits(taken_rviBits, 30, 25) node taken_rviImm_b10_5 = mux(_taken_rviImm_b10_5_T_2, UInt<1>(0h0), _taken_rviImm_b10_5_T_3) node _taken_rviImm_b4_1_T = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b4_1_T_1 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _taken_rviImm_b4_1_T_2 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _taken_rviImm_b4_1_T_3 = or(_taken_rviImm_b4_1_T_1, _taken_rviImm_b4_1_T_2) node _taken_rviImm_b4_1_T_4 = bits(taken_rviBits, 11, 8) node _taken_rviImm_b4_1_T_5 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b4_1_T_6 = bits(taken_rviBits, 19, 16) node _taken_rviImm_b4_1_T_7 = bits(taken_rviBits, 24, 21) node _taken_rviImm_b4_1_T_8 = mux(_taken_rviImm_b4_1_T_5, _taken_rviImm_b4_1_T_6, _taken_rviImm_b4_1_T_7) node _taken_rviImm_b4_1_T_9 = mux(_taken_rviImm_b4_1_T_3, _taken_rviImm_b4_1_T_4, _taken_rviImm_b4_1_T_8) node taken_rviImm_b4_1 = mux(_taken_rviImm_b4_1_T, UInt<1>(0h0), _taken_rviImm_b4_1_T_9) node _taken_rviImm_b0_T = eq(UInt<3>(0h3), UInt<3>(0h0)) node _taken_rviImm_b0_T_1 = bits(taken_rviBits, 7, 7) node _taken_rviImm_b0_T_2 = eq(UInt<3>(0h3), UInt<3>(0h4)) node _taken_rviImm_b0_T_3 = bits(taken_rviBits, 20, 20) node _taken_rviImm_b0_T_4 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b0_T_5 = bits(taken_rviBits, 15, 15) node _taken_rviImm_b0_T_6 = mux(_taken_rviImm_b0_T_4, _taken_rviImm_b0_T_5, UInt<1>(0h0)) node _taken_rviImm_b0_T_7 = mux(_taken_rviImm_b0_T_2, _taken_rviImm_b0_T_3, _taken_rviImm_b0_T_6) node taken_rviImm_b0 = mux(_taken_rviImm_b0_T, _taken_rviImm_b0_T_1, _taken_rviImm_b0_T_7) node taken_rviImm_lo_hi = cat(taken_rviImm_b10_5, taken_rviImm_b4_1) node taken_rviImm_lo = cat(taken_rviImm_lo_hi, taken_rviImm_b0) node taken_rviImm_hi_lo_lo = asUInt(taken_rviImm_b11) node taken_rviImm_hi_lo_hi = asUInt(taken_rviImm_b19_12) node taken_rviImm_hi_lo = cat(taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo) node taken_rviImm_hi_hi_lo = asUInt(taken_rviImm_b30_20) node taken_rviImm_hi_hi_hi = asUInt(taken_rviImm_sign) node taken_rviImm_hi_hi = cat(taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo) node taken_rviImm_hi = cat(taken_rviImm_hi_hi, taken_rviImm_hi_lo) node _taken_rviImm_T_1 = cat(taken_rviImm_hi, taken_rviImm_lo) node _taken_rviImm_T_2 = asSInt(_taken_rviImm_T_1) node _taken_rviImm_sign_T_3 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_sign_T_4 = bits(taken_rviBits, 31, 31) node _taken_rviImm_sign_T_5 = asSInt(_taken_rviImm_sign_T_4) node taken_rviImm_sign_1 = mux(_taken_rviImm_sign_T_3, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_5) node _taken_rviImm_b30_20_T_3 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b30_20_T_4 = bits(taken_rviBits, 30, 20) node _taken_rviImm_b30_20_T_5 = asSInt(_taken_rviImm_b30_20_T_4) node taken_rviImm_b30_20_1 = mux(_taken_rviImm_b30_20_T_3, _taken_rviImm_b30_20_T_5, taken_rviImm_sign_1) node _taken_rviImm_b19_12_T_5 = neq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b19_12_T_6 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _taken_rviImm_b19_12_T_7 = and(_taken_rviImm_b19_12_T_5, _taken_rviImm_b19_12_T_6) node _taken_rviImm_b19_12_T_8 = bits(taken_rviBits, 19, 12) node _taken_rviImm_b19_12_T_9 = asSInt(_taken_rviImm_b19_12_T_8) node taken_rviImm_b19_12_1 = mux(_taken_rviImm_b19_12_T_7, taken_rviImm_sign_1, _taken_rviImm_b19_12_T_9) node _taken_rviImm_b11_T_11 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b11_T_12 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b11_T_13 = or(_taken_rviImm_b11_T_11, _taken_rviImm_b11_T_12) node _taken_rviImm_b11_T_14 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _taken_rviImm_b11_T_15 = bits(taken_rviBits, 20, 20) node _taken_rviImm_b11_T_16 = asSInt(_taken_rviImm_b11_T_15) node _taken_rviImm_b11_T_17 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _taken_rviImm_b11_T_18 = bits(taken_rviBits, 7, 7) node _taken_rviImm_b11_T_19 = asSInt(_taken_rviImm_b11_T_18) node _taken_rviImm_b11_T_20 = mux(_taken_rviImm_b11_T_17, _taken_rviImm_b11_T_19, taken_rviImm_sign_1) node _taken_rviImm_b11_T_21 = mux(_taken_rviImm_b11_T_14, _taken_rviImm_b11_T_16, _taken_rviImm_b11_T_20) node taken_rviImm_b11_1 = mux(_taken_rviImm_b11_T_13, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_21) node _taken_rviImm_b10_5_T_4 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b10_5_T_5 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b10_5_T_6 = or(_taken_rviImm_b10_5_T_4, _taken_rviImm_b10_5_T_5) node _taken_rviImm_b10_5_T_7 = bits(taken_rviBits, 30, 25) node taken_rviImm_b10_5_1 = mux(_taken_rviImm_b10_5_T_6, UInt<1>(0h0), _taken_rviImm_b10_5_T_7) node _taken_rviImm_b4_1_T_10 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b4_1_T_11 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _taken_rviImm_b4_1_T_12 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _taken_rviImm_b4_1_T_13 = or(_taken_rviImm_b4_1_T_11, _taken_rviImm_b4_1_T_12) node _taken_rviImm_b4_1_T_14 = bits(taken_rviBits, 11, 8) node _taken_rviImm_b4_1_T_15 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b4_1_T_16 = bits(taken_rviBits, 19, 16) node _taken_rviImm_b4_1_T_17 = bits(taken_rviBits, 24, 21) node _taken_rviImm_b4_1_T_18 = mux(_taken_rviImm_b4_1_T_15, _taken_rviImm_b4_1_T_16, _taken_rviImm_b4_1_T_17) node _taken_rviImm_b4_1_T_19 = mux(_taken_rviImm_b4_1_T_13, _taken_rviImm_b4_1_T_14, _taken_rviImm_b4_1_T_18) node taken_rviImm_b4_1_1 = mux(_taken_rviImm_b4_1_T_10, UInt<1>(0h0), _taken_rviImm_b4_1_T_19) node _taken_rviImm_b0_T_8 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _taken_rviImm_b0_T_9 = bits(taken_rviBits, 7, 7) node _taken_rviImm_b0_T_10 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _taken_rviImm_b0_T_11 = bits(taken_rviBits, 20, 20) node _taken_rviImm_b0_T_12 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b0_T_13 = bits(taken_rviBits, 15, 15) node _taken_rviImm_b0_T_14 = mux(_taken_rviImm_b0_T_12, _taken_rviImm_b0_T_13, UInt<1>(0h0)) node _taken_rviImm_b0_T_15 = mux(_taken_rviImm_b0_T_10, _taken_rviImm_b0_T_11, _taken_rviImm_b0_T_14) node taken_rviImm_b0_1 = mux(_taken_rviImm_b0_T_8, _taken_rviImm_b0_T_9, _taken_rviImm_b0_T_15) node taken_rviImm_lo_hi_1 = cat(taken_rviImm_b10_5_1, taken_rviImm_b4_1_1) node taken_rviImm_lo_1 = cat(taken_rviImm_lo_hi_1, taken_rviImm_b0_1) node taken_rviImm_hi_lo_lo_1 = asUInt(taken_rviImm_b11_1) node taken_rviImm_hi_lo_hi_1 = asUInt(taken_rviImm_b19_12_1) node taken_rviImm_hi_lo_1 = cat(taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1) node taken_rviImm_hi_hi_lo_1 = asUInt(taken_rviImm_b30_20_1) node taken_rviImm_hi_hi_hi_1 = asUInt(taken_rviImm_sign_1) node taken_rviImm_hi_hi_1 = cat(taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1) node taken_rviImm_hi_1 = cat(taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1) node _taken_rviImm_T_3 = cat(taken_rviImm_hi_1, taken_rviImm_lo_1) node _taken_rviImm_T_4 = asSInt(_taken_rviImm_T_3) node taken_rviImm = mux(_taken_rviImm_T, _taken_rviImm_T_2, _taken_rviImm_T_4) node _taken_predict_taken_T = bits(s2_btb_resp_bits.bht.value, 0, 0) node taken_predict_taken = or(_taken_predict_taken_T, UInt<1>(0h0)) node _taken_taken_T = or(taken_rviJump, taken_rviJALR) node _taken_taken_T_1 = and(taken_rviBranch, taken_predict_taken) node _taken_taken_T_2 = or(_taken_taken_T, _taken_taken_T_1) node _taken_taken_T_3 = and(taken_prevRVI, _taken_taken_T_2) node _taken_taken_T_4 = or(taken_rvcJump, taken_rvcJALR) node _taken_taken_T_5 = or(_taken_taken_T_4, taken_rvcJR) node _taken_taken_T_6 = and(taken_rvcBranch, taken_predict_taken) node _taken_taken_T_7 = or(_taken_taken_T_5, _taken_taken_T_6) node _taken_taken_T_8 = and(taken_valid, _taken_taken_T_7) node taken_taken = or(_taken_taken_T_3, _taken_taken_T_8) node _taken_predictReturn_T = and(taken_prevRVI, taken_rviReturn) node _taken_predictReturn_T_1 = and(taken_valid, taken_rvcReturn) node _taken_predictReturn_T_2 = or(_taken_predictReturn_T, _taken_predictReturn_T_1) node taken_predictReturn = and(btb.io.ras_head.valid, _taken_predictReturn_T_2) node _taken_predictJump_T = and(taken_prevRVI, taken_rviJump) node _taken_predictJump_T_1 = and(taken_valid, taken_rvcJump) node taken_predictJump = or(_taken_predictJump_T, _taken_predictJump_T_1) node _taken_predictBranch_T = and(taken_prevRVI, taken_rviBranch) node _taken_predictBranch_T_1 = and(taken_valid, taken_rvcBranch) node _taken_predictBranch_T_2 = or(_taken_predictBranch_T, _taken_predictBranch_T_1) node taken_predictBranch = and(taken_predict_taken, _taken_predictBranch_T_2) node _taken_T = and(s2_valid, s2_btb_resp_valid) node _taken_T_1 = eq(s2_btb_resp_bits.bridx, UInt<1>(0h0)) node _taken_T_2 = and(_taken_T, _taken_T_1) node _taken_T_3 = and(_taken_T_2, taken_valid) node _taken_T_4 = eq(taken_rvc, UInt<1>(0h0)) node _taken_T_5 = and(_taken_T_3, _taken_T_4) when _taken_T_5 : connect btb.io.flush, UInt<1>(0h1) connect fq.io.enq.bits.replay, UInt<1>(0h1) connect wrong_path, UInt<1>(0h1) node _taken_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _taken_T_6 : connect taken_idx, UInt<1>(0h0) connect after_idx, UInt<1>(0h1) node _taken_btb_io_ras_update_valid_T = and(fq.io.enq.ready, fq.io.enq.valid) node _taken_btb_io_ras_update_valid_T_1 = eq(wrong_path, UInt<1>(0h0)) node _taken_btb_io_ras_update_valid_T_2 = and(_taken_btb_io_ras_update_valid_T, _taken_btb_io_ras_update_valid_T_1) node _taken_btb_io_ras_update_valid_T_3 = or(taken_rviCall, taken_rviReturn) node _taken_btb_io_ras_update_valid_T_4 = and(taken_prevRVI, _taken_btb_io_ras_update_valid_T_3) node _taken_btb_io_ras_update_valid_T_5 = or(taken_rvcCall, taken_rvcReturn) node _taken_btb_io_ras_update_valid_T_6 = and(taken_valid, _taken_btb_io_ras_update_valid_T_5) node _taken_btb_io_ras_update_valid_T_7 = or(_taken_btb_io_ras_update_valid_T_4, _taken_btb_io_ras_update_valid_T_6) node _taken_btb_io_ras_update_valid_T_8 = and(_taken_btb_io_ras_update_valid_T_2, _taken_btb_io_ras_update_valid_T_7) connect btb.io.ras_update.valid, _taken_btb_io_ras_update_valid_T_8 node _taken_btb_io_ras_update_bits_cfiType_T = mux(taken_prevRVI, taken_rviReturn, taken_rvcReturn) node _taken_btb_io_ras_update_bits_cfiType_T_1 = mux(taken_prevRVI, taken_rviCall, taken_rvcCall) node _taken_btb_io_ras_update_bits_cfiType_T_2 = mux(taken_prevRVI, taken_rviBranch, taken_rvcBranch) node _taken_btb_io_ras_update_bits_cfiType_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _taken_btb_io_ras_update_bits_cfiType_T_4 = and(_taken_btb_io_ras_update_bits_cfiType_T_2, _taken_btb_io_ras_update_bits_cfiType_T_3) node _taken_btb_io_ras_update_bits_cfiType_T_5 = mux(_taken_btb_io_ras_update_bits_cfiType_T_4, UInt<1>(0h0), UInt<1>(0h1)) node _taken_btb_io_ras_update_bits_cfiType_T_6 = mux(_taken_btb_io_ras_update_bits_cfiType_T_1, UInt<2>(0h2), _taken_btb_io_ras_update_bits_cfiType_T_5) node _taken_btb_io_ras_update_bits_cfiType_T_7 = mux(_taken_btb_io_ras_update_bits_cfiType_T, UInt<2>(0h3), _taken_btb_io_ras_update_bits_cfiType_T_6) connect btb.io.ras_update.bits.cfiType, _taken_btb_io_ras_update_bits_cfiType_T_7 node _taken_T_7 = eq(s2_btb_taken, UInt<1>(0h0)) when _taken_T_7 : node _taken_T_8 = and(fq.io.enq.ready, fq.io.enq.valid) node _taken_T_9 = and(_taken_T_8, taken_taken) node _taken_T_10 = eq(taken_predictBranch, UInt<1>(0h0)) node _taken_T_11 = and(_taken_T_9, _taken_T_10) node _taken_T_12 = eq(taken_predictJump, UInt<1>(0h0)) node _taken_T_13 = and(_taken_T_11, _taken_T_12) node _taken_T_14 = eq(taken_predictReturn, UInt<1>(0h0)) node _taken_T_15 = and(_taken_T_13, _taken_T_14) when _taken_T_15 : connect wrong_path, UInt<1>(0h1) node _taken_T_16 = and(s2_valid, taken_predictReturn) when _taken_T_16 : connect useRAS, UInt<1>(0h1) node _taken_T_17 = or(taken_predictBranch, taken_predictJump) node _taken_T_18 = and(s2_valid, _taken_T_17) when _taken_T_18 : node taken_pc = or(s2_base_pc, UInt<1>(0h0)) node _taken_npc_T = asSInt(taken_pc) node _taken_npc_T_1 = sub(taken_rviImm, asSInt(UInt<3>(0h2))) node _taken_npc_T_2 = mux(taken_prevRVI, _taken_npc_T_1, taken_rvcImm) node _taken_npc_T_3 = add(_taken_npc_T, _taken_npc_T_2) node _taken_npc_T_4 = tail(_taken_npc_T_3, 1) node taken_npc = asSInt(_taken_npc_T_4) node _taken_predicted_npc_T = asUInt(taken_npc) connect predicted_npc, _taken_predicted_npc_T node _taken_T_19 = and(taken_prevRVI, taken_rviBranch) node _taken_T_20 = and(taken_valid, taken_rvcBranch) node _taken_T_21 = or(_taken_T_19, _taken_T_20) when _taken_T_21 : node _taken_btb_io_bht_advance_valid_T = and(fq.io.enq.ready, fq.io.enq.valid) node _taken_btb_io_bht_advance_valid_T_1 = eq(wrong_path, UInt<1>(0h0)) node _taken_btb_io_bht_advance_valid_T_2 = and(_taken_btb_io_bht_advance_valid_T, _taken_btb_io_bht_advance_valid_T_1) connect btb.io.bht_advance.valid, _taken_btb_io_bht_advance_valid_T_2 connect btb.io.bht_advance.bits.bht.value, s2_btb_resp_bits.bht.value connect btb.io.bht_advance.bits.bht.history, s2_btb_resp_bits.bht.history connect btb.io.bht_advance.bits.entry, s2_btb_resp_bits.entry connect btb.io.bht_advance.bits.target, s2_btb_resp_bits.target connect btb.io.bht_advance.bits.bridx, s2_btb_resp_bits.bridx connect btb.io.bht_advance.bits.mask, s2_btb_resp_bits.mask connect btb.io.bht_advance.bits.taken, s2_btb_resp_bits.taken connect btb.io.bht_advance.bits.cfiType, s2_btb_resp_bits.cfiType node _taken_T_22 = eq(s2_btb_resp_valid, UInt<1>(0h0)) node _taken_T_23 = eq(s2_btb_resp_bits.bht.value, UInt<1>(0h1)) node _taken_T_24 = and(taken_predictBranch, _taken_T_23) node _taken_T_25 = or(_taken_T_24, taken_predictJump) node _taken_T_26 = or(_taken_T_25, taken_predictReturn) node _taken_T_27 = and(_taken_T_22, _taken_T_26) when _taken_T_27 : connect updateBTB, UInt<1>(0h1) node _taken_T_28 = or(UInt<1>(0h0), taken_taken) node _taken_prevRVI_T_3 = bits(taken_bits, 1, 0) node _taken_prevRVI_T_4 = neq(_taken_prevRVI_T_3, UInt<2>(0h3)) node _taken_prevRVI_T_5 = eq(_taken_prevRVI_T_4, UInt<1>(0h0)) node taken_prevRVI_1 = and(taken_valid, _taken_prevRVI_T_5) node _taken_valid_T_2 = bits(fq.io.enq.bits.mask, 1, 1) node _taken_valid_T_3 = eq(taken_prevRVI_1, UInt<1>(0h0)) node taken_valid_1 = and(_taken_valid_T_2, _taken_valid_T_3) node taken_bits_1 = bits(fq.io.enq.bits.data, 31, 16) node _taken_rvc_T_1 = bits(taken_bits_1, 1, 0) node taken_rvc_1 = neq(_taken_rvc_T_1, UInt<2>(0h3)) node taken_rviBits_1 = cat(taken_bits_1, taken_bits) node _taken_rviBranch_T_1 = bits(taken_rviBits_1, 6, 0) node taken_rviBranch_1 = eq(_taken_rviBranch_T_1, UInt<7>(0h63)) node _taken_rviJump_T_1 = bits(taken_rviBits_1, 6, 0) node taken_rviJump_1 = eq(_taken_rviJump_T_1, UInt<7>(0h6f)) node _taken_rviJALR_T_1 = bits(taken_rviBits_1, 6, 0) node taken_rviJALR_1 = eq(_taken_rviJALR_T_1, UInt<7>(0h67)) node _taken_rviReturn_T_6 = bits(taken_rviBits_1, 7, 7) node _taken_rviReturn_T_7 = eq(_taken_rviReturn_T_6, UInt<1>(0h0)) node _taken_rviReturn_T_8 = and(taken_rviJALR_1, _taken_rviReturn_T_7) node _taken_rviReturn_T_9 = bits(taken_rviBits_1, 19, 15) node _taken_rviReturn_T_10 = and(_taken_rviReturn_T_9, UInt<5>(0h1b)) node _taken_rviReturn_T_11 = eq(UInt<1>(0h1), _taken_rviReturn_T_10) node taken_rviReturn_1 = and(_taken_rviReturn_T_8, _taken_rviReturn_T_11) node _taken_rviCall_T_2 = or(taken_rviJALR_1, taken_rviJump_1) node _taken_rviCall_T_3 = bits(taken_rviBits_1, 7, 7) node taken_rviCall_1 = and(_taken_rviCall_T_2, _taken_rviCall_T_3) node _taken_rvcBranch_T_4 = and(taken_bits_1, UInt<16>(0he003)) node _taken_rvcBranch_T_5 = eq(UInt<16>(0hc001), _taken_rvcBranch_T_4) node _taken_rvcBranch_T_6 = and(taken_bits_1, UInt<16>(0he003)) node _taken_rvcBranch_T_7 = eq(UInt<16>(0he001), _taken_rvcBranch_T_6) node taken_rvcBranch_1 = or(_taken_rvcBranch_T_5, _taken_rvcBranch_T_7) node _taken_rvcJAL_T_2 = and(taken_bits_1, UInt<16>(0he003)) node _taken_rvcJAL_T_3 = eq(UInt<14>(0h2001), _taken_rvcJAL_T_2) node taken_rvcJAL_1 = and(UInt<1>(0h0), _taken_rvcJAL_T_3) node _taken_rvcJump_T_2 = and(taken_bits_1, UInt<16>(0he003)) node _taken_rvcJump_T_3 = eq(UInt<16>(0ha001), _taken_rvcJump_T_2) node taken_rvcJump_1 = or(_taken_rvcJump_T_3, taken_rvcJAL_1) node _taken_rvcImm_T_20 = bits(taken_bits_1, 14, 14) node _taken_rvcImm_T_21 = bits(taken_bits_1, 12, 12) node _taken_rvcImm_T_22 = mux(_taken_rvcImm_T_21, UInt<5>(0h1f), UInt<5>(0h0)) node _taken_rvcImm_T_23 = bits(taken_bits_1, 6, 5) node _taken_rvcImm_T_24 = bits(taken_bits_1, 2, 2) node _taken_rvcImm_T_25 = bits(taken_bits_1, 11, 10) node _taken_rvcImm_T_26 = bits(taken_bits_1, 4, 3) node taken_rvcImm_lo_hi_2 = cat(_taken_rvcImm_T_25, _taken_rvcImm_T_26) node taken_rvcImm_lo_2 = cat(taken_rvcImm_lo_hi_2, UInt<1>(0h0)) node taken_rvcImm_hi_hi_2 = cat(_taken_rvcImm_T_22, _taken_rvcImm_T_23) node taken_rvcImm_hi_2 = cat(taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24) node _taken_rvcImm_T_27 = cat(taken_rvcImm_hi_2, taken_rvcImm_lo_2) node _taken_rvcImm_T_28 = asSInt(_taken_rvcImm_T_27) node _taken_rvcImm_T_29 = bits(taken_bits_1, 12, 12) node _taken_rvcImm_T_30 = mux(_taken_rvcImm_T_29, UInt<10>(0h3ff), UInt<10>(0h0)) node _taken_rvcImm_T_31 = bits(taken_bits_1, 8, 8) node _taken_rvcImm_T_32 = bits(taken_bits_1, 10, 9) node _taken_rvcImm_T_33 = bits(taken_bits_1, 6, 6) node _taken_rvcImm_T_34 = bits(taken_bits_1, 7, 7) node _taken_rvcImm_T_35 = bits(taken_bits_1, 2, 2) node _taken_rvcImm_T_36 = bits(taken_bits_1, 11, 11) node _taken_rvcImm_T_37 = bits(taken_bits_1, 5, 3) node taken_rvcImm_lo_lo_1 = cat(_taken_rvcImm_T_37, UInt<1>(0h0)) node taken_rvcImm_lo_hi_3 = cat(_taken_rvcImm_T_35, _taken_rvcImm_T_36) node taken_rvcImm_lo_3 = cat(taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1) node taken_rvcImm_hi_lo_1 = cat(_taken_rvcImm_T_33, _taken_rvcImm_T_34) node taken_rvcImm_hi_hi_hi_1 = cat(_taken_rvcImm_T_30, _taken_rvcImm_T_31) node taken_rvcImm_hi_hi_3 = cat(taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32) node taken_rvcImm_hi_3 = cat(taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1) node _taken_rvcImm_T_38 = cat(taken_rvcImm_hi_3, taken_rvcImm_lo_3) node _taken_rvcImm_T_39 = asSInt(_taken_rvcImm_T_38) node taken_rvcImm_1 = mux(_taken_rvcImm_T_20, _taken_rvcImm_T_28, _taken_rvcImm_T_39) node _taken_rvcJR_T_4 = and(taken_bits_1, UInt<16>(0hf003)) node _taken_rvcJR_T_5 = eq(UInt<16>(0h8002), _taken_rvcJR_T_4) node _taken_rvcJR_T_6 = bits(taken_bits_1, 6, 2) node _taken_rvcJR_T_7 = eq(_taken_rvcJR_T_6, UInt<1>(0h0)) node taken_rvcJR_1 = and(_taken_rvcJR_T_5, _taken_rvcJR_T_7) node _taken_rvcReturn_T_3 = bits(taken_bits_1, 11, 7) node _taken_rvcReturn_T_4 = and(_taken_rvcReturn_T_3, UInt<5>(0h1b)) node _taken_rvcReturn_T_5 = eq(UInt<1>(0h1), _taken_rvcReturn_T_4) node taken_rvcReturn_1 = and(taken_rvcJR_1, _taken_rvcReturn_T_5) node _taken_rvcJALR_T_4 = and(taken_bits_1, UInt<16>(0hf003)) node _taken_rvcJALR_T_5 = eq(UInt<16>(0h9002), _taken_rvcJALR_T_4) node _taken_rvcJALR_T_6 = bits(taken_bits_1, 6, 2) node _taken_rvcJALR_T_7 = eq(_taken_rvcJALR_T_6, UInt<1>(0h0)) node taken_rvcJALR_1 = and(_taken_rvcJALR_T_5, _taken_rvcJALR_T_7) node taken_rvcCall_1 = or(taken_rvcJAL_1, taken_rvcJALR_1) node _taken_rviImm_T_5 = bits(taken_rviBits_1, 3, 3) node _taken_rviImm_sign_T_6 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_sign_T_7 = bits(taken_rviBits_1, 31, 31) node _taken_rviImm_sign_T_8 = asSInt(_taken_rviImm_sign_T_7) node taken_rviImm_sign_2 = mux(_taken_rviImm_sign_T_6, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_8) node _taken_rviImm_b30_20_T_6 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b30_20_T_7 = bits(taken_rviBits_1, 30, 20) node _taken_rviImm_b30_20_T_8 = asSInt(_taken_rviImm_b30_20_T_7) node taken_rviImm_b30_20_2 = mux(_taken_rviImm_b30_20_T_6, _taken_rviImm_b30_20_T_8, taken_rviImm_sign_2) node _taken_rviImm_b19_12_T_10 = neq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b19_12_T_11 = neq(UInt<3>(0h3), UInt<3>(0h3)) node _taken_rviImm_b19_12_T_12 = and(_taken_rviImm_b19_12_T_10, _taken_rviImm_b19_12_T_11) node _taken_rviImm_b19_12_T_13 = bits(taken_rviBits_1, 19, 12) node _taken_rviImm_b19_12_T_14 = asSInt(_taken_rviImm_b19_12_T_13) node taken_rviImm_b19_12_2 = mux(_taken_rviImm_b19_12_T_12, taken_rviImm_sign_2, _taken_rviImm_b19_12_T_14) node _taken_rviImm_b11_T_22 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b11_T_23 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b11_T_24 = or(_taken_rviImm_b11_T_22, _taken_rviImm_b11_T_23) node _taken_rviImm_b11_T_25 = eq(UInt<3>(0h3), UInt<3>(0h3)) node _taken_rviImm_b11_T_26 = bits(taken_rviBits_1, 20, 20) node _taken_rviImm_b11_T_27 = asSInt(_taken_rviImm_b11_T_26) node _taken_rviImm_b11_T_28 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _taken_rviImm_b11_T_29 = bits(taken_rviBits_1, 7, 7) node _taken_rviImm_b11_T_30 = asSInt(_taken_rviImm_b11_T_29) node _taken_rviImm_b11_T_31 = mux(_taken_rviImm_b11_T_28, _taken_rviImm_b11_T_30, taken_rviImm_sign_2) node _taken_rviImm_b11_T_32 = mux(_taken_rviImm_b11_T_25, _taken_rviImm_b11_T_27, _taken_rviImm_b11_T_31) node taken_rviImm_b11_2 = mux(_taken_rviImm_b11_T_24, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_32) node _taken_rviImm_b10_5_T_8 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b10_5_T_9 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b10_5_T_10 = or(_taken_rviImm_b10_5_T_8, _taken_rviImm_b10_5_T_9) node _taken_rviImm_b10_5_T_11 = bits(taken_rviBits_1, 30, 25) node taken_rviImm_b10_5_2 = mux(_taken_rviImm_b10_5_T_10, UInt<1>(0h0), _taken_rviImm_b10_5_T_11) node _taken_rviImm_b4_1_T_20 = eq(UInt<3>(0h3), UInt<3>(0h2)) node _taken_rviImm_b4_1_T_21 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _taken_rviImm_b4_1_T_22 = eq(UInt<3>(0h3), UInt<3>(0h1)) node _taken_rviImm_b4_1_T_23 = or(_taken_rviImm_b4_1_T_21, _taken_rviImm_b4_1_T_22) node _taken_rviImm_b4_1_T_24 = bits(taken_rviBits_1, 11, 8) node _taken_rviImm_b4_1_T_25 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b4_1_T_26 = bits(taken_rviBits_1, 19, 16) node _taken_rviImm_b4_1_T_27 = bits(taken_rviBits_1, 24, 21) node _taken_rviImm_b4_1_T_28 = mux(_taken_rviImm_b4_1_T_25, _taken_rviImm_b4_1_T_26, _taken_rviImm_b4_1_T_27) node _taken_rviImm_b4_1_T_29 = mux(_taken_rviImm_b4_1_T_23, _taken_rviImm_b4_1_T_24, _taken_rviImm_b4_1_T_28) node taken_rviImm_b4_1_2 = mux(_taken_rviImm_b4_1_T_20, UInt<1>(0h0), _taken_rviImm_b4_1_T_29) node _taken_rviImm_b0_T_16 = eq(UInt<3>(0h3), UInt<3>(0h0)) node _taken_rviImm_b0_T_17 = bits(taken_rviBits_1, 7, 7) node _taken_rviImm_b0_T_18 = eq(UInt<3>(0h3), UInt<3>(0h4)) node _taken_rviImm_b0_T_19 = bits(taken_rviBits_1, 20, 20) node _taken_rviImm_b0_T_20 = eq(UInt<3>(0h3), UInt<3>(0h5)) node _taken_rviImm_b0_T_21 = bits(taken_rviBits_1, 15, 15) node _taken_rviImm_b0_T_22 = mux(_taken_rviImm_b0_T_20, _taken_rviImm_b0_T_21, UInt<1>(0h0)) node _taken_rviImm_b0_T_23 = mux(_taken_rviImm_b0_T_18, _taken_rviImm_b0_T_19, _taken_rviImm_b0_T_22) node taken_rviImm_b0_2 = mux(_taken_rviImm_b0_T_16, _taken_rviImm_b0_T_17, _taken_rviImm_b0_T_23) node taken_rviImm_lo_hi_2 = cat(taken_rviImm_b10_5_2, taken_rviImm_b4_1_2) node taken_rviImm_lo_2 = cat(taken_rviImm_lo_hi_2, taken_rviImm_b0_2) node taken_rviImm_hi_lo_lo_2 = asUInt(taken_rviImm_b11_2) node taken_rviImm_hi_lo_hi_2 = asUInt(taken_rviImm_b19_12_2) node taken_rviImm_hi_lo_2 = cat(taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2) node taken_rviImm_hi_hi_lo_2 = asUInt(taken_rviImm_b30_20_2) node taken_rviImm_hi_hi_hi_2 = asUInt(taken_rviImm_sign_2) node taken_rviImm_hi_hi_2 = cat(taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2) node taken_rviImm_hi_2 = cat(taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2) node _taken_rviImm_T_6 = cat(taken_rviImm_hi_2, taken_rviImm_lo_2) node _taken_rviImm_T_7 = asSInt(_taken_rviImm_T_6) node _taken_rviImm_sign_T_9 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_sign_T_10 = bits(taken_rviBits_1, 31, 31) node _taken_rviImm_sign_T_11 = asSInt(_taken_rviImm_sign_T_10) node taken_rviImm_sign_3 = mux(_taken_rviImm_sign_T_9, asSInt(UInt<1>(0h0)), _taken_rviImm_sign_T_11) node _taken_rviImm_b30_20_T_9 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b30_20_T_10 = bits(taken_rviBits_1, 30, 20) node _taken_rviImm_b30_20_T_11 = asSInt(_taken_rviImm_b30_20_T_10) node taken_rviImm_b30_20_3 = mux(_taken_rviImm_b30_20_T_9, _taken_rviImm_b30_20_T_11, taken_rviImm_sign_3) node _taken_rviImm_b19_12_T_15 = neq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b19_12_T_16 = neq(UInt<3>(0h1), UInt<3>(0h3)) node _taken_rviImm_b19_12_T_17 = and(_taken_rviImm_b19_12_T_15, _taken_rviImm_b19_12_T_16) node _taken_rviImm_b19_12_T_18 = bits(taken_rviBits_1, 19, 12) node _taken_rviImm_b19_12_T_19 = asSInt(_taken_rviImm_b19_12_T_18) node taken_rviImm_b19_12_3 = mux(_taken_rviImm_b19_12_T_17, taken_rviImm_sign_3, _taken_rviImm_b19_12_T_19) node _taken_rviImm_b11_T_33 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b11_T_34 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b11_T_35 = or(_taken_rviImm_b11_T_33, _taken_rviImm_b11_T_34) node _taken_rviImm_b11_T_36 = eq(UInt<3>(0h1), UInt<3>(0h3)) node _taken_rviImm_b11_T_37 = bits(taken_rviBits_1, 20, 20) node _taken_rviImm_b11_T_38 = asSInt(_taken_rviImm_b11_T_37) node _taken_rviImm_b11_T_39 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _taken_rviImm_b11_T_40 = bits(taken_rviBits_1, 7, 7) node _taken_rviImm_b11_T_41 = asSInt(_taken_rviImm_b11_T_40) node _taken_rviImm_b11_T_42 = mux(_taken_rviImm_b11_T_39, _taken_rviImm_b11_T_41, taken_rviImm_sign_3) node _taken_rviImm_b11_T_43 = mux(_taken_rviImm_b11_T_36, _taken_rviImm_b11_T_38, _taken_rviImm_b11_T_42) node taken_rviImm_b11_3 = mux(_taken_rviImm_b11_T_35, asSInt(UInt<1>(0h0)), _taken_rviImm_b11_T_43) node _taken_rviImm_b10_5_T_12 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b10_5_T_13 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b10_5_T_14 = or(_taken_rviImm_b10_5_T_12, _taken_rviImm_b10_5_T_13) node _taken_rviImm_b10_5_T_15 = bits(taken_rviBits_1, 30, 25) node taken_rviImm_b10_5_3 = mux(_taken_rviImm_b10_5_T_14, UInt<1>(0h0), _taken_rviImm_b10_5_T_15) node _taken_rviImm_b4_1_T_30 = eq(UInt<3>(0h1), UInt<3>(0h2)) node _taken_rviImm_b4_1_T_31 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _taken_rviImm_b4_1_T_32 = eq(UInt<3>(0h1), UInt<3>(0h1)) node _taken_rviImm_b4_1_T_33 = or(_taken_rviImm_b4_1_T_31, _taken_rviImm_b4_1_T_32) node _taken_rviImm_b4_1_T_34 = bits(taken_rviBits_1, 11, 8) node _taken_rviImm_b4_1_T_35 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b4_1_T_36 = bits(taken_rviBits_1, 19, 16) node _taken_rviImm_b4_1_T_37 = bits(taken_rviBits_1, 24, 21) node _taken_rviImm_b4_1_T_38 = mux(_taken_rviImm_b4_1_T_35, _taken_rviImm_b4_1_T_36, _taken_rviImm_b4_1_T_37) node _taken_rviImm_b4_1_T_39 = mux(_taken_rviImm_b4_1_T_33, _taken_rviImm_b4_1_T_34, _taken_rviImm_b4_1_T_38) node taken_rviImm_b4_1_3 = mux(_taken_rviImm_b4_1_T_30, UInt<1>(0h0), _taken_rviImm_b4_1_T_39) node _taken_rviImm_b0_T_24 = eq(UInt<3>(0h1), UInt<3>(0h0)) node _taken_rviImm_b0_T_25 = bits(taken_rviBits_1, 7, 7) node _taken_rviImm_b0_T_26 = eq(UInt<3>(0h1), UInt<3>(0h4)) node _taken_rviImm_b0_T_27 = bits(taken_rviBits_1, 20, 20) node _taken_rviImm_b0_T_28 = eq(UInt<3>(0h1), UInt<3>(0h5)) node _taken_rviImm_b0_T_29 = bits(taken_rviBits_1, 15, 15) node _taken_rviImm_b0_T_30 = mux(_taken_rviImm_b0_T_28, _taken_rviImm_b0_T_29, UInt<1>(0h0)) node _taken_rviImm_b0_T_31 = mux(_taken_rviImm_b0_T_26, _taken_rviImm_b0_T_27, _taken_rviImm_b0_T_30) node taken_rviImm_b0_3 = mux(_taken_rviImm_b0_T_24, _taken_rviImm_b0_T_25, _taken_rviImm_b0_T_31) node taken_rviImm_lo_hi_3 = cat(taken_rviImm_b10_5_3, taken_rviImm_b4_1_3) node taken_rviImm_lo_3 = cat(taken_rviImm_lo_hi_3, taken_rviImm_b0_3) node taken_rviImm_hi_lo_lo_3 = asUInt(taken_rviImm_b11_3) node taken_rviImm_hi_lo_hi_3 = asUInt(taken_rviImm_b19_12_3) node taken_rviImm_hi_lo_3 = cat(taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3) node taken_rviImm_hi_hi_lo_3 = asUInt(taken_rviImm_b30_20_3) node taken_rviImm_hi_hi_hi_3 = asUInt(taken_rviImm_sign_3) node taken_rviImm_hi_hi_3 = cat(taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3) node taken_rviImm_hi_3 = cat(taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3) node _taken_rviImm_T_8 = cat(taken_rviImm_hi_3, taken_rviImm_lo_3) node _taken_rviImm_T_9 = asSInt(_taken_rviImm_T_8) node taken_rviImm_1 = mux(_taken_rviImm_T_5, _taken_rviImm_T_7, _taken_rviImm_T_9) node _taken_predict_taken_T_1 = bits(s2_btb_resp_bits.bht.value, 0, 0) node taken_predict_taken_1 = or(_taken_predict_taken_T_1, UInt<1>(0h0)) node _taken_taken_T_9 = or(taken_rviJump_1, taken_rviJALR_1) node _taken_taken_T_10 = and(taken_rviBranch_1, taken_predict_taken_1) node _taken_taken_T_11 = or(_taken_taken_T_9, _taken_taken_T_10) node _taken_taken_T_12 = and(taken_prevRVI_1, _taken_taken_T_11) node _taken_taken_T_13 = or(taken_rvcJump_1, taken_rvcJALR_1) node _taken_taken_T_14 = or(_taken_taken_T_13, taken_rvcJR_1) node _taken_taken_T_15 = and(taken_rvcBranch_1, taken_predict_taken_1) node _taken_taken_T_16 = or(_taken_taken_T_14, _taken_taken_T_15) node _taken_taken_T_17 = and(taken_valid_1, _taken_taken_T_16) node taken_taken_1 = or(_taken_taken_T_12, _taken_taken_T_17) node _taken_predictReturn_T_3 = and(taken_prevRVI_1, taken_rviReturn_1) node _taken_predictReturn_T_4 = and(taken_valid_1, taken_rvcReturn_1) node _taken_predictReturn_T_5 = or(_taken_predictReturn_T_3, _taken_predictReturn_T_4) node taken_predictReturn_1 = and(btb.io.ras_head.valid, _taken_predictReturn_T_5) node _taken_predictJump_T_2 = and(taken_prevRVI_1, taken_rviJump_1) node _taken_predictJump_T_3 = and(taken_valid_1, taken_rvcJump_1) node taken_predictJump_1 = or(_taken_predictJump_T_2, _taken_predictJump_T_3) node _taken_predictBranch_T_3 = and(taken_prevRVI_1, taken_rviBranch_1) node _taken_predictBranch_T_4 = and(taken_valid_1, taken_rvcBranch_1) node _taken_predictBranch_T_5 = or(_taken_predictBranch_T_3, _taken_predictBranch_T_4) node taken_predictBranch_1 = and(taken_predict_taken_1, _taken_predictBranch_T_5) node _taken_T_29 = and(s2_valid, s2_btb_resp_valid) node _taken_T_30 = eq(s2_btb_resp_bits.bridx, UInt<1>(0h1)) node _taken_T_31 = and(_taken_T_29, _taken_T_30) node _taken_T_32 = and(_taken_T_31, taken_valid_1) node _taken_T_33 = eq(taken_rvc_1, UInt<1>(0h0)) node _taken_T_34 = and(_taken_T_32, _taken_T_33) when _taken_T_34 : connect btb.io.flush, UInt<1>(0h1) connect fq.io.enq.bits.replay, UInt<1>(0h1) connect wrong_path, UInt<1>(0h1) node _taken_T_35 = eq(_taken_T_28, UInt<1>(0h0)) when _taken_T_35 : connect taken_idx, UInt<1>(0h1) connect after_idx, UInt<2>(0h2) node _taken_btb_io_ras_update_valid_T_9 = and(fq.io.enq.ready, fq.io.enq.valid) node _taken_btb_io_ras_update_valid_T_10 = eq(wrong_path, UInt<1>(0h0)) node _taken_btb_io_ras_update_valid_T_11 = and(_taken_btb_io_ras_update_valid_T_9, _taken_btb_io_ras_update_valid_T_10) node _taken_btb_io_ras_update_valid_T_12 = or(taken_rviCall_1, taken_rviReturn_1) node _taken_btb_io_ras_update_valid_T_13 = and(taken_prevRVI_1, _taken_btb_io_ras_update_valid_T_12) node _taken_btb_io_ras_update_valid_T_14 = or(taken_rvcCall_1, taken_rvcReturn_1) node _taken_btb_io_ras_update_valid_T_15 = and(taken_valid_1, _taken_btb_io_ras_update_valid_T_14) node _taken_btb_io_ras_update_valid_T_16 = or(_taken_btb_io_ras_update_valid_T_13, _taken_btb_io_ras_update_valid_T_15) node _taken_btb_io_ras_update_valid_T_17 = and(_taken_btb_io_ras_update_valid_T_11, _taken_btb_io_ras_update_valid_T_16) connect btb.io.ras_update.valid, _taken_btb_io_ras_update_valid_T_17 node _taken_btb_io_ras_update_bits_cfiType_T_8 = mux(taken_prevRVI_1, taken_rviReturn_1, taken_rvcReturn_1) node _taken_btb_io_ras_update_bits_cfiType_T_9 = mux(taken_prevRVI_1, taken_rviCall_1, taken_rvcCall_1) node _taken_btb_io_ras_update_bits_cfiType_T_10 = mux(taken_prevRVI_1, taken_rviBranch_1, taken_rvcBranch_1) node _taken_btb_io_ras_update_bits_cfiType_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _taken_btb_io_ras_update_bits_cfiType_T_12 = and(_taken_btb_io_ras_update_bits_cfiType_T_10, _taken_btb_io_ras_update_bits_cfiType_T_11) node _taken_btb_io_ras_update_bits_cfiType_T_13 = mux(_taken_btb_io_ras_update_bits_cfiType_T_12, UInt<1>(0h0), UInt<1>(0h1)) node _taken_btb_io_ras_update_bits_cfiType_T_14 = mux(_taken_btb_io_ras_update_bits_cfiType_T_9, UInt<2>(0h2), _taken_btb_io_ras_update_bits_cfiType_T_13) node _taken_btb_io_ras_update_bits_cfiType_T_15 = mux(_taken_btb_io_ras_update_bits_cfiType_T_8, UInt<2>(0h3), _taken_btb_io_ras_update_bits_cfiType_T_14) connect btb.io.ras_update.bits.cfiType, _taken_btb_io_ras_update_bits_cfiType_T_15 node _taken_T_36 = eq(s2_btb_taken, UInt<1>(0h0)) when _taken_T_36 : node _taken_T_37 = and(fq.io.enq.ready, fq.io.enq.valid) node _taken_T_38 = and(_taken_T_37, taken_taken_1) node _taken_T_39 = eq(taken_predictBranch_1, UInt<1>(0h0)) node _taken_T_40 = and(_taken_T_38, _taken_T_39) node _taken_T_41 = eq(taken_predictJump_1, UInt<1>(0h0)) node _taken_T_42 = and(_taken_T_40, _taken_T_41) node _taken_T_43 = eq(taken_predictReturn_1, UInt<1>(0h0)) node _taken_T_44 = and(_taken_T_42, _taken_T_43) when _taken_T_44 : connect wrong_path, UInt<1>(0h1) node _taken_T_45 = and(s2_valid, taken_predictReturn_1) when _taken_T_45 : connect useRAS, UInt<1>(0h1) node _taken_T_46 = or(taken_predictBranch_1, taken_predictJump_1) node _taken_T_47 = and(s2_valid, _taken_T_46) when _taken_T_47 : node taken_pc_1 = or(s2_base_pc, UInt<2>(0h2)) node _taken_npc_T_5 = sub(taken_pc_1, UInt<2>(0h2)) node _taken_npc_T_6 = tail(_taken_npc_T_5, 1) node _taken_npc_T_7 = mux(taken_prevRVI_1, _taken_npc_T_6, taken_pc_1) node _taken_npc_T_8 = asSInt(_taken_npc_T_7) node _taken_npc_T_9 = mux(taken_prevRVI_1, taken_rviImm_1, taken_rvcImm_1) node _taken_npc_T_10 = add(_taken_npc_T_8, _taken_npc_T_9) node _taken_npc_T_11 = tail(_taken_npc_T_10, 1) node taken_npc_1 = asSInt(_taken_npc_T_11) node _taken_predicted_npc_T_1 = asUInt(taken_npc_1) connect predicted_npc, _taken_predicted_npc_T_1 node _taken_T_48 = and(taken_prevRVI_1, taken_rviBranch_1) node _taken_T_49 = and(taken_valid_1, taken_rvcBranch_1) node _taken_T_50 = or(_taken_T_48, _taken_T_49) when _taken_T_50 : node _taken_btb_io_bht_advance_valid_T_3 = and(fq.io.enq.ready, fq.io.enq.valid) node _taken_btb_io_bht_advance_valid_T_4 = eq(wrong_path, UInt<1>(0h0)) node _taken_btb_io_bht_advance_valid_T_5 = and(_taken_btb_io_bht_advance_valid_T_3, _taken_btb_io_bht_advance_valid_T_4) connect btb.io.bht_advance.valid, _taken_btb_io_bht_advance_valid_T_5 connect btb.io.bht_advance.bits.bht.value, s2_btb_resp_bits.bht.value connect btb.io.bht_advance.bits.bht.history, s2_btb_resp_bits.bht.history connect btb.io.bht_advance.bits.entry, s2_btb_resp_bits.entry connect btb.io.bht_advance.bits.target, s2_btb_resp_bits.target connect btb.io.bht_advance.bits.bridx, s2_btb_resp_bits.bridx connect btb.io.bht_advance.bits.mask, s2_btb_resp_bits.mask connect btb.io.bht_advance.bits.taken, s2_btb_resp_bits.taken connect btb.io.bht_advance.bits.cfiType, s2_btb_resp_bits.cfiType node _taken_T_51 = eq(s2_btb_resp_valid, UInt<1>(0h0)) node _taken_T_52 = eq(s2_btb_resp_bits.bht.value, UInt<1>(0h1)) node _taken_T_53 = and(taken_predictBranch_1, _taken_T_52) node _taken_T_54 = or(_taken_T_53, taken_predictJump_1) node _taken_T_55 = or(_taken_T_54, taken_predictReturn_1) node _taken_T_56 = and(_taken_T_51, _taken_T_55) when _taken_T_56 : connect updateBTB, UInt<1>(0h1) node _taken_T_57 = and(fq.io.enq.ready, fq.io.enq.valid) when _taken_T_57 : connect s2_partial_insn_valid, UInt<1>(0h0) node _taken_T_58 = eq(_taken_T_28, UInt<1>(0h0)) node _taken_T_59 = and(taken_valid_1, _taken_T_58) node _taken_T_60 = eq(taken_rvc_1, UInt<1>(0h0)) node _taken_T_61 = and(_taken_T_59, _taken_T_60) when _taken_T_61 : connect s2_partial_insn_valid, UInt<1>(0h1) node _taken_s2_partial_insn_T = or(taken_bits_1, UInt<2>(0h3)) connect s2_partial_insn, _taken_s2_partial_insn_T node taken = or(_taken_T_28, taken_taken_1) when useRAS : connect predicted_npc, btb.io.ras_head.bits node _T_26 = and(fq.io.enq.ready, fq.io.enq.valid) node _T_27 = or(s2_btb_taken, taken) node _T_28 = and(_T_26, _T_27) when _T_28 : connect s2_partial_insn_valid, UInt<1>(0h0) node _T_29 = eq(s2_btb_taken, UInt<1>(0h0)) when _T_29 : when taken : connect fq.io.enq.bits.btb.bridx, taken_idx connect fq.io.enq.bits.btb.taken, UInt<1>(0h1) connect fq.io.enq.bits.btb.entry, UInt<5>(0h1c) node _T_30 = and(fq.io.enq.ready, fq.io.enq.valid) when _T_30 : connect s2_redirect, UInt<1>(0h1) node _T_31 = eq(s2_partial_insn_valid, UInt<1>(0h0)) node _T_32 = bits(fq.io.enq.bits.mask, 0, 0) node _T_33 = or(_T_31, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Frontend.scala:345 assert(!s2_partial_insn_valid || fq.io.enq.bits.mask(0))\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 when s2_redirect : connect s2_partial_insn_valid, UInt<1>(0h0) when io.cpu.req.valid : connect wrong_path, UInt<1>(0h0) connect io.cpu.resp.bits, fq.io.deq.bits connect io.cpu.resp.valid, fq.io.deq.valid connect fq.io.deq.ready, io.cpu.resp.ready reg gpa_valid : UInt<1>, clock reg gpa : UInt<40>, clock reg gpa_is_pte : UInt<1>, clock node _T_37 = and(fq.io.enq.ready, fq.io.enq.valid) node _T_38 = and(_T_37, s2_tlb_resp.gf.inst) when _T_38 : node _T_39 = eq(gpa_valid, UInt<1>(0h0)) when _T_39 : connect gpa, s2_tlb_resp.gpa connect gpa_is_pte, s2_tlb_resp.gpa_is_pte connect gpa_valid, UInt<1>(0h1) when io.cpu.req.valid : connect gpa_valid, UInt<1>(0h0) connect io.cpu.gpa.valid, gpa_valid connect io.cpu.gpa.bits, gpa connect io.cpu.gpa_is_pte, gpa_is_pte connect io.cpu.perf.acquire, icache.io.perf.acquire node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid) connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T connect io.errors, icache.io.errors node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _clock_en_reg_T_1 = or(_clock_en_reg_T, io.cpu.might_request) node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, icache.io.keep_clock_enabled) node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, s1_valid) node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, s2_valid) node _clock_en_reg_T_5 = eq(tlb.io.req.ready, UInt<1>(0h0)) node _clock_en_reg_T_6 = or(_clock_en_reg_T_4, _clock_en_reg_T_5) node _clock_en_reg_T_7 = bits(fq.io.mask, 4, 4) node _clock_en_reg_T_8 = eq(_clock_en_reg_T_7, UInt<1>(0h0)) node _clock_en_reg_T_9 = or(_clock_en_reg_T_6, _clock_en_reg_T_8) connect clock_en_reg, _clock_en_reg_T_9
module Frontend( // @[Frontend.scala:82:7] input clock, // @[Frontend.scala:82:7] input reset, // @[Frontend.scala:82:7] output auto_icache_slave_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_icache_slave_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_slave_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_slave_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icache_slave_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [12:0] auto_icache_slave_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [21:0] auto_icache_slave_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_slave_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [31:0] auto_icache_slave_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_slave_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_icache_slave_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_slave_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_icache_slave_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_icache_slave_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [12:0] auto_icache_slave_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_slave_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_a_valid, // @[LazyModuleImp.scala:107:25] output [31:0] auto_icache_master_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output auto_icache_master_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_icache_master_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_icache_master_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_icache_master_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_icache_master_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_icache_master_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_icache_hart_id_sink_in, // @[LazyModuleImp.scala:107:25] input io_cpu_might_request, // @[Frontend.scala:85:14] input io_cpu_req_valid, // @[Frontend.scala:85:14] input [39:0] io_cpu_req_bits_pc, // @[Frontend.scala:85:14] input io_cpu_req_bits_speculative, // @[Frontend.scala:85:14] input io_cpu_sfence_valid, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs1, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_rs2, // @[Frontend.scala:85:14] input [38:0] io_cpu_sfence_bits_addr, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_asid, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_hv, // @[Frontend.scala:85:14] input io_cpu_sfence_bits_hg, // @[Frontend.scala:85:14] input io_cpu_resp_ready, // @[Frontend.scala:85:14] output io_cpu_resp_valid, // @[Frontend.scala:85:14] output [1:0] io_cpu_resp_bits_btb_cfiType, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_taken, // @[Frontend.scala:85:14] output [1:0] io_cpu_resp_bits_btb_mask, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_bridx, // @[Frontend.scala:85:14] output [38:0] io_cpu_resp_bits_btb_target, // @[Frontend.scala:85:14] output [4:0] io_cpu_resp_bits_btb_entry, // @[Frontend.scala:85:14] output [7:0] io_cpu_resp_bits_btb_bht_history, // @[Frontend.scala:85:14] output io_cpu_resp_bits_btb_bht_value, // @[Frontend.scala:85:14] output [39:0] io_cpu_resp_bits_pc, // @[Frontend.scala:85:14] output [31:0] io_cpu_resp_bits_data, // @[Frontend.scala:85:14] output [1:0] io_cpu_resp_bits_mask, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_pf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_gf_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_xcpt_ae_inst, // @[Frontend.scala:85:14] output io_cpu_resp_bits_replay, // @[Frontend.scala:85:14] output io_cpu_gpa_valid, // @[Frontend.scala:85:14] output [39:0] io_cpu_gpa_bits, // @[Frontend.scala:85:14] output io_cpu_gpa_is_pte, // @[Frontend.scala:85:14] input io_cpu_btb_update_valid, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_prediction_cfiType, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_prediction_taken, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_prediction_mask, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_prediction_bridx, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_prediction_target, // @[Frontend.scala:85:14] input [4:0] io_cpu_btb_update_bits_prediction_entry, // @[Frontend.scala:85:14] input [7:0] io_cpu_btb_update_bits_prediction_bht_history, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_prediction_bht_value, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_pc, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_target, // @[Frontend.scala:85:14] input io_cpu_btb_update_bits_isValid, // @[Frontend.scala:85:14] input [38:0] io_cpu_btb_update_bits_br_pc, // @[Frontend.scala:85:14] input [1:0] io_cpu_btb_update_bits_cfiType, // @[Frontend.scala:85:14] input io_cpu_bht_update_valid, // @[Frontend.scala:85:14] input [7:0] io_cpu_bht_update_bits_prediction_history, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_prediction_value, // @[Frontend.scala:85:14] input [38:0] io_cpu_bht_update_bits_pc, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_branch, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_taken, // @[Frontend.scala:85:14] input io_cpu_bht_update_bits_mispredict, // @[Frontend.scala:85:14] input io_cpu_flush_icache, // @[Frontend.scala:85:14] output [39:0] io_cpu_npc, // @[Frontend.scala:85:14] output io_cpu_perf_acquire, // @[Frontend.scala:85:14] output io_cpu_perf_tlbMiss, // @[Frontend.scala:85:14] input io_cpu_progress, // @[Frontend.scala:85:14] input io_ptw_req_ready, // @[Frontend.scala:85:14] output io_ptw_req_valid, // @[Frontend.scala:85:14] output io_ptw_req_bits_valid, // @[Frontend.scala:85:14] output [26:0] io_ptw_req_bits_bits_addr, // @[Frontend.scala:85:14] output io_ptw_req_bits_bits_need_gpa, // @[Frontend.scala:85:14] input io_ptw_resp_valid, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_ptw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_ae_final, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gf, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hr, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hw, // @[Frontend.scala:85:14] input io_ptw_resp_bits_hx, // @[Frontend.scala:85:14] input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[Frontend.scala:85:14] input [43:0] io_ptw_resp_bits_pte_ppn, // @[Frontend.scala:85:14] input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_d, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_a, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_g, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_u, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_x, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_w, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_r, // @[Frontend.scala:85:14] input io_ptw_resp_bits_pte_v, // @[Frontend.scala:85:14] input [1:0] io_ptw_resp_bits_level, // @[Frontend.scala:85:14] input io_ptw_resp_bits_homogeneous, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gpa_valid, // @[Frontend.scala:85:14] input [38:0] io_ptw_resp_bits_gpa_bits, // @[Frontend.scala:85:14] input io_ptw_resp_bits_gpa_is_pte, // @[Frontend.scala:85:14] input [3:0] io_ptw_ptbr_mode, // @[Frontend.scala:85:14] input [43:0] io_ptw_ptbr_ppn, // @[Frontend.scala:85:14] input io_ptw_status_debug, // @[Frontend.scala:85:14] input io_ptw_status_cease, // @[Frontend.scala:85:14] input io_ptw_status_wfi, // @[Frontend.scala:85:14] input [31:0] io_ptw_status_isa, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_dprv, // @[Frontend.scala:85:14] input io_ptw_status_dv, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_prv, // @[Frontend.scala:85:14] input io_ptw_status_v, // @[Frontend.scala:85:14] input io_ptw_status_sd, // @[Frontend.scala:85:14] input io_ptw_status_mpv, // @[Frontend.scala:85:14] input io_ptw_status_gva, // @[Frontend.scala:85:14] input io_ptw_status_tsr, // @[Frontend.scala:85:14] input io_ptw_status_tw, // @[Frontend.scala:85:14] input io_ptw_status_tvm, // @[Frontend.scala:85:14] input io_ptw_status_mxr, // @[Frontend.scala:85:14] input io_ptw_status_sum, // @[Frontend.scala:85:14] input io_ptw_status_mprv, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_fs, // @[Frontend.scala:85:14] input [1:0] io_ptw_status_mpp, // @[Frontend.scala:85:14] input io_ptw_status_spp, // @[Frontend.scala:85:14] input io_ptw_status_mpie, // @[Frontend.scala:85:14] input io_ptw_status_spie, // @[Frontend.scala:85:14] input io_ptw_status_mie, // @[Frontend.scala:85:14] input io_ptw_status_sie, // @[Frontend.scala:85:14] input io_ptw_hstatus_spvp, // @[Frontend.scala:85:14] input io_ptw_hstatus_spv, // @[Frontend.scala:85:14] input io_ptw_hstatus_gva, // @[Frontend.scala:85:14] input io_ptw_gstatus_debug, // @[Frontend.scala:85:14] input io_ptw_gstatus_cease, // @[Frontend.scala:85:14] input io_ptw_gstatus_wfi, // @[Frontend.scala:85:14] input [31:0] io_ptw_gstatus_isa, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_dprv, // @[Frontend.scala:85:14] input io_ptw_gstatus_dv, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_prv, // @[Frontend.scala:85:14] input io_ptw_gstatus_v, // @[Frontend.scala:85:14] input io_ptw_gstatus_sd, // @[Frontend.scala:85:14] input [22:0] io_ptw_gstatus_zero2, // @[Frontend.scala:85:14] input io_ptw_gstatus_mpv, // @[Frontend.scala:85:14] input io_ptw_gstatus_gva, // @[Frontend.scala:85:14] input io_ptw_gstatus_mbe, // @[Frontend.scala:85:14] input io_ptw_gstatus_sbe, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_sxl, // @[Frontend.scala:85:14] input [7:0] io_ptw_gstatus_zero1, // @[Frontend.scala:85:14] input io_ptw_gstatus_tsr, // @[Frontend.scala:85:14] input io_ptw_gstatus_tw, // @[Frontend.scala:85:14] input io_ptw_gstatus_tvm, // @[Frontend.scala:85:14] input io_ptw_gstatus_mxr, // @[Frontend.scala:85:14] input io_ptw_gstatus_sum, // @[Frontend.scala:85:14] input io_ptw_gstatus_mprv, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_fs, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_mpp, // @[Frontend.scala:85:14] input [1:0] io_ptw_gstatus_vs, // @[Frontend.scala:85:14] input io_ptw_gstatus_spp, // @[Frontend.scala:85:14] input io_ptw_gstatus_mpie, // @[Frontend.scala:85:14] input io_ptw_gstatus_ube, // @[Frontend.scala:85:14] input io_ptw_gstatus_spie, // @[Frontend.scala:85:14] input io_ptw_gstatus_upie, // @[Frontend.scala:85:14] input io_ptw_gstatus_mie, // @[Frontend.scala:85:14] input io_ptw_gstatus_hie, // @[Frontend.scala:85:14] input io_ptw_gstatus_sie, // @[Frontend.scala:85:14] input io_ptw_gstatus_uie, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_0_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_0_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_0_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_0_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_1_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_1_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_1_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_1_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_2_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_2_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_2_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_2_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_3_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_3_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_3_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_3_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_4_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_4_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_4_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_4_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_5_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_5_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_5_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_5_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_6_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_6_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_6_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_6_mask, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_l, // @[Frontend.scala:85:14] input [1:0] io_ptw_pmp_7_cfg_a, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_x, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_w, // @[Frontend.scala:85:14] input io_ptw_pmp_7_cfg_r, // @[Frontend.scala:85:14] input [29:0] io_ptw_pmp_7_addr, // @[Frontend.scala:85:14] input [31:0] io_ptw_pmp_7_mask, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_0_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_0_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_0_value, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_1_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_1_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_1_value, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_2_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_2_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_2_value, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_3_ren, // @[Frontend.scala:85:14] input io_ptw_customCSRs_csrs_3_wen, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[Frontend.scala:85:14] input [63:0] io_ptw_customCSRs_csrs_3_value // @[Frontend.scala:85:14] ); wire [1:0] btb_io_ras_update_bits_cfiType; // @[Frontend.scala:270:25, :274:40] wire _btb_io_resp_valid; // @[Frontend.scala:198:21] wire [1:0] _btb_io_resp_bits_cfiType; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_taken; // @[Frontend.scala:198:21] wire [1:0] _btb_io_resp_bits_mask; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bridx; // @[Frontend.scala:198:21] wire [38:0] _btb_io_resp_bits_target; // @[Frontend.scala:198:21] wire [4:0] _btb_io_resp_bits_entry; // @[Frontend.scala:198:21] wire [7:0] _btb_io_resp_bits_bht_history; // @[Frontend.scala:198:21] wire _btb_io_resp_bits_bht_value; // @[Frontend.scala:198:21] wire _btb_io_ras_head_valid; // @[Frontend.scala:198:21] wire [38:0] _btb_io_ras_head_bits; // @[Frontend.scala:198:21] wire _tlb_io_req_ready; // @[Frontend.scala:105:19] wire _tlb_io_resp_miss; // @[Frontend.scala:105:19] wire [31:0] _tlb_io_resp_paddr; // @[Frontend.scala:105:19] wire [39:0] _tlb_io_resp_gpa; // @[Frontend.scala:105:19] wire _tlb_io_resp_pf_ld; // @[Frontend.scala:105:19] wire _tlb_io_resp_pf_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_ae_ld; // @[Frontend.scala:105:19] wire _tlb_io_resp_ae_inst; // @[Frontend.scala:105:19] wire _tlb_io_resp_ma_ld; // @[Frontend.scala:105:19] wire _tlb_io_resp_cacheable; // @[Frontend.scala:105:19] wire _tlb_io_resp_prefetchable; // @[Frontend.scala:105:19] wire _fq_io_enq_ready; // @[Frontend.scala:91:64] wire [4:0] _fq_io_mask; // @[Frontend.scala:91:64] wire _icache_io_resp_valid; // @[Frontend.scala:70:26] wire [31:0] _icache_io_resp_bits_data; // @[Frontend.scala:70:26] wire _icache_io_resp_bits_ae; // @[Frontend.scala:70:26] wire auto_icache_slave_in_a_valid_0 = auto_icache_slave_in_a_valid; // @[Frontend.scala:82:7] wire [2:0] auto_icache_slave_in_a_bits_opcode_0 = auto_icache_slave_in_a_bits_opcode; // @[Frontend.scala:82:7] wire [2:0] auto_icache_slave_in_a_bits_param_0 = auto_icache_slave_in_a_bits_param; // @[Frontend.scala:82:7] wire [1:0] auto_icache_slave_in_a_bits_size_0 = auto_icache_slave_in_a_bits_size; // @[Frontend.scala:82:7] wire [12:0] auto_icache_slave_in_a_bits_source_0 = auto_icache_slave_in_a_bits_source; // @[Frontend.scala:82:7] wire [21:0] auto_icache_slave_in_a_bits_address_0 = auto_icache_slave_in_a_bits_address; // @[Frontend.scala:82:7] wire [3:0] auto_icache_slave_in_a_bits_mask_0 = auto_icache_slave_in_a_bits_mask; // @[Frontend.scala:82:7] wire [31:0] auto_icache_slave_in_a_bits_data_0 = auto_icache_slave_in_a_bits_data; // @[Frontend.scala:82:7] wire auto_icache_slave_in_a_bits_corrupt_0 = auto_icache_slave_in_a_bits_corrupt; // @[Frontend.scala:82:7] wire auto_icache_slave_in_d_ready_0 = auto_icache_slave_in_d_ready; // @[Frontend.scala:82:7] wire auto_icache_master_out_a_ready_0 = auto_icache_master_out_a_ready; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_valid_0 = auto_icache_master_out_d_valid; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_d_bits_opcode_0 = auto_icache_master_out_d_bits_opcode; // @[Frontend.scala:82:7] wire [1:0] auto_icache_master_out_d_bits_param_0 = auto_icache_master_out_d_bits_param; // @[Frontend.scala:82:7] wire [3:0] auto_icache_master_out_d_bits_size_0 = auto_icache_master_out_d_bits_size; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_d_bits_sink_0 = auto_icache_master_out_d_bits_sink; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_bits_denied_0 = auto_icache_master_out_d_bits_denied; // @[Frontend.scala:82:7] wire [63:0] auto_icache_master_out_d_bits_data_0 = auto_icache_master_out_d_bits_data; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_bits_corrupt_0 = auto_icache_master_out_d_bits_corrupt; // @[Frontend.scala:82:7] wire auto_icache_hart_id_sink_in_0 = auto_icache_hart_id_sink_in; // @[Frontend.scala:82:7] wire io_cpu_might_request_0 = io_cpu_might_request; // @[Frontend.scala:82:7] wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[Frontend.scala:82:7] wire [39:0] io_cpu_req_bits_pc_0 = io_cpu_req_bits_pc; // @[Frontend.scala:82:7] wire io_cpu_req_bits_speculative_0 = io_cpu_req_bits_speculative; // @[Frontend.scala:82:7] wire io_cpu_sfence_valid_0 = io_cpu_sfence_valid; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_rs1_0 = io_cpu_sfence_bits_rs1; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_rs2_0 = io_cpu_sfence_bits_rs2; // @[Frontend.scala:82:7] wire [38:0] io_cpu_sfence_bits_addr_0 = io_cpu_sfence_bits_addr; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_asid_0 = io_cpu_sfence_bits_asid; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_hv_0 = io_cpu_sfence_bits_hv; // @[Frontend.scala:82:7] wire io_cpu_sfence_bits_hg_0 = io_cpu_sfence_bits_hg; // @[Frontend.scala:82:7] wire io_cpu_resp_ready_0 = io_cpu_resp_ready; // @[Frontend.scala:82:7] wire io_cpu_btb_update_valid_0 = io_cpu_btb_update_valid; // @[Frontend.scala:82:7] wire [1:0] io_cpu_btb_update_bits_prediction_cfiType_0 = io_cpu_btb_update_bits_prediction_cfiType; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_prediction_taken_0 = io_cpu_btb_update_bits_prediction_taken; // @[Frontend.scala:82:7] wire [1:0] io_cpu_btb_update_bits_prediction_mask_0 = io_cpu_btb_update_bits_prediction_mask; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_prediction_bridx_0 = io_cpu_btb_update_bits_prediction_bridx; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_prediction_target_0 = io_cpu_btb_update_bits_prediction_target; // @[Frontend.scala:82:7] wire [4:0] io_cpu_btb_update_bits_prediction_entry_0 = io_cpu_btb_update_bits_prediction_entry; // @[Frontend.scala:82:7] wire [7:0] io_cpu_btb_update_bits_prediction_bht_history_0 = io_cpu_btb_update_bits_prediction_bht_history; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_prediction_bht_value_0 = io_cpu_btb_update_bits_prediction_bht_value; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_pc_0 = io_cpu_btb_update_bits_pc; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_target_0 = io_cpu_btb_update_bits_target; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_isValid_0 = io_cpu_btb_update_bits_isValid; // @[Frontend.scala:82:7] wire [38:0] io_cpu_btb_update_bits_br_pc_0 = io_cpu_btb_update_bits_br_pc; // @[Frontend.scala:82:7] wire [1:0] io_cpu_btb_update_bits_cfiType_0 = io_cpu_btb_update_bits_cfiType; // @[Frontend.scala:82:7] wire io_cpu_bht_update_valid_0 = io_cpu_bht_update_valid; // @[Frontend.scala:82:7] wire [7:0] io_cpu_bht_update_bits_prediction_history_0 = io_cpu_bht_update_bits_prediction_history; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_prediction_value_0 = io_cpu_bht_update_bits_prediction_value; // @[Frontend.scala:82:7] wire [38:0] io_cpu_bht_update_bits_pc_0 = io_cpu_bht_update_bits_pc; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_branch_0 = io_cpu_bht_update_bits_branch; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_taken_0 = io_cpu_bht_update_bits_taken; // @[Frontend.scala:82:7] wire io_cpu_bht_update_bits_mispredict_0 = io_cpu_bht_update_bits_mispredict; // @[Frontend.scala:82:7] wire io_cpu_flush_icache_0 = io_cpu_flush_icache; // @[Frontend.scala:82:7] wire io_cpu_progress_0 = io_cpu_progress; // @[Frontend.scala:82:7] wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[Frontend.scala:82:7] wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[Frontend.scala:82:7] wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[Frontend.scala:82:7] wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[Frontend.scala:82:7] wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[Frontend.scala:82:7] wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[Frontend.scala:82:7] wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[Frontend.scala:82:7] wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[Frontend.scala:82:7] wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[Frontend.scala:82:7] wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[Frontend.scala:82:7] wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[Frontend.scala:82:7] wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[Frontend.scala:82:7] wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[Frontend.scala:82:7] wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[Frontend.scala:82:7] wire io_ptw_status_v_0 = io_ptw_status_v; // @[Frontend.scala:82:7] wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[Frontend.scala:82:7] wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[Frontend.scala:82:7] wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[Frontend.scala:82:7] wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[Frontend.scala:82:7] wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[Frontend.scala:82:7] wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[Frontend.scala:82:7] wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[Frontend.scala:82:7] wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[Frontend.scala:82:7] wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[Frontend.scala:82:7] wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[Frontend.scala:82:7] wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[Frontend.scala:82:7] wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[Frontend.scala:82:7] wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[Frontend.scala:82:7] wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[Frontend.scala:82:7] wire io_ptw_hstatus_spvp_0 = io_ptw_hstatus_spvp; // @[Frontend.scala:82:7] wire io_ptw_hstatus_spv_0 = io_ptw_hstatus_spv; // @[Frontend.scala:82:7] wire io_ptw_hstatus_gva_0 = io_ptw_hstatus_gva; // @[Frontend.scala:82:7] wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[Frontend.scala:82:7] wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[Frontend.scala:82:7] wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[Frontend.scala:82:7] wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[Frontend.scala:82:7] wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[Frontend.scala:82:7] wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[Frontend.scala:82:7] wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[Frontend.scala:82:7] wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[Frontend.scala:82:7] wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[Frontend.scala:82:7] wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[Frontend.scala:82:7] wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[Frontend.scala:82:7] wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[Frontend.scala:82:7] wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[Frontend.scala:82:7] wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[Frontend.scala:82:7] wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[Frontend.scala:82:7] wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[Frontend.scala:82:7] wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[Frontend.scala:82:7] wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[Frontend.scala:82:7] wire auto_icache_slave_in_d_bits_sink = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_slave_in_d_bits_denied = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_slave_in_d_bits_corrupt = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_master_out_a_bits_source = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_master_out_a_bits_corrupt = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_bits_source = 1'h0; // @[Frontend.scala:82:7] wire auto_icache_mmio_address_prefix_sink_in = 1'h0; // @[Frontend.scala:82:7] wire io_cpu_btb_update_bits_taken = 1'h0; // @[Frontend.scala:82:7] wire io_cpu_ras_update_valid = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_mbe = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_sbe = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_ube = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_upie = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_hie = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_status_uie = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vtw = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_hu = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[Frontend.scala:82:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[Frontend.scala:82:7] wire taken_rvcJAL = 1'h0; // @[Frontend.scala:245:35] wire _taken_rviImm_sign_T = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b19_12_T_1 = 1'h0; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_2 = 1'h0; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_1 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_2 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_6 = 1'h0; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b10_5_T = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_1 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_2 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_1 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_2 = 1'h0; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_3 = 1'h0; // @[RocketCore.scala:1349:34] wire _taken_rviImm_b4_1_T_5 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_2 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_4 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_6 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_7 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0 = 1'h0; // @[RocketCore.scala:1351:17] wire _taken_rviImm_sign_T_3 = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T_3 = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b11_T_11 = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_12 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_13 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_14 = 1'h0; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b10_5_T_4 = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_5 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_6 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T_10 = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_11 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_15 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T_8 = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_10 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_12 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_14 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_15 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0_1 = 1'h0; // @[RocketCore.scala:1351:17] wire taken_rvcJAL_1 = 1'h0; // @[Frontend.scala:245:35] wire _taken_rviImm_sign_T_6 = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T_6 = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b19_12_T_11 = 1'h0; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_12 = 1'h0; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T_22 = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_23 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_24 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_28 = 1'h0; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b10_5_T_8 = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_9 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_10 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T_20 = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_21 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_22 = 1'h0; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_23 = 1'h0; // @[RocketCore.scala:1349:34] wire _taken_rviImm_b4_1_T_25 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T_16 = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_18 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_20 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_22 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_23 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0_2 = 1'h0; // @[RocketCore.scala:1351:17] wire _taken_rviImm_sign_T_9 = 1'h0; // @[RocketCore.scala:1341:24] wire _taken_rviImm_b30_20_T_9 = 1'h0; // @[RocketCore.scala:1342:26] wire _taken_rviImm_b11_T_33 = 1'h0; // @[RocketCore.scala:1344:23] wire _taken_rviImm_b11_T_34 = 1'h0; // @[RocketCore.scala:1344:40] wire _taken_rviImm_b11_T_35 = 1'h0; // @[RocketCore.scala:1344:33] wire _taken_rviImm_b11_T_36 = 1'h0; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b10_5_T_12 = 1'h0; // @[RocketCore.scala:1347:25] wire _taken_rviImm_b10_5_T_13 = 1'h0; // @[RocketCore.scala:1347:42] wire _taken_rviImm_b10_5_T_14 = 1'h0; // @[RocketCore.scala:1347:35] wire _taken_rviImm_b4_1_T_30 = 1'h0; // @[RocketCore.scala:1348:24] wire _taken_rviImm_b4_1_T_31 = 1'h0; // @[RocketCore.scala:1349:24] wire _taken_rviImm_b4_1_T_35 = 1'h0; // @[RocketCore.scala:1350:24] wire _taken_rviImm_b0_T_24 = 1'h0; // @[RocketCore.scala:1351:22] wire _taken_rviImm_b0_T_26 = 1'h0; // @[RocketCore.scala:1352:22] wire _taken_rviImm_b0_T_28 = 1'h0; // @[RocketCore.scala:1353:22] wire _taken_rviImm_b0_T_30 = 1'h0; // @[RocketCore.scala:1353:17] wire _taken_rviImm_b0_T_31 = 1'h0; // @[RocketCore.scala:1352:17] wire taken_rviImm_b0_3 = 1'h0; // @[RocketCore.scala:1351:17] wire io_cpu_clock_enabled = 1'h1; // @[Frontend.scala:82:7] wire clock_en = 1'h1; // @[Frontend.scala:94:31] wire _taken_rviImm_b19_12_T = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b11_T_3 = 1'h1; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b19_12_T_5 = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b19_12_T_6 = 1'h1; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_7 = 1'h1; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T_17 = 1'h1; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b4_1_T_12 = 1'h1; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_13 = 1'h1; // @[RocketCore.scala:1349:34] wire _taken_T_6 = 1'h1; // @[Frontend.scala:270:13] wire _taken_btb_io_ras_update_bits_cfiType_T_3 = 1'h1; // @[Frontend.scala:276:85] wire _taken_rviImm_b19_12_T_10 = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b11_T_25 = 1'h1; // @[RocketCore.scala:1345:23] wire _taken_rviImm_b19_12_T_15 = 1'h1; // @[RocketCore.scala:1343:26] wire _taken_rviImm_b19_12_T_16 = 1'h1; // @[RocketCore.scala:1343:43] wire _taken_rviImm_b19_12_T_17 = 1'h1; // @[RocketCore.scala:1343:36] wire _taken_rviImm_b11_T_39 = 1'h1; // @[RocketCore.scala:1346:23] wire _taken_rviImm_b4_1_T_32 = 1'h1; // @[RocketCore.scala:1349:41] wire _taken_rviImm_b4_1_T_33 = 1'h1; // @[RocketCore.scala:1349:34] wire _taken_btb_io_ras_update_bits_cfiType_T_11 = 1'h1; // @[Frontend.scala:276:85] wire _clock_en_reg_T = 1'h1; // @[Frontend.scala:376:19] wire _clock_en_reg_T_1 = 1'h1; // @[Frontend.scala:376:45] wire _clock_en_reg_T_2 = 1'h1; // @[Frontend.scala:377:26] wire _clock_en_reg_T_3 = 1'h1; // @[Frontend.scala:378:34] wire _clock_en_reg_T_4 = 1'h1; // @[Frontend.scala:379:14] wire _clock_en_reg_T_6 = 1'h1; // @[Frontend.scala:379:26] wire _clock_en_reg_T_9 = 1'h1; // @[Frontend.scala:380:23] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[Frontend.scala:82:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[Frontend.scala:82:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[Frontend.scala:82:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[Frontend.scala:82:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[Frontend.scala:82:7] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[Frontend.scala:82:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[Frontend.scala:82:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[Frontend.scala:82:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[Frontend.scala:82:7] wire [1:0] auto_icache_slave_in_d_bits_param = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_ras_update_bits_cfiType = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[Frontend.scala:82:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[Frontend.scala:82:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[Frontend.scala:82:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[Frontend.scala:82:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[Frontend.scala:82:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[Frontend.scala:82:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h2; // @[Frontend.scala:82:7] wire [1:0] io_ptw_gstatus_uxl = 2'h2; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_a_bits_opcode = 3'h4; // @[Frontend.scala:82:7] wire [2:0] auto_icache_master_out_a_bits_param = 3'h0; // @[Frontend.scala:82:7] wire [3:0] auto_icache_master_out_a_bits_size = 4'h6; // @[Frontend.scala:82:7] wire [7:0] auto_icache_master_out_a_bits_mask = 8'hFF; // @[Frontend.scala:82:7] wire [63:0] auto_icache_master_out_a_bits_data = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[Frontend.scala:82:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[Frontend.scala:82:7] wire [31:0] auto_reset_vector_sink_in = 32'h10000; // @[Frontend.scala:82:7] wire [31:0] resetVectorSinkNodeIn = 32'h10000; // @[MixedNode.scala:551:17] wire [31:0] _s2_pc_T_2 = 32'h10000; // @[Frontend.scala:384:27] wire [38:0] io_cpu_ras_update_bits_returnAddr = 39'h0; // @[Frontend.scala:82:7] wire [31:0] _s2_pc_T = 32'hFFFEFFFF; // @[Frontend.scala:384:29] wire [31:0] _s2_pc_T_1 = 32'hFFFEFFFF; // @[Frontend.scala:384:33] wire [39:0] _io_cpu_npc_T_3; // @[Frontend.scala:384:27] wire _io_cpu_perf_tlbMiss_T; // @[Decoupled.scala:51:35] wire auto_icache_slave_in_a_ready_0; // @[Frontend.scala:82:7] wire [2:0] auto_icache_slave_in_d_bits_opcode_0; // @[Frontend.scala:82:7] wire [1:0] auto_icache_slave_in_d_bits_size_0; // @[Frontend.scala:82:7] wire [12:0] auto_icache_slave_in_d_bits_source_0; // @[Frontend.scala:82:7] wire [31:0] auto_icache_slave_in_d_bits_data_0; // @[Frontend.scala:82:7] wire auto_icache_slave_in_d_valid_0; // @[Frontend.scala:82:7] wire [31:0] auto_icache_master_out_a_bits_address_0; // @[Frontend.scala:82:7] wire auto_icache_master_out_a_valid_0; // @[Frontend.scala:82:7] wire auto_icache_master_out_d_ready_0; // @[Frontend.scala:82:7] wire [7:0] io_cpu_resp_bits_btb_bht_history_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_btb_bht_value_0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_resp_bits_btb_cfiType_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_btb_taken_0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_resp_bits_btb_mask_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_btb_bridx_0; // @[Frontend.scala:82:7] wire [38:0] io_cpu_resp_bits_btb_target_0; // @[Frontend.scala:82:7] wire [4:0] io_cpu_resp_bits_btb_entry_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_xcpt_pf_inst_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_xcpt_gf_inst_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_xcpt_ae_inst_0; // @[Frontend.scala:82:7] wire [39:0] io_cpu_resp_bits_pc_0; // @[Frontend.scala:82:7] wire [31:0] io_cpu_resp_bits_data_0; // @[Frontend.scala:82:7] wire [1:0] io_cpu_resp_bits_mask_0; // @[Frontend.scala:82:7] wire io_cpu_resp_bits_replay_0; // @[Frontend.scala:82:7] wire io_cpu_resp_valid_0; // @[Frontend.scala:82:7] wire io_cpu_gpa_valid_0; // @[Frontend.scala:82:7] wire [39:0] io_cpu_gpa_bits_0; // @[Frontend.scala:82:7] wire io_cpu_perf_acquire_0; // @[Frontend.scala:82:7] wire io_cpu_perf_tlbMiss_0; // @[Frontend.scala:82:7] wire io_cpu_gpa_is_pte_0; // @[Frontend.scala:82:7] wire [39:0] io_cpu_npc_0; // @[Frontend.scala:82:7] wire [26:0] io_ptw_req_bits_bits_addr_0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_bits_need_gpa_0; // @[Frontend.scala:82:7] wire io_ptw_req_bits_valid_0; // @[Frontend.scala:82:7] wire io_ptw_req_valid_0; // @[Frontend.scala:82:7] wire io_errors_bus_valid; // @[Frontend.scala:82:7] wire [31:0] io_errors_bus_bits; // @[Frontend.scala:82:7] reg s1_valid; // @[Frontend.scala:107:21] reg s2_valid; // @[Frontend.scala:108:25] wire _s0_fq_has_space_T = _fq_io_mask[2]; // @[Frontend.scala:91:64, :110:16] wire _s0_fq_has_space_T_1 = ~_s0_fq_has_space_T; // @[Frontend.scala:110:{5,16}] wire _s0_fq_has_space_T_2 = _fq_io_mask[3]; // @[Frontend.scala:91:64, :111:17] wire _s0_fq_has_space_T_3 = ~_s0_fq_has_space_T_2; // @[Frontend.scala:111:{6,17}] wire _s0_fq_has_space_T_4 = ~s1_valid; // @[Frontend.scala:107:21, :111:45] wire _s0_fq_has_space_T_5 = ~s2_valid; // @[Frontend.scala:108:25, :111:58] wire _s0_fq_has_space_T_6 = _s0_fq_has_space_T_4 | _s0_fq_has_space_T_5; // @[Frontend.scala:111:{45,55,58}] wire _s0_fq_has_space_T_7 = _s0_fq_has_space_T_3 & _s0_fq_has_space_T_6; // @[Frontend.scala:111:{6,41,55}] wire _s0_fq_has_space_T_8 = _s0_fq_has_space_T_1 | _s0_fq_has_space_T_7; // @[Frontend.scala:110:{5,40}, :111:41] wire _s0_fq_has_space_T_9 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17] wire _clock_en_reg_T_7 = _fq_io_mask[4]; // @[Frontend.scala:91:64, :112:17, :381:16] wire _s0_fq_has_space_T_10 = ~_s0_fq_has_space_T_9; // @[Frontend.scala:112:{6,17}] wire _s0_fq_has_space_T_11 = ~s1_valid; // @[Frontend.scala:107:21, :111:45, :112:45] wire _s0_fq_has_space_T_12 = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :112:58] wire _s0_fq_has_space_T_13 = _s0_fq_has_space_T_11 & _s0_fq_has_space_T_12; // @[Frontend.scala:112:{45,55,58}] wire _s0_fq_has_space_T_14 = _s0_fq_has_space_T_10 & _s0_fq_has_space_T_13; // @[Frontend.scala:112:{6,41,55}] wire s0_fq_has_space = _s0_fq_has_space_T_8 | _s0_fq_has_space_T_14; // @[Frontend.scala:110:40, :111:70, :112:41] wire s0_valid = io_cpu_req_valid_0 | s0_fq_has_space; // @[Frontend.scala:82:7, :111:70, :113:35] reg [39:0] s1_pc; // @[Frontend.scala:115:18] reg s1_speculative; // @[Frontend.scala:116:27] reg [39:0] s2_pc; // @[Frontend.scala:117:22] reg s2_btb_resp_valid; // @[Frontend.scala:118:44] reg [1:0] s2_btb_resp_bits_cfiType; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_taken; // @[Frontend.scala:119:29] reg [1:0] s2_btb_resp_bits_mask; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29] wire _taken_T_30 = s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69] reg [38:0] s2_btb_resp_bits_target; // @[Frontend.scala:119:29] reg [4:0] s2_btb_resp_bits_entry; // @[Frontend.scala:119:29] reg [7:0] s2_btb_resp_bits_bht_history; // @[Frontend.scala:119:29] reg s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_predict_taken_T = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_T_23 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_predict_taken_T_1 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire _taken_T_52 = s2_btb_resp_bits_bht_value; // @[Frontend.scala:119:29] wire s2_btb_taken = s2_btb_resp_valid & s2_btb_resp_bits_taken; // @[Frontend.scala:118:44, :119:29, :120:40] reg s2_tlb_resp_miss; // @[Frontend.scala:121:24] reg [31:0] s2_tlb_resp_paddr; // @[Frontend.scala:121:24] reg [39:0] s2_tlb_resp_gpa; // @[Frontend.scala:121:24] reg s2_tlb_resp_pf_ld; // @[Frontend.scala:121:24] reg s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_ae_ld; // @[Frontend.scala:121:24] reg s2_tlb_resp_ae_inst; // @[Frontend.scala:121:24] reg s2_tlb_resp_ma_ld; // @[Frontend.scala:121:24] reg s2_tlb_resp_cacheable; // @[Frontend.scala:121:24] reg s2_tlb_resp_prefetchable; // @[Frontend.scala:121:24] wire _s2_xcpt_T = s2_tlb_resp_ae_inst | s2_tlb_resp_pf_inst; // @[Frontend.scala:121:24, :122:37] wire s2_xcpt = _s2_xcpt_T; // @[Frontend.scala:122:{37,60}] reg s2_speculative; // @[Frontend.scala:123:31] reg s2_partial_insn_valid; // @[Frontend.scala:124:38] reg [15:0] s2_partial_insn; // @[Frontend.scala:125:28] reg wrong_path; // @[Frontend.scala:126:27] wire [39:0] _s1_base_pc_T = ~s1_pc; // @[Frontend.scala:115:18, :128:22] wire [39:0] _s1_base_pc_T_1 = {_s1_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:128:{22,29}] wire [39:0] s1_base_pc = ~_s1_base_pc_T_1; // @[Frontend.scala:128:{20,29}] wire [40:0] _ntpc_T = {1'h0, s1_base_pc} + 41'h4; // @[Frontend.scala:128:20, :129:25] wire [39:0] ntpc = _ntpc_T[39:0]; // @[Frontend.scala:129:25] wire [39:0] predicted_npc; // @[Frontend.scala:130:34] wire predicted_taken; // @[Frontend.scala:131:36] wire _s2_replay_T_5; // @[Frontend.scala:134:46] wire s2_replay; // @[Frontend.scala:133:23] wire _fq_io_enq_valid_T_6; // @[Frontend.scala:184:52] wire _T_37 = _fq_io_enq_ready & _fq_io_enq_valid_T_6; // @[Decoupled.scala:51:35] wire _s2_replay_T; // @[Decoupled.scala:51:35] assign _s2_replay_T = _T_37; // @[Decoupled.scala:51:35] wire _btb_io_btb_update_valid_T; // @[Decoupled.scala:51:35] assign _btb_io_btb_update_valid_T = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T; // @[Decoupled.scala:51:35] assign _taken_btb_io_ras_update_valid_T = _T_37; // @[Decoupled.scala:51:35] wire _taken_T_8; // @[Decoupled.scala:51:35] assign _taken_T_8 = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_bht_advance_valid_T; // @[Decoupled.scala:51:35] assign _taken_btb_io_bht_advance_valid_T = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T_9; // @[Decoupled.scala:51:35] assign _taken_btb_io_ras_update_valid_T_9 = _T_37; // @[Decoupled.scala:51:35] wire _taken_T_37; // @[Decoupled.scala:51:35] assign _taken_T_37 = _T_37; // @[Decoupled.scala:51:35] wire _taken_btb_io_bht_advance_valid_T_3; // @[Decoupled.scala:51:35] assign _taken_btb_io_bht_advance_valid_T_3 = _T_37; // @[Decoupled.scala:51:35] wire _taken_T_57; // @[Decoupled.scala:51:35] assign _taken_T_57 = _T_37; // @[Decoupled.scala:51:35] wire _s2_replay_T_1 = ~_s2_replay_T; // @[Decoupled.scala:51:35] wire _s2_replay_T_2 = s2_valid & _s2_replay_T_1; // @[Frontend.scala:108:25, :134:{26,29}] wire _s2_replay_T_3 = ~s0_valid; // @[Frontend.scala:113:35, :134:70] wire _s2_replay_T_4 = s2_replay & _s2_replay_T_3; // @[Frontend.scala:133:23, :134:{67,70}] reg s2_replay_REG; // @[Frontend.scala:134:56] assign _s2_replay_T_5 = _s2_replay_T_2 | s2_replay_REG; // @[Frontend.scala:134:{26,46,56}] assign s2_replay = _s2_replay_T_5; // @[Frontend.scala:133:23, :134:46] wire [39:0] npc = s2_replay ? s2_pc : predicted_npc; // @[Frontend.scala:117:22, :130:34, :133:23, :135:16] wire _s0_speculative_T = ~s2_speculative; // @[Frontend.scala:123:31, :141:56] wire _s0_speculative_T_1 = s2_valid & _s0_speculative_T; // @[Frontend.scala:108:25, :141:{53,56}] wire _s0_speculative_T_2 = s1_speculative | _s0_speculative_T_1; // @[Frontend.scala:116:27, :141:{41,53}] wire s0_speculative = _s0_speculative_T_2 | predicted_taken; // @[Frontend.scala:131:36, :141:{41,72}] wire _s1_speculative_T = s2_replay ? s2_speculative : s0_speculative; // @[Frontend.scala:123:31, :133:23, :141:72, :143:75] wire _s1_speculative_T_1 = io_cpu_req_valid_0 ? io_cpu_req_bits_speculative_0 : _s1_speculative_T; // @[Frontend.scala:82:7, :143:{24,75}] wire s2_redirect; // @[Frontend.scala:145:32] wire _s2_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17] reg [1:0] recent_progress_counter; // @[Frontend.scala:155:40] wire recent_progress = |recent_progress_counter; // @[Frontend.scala:155:40, :156:49] assign _io_cpu_perf_tlbMiss_T = io_ptw_req_ready_0 & io_ptw_req_valid_0; // @[Decoupled.scala:51:35] wire [2:0] _recent_progress_counter_T = {1'h0, recent_progress_counter} - 3'h1; // @[Frontend.scala:155:40, :157:97] wire [1:0] _recent_progress_counter_T_1 = _recent_progress_counter_T[1:0]; // @[Frontend.scala:157:97] wire _s2_kill_speculative_tlb_refill_T = ~recent_progress; // @[Frontend.scala:156:49, :160:58] wire s2_kill_speculative_tlb_refill = s2_speculative & _s2_kill_speculative_tlb_refill_T; // @[Frontend.scala:123:31, :160:{55,58}] wire _tlb_io_req_valid_T = ~s2_replay; // @[Frontend.scala:133:23, :147:9, :163:35] wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[Frontend.scala:107:21, :163:{32,35}] wire _tlb_io_kill_T = ~s2_valid; // @[Frontend.scala:108:25, :111:58, :171:18] wire _tlb_io_kill_T_1 = _tlb_io_kill_T | s2_kill_speculative_tlb_refill; // @[Frontend.scala:160:55, :171:{18,28}] wire _icache_io_s1_kill_T = s2_redirect | _tlb_io_resp_miss; // @[Frontend.scala:105:19, :145:32, :178:36] wire _icache_io_s1_kill_T_1 = _icache_io_s1_kill_T | s2_replay; // @[Frontend.scala:133:23, :178:{36,56}] wire _s2_can_speculatively_refill_T = io_ptw_customCSRs_csrs_0_value_0[3]; // @[CustomCSRs.scala:46:69] wire _s2_can_speculatively_refill_T_1 = ~_s2_can_speculatively_refill_T; // @[CustomCSRs.scala:46:69] wire s2_can_speculatively_refill = s2_tlb_resp_cacheable & _s2_can_speculatively_refill_T_1; // @[Frontend.scala:121:24, :179:{59,62}] wire _icache_io_s2_kill_T = ~s2_can_speculatively_refill; // @[Frontend.scala:179:59, :180:42] wire _icache_io_s2_kill_T_1 = s2_speculative & _icache_io_s2_kill_T; // @[Frontend.scala:123:31, :180:{39,42}] wire _icache_io_s2_kill_T_2 = _icache_io_s2_kill_T_1 | s2_xcpt; // @[Frontend.scala:122:60, :180:{39,71}] wire _icache_io_s2_prefetch_T = io_ptw_customCSRs_csrs_0_value_0[17]; // @[RocketCore.scala:115:60] wire _icache_io_s2_prefetch_T_1 = ~_icache_io_s2_prefetch_T; // @[RocketCore.scala:115:60] wire _icache_io_s2_prefetch_T_2 = s2_tlb_resp_prefetchable & _icache_io_s2_prefetch_T_1; // @[Frontend.scala:121:24, :182:{53,56}] reg fq_io_enq_valid_REG; // @[Frontend.scala:184:29] wire _fq_io_enq_valid_T = fq_io_enq_valid_REG & s2_valid; // @[Frontend.scala:108:25, :184:{29,40}] wire _GEN = s2_kill_speculative_tlb_refill & s2_tlb_resp_miss; // @[Frontend.scala:121:24, :160:55, :184:112] wire _fq_io_enq_valid_T_1; // @[Frontend.scala:184:112] assign _fq_io_enq_valid_T_1 = _GEN; // @[Frontend.scala:184:112] wire _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:150] assign _fq_io_enq_bits_replay_T_5 = _GEN; // @[Frontend.scala:184:112, :190:150] wire _fq_io_enq_valid_T_2 = _icache_io_resp_valid | _fq_io_enq_valid_T_1; // @[Frontend.scala:70:26, :184:{77,112}] wire _fq_io_enq_valid_T_3 = ~s2_tlb_resp_miss; // @[Frontend.scala:121:24, :184:137] wire _fq_io_enq_valid_T_4 = _fq_io_enq_valid_T_3 & _icache_io_s2_kill_T_2; // @[Frontend.scala:180:71, :184:{137,155}] wire _fq_io_enq_valid_T_5 = _fq_io_enq_valid_T_2 | _fq_io_enq_valid_T_4; // @[Frontend.scala:184:{77,133,155}] assign _fq_io_enq_valid_T_6 = _fq_io_enq_valid_T & _fq_io_enq_valid_T_5; // @[Frontend.scala:184:{40,52,133}] wire [39:0] _io_cpu_npc_T = io_cpu_req_valid_0 ? io_cpu_req_bits_pc_0 : npc; // @[Frontend.scala:82:7, :135:16, :186:28] wire [39:0] _io_cpu_npc_T_1 = ~_io_cpu_npc_T; // @[Frontend.scala:186:28, :384:29] wire [39:0] _io_cpu_npc_T_2 = {_io_cpu_npc_T_1[39:1], 1'h1}; // @[Frontend.scala:384:{29,33}] assign _io_cpu_npc_T_3 = ~_io_cpu_npc_T_2; // @[Frontend.scala:384:{27,33}] assign io_cpu_npc_0 = _io_cpu_npc_T_3; // @[Frontend.scala:82:7, :384:27] wire _fq_io_enq_bits_mask_T = s2_pc[1]; // @[package.scala:163:13] wire [2:0] _fq_io_enq_bits_mask_T_1 = 3'h3 << _fq_io_enq_bits_mask_T; // @[package.scala:163:13] wire _fq_io_enq_bits_replay_T = ~_icache_io_resp_valid; // @[Frontend.scala:70:26, :190:80] wire _fq_io_enq_bits_replay_T_1 = _icache_io_s2_kill_T_2 & _fq_io_enq_bits_replay_T; // @[Frontend.scala:180:71, :190:{77,80}] wire _fq_io_enq_bits_replay_T_2 = ~s2_xcpt; // @[Frontend.scala:122:60, :190:105] wire _fq_io_enq_bits_replay_T_3 = _fq_io_enq_bits_replay_T_1 & _fq_io_enq_bits_replay_T_2; // @[Frontend.scala:190:{77,102,105}] wire _fq_io_enq_bits_replay_T_4 = _fq_io_enq_bits_replay_T_3; // @[Frontend.scala:190:{56,102}] wire _fq_io_enq_bits_replay_T_6 = _fq_io_enq_bits_replay_T_4 | _fq_io_enq_bits_replay_T_5; // @[Frontend.scala:190:{56,115,150}] wire _btb_io_req_valid_T = ~s2_redirect; // @[Frontend.scala:145:32, :148:17, :209:27] assign predicted_taken = _btb_io_resp_valid & _btb_io_resp_bits_taken; // @[Frontend.scala:131:36, :198:21, :213:29] wire _predicted_npc_T = _btb_io_resp_bits_target[38]; // @[package.scala:132:38] wire [39:0] _predicted_npc_T_1 = {_predicted_npc_T, _btb_io_resp_bits_target}; // @[package.scala:132:{15,38}] wire [39:0] _s2_base_pc_T = ~s2_pc; // @[Frontend.scala:117:22, :222:24] wire [39:0] _s2_base_pc_T_1 = {_s2_base_pc_T[39:2], 2'h3}; // @[Frontend.scala:222:{24,31}] wire [39:0] s2_base_pc = ~_s2_base_pc_T_1; // @[Frontend.scala:222:{22,31}] wire [39:0] taken_pc = s2_base_pc; // @[Frontend.scala:222:22, :287:33] wire _taken_T_35; // @[Frontend.scala:270:13] wire taken_idx; // @[Frontend.scala:223:25] wire [1:0] after_idx; // @[Frontend.scala:224:25] wire useRAS; // @[Frontend.scala:225:29] wire updateBTB; // @[Frontend.scala:226:32] wire _fetch_bubble_likely_T = _fq_io_mask[1]; // @[Frontend.scala:91:64, :318:44] wire fetch_bubble_likely = ~_fetch_bubble_likely_T; // @[Frontend.scala:318:{33,44}] wire _btb_io_btb_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :319:52] wire _btb_io_btb_update_valid_T_2 = _btb_io_btb_update_valid_T & _btb_io_btb_update_valid_T_1; // @[Decoupled.scala:51:35] wire _btb_io_btb_update_valid_T_3 = _btb_io_btb_update_valid_T_2 & fetch_bubble_likely; // @[Frontend.scala:318:33, :319:{49,64}] wire _btb_io_btb_update_valid_T_4 = _btb_io_btb_update_valid_T_3 & updateBTB; // @[Frontend.scala:226:32, :319:{64,87}] wire [1:0] _btb_io_btb_update_bits_br_pc_T = {taken_idx, 1'h0}; // @[Frontend.scala:223:25, :323:63] wire [39:0] _btb_io_btb_update_bits_br_pc_T_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | _btb_io_btb_update_bits_br_pc_T}; // @[Frontend.scala:222:22, :323:{50,63}] wire [2:0] _btb_io_ras_update_bits_returnAddr_T = {after_idx, 1'h0}; // @[Frontend.scala:224:25, :327:66] wire [40:0] _btb_io_ras_update_bits_returnAddr_T_1 = {1'h0, s2_base_pc} + {38'h0, _btb_io_ras_update_bits_returnAddr_T}; // @[Frontend.scala:129:25, :222:22, :327:{53,66}] wire [39:0] _btb_io_ras_update_bits_returnAddr_T_2 = _btb_io_ras_update_bits_returnAddr_T_1[39:0]; // @[Frontend.scala:327:53] wire [1:0] _taken_prevRVI_T = s2_partial_insn[1:0]; // @[Frontend.scala:125:28, :233:39] wire _taken_prevRVI_T_1 = _taken_prevRVI_T != 2'h3; // @[Frontend.scala:233:{39,45}] wire _taken_prevRVI_T_2 = ~_taken_prevRVI_T_1; // @[Frontend.scala:233:45, :234:34] wire taken_prevRVI = s2_partial_insn_valid & _taken_prevRVI_T_2; // @[Frontend.scala:124:38, :234:{31,34}] wire _taken_valid_T = _fq_io_enq_bits_mask_T_1[0]; // @[Frontend.scala:189:50, :235:38] wire _taken_valid_T_1 = ~taken_prevRVI; // @[Frontend.scala:234:31, :235:47] wire taken_valid = _taken_valid_T & _taken_valid_T_1; // @[Frontend.scala:235:{38,44,47}] wire [15:0] taken_bits = _icache_io_resp_bits_data[15:0]; // @[Frontend.scala:70:26, :236:37] wire [1:0] _taken_rvc_T = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37] wire [1:0] _taken_prevRVI_T_3 = taken_bits[1:0]; // @[Frontend.scala:233:39, :236:37] wire taken_rvc = _taken_rvc_T != 2'h3; // @[Frontend.scala:233:{39,45}] wire [31:0] taken_rviBits = {taken_bits, s2_partial_insn}; // @[Frontend.scala:125:28, :236:37, :238:24] wire [6:0] _taken_rviBranch_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30] wire [6:0] _taken_rviJump_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28] wire [6:0] _taken_rviJALR_T = taken_rviBits[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28] wire taken_rviBranch = _taken_rviBranch_T == 7'h63; // @[Frontend.scala:239:{30,36}] wire taken_rviJump = _taken_rviJump_T == 7'h6F; // @[Frontend.scala:240:{28,34}] wire taken_rviJALR = _taken_rviJALR_T == 7'h67; // @[Frontend.scala:241:{28,34}] wire _taken_rviReturn_T = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42] wire _taken_rviCall_T_1 = taken_rviBits[7]; // @[Frontend.scala:238:24, :242:42, :243:52] wire _taken_rviImm_b11_T_7 = taken_rviBits[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_1 = taken_rviBits[7]; // @[RocketCore.scala:1351:37] wire _taken_rviImm_b11_T_18 = taken_rviBits[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_9 = taken_rviBits[7]; // @[RocketCore.scala:1351:37] wire _taken_rviReturn_T_1 = ~_taken_rviReturn_T; // @[Frontend.scala:242:{34,42}] wire _taken_rviReturn_T_2 = taken_rviJALR & _taken_rviReturn_T_1; // @[Frontend.scala:241:34, :242:{31,34}] wire [4:0] _taken_rviReturn_T_3 = taken_rviBits[19:15]; // @[Frontend.scala:238:24, :242:77] wire [4:0] _taken_rviReturn_T_4 = _taken_rviReturn_T_3 & 5'h1B; // @[Frontend.scala:242:{66,77}] wire _taken_rviReturn_T_5 = _taken_rviReturn_T_4 == 5'h1; // @[Frontend.scala:242:66] wire taken_rviReturn = _taken_rviReturn_T_2 & _taken_rviReturn_T_5; // @[Frontend.scala:242:{31,46,66}] wire _GEN_0 = taken_rviJALR | taken_rviJump; // @[Frontend.scala:240:34, :241:34, :243:30] wire _taken_rviCall_T; // @[Frontend.scala:243:30] assign _taken_rviCall_T = _GEN_0; // @[Frontend.scala:243:30] wire _taken_taken_T; // @[Frontend.scala:255:29] assign _taken_taken_T = _GEN_0; // @[Frontend.scala:243:30, :255:29] wire taken_rviCall = _taken_rviCall_T & _taken_rviCall_T_1; // @[Frontend.scala:243:{30,42,52}] wire [15:0] _GEN_1 = taken_bits & 16'hE003; // @[Frontend.scala:236:37, :244:28] wire [15:0] _taken_rvcBranch_T; // @[Frontend.scala:244:28] assign _taken_rvcBranch_T = _GEN_1; // @[Frontend.scala:244:28] wire [15:0] _taken_rvcBranch_T_2; // @[Frontend.scala:244:60] assign _taken_rvcBranch_T_2 = _GEN_1; // @[Frontend.scala:244:{28,60}] wire [15:0] _taken_rvcJAL_T; // @[Frontend.scala:245:43] assign _taken_rvcJAL_T = _GEN_1; // @[Frontend.scala:244:28, :245:43] wire [15:0] _taken_rvcJump_T; // @[Frontend.scala:246:26] assign _taken_rvcJump_T = _GEN_1; // @[Frontend.scala:244:28, :246:26] wire _taken_rvcBranch_T_1 = _taken_rvcBranch_T == 16'hC001; // @[Frontend.scala:244:28] wire _taken_rvcBranch_T_3 = _taken_rvcBranch_T_2 == 16'hE001; // @[Frontend.scala:244:60] wire taken_rvcBranch = _taken_rvcBranch_T_1 | _taken_rvcBranch_T_3; // @[Frontend.scala:244:{28,52,60}] wire _taken_rvcJAL_T_1 = _taken_rvcJAL_T == 16'h2001; // @[Frontend.scala:245:43] wire _taken_rvcJump_T_1 = _taken_rvcJump_T == 16'hA001; // @[Frontend.scala:246:26] wire taken_rvcJump = _taken_rvcJump_T_1; // @[Frontend.scala:246:{26,47}] wire _taken_rvcImm_T = taken_bits[14]; // @[Frontend.scala:236:37, :247:28] wire _taken_rvcImm_T_1 = taken_bits[12]; // @[RVC.scala:45:27] wire _taken_rvcImm_T_9 = taken_bits[12]; // @[RVC.scala:44:28, :45:27] wire [4:0] _taken_rvcImm_T_2 = {5{_taken_rvcImm_T_1}}; // @[RVC.scala:45:{22,27}] wire [1:0] _taken_rvcImm_T_3 = taken_bits[6:5]; // @[RVC.scala:45:35] wire _taken_rvcImm_T_4 = taken_bits[2]; // @[RVC.scala:45:43] wire _taken_rvcImm_T_15 = taken_bits[2]; // @[RVC.scala:44:63, :45:43] wire [1:0] _taken_rvcImm_T_5 = taken_bits[11:10]; // @[RVC.scala:45:49] wire [1:0] _taken_rvcImm_T_6 = taken_bits[4:3]; // @[RVC.scala:45:59] wire [3:0] taken_rvcImm_lo_hi = {_taken_rvcImm_T_5, _taken_rvcImm_T_6}; // @[RVC.scala:45:{17,49,59}] wire [4:0] taken_rvcImm_lo = {taken_rvcImm_lo_hi, 1'h0}; // @[RVC.scala:45:17] wire [6:0] taken_rvcImm_hi_hi = {_taken_rvcImm_T_2, _taken_rvcImm_T_3}; // @[RVC.scala:45:{17,22,35}] wire [7:0] taken_rvcImm_hi = {taken_rvcImm_hi_hi, _taken_rvcImm_T_4}; // @[RVC.scala:45:{17,43}] wire [12:0] _taken_rvcImm_T_7 = {taken_rvcImm_hi, taken_rvcImm_lo}; // @[RVC.scala:45:17] wire [12:0] _taken_rvcImm_T_8 = _taken_rvcImm_T_7; // @[RVC.scala:45:17] wire [9:0] _taken_rvcImm_T_10 = {10{_taken_rvcImm_T_9}}; // @[RVC.scala:44:{22,28}] wire _taken_rvcImm_T_11 = taken_bits[8]; // @[RVC.scala:44:36] wire [1:0] _taken_rvcImm_T_12 = taken_bits[10:9]; // @[RVC.scala:44:42] wire _taken_rvcImm_T_13 = taken_bits[6]; // @[RVC.scala:44:51] wire _taken_rvcImm_T_14 = taken_bits[7]; // @[RVC.scala:44:57] wire _taken_rvcImm_T_16 = taken_bits[11]; // @[RVC.scala:44:69] wire [2:0] _taken_rvcImm_T_17 = taken_bits[5:3]; // @[RVC.scala:44:76] wire [3:0] taken_rvcImm_lo_lo = {_taken_rvcImm_T_17, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] taken_rvcImm_lo_hi_1 = {_taken_rvcImm_T_15, _taken_rvcImm_T_16}; // @[RVC.scala:44:{17,63,69}] wire [5:0] taken_rvcImm_lo_1 = {taken_rvcImm_lo_hi_1, taken_rvcImm_lo_lo}; // @[RVC.scala:44:17] wire [1:0] taken_rvcImm_hi_lo = {_taken_rvcImm_T_13, _taken_rvcImm_T_14}; // @[RVC.scala:44:{17,51,57}] wire [10:0] taken_rvcImm_hi_hi_hi = {_taken_rvcImm_T_10, _taken_rvcImm_T_11}; // @[RVC.scala:44:{17,22,36}] wire [12:0] taken_rvcImm_hi_hi_1 = {taken_rvcImm_hi_hi_hi, _taken_rvcImm_T_12}; // @[RVC.scala:44:{17,42}] wire [14:0] taken_rvcImm_hi_1 = {taken_rvcImm_hi_hi_1, taken_rvcImm_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_18 = {taken_rvcImm_hi_1, taken_rvcImm_lo_1}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_19 = _taken_rvcImm_T_18; // @[RVC.scala:44:17] wire [20:0] taken_rvcImm = _taken_rvcImm_T ? {{8{_taken_rvcImm_T_8[12]}}, _taken_rvcImm_T_8} : _taken_rvcImm_T_19; // @[Frontend.scala:247:{23,28,72,118}] wire [15:0] _GEN_2 = taken_bits & 16'hF003; // @[Frontend.scala:236:37, :248:24] wire [15:0] _taken_rvcJR_T; // @[Frontend.scala:248:24] assign _taken_rvcJR_T = _GEN_2; // @[Frontend.scala:248:24] wire [15:0] _taken_rvcJALR_T; // @[Frontend.scala:250:26] assign _taken_rvcJALR_T = _GEN_2; // @[Frontend.scala:248:24, :250:26] wire _taken_rvcJR_T_1 = _taken_rvcJR_T == 16'h8002; // @[Frontend.scala:248:24] wire [4:0] _taken_rvcJR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53] wire [4:0] _taken_rvcJALR_T_2 = taken_bits[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56] wire _taken_rvcJR_T_3 = _taken_rvcJR_T_2 == 5'h0; // @[Frontend.scala:248:{53,59}] wire taken_rvcJR = _taken_rvcJR_T_1 & _taken_rvcJR_T_3; // @[Frontend.scala:248:{24,46,59}] wire [4:0] _taken_rvcReturn_T = taken_bits[11:7]; // @[Frontend.scala:236:37, :249:57] wire [4:0] _taken_rvcReturn_T_1 = _taken_rvcReturn_T & 5'h1B; // @[Frontend.scala:249:{49,57}] wire _taken_rvcReturn_T_2 = _taken_rvcReturn_T_1 == 5'h1; // @[Frontend.scala:249:49] wire taken_rvcReturn = taken_rvcJR & _taken_rvcReturn_T_2; // @[Frontend.scala:248:46, :249:{29,49}] wire _taken_rvcJALR_T_1 = _taken_rvcJALR_T == 16'h9002; // @[Frontend.scala:250:26] wire _taken_rvcJALR_T_3 = _taken_rvcJALR_T_2 == 5'h0; // @[Frontend.scala:250:{56,62}] wire taken_rvcJALR = _taken_rvcJALR_T_1 & _taken_rvcJALR_T_3; // @[Frontend.scala:250:{26,49,62}] wire taken_rvcCall = taken_rvcJALR; // @[Frontend.scala:250:49, :251:28] wire _taken_rviImm_T = taken_rviBits[3]; // @[Frontend.scala:238:24, :252:31] wire _taken_rviImm_sign_T_1 = taken_rviBits[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_4 = taken_rviBits[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_2 = _taken_rviImm_sign_T_1; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign = _taken_rviImm_sign_T_2; // @[RocketCore.scala:1341:{19,49}] wire _taken_rviImm_b11_T_9 = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1346:18] wire taken_rviImm_hi_hi_hi = taken_rviImm_sign; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_1 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_4 = taken_rviBits[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_2 = _taken_rviImm_b30_20_T_1; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20 = {11{taken_rviImm_sign}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo = taken_rviImm_b30_20; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_3 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_8 = taken_rviBits[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_4 = _taken_rviImm_b19_12_T_3; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12 = _taken_rviImm_b19_12_T_4; // @[RocketCore.scala:1343:{21,73}] wire [7:0] taken_rviImm_hi_lo_hi = taken_rviImm_b19_12; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_4 = taken_rviBits[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_3 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_15 = taken_rviBits[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_11 = taken_rviBits[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_5 = _taken_rviImm_b11_T_4; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_10 = _taken_rviImm_b11_T_5; // @[RocketCore.scala:1345:{18,44}] wire _taken_rviImm_b11_T_8 = _taken_rviImm_b11_T_7; // @[RocketCore.scala:1346:{39,43}] wire taken_rviImm_b11 = _taken_rviImm_b11_T_10; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo = taken_rviImm_b11; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _taken_rviImm_b10_5_T_3 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] _taken_rviImm_b10_5_T_7 = taken_rviBits[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] taken_rviImm_b10_5 = _taken_rviImm_b10_5_T_3; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_4 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_14 = taken_rviBits[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_6 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_16 = taken_rviBits[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_7 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_17 = taken_rviBits[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_8 = _taken_rviImm_b4_1_T_7; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _taken_rviImm_b4_1_T_9 = _taken_rviImm_b4_1_T_8; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] taken_rviImm_b4_1 = _taken_rviImm_b4_1_T_9; // @[RocketCore.scala:1348:19, :1349:19] wire _taken_rviImm_b0_T_5 = taken_rviBits[15]; // @[RocketCore.scala:1353:37] wire _taken_rviImm_b0_T_13 = taken_rviBits[15]; // @[RocketCore.scala:1353:37] wire [9:0] taken_rviImm_lo_hi = {taken_rviImm_b10_5, taken_rviImm_b4_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo = {taken_rviImm_lo_hi, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo = {taken_rviImm_hi_lo_hi, taken_rviImm_hi_lo_lo}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi = {taken_rviImm_hi_hi_hi, taken_rviImm_hi_hi_lo}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi = {taken_rviImm_hi_hi, taken_rviImm_hi_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_1 = {taken_rviImm_hi, taken_rviImm_lo}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_2 = _taken_rviImm_T_1; // @[RocketCore.scala:1355:{8,53}] wire _taken_rviImm_sign_T_5 = _taken_rviImm_sign_T_4; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign_1 = _taken_rviImm_sign_T_5; // @[RocketCore.scala:1341:{19,49}] wire taken_rviImm_hi_hi_hi_1 = taken_rviImm_sign_1; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_5 = _taken_rviImm_b30_20_T_4; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20_1 = {11{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo_1 = taken_rviImm_b30_20_1; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_9 = _taken_rviImm_b19_12_T_8; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12_1 = {8{taken_rviImm_sign_1}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] taken_rviImm_hi_lo_hi_1 = taken_rviImm_b19_12_1; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_16 = _taken_rviImm_b11_T_15; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_19 = _taken_rviImm_b11_T_18; // @[RocketCore.scala:1346:{39,43}] wire _taken_rviImm_b11_T_20 = _taken_rviImm_b11_T_19; // @[RocketCore.scala:1346:{18,43}] wire _taken_rviImm_b11_T_21 = _taken_rviImm_b11_T_20; // @[RocketCore.scala:1345:18, :1346:18] wire taken_rviImm_b11_1 = _taken_rviImm_b11_T_21; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo_1 = taken_rviImm_b11_1; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] taken_rviImm_b10_5_1 = _taken_rviImm_b10_5_T_7; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_19 = _taken_rviImm_b4_1_T_14; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _taken_rviImm_b4_1_T_18 = _taken_rviImm_b4_1_T_17; // @[RocketCore.scala:1350:{19,52}] wire [3:0] taken_rviImm_b4_1_1 = _taken_rviImm_b4_1_T_19; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] taken_rviImm_lo_hi_1 = {taken_rviImm_b10_5_1, taken_rviImm_b4_1_1}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo_1 = {taken_rviImm_lo_hi_1, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo_1 = {taken_rviImm_hi_lo_hi_1, taken_rviImm_hi_lo_lo_1}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi_1 = {taken_rviImm_hi_hi_hi_1, taken_rviImm_hi_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi_1 = {taken_rviImm_hi_hi_1, taken_rviImm_hi_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_3 = {taken_rviImm_hi_1, taken_rviImm_lo_1}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_4 = _taken_rviImm_T_3; // @[RocketCore.scala:1355:{8,53}] wire [31:0] taken_rviImm = _taken_rviImm_T ? _taken_rviImm_T_2 : _taken_rviImm_T_4; // @[RocketCore.scala:1355:53] wire taken_predict_taken = _taken_predict_taken_T; // @[Frontend.scala:253:54] wire _taken_taken_T_1 = taken_rviBranch & taken_predict_taken; // @[Frontend.scala:239:36, :253:54, :255:53] wire _taken_taken_T_2 = _taken_taken_T | _taken_taken_T_1; // @[Frontend.scala:255:{29,40,53}] wire _taken_taken_T_3 = taken_prevRVI & _taken_taken_T_2; // @[Frontend.scala:234:31, :255:{17,40}] wire _taken_taken_T_4 = taken_rvcJump | taken_rvcJALR; // @[Frontend.scala:246:47, :250:49, :256:27] wire _taken_taken_T_5 = _taken_taken_T_4 | taken_rvcJR; // @[Frontend.scala:248:46, :256:{27,38}] wire _taken_taken_T_6 = taken_rvcBranch & taken_predict_taken; // @[Frontend.scala:244:52, :253:54, :256:60] wire _taken_taken_T_7 = _taken_taken_T_5 | _taken_taken_T_6; // @[Frontend.scala:256:{38,47,60}] wire _taken_taken_T_8 = taken_valid & _taken_taken_T_7; // @[Frontend.scala:235:44, :256:{15,47}] wire taken_taken = _taken_taken_T_3 | _taken_taken_T_8; // @[Frontend.scala:255:{17,71}, :256:15] wire _taken_T_28 = taken_taken; // @[Frontend.scala:255:71, :313:51] wire _taken_predictReturn_T = taken_prevRVI & taken_rviReturn; // @[Frontend.scala:234:31, :242:46, :257:61] wire _taken_predictReturn_T_1 = taken_valid & taken_rvcReturn; // @[Frontend.scala:235:44, :249:29, :257:83] wire _taken_predictReturn_T_2 = _taken_predictReturn_T | _taken_predictReturn_T_1; // @[Frontend.scala:257:{61,74,83}] wire taken_predictReturn = _btb_io_ras_head_valid & _taken_predictReturn_T_2; // @[Frontend.scala:198:21, :257:{49,74}] wire _taken_predictJump_T = taken_prevRVI & taken_rviJump; // @[Frontend.scala:234:31, :240:34, :258:33] wire _taken_predictJump_T_1 = taken_valid & taken_rvcJump; // @[Frontend.scala:235:44, :246:47, :258:53] wire taken_predictJump = _taken_predictJump_T | _taken_predictJump_T_1; // @[Frontend.scala:258:{33,44,53}] wire _GEN_3 = taken_prevRVI & taken_rviBranch; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_predictBranch_T; // @[Frontend.scala:259:53] assign _taken_predictBranch_T = _GEN_3; // @[Frontend.scala:259:53] wire _taken_T_19; // @[Frontend.scala:294:23] assign _taken_T_19 = _GEN_3; // @[Frontend.scala:259:53, :294:23] wire _GEN_4 = taken_valid & taken_rvcBranch; // @[Frontend.scala:235:44, :244:52, :259:75] wire _taken_predictBranch_T_1; // @[Frontend.scala:259:75] assign _taken_predictBranch_T_1 = _GEN_4; // @[Frontend.scala:259:75] wire _taken_T_20; // @[Frontend.scala:294:45] assign _taken_T_20 = _GEN_4; // @[Frontend.scala:259:75, :294:45] wire _taken_predictBranch_T_2 = _taken_predictBranch_T | _taken_predictBranch_T_1; // @[Frontend.scala:259:{53,66,75}] wire taken_predictBranch = taken_predict_taken & _taken_predictBranch_T_2; // @[Frontend.scala:253:54, :259:{41,66}] wire _GEN_5 = s2_valid & s2_btb_resp_valid; // @[Frontend.scala:108:25, :118:44, :261:22] wire _taken_T; // @[Frontend.scala:261:22] assign _taken_T = _GEN_5; // @[Frontend.scala:261:22] wire _taken_T_29; // @[Frontend.scala:261:22] assign _taken_T_29 = _GEN_5; // @[Frontend.scala:261:22] wire _taken_T_1 = ~s2_btb_resp_bits_bridx; // @[Frontend.scala:119:29, :261:69] wire _taken_T_2 = _taken_T & _taken_T_1; // @[Frontend.scala:261:{22,43,69}] wire _taken_T_3 = _taken_T_2 & taken_valid; // @[Frontend.scala:235:44, :261:{43,79}] wire _taken_T_4 = ~taken_rvc; // @[Frontend.scala:233:45, :261:91] wire _taken_T_5 = _taken_T_3 & _taken_T_4; // @[Frontend.scala:261:{79,88,91}] wire _taken_btb_io_ras_update_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52] wire _taken_btb_io_ras_update_valid_T_2 = _taken_btb_io_ras_update_valid_T & _taken_btb_io_ras_update_valid_T_1; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T_3 = taken_rviCall | taken_rviReturn; // @[Frontend.scala:242:46, :243:42, :273:90] wire _taken_btb_io_ras_update_valid_T_4 = taken_prevRVI & _taken_btb_io_ras_update_valid_T_3; // @[Frontend.scala:234:31, :273:{78,90}] wire _taken_btb_io_ras_update_valid_T_5 = taken_rvcCall | taken_rvcReturn; // @[Frontend.scala:249:29, :251:28, :273:125] wire _taken_btb_io_ras_update_valid_T_6 = taken_valid & _taken_btb_io_ras_update_valid_T_5; // @[Frontend.scala:235:44, :273:{113,125}] wire _taken_btb_io_ras_update_valid_T_7 = _taken_btb_io_ras_update_valid_T_4 | _taken_btb_io_ras_update_valid_T_6; // @[Frontend.scala:273:{78,104,113}] wire _taken_btb_io_ras_update_valid_T_8 = _taken_btb_io_ras_update_valid_T_2 & _taken_btb_io_ras_update_valid_T_7; // @[Frontend.scala:273:{51,66,104}] wire _taken_btb_io_ras_update_bits_cfiType_T = taken_prevRVI ? taken_rviReturn : taken_rvcReturn; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50] wire _taken_btb_io_ras_update_bits_cfiType_T_1 = taken_prevRVI ? taken_rviCall : taken_rvcCall; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50] wire _taken_btb_io_ras_update_bits_cfiType_T_2 = taken_prevRVI ? taken_rviBranch : taken_rvcBranch; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50] wire _taken_btb_io_ras_update_bits_cfiType_T_4 = _taken_btb_io_ras_update_bits_cfiType_T_2; // @[Frontend.scala:276:{50,82}] wire _taken_btb_io_ras_update_bits_cfiType_T_5 = ~_taken_btb_io_ras_update_bits_cfiType_T_4; // @[Frontend.scala:276:{46,82}] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_6 = _taken_btb_io_ras_update_bits_cfiType_T_1 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_5}; // @[Frontend.scala:275:{46,50}, :276:46] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_7 = _taken_btb_io_ras_update_bits_cfiType_T ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_6; // @[Frontend.scala:274:{46,50}, :275:46] wire _taken_T_7 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15] wire _taken_T_9 = _taken_T_8 & taken_taken; // @[Decoupled.scala:51:35] wire _taken_T_10 = ~taken_predictBranch; // @[Frontend.scala:259:41, :280:44] wire _taken_T_11 = _taken_T_9 & _taken_T_10; // @[Frontend.scala:280:{32,41,44}] wire _taken_T_12 = ~taken_predictJump; // @[Frontend.scala:258:44, :280:62] wire _taken_T_13 = _taken_T_11 & _taken_T_12; // @[Frontend.scala:280:{41,59,62}] wire _taken_T_14 = ~taken_predictReturn; // @[Frontend.scala:257:49, :280:78] wire _taken_T_15 = _taken_T_13 & _taken_T_14; // @[Frontend.scala:280:{59,75,78}] wire _taken_T_16 = s2_valid & taken_predictReturn; // @[Frontend.scala:108:25, :257:49, :283:26] wire _taken_T_17 = taken_predictBranch | taken_predictJump; // @[Frontend.scala:258:44, :259:41, :286:44] wire _taken_T_18 = s2_valid & _taken_T_17; // @[Frontend.scala:108:25, :286:{26,44}] wire [39:0] _taken_npc_T = taken_pc; // @[Frontend.scala:287:33, :289:32] wire [32:0] _taken_npc_T_1 = {taken_rviImm[31], taken_rviImm} - 33'h2; // @[Frontend.scala:252:23, :289:61] wire [32:0] _taken_npc_T_2 = taken_prevRVI ? _taken_npc_T_1 : {{12{taken_rvcImm[20]}}, taken_rvcImm}; // @[Frontend.scala:234:31, :247:23, :289:{44,61}] wire [40:0] _taken_npc_T_3 = {_taken_npc_T[39], _taken_npc_T} + {{8{_taken_npc_T_2[32]}}, _taken_npc_T_2}; // @[Frontend.scala:289:{32,39,44}] wire [39:0] _taken_npc_T_4 = _taken_npc_T_3[39:0]; // @[Frontend.scala:289:39] wire [39:0] taken_npc = _taken_npc_T_4; // @[Frontend.scala:289:39] wire [39:0] _taken_predicted_npc_T = taken_npc; // @[Frontend.scala:289:39, :291:34] wire _taken_T_21 = _taken_T_19 | _taken_T_20; // @[Frontend.scala:294:{23,36,45}] wire _taken_btb_io_bht_advance_valid_T_1 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52] wire _taken_btb_io_bht_advance_valid_T_2 = _taken_btb_io_bht_advance_valid_T & _taken_btb_io_bht_advance_valid_T_1; // @[Decoupled.scala:51:35] wire _taken_T_22 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15] wire _taken_T_24 = taken_predictBranch & _taken_T_23; // @[Frontend.scala:259:41, :298:52] wire _taken_T_25 = _taken_T_24 | taken_predictJump; // @[Frontend.scala:258:44, :298:{52,91}] wire _taken_T_26 = _taken_T_25 | taken_predictReturn; // @[Frontend.scala:257:49, :298:{91,106}] wire _taken_T_27 = _taken_T_22 & _taken_T_26; // @[Frontend.scala:298:{15,34,106}] wire _taken_prevRVI_T_4 = _taken_prevRVI_T_3 != 2'h3; // @[Frontend.scala:233:{39,45}] wire _taken_prevRVI_T_5 = ~_taken_prevRVI_T_4; // @[Frontend.scala:233:45, :234:34] wire taken_prevRVI_1 = taken_valid & _taken_prevRVI_T_5; // @[Frontend.scala:234:{31,34}, :235:44] wire _taken_valid_T_2 = _fq_io_enq_bits_mask_T_1[1]; // @[Frontend.scala:189:50, :235:38] wire _taken_valid_T_3 = ~taken_prevRVI_1; // @[Frontend.scala:234:31, :235:47] wire taken_valid_1 = _taken_valid_T_2 & _taken_valid_T_3; // @[Frontend.scala:235:{38,44,47}] wire [15:0] taken_bits_1 = _icache_io_resp_bits_data[31:16]; // @[Frontend.scala:70:26, :236:37] wire [1:0] _taken_rvc_T_1 = taken_bits_1[1:0]; // @[Frontend.scala:233:39, :236:37] wire taken_rvc_1 = _taken_rvc_T_1 != 2'h3; // @[Frontend.scala:233:{39,45}] wire [31:0] taken_rviBits_1 = {taken_bits_1, taken_bits}; // @[Frontend.scala:236:37, :238:24] wire [6:0] _taken_rviBranch_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30] wire [6:0] _taken_rviJump_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :240:28] wire [6:0] _taken_rviJALR_T_1 = taken_rviBits_1[6:0]; // @[Frontend.scala:238:24, :239:30, :241:28] wire taken_rviBranch_1 = _taken_rviBranch_T_1 == 7'h63; // @[Frontend.scala:239:{30,36}] wire taken_rviJump_1 = _taken_rviJump_T_1 == 7'h6F; // @[Frontend.scala:240:{28,34}] wire taken_rviJALR_1 = _taken_rviJALR_T_1 == 7'h67; // @[Frontend.scala:241:{28,34}] wire _taken_rviReturn_T_6 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42] wire _taken_rviCall_T_3 = taken_rviBits_1[7]; // @[Frontend.scala:238:24, :242:42, :243:52] wire _taken_rviImm_b11_T_29 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_17 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37] wire _taken_rviImm_b11_T_40 = taken_rviBits_1[7]; // @[RocketCore.scala:1346:39] wire _taken_rviImm_b0_T_25 = taken_rviBits_1[7]; // @[RocketCore.scala:1351:37] wire _taken_rviReturn_T_7 = ~_taken_rviReturn_T_6; // @[Frontend.scala:242:{34,42}] wire _taken_rviReturn_T_8 = taken_rviJALR_1 & _taken_rviReturn_T_7; // @[Frontend.scala:241:34, :242:{31,34}] wire [4:0] _taken_rviReturn_T_9 = taken_rviBits_1[19:15]; // @[Frontend.scala:238:24, :242:77] wire [4:0] _taken_rviReturn_T_10 = _taken_rviReturn_T_9 & 5'h1B; // @[Frontend.scala:242:{66,77}] wire _taken_rviReturn_T_11 = _taken_rviReturn_T_10 == 5'h1; // @[Frontend.scala:242:66] wire taken_rviReturn_1 = _taken_rviReturn_T_8 & _taken_rviReturn_T_11; // @[Frontend.scala:242:{31,46,66}] wire _GEN_6 = taken_rviJALR_1 | taken_rviJump_1; // @[Frontend.scala:240:34, :241:34, :243:30] wire _taken_rviCall_T_2; // @[Frontend.scala:243:30] assign _taken_rviCall_T_2 = _GEN_6; // @[Frontend.scala:243:30] wire _taken_taken_T_9; // @[Frontend.scala:255:29] assign _taken_taken_T_9 = _GEN_6; // @[Frontend.scala:243:30, :255:29] wire taken_rviCall_1 = _taken_rviCall_T_2 & _taken_rviCall_T_3; // @[Frontend.scala:243:{30,42,52}] wire [15:0] _GEN_7 = taken_bits_1 & 16'hE003; // @[Frontend.scala:236:37, :244:28] wire [15:0] _taken_rvcBranch_T_4; // @[Frontend.scala:244:28] assign _taken_rvcBranch_T_4 = _GEN_7; // @[Frontend.scala:244:28] wire [15:0] _taken_rvcBranch_T_6; // @[Frontend.scala:244:60] assign _taken_rvcBranch_T_6 = _GEN_7; // @[Frontend.scala:244:{28,60}] wire [15:0] _taken_rvcJAL_T_2; // @[Frontend.scala:245:43] assign _taken_rvcJAL_T_2 = _GEN_7; // @[Frontend.scala:244:28, :245:43] wire [15:0] _taken_rvcJump_T_2; // @[Frontend.scala:246:26] assign _taken_rvcJump_T_2 = _GEN_7; // @[Frontend.scala:244:28, :246:26] wire _taken_rvcBranch_T_5 = _taken_rvcBranch_T_4 == 16'hC001; // @[Frontend.scala:244:28] wire _taken_rvcBranch_T_7 = _taken_rvcBranch_T_6 == 16'hE001; // @[Frontend.scala:244:60] wire taken_rvcBranch_1 = _taken_rvcBranch_T_5 | _taken_rvcBranch_T_7; // @[Frontend.scala:244:{28,52,60}] wire _taken_rvcJAL_T_3 = _taken_rvcJAL_T_2 == 16'h2001; // @[Frontend.scala:245:43] wire _taken_rvcJump_T_3 = _taken_rvcJump_T_2 == 16'hA001; // @[Frontend.scala:246:26] wire taken_rvcJump_1 = _taken_rvcJump_T_3; // @[Frontend.scala:246:{26,47}] wire _taken_rvcImm_T_20 = taken_bits_1[14]; // @[Frontend.scala:236:37, :247:28] wire _taken_rvcImm_T_21 = taken_bits_1[12]; // @[RVC.scala:45:27] wire _taken_rvcImm_T_29 = taken_bits_1[12]; // @[RVC.scala:44:28, :45:27] wire [4:0] _taken_rvcImm_T_22 = {5{_taken_rvcImm_T_21}}; // @[RVC.scala:45:{22,27}] wire [1:0] _taken_rvcImm_T_23 = taken_bits_1[6:5]; // @[RVC.scala:45:35] wire _taken_rvcImm_T_24 = taken_bits_1[2]; // @[RVC.scala:45:43] wire _taken_rvcImm_T_35 = taken_bits_1[2]; // @[RVC.scala:44:63, :45:43] wire [1:0] _taken_rvcImm_T_25 = taken_bits_1[11:10]; // @[RVC.scala:45:49] wire [1:0] _taken_rvcImm_T_26 = taken_bits_1[4:3]; // @[RVC.scala:45:59] wire [3:0] taken_rvcImm_lo_hi_2 = {_taken_rvcImm_T_25, _taken_rvcImm_T_26}; // @[RVC.scala:45:{17,49,59}] wire [4:0] taken_rvcImm_lo_2 = {taken_rvcImm_lo_hi_2, 1'h0}; // @[RVC.scala:45:17] wire [6:0] taken_rvcImm_hi_hi_2 = {_taken_rvcImm_T_22, _taken_rvcImm_T_23}; // @[RVC.scala:45:{17,22,35}] wire [7:0] taken_rvcImm_hi_2 = {taken_rvcImm_hi_hi_2, _taken_rvcImm_T_24}; // @[RVC.scala:45:{17,43}] wire [12:0] _taken_rvcImm_T_27 = {taken_rvcImm_hi_2, taken_rvcImm_lo_2}; // @[RVC.scala:45:17] wire [12:0] _taken_rvcImm_T_28 = _taken_rvcImm_T_27; // @[RVC.scala:45:17] wire [9:0] _taken_rvcImm_T_30 = {10{_taken_rvcImm_T_29}}; // @[RVC.scala:44:{22,28}] wire _taken_rvcImm_T_31 = taken_bits_1[8]; // @[RVC.scala:44:36] wire [1:0] _taken_rvcImm_T_32 = taken_bits_1[10:9]; // @[RVC.scala:44:42] wire _taken_rvcImm_T_33 = taken_bits_1[6]; // @[RVC.scala:44:51] wire _taken_rvcImm_T_34 = taken_bits_1[7]; // @[RVC.scala:44:57] wire _taken_rvcImm_T_36 = taken_bits_1[11]; // @[RVC.scala:44:69] wire [2:0] _taken_rvcImm_T_37 = taken_bits_1[5:3]; // @[RVC.scala:44:76] wire [3:0] taken_rvcImm_lo_lo_1 = {_taken_rvcImm_T_37, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] taken_rvcImm_lo_hi_3 = {_taken_rvcImm_T_35, _taken_rvcImm_T_36}; // @[RVC.scala:44:{17,63,69}] wire [5:0] taken_rvcImm_lo_3 = {taken_rvcImm_lo_hi_3, taken_rvcImm_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] taken_rvcImm_hi_lo_1 = {_taken_rvcImm_T_33, _taken_rvcImm_T_34}; // @[RVC.scala:44:{17,51,57}] wire [10:0] taken_rvcImm_hi_hi_hi_1 = {_taken_rvcImm_T_30, _taken_rvcImm_T_31}; // @[RVC.scala:44:{17,22,36}] wire [12:0] taken_rvcImm_hi_hi_3 = {taken_rvcImm_hi_hi_hi_1, _taken_rvcImm_T_32}; // @[RVC.scala:44:{17,42}] wire [14:0] taken_rvcImm_hi_3 = {taken_rvcImm_hi_hi_3, taken_rvcImm_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_38 = {taken_rvcImm_hi_3, taken_rvcImm_lo_3}; // @[RVC.scala:44:17] wire [20:0] _taken_rvcImm_T_39 = _taken_rvcImm_T_38; // @[RVC.scala:44:17] wire [20:0] taken_rvcImm_1 = _taken_rvcImm_T_20 ? {{8{_taken_rvcImm_T_28[12]}}, _taken_rvcImm_T_28} : _taken_rvcImm_T_39; // @[Frontend.scala:247:{23,28,72,118}] wire [15:0] _GEN_8 = taken_bits_1 & 16'hF003; // @[Frontend.scala:236:37, :248:24] wire [15:0] _taken_rvcJR_T_4; // @[Frontend.scala:248:24] assign _taken_rvcJR_T_4 = _GEN_8; // @[Frontend.scala:248:24] wire [15:0] _taken_rvcJALR_T_4; // @[Frontend.scala:250:26] assign _taken_rvcJALR_T_4 = _GEN_8; // @[Frontend.scala:248:24, :250:26] wire _taken_rvcJR_T_5 = _taken_rvcJR_T_4 == 16'h8002; // @[Frontend.scala:248:24] wire [4:0] _taken_rvcJR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53] wire [4:0] _taken_rvcJALR_T_6 = taken_bits_1[6:2]; // @[Frontend.scala:236:37, :248:53, :250:56] wire _taken_rvcJR_T_7 = _taken_rvcJR_T_6 == 5'h0; // @[Frontend.scala:248:{53,59}] wire taken_rvcJR_1 = _taken_rvcJR_T_5 & _taken_rvcJR_T_7; // @[Frontend.scala:248:{24,46,59}] wire [4:0] _taken_rvcReturn_T_3 = taken_bits_1[11:7]; // @[Frontend.scala:236:37, :249:57] wire [4:0] _taken_rvcReturn_T_4 = _taken_rvcReturn_T_3 & 5'h1B; // @[Frontend.scala:249:{49,57}] wire _taken_rvcReturn_T_5 = _taken_rvcReturn_T_4 == 5'h1; // @[Frontend.scala:249:49] wire taken_rvcReturn_1 = taken_rvcJR_1 & _taken_rvcReturn_T_5; // @[Frontend.scala:248:46, :249:{29,49}] wire _taken_rvcJALR_T_5 = _taken_rvcJALR_T_4 == 16'h9002; // @[Frontend.scala:250:26] wire _taken_rvcJALR_T_7 = _taken_rvcJALR_T_6 == 5'h0; // @[Frontend.scala:250:{56,62}] wire taken_rvcJALR_1 = _taken_rvcJALR_T_5 & _taken_rvcJALR_T_7; // @[Frontend.scala:250:{26,49,62}] wire taken_rvcCall_1 = taken_rvcJALR_1; // @[Frontend.scala:250:49, :251:28] wire _taken_rviImm_T_5 = taken_rviBits_1[3]; // @[Frontend.scala:238:24, :252:31] wire _taken_rviImm_sign_T_7 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_10 = taken_rviBits_1[31]; // @[RocketCore.scala:1341:44] wire _taken_rviImm_sign_T_8 = _taken_rviImm_sign_T_7; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign_2 = _taken_rviImm_sign_T_8; // @[RocketCore.scala:1341:{19,49}] wire _taken_rviImm_b11_T_31 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1346:18] wire taken_rviImm_hi_hi_hi_2 = taken_rviImm_sign_2; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_7 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_10 = taken_rviBits_1[30:20]; // @[RocketCore.scala:1342:41] wire [10:0] _taken_rviImm_b30_20_T_8 = _taken_rviImm_b30_20_T_7; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20_2 = {11{taken_rviImm_sign_2}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo_2 = taken_rviImm_b30_20_2; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_13 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_18 = taken_rviBits_1[19:12]; // @[RocketCore.scala:1343:65] wire [7:0] _taken_rviImm_b19_12_T_14 = _taken_rviImm_b19_12_T_13; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12_2 = _taken_rviImm_b19_12_T_14; // @[RocketCore.scala:1343:{21,73}] wire [7:0] taken_rviImm_hi_lo_hi_2 = taken_rviImm_b19_12_2; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_26 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_19 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_37 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39] wire _taken_rviImm_b0_T_27 = taken_rviBits_1[20]; // @[RocketCore.scala:1345:39, :1352:37] wire _taken_rviImm_b11_T_27 = _taken_rviImm_b11_T_26; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_32 = _taken_rviImm_b11_T_27; // @[RocketCore.scala:1345:{18,44}] wire _taken_rviImm_b11_T_30 = _taken_rviImm_b11_T_29; // @[RocketCore.scala:1346:{39,43}] wire taken_rviImm_b11_2 = _taken_rviImm_b11_T_32; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo_2 = taken_rviImm_b11_2; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] _taken_rviImm_b10_5_T_11 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] _taken_rviImm_b10_5_T_15 = taken_rviBits_1[30:25]; // @[RocketCore.scala:1347:62] wire [5:0] taken_rviImm_b10_5_2 = _taken_rviImm_b10_5_T_11; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_24 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_34 = taken_rviBits_1[11:8]; // @[RocketCore.scala:1349:57] wire [3:0] _taken_rviImm_b4_1_T_26 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_36 = taken_rviBits_1[19:16]; // @[RocketCore.scala:1350:39] wire [3:0] _taken_rviImm_b4_1_T_27 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_37 = taken_rviBits_1[24:21]; // @[RocketCore.scala:1350:52] wire [3:0] _taken_rviImm_b4_1_T_28 = _taken_rviImm_b4_1_T_27; // @[RocketCore.scala:1350:{19,52}] wire [3:0] _taken_rviImm_b4_1_T_29 = _taken_rviImm_b4_1_T_28; // @[RocketCore.scala:1349:19, :1350:19] wire [3:0] taken_rviImm_b4_1_2 = _taken_rviImm_b4_1_T_29; // @[RocketCore.scala:1348:19, :1349:19] wire _taken_rviImm_b0_T_21 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37] wire _taken_rviImm_b0_T_29 = taken_rviBits_1[15]; // @[RocketCore.scala:1353:37] wire [9:0] taken_rviImm_lo_hi_2 = {taken_rviImm_b10_5_2, taken_rviImm_b4_1_2}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo_2 = {taken_rviImm_lo_hi_2, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo_2 = {taken_rviImm_hi_lo_hi_2, taken_rviImm_hi_lo_lo_2}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi_2 = {taken_rviImm_hi_hi_hi_2, taken_rviImm_hi_hi_lo_2}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi_2 = {taken_rviImm_hi_hi_2, taken_rviImm_hi_lo_2}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_6 = {taken_rviImm_hi_2, taken_rviImm_lo_2}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_7 = _taken_rviImm_T_6; // @[RocketCore.scala:1355:{8,53}] wire _taken_rviImm_sign_T_11 = _taken_rviImm_sign_T_10; // @[RocketCore.scala:1341:{44,49}] wire taken_rviImm_sign_3 = _taken_rviImm_sign_T_11; // @[RocketCore.scala:1341:{19,49}] wire taken_rviImm_hi_hi_hi_3 = taken_rviImm_sign_3; // @[RocketCore.scala:1341:19, :1355:8] wire [10:0] _taken_rviImm_b30_20_T_11 = _taken_rviImm_b30_20_T_10; // @[RocketCore.scala:1342:{41,49}] wire [10:0] taken_rviImm_b30_20_3 = {11{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1342:21] wire [10:0] taken_rviImm_hi_hi_lo_3 = taken_rviImm_b30_20_3; // @[RocketCore.scala:1342:21, :1355:8] wire [7:0] _taken_rviImm_b19_12_T_19 = _taken_rviImm_b19_12_T_18; // @[RocketCore.scala:1343:{65,73}] wire [7:0] taken_rviImm_b19_12_3 = {8{taken_rviImm_sign_3}}; // @[RocketCore.scala:1341:19, :1343:21] wire [7:0] taken_rviImm_hi_lo_hi_3 = taken_rviImm_b19_12_3; // @[RocketCore.scala:1343:21, :1355:8] wire _taken_rviImm_b11_T_38 = _taken_rviImm_b11_T_37; // @[RocketCore.scala:1345:{39,44}] wire _taken_rviImm_b11_T_41 = _taken_rviImm_b11_T_40; // @[RocketCore.scala:1346:{39,43}] wire _taken_rviImm_b11_T_42 = _taken_rviImm_b11_T_41; // @[RocketCore.scala:1346:{18,43}] wire _taken_rviImm_b11_T_43 = _taken_rviImm_b11_T_42; // @[RocketCore.scala:1345:18, :1346:18] wire taken_rviImm_b11_3 = _taken_rviImm_b11_T_43; // @[RocketCore.scala:1344:18, :1345:18] wire taken_rviImm_hi_lo_lo_3 = taken_rviImm_b11_3; // @[RocketCore.scala:1344:18, :1355:8] wire [5:0] taken_rviImm_b10_5_3 = _taken_rviImm_b10_5_T_15; // @[RocketCore.scala:1347:{20,62}] wire [3:0] _taken_rviImm_b4_1_T_39 = _taken_rviImm_b4_1_T_34; // @[RocketCore.scala:1349:{19,57}] wire [3:0] _taken_rviImm_b4_1_T_38 = _taken_rviImm_b4_1_T_37; // @[RocketCore.scala:1350:{19,52}] wire [3:0] taken_rviImm_b4_1_3 = _taken_rviImm_b4_1_T_39; // @[RocketCore.scala:1348:19, :1349:19] wire [9:0] taken_rviImm_lo_hi_3 = {taken_rviImm_b10_5_3, taken_rviImm_b4_1_3}; // @[RocketCore.scala:1347:20, :1348:19, :1355:8] wire [10:0] taken_rviImm_lo_3 = {taken_rviImm_lo_hi_3, 1'h0}; // @[RocketCore.scala:1355:8] wire [8:0] taken_rviImm_hi_lo_3 = {taken_rviImm_hi_lo_hi_3, taken_rviImm_hi_lo_lo_3}; // @[RocketCore.scala:1355:8] wire [11:0] taken_rviImm_hi_hi_3 = {taken_rviImm_hi_hi_hi_3, taken_rviImm_hi_hi_lo_3}; // @[RocketCore.scala:1355:8] wire [20:0] taken_rviImm_hi_3 = {taken_rviImm_hi_hi_3, taken_rviImm_hi_lo_3}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_8 = {taken_rviImm_hi_3, taken_rviImm_lo_3}; // @[RocketCore.scala:1355:8] wire [31:0] _taken_rviImm_T_9 = _taken_rviImm_T_8; // @[RocketCore.scala:1355:{8,53}] wire [31:0] taken_rviImm_1 = _taken_rviImm_T_5 ? _taken_rviImm_T_7 : _taken_rviImm_T_9; // @[RocketCore.scala:1355:53] wire taken_predict_taken_1 = _taken_predict_taken_T_1; // @[Frontend.scala:253:54] wire _taken_taken_T_10 = taken_rviBranch_1 & taken_predict_taken_1; // @[Frontend.scala:239:36, :253:54, :255:53] wire _taken_taken_T_11 = _taken_taken_T_9 | _taken_taken_T_10; // @[Frontend.scala:255:{29,40,53}] wire _taken_taken_T_12 = taken_prevRVI_1 & _taken_taken_T_11; // @[Frontend.scala:234:31, :255:{17,40}] wire _taken_taken_T_13 = taken_rvcJump_1 | taken_rvcJALR_1; // @[Frontend.scala:246:47, :250:49, :256:27] wire _taken_taken_T_14 = _taken_taken_T_13 | taken_rvcJR_1; // @[Frontend.scala:248:46, :256:{27,38}] wire _taken_taken_T_15 = taken_rvcBranch_1 & taken_predict_taken_1; // @[Frontend.scala:244:52, :253:54, :256:60] wire _taken_taken_T_16 = _taken_taken_T_14 | _taken_taken_T_15; // @[Frontend.scala:256:{38,47,60}] wire _taken_taken_T_17 = taken_valid_1 & _taken_taken_T_16; // @[Frontend.scala:235:44, :256:{15,47}] wire taken_taken_1 = _taken_taken_T_12 | _taken_taken_T_17; // @[Frontend.scala:255:{17,71}, :256:15] wire _taken_predictReturn_T_3 = taken_prevRVI_1 & taken_rviReturn_1; // @[Frontend.scala:234:31, :242:46, :257:61] wire _taken_predictReturn_T_4 = taken_valid_1 & taken_rvcReturn_1; // @[Frontend.scala:235:44, :249:29, :257:83] wire _taken_predictReturn_T_5 = _taken_predictReturn_T_3 | _taken_predictReturn_T_4; // @[Frontend.scala:257:{61,74,83}] wire taken_predictReturn_1 = _btb_io_ras_head_valid & _taken_predictReturn_T_5; // @[Frontend.scala:198:21, :257:{49,74}] wire _taken_predictJump_T_2 = taken_prevRVI_1 & taken_rviJump_1; // @[Frontend.scala:234:31, :240:34, :258:33] wire _taken_predictJump_T_3 = taken_valid_1 & taken_rvcJump_1; // @[Frontend.scala:235:44, :246:47, :258:53] wire taken_predictJump_1 = _taken_predictJump_T_2 | _taken_predictJump_T_3; // @[Frontend.scala:258:{33,44,53}] wire _GEN_9 = taken_prevRVI_1 & taken_rviBranch_1; // @[Frontend.scala:234:31, :239:36, :259:53] wire _taken_predictBranch_T_3; // @[Frontend.scala:259:53] assign _taken_predictBranch_T_3 = _GEN_9; // @[Frontend.scala:259:53] wire _taken_T_48; // @[Frontend.scala:294:23] assign _taken_T_48 = _GEN_9; // @[Frontend.scala:259:53, :294:23] wire _GEN_10 = taken_valid_1 & taken_rvcBranch_1; // @[Frontend.scala:235:44, :244:52, :259:75] wire _taken_predictBranch_T_4; // @[Frontend.scala:259:75] assign _taken_predictBranch_T_4 = _GEN_10; // @[Frontend.scala:259:75] wire _taken_T_49; // @[Frontend.scala:294:45] assign _taken_T_49 = _GEN_10; // @[Frontend.scala:259:75, :294:45] wire _taken_predictBranch_T_5 = _taken_predictBranch_T_3 | _taken_predictBranch_T_4; // @[Frontend.scala:259:{53,66,75}] wire taken_predictBranch_1 = taken_predict_taken_1 & _taken_predictBranch_T_5; // @[Frontend.scala:253:54, :259:{41,66}] wire _taken_T_31 = _taken_T_29 & _taken_T_30; // @[Frontend.scala:261:{22,43,69}] wire _taken_T_32 = _taken_T_31 & taken_valid_1; // @[Frontend.scala:235:44, :261:{43,79}] wire _taken_T_33 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91] wire _taken_T_34 = _taken_T_32 & _taken_T_33; // @[Frontend.scala:261:{79,88,91}] assign _taken_T_35 = ~_taken_T_28; // @[Frontend.scala:270:13, :313:51] assign taken_idx = _taken_T_35; // @[Frontend.scala:223:25, :270:13] assign after_idx = _taken_T_35 ? 2'h2 : 2'h1; // @[Frontend.scala:224:25, :270:{13,25}, :272:19] wire _taken_btb_io_ras_update_valid_T_10 = ~wrong_path; // @[Frontend.scala:126:27, :273:54, :319:52] wire _taken_btb_io_ras_update_valid_T_11 = _taken_btb_io_ras_update_valid_T_9 & _taken_btb_io_ras_update_valid_T_10; // @[Decoupled.scala:51:35] wire _taken_btb_io_ras_update_valid_T_12 = taken_rviCall_1 | taken_rviReturn_1; // @[Frontend.scala:242:46, :243:42, :273:90] wire _taken_btb_io_ras_update_valid_T_13 = taken_prevRVI_1 & _taken_btb_io_ras_update_valid_T_12; // @[Frontend.scala:234:31, :273:{78,90}] wire _taken_btb_io_ras_update_valid_T_14 = taken_rvcCall_1 | taken_rvcReturn_1; // @[Frontend.scala:249:29, :251:28, :273:125] wire _taken_btb_io_ras_update_valid_T_15 = taken_valid_1 & _taken_btb_io_ras_update_valid_T_14; // @[Frontend.scala:235:44, :273:{113,125}] wire _taken_btb_io_ras_update_valid_T_16 = _taken_btb_io_ras_update_valid_T_13 | _taken_btb_io_ras_update_valid_T_15; // @[Frontend.scala:273:{78,104,113}] wire _taken_btb_io_ras_update_valid_T_17 = _taken_btb_io_ras_update_valid_T_11 & _taken_btb_io_ras_update_valid_T_16; // @[Frontend.scala:273:{51,66,104}] wire _taken_btb_io_ras_update_bits_cfiType_T_8 = taken_prevRVI_1 ? taken_rviReturn_1 : taken_rvcReturn_1; // @[Frontend.scala:234:31, :242:46, :249:29, :274:50] wire _taken_btb_io_ras_update_bits_cfiType_T_9 = taken_prevRVI_1 ? taken_rviCall_1 : taken_rvcCall_1; // @[Frontend.scala:234:31, :243:42, :251:28, :275:50] wire _taken_btb_io_ras_update_bits_cfiType_T_10 = taken_prevRVI_1 ? taken_rviBranch_1 : taken_rvcBranch_1; // @[Frontend.scala:234:31, :239:36, :244:52, :276:50] wire _taken_btb_io_ras_update_bits_cfiType_T_12 = _taken_btb_io_ras_update_bits_cfiType_T_10; // @[Frontend.scala:276:{50,82}] wire _taken_btb_io_ras_update_bits_cfiType_T_13 = ~_taken_btb_io_ras_update_bits_cfiType_T_12; // @[Frontend.scala:276:{46,82}] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_14 = _taken_btb_io_ras_update_bits_cfiType_T_9 ? 2'h2 : {1'h0, _taken_btb_io_ras_update_bits_cfiType_T_13}; // @[Frontend.scala:275:{46,50}, :276:46] wire [1:0] _taken_btb_io_ras_update_bits_cfiType_T_15 = _taken_btb_io_ras_update_bits_cfiType_T_8 ? 2'h3 : _taken_btb_io_ras_update_bits_cfiType_T_14; // @[Frontend.scala:274:{46,50}, :275:46] assign btb_io_ras_update_bits_cfiType = _taken_T_35 ? _taken_btb_io_ras_update_bits_cfiType_T_15 : _taken_btb_io_ras_update_bits_cfiType_T_7; // @[Frontend.scala:270:{13,25}, :274:{40,46}] wire _taken_T_36 = ~s2_btb_taken; // @[Frontend.scala:120:40, :279:15] wire _taken_T_38 = _taken_T_37 & taken_taken_1; // @[Decoupled.scala:51:35] wire _taken_T_39 = ~taken_predictBranch_1; // @[Frontend.scala:259:41, :280:44] wire _taken_T_40 = _taken_T_38 & _taken_T_39; // @[Frontend.scala:280:{32,41,44}] wire _taken_T_41 = ~taken_predictJump_1; // @[Frontend.scala:258:44, :280:62] wire _taken_T_42 = _taken_T_40 & _taken_T_41; // @[Frontend.scala:280:{41,59,62}] wire _taken_T_43 = ~taken_predictReturn_1; // @[Frontend.scala:257:49, :280:78] wire _taken_T_44 = _taken_T_42 & _taken_T_43; // @[Frontend.scala:280:{59,75,78}] wire _taken_T_45 = s2_valid & taken_predictReturn_1; // @[Frontend.scala:108:25, :257:49, :283:26] assign useRAS = _taken_T_35 & _taken_T_36 & _taken_T_45 | _taken_T_7 & _taken_T_16; // @[Frontend.scala:225:29, :270:{13,25}, :279:{15,30}, :283:{26,44}, :284:20] wire _taken_T_46 = taken_predictBranch_1 | taken_predictJump_1; // @[Frontend.scala:258:44, :259:41, :286:44] wire _taken_T_47 = s2_valid & _taken_T_46; // @[Frontend.scala:108:25, :286:{26,44}] wire [39:0] taken_pc_1 = {s2_base_pc[39:2], s2_base_pc[1:0] | 2'h2}; // @[Frontend.scala:222:22, :287:33, :323:50] wire [40:0] _taken_npc_T_5 = {1'h0, taken_pc_1} - 41'h2; // @[Frontend.scala:287:33, :290:36] wire [39:0] _taken_npc_T_6 = _taken_npc_T_5[39:0]; // @[Frontend.scala:290:36] wire [39:0] _taken_npc_T_7 = taken_prevRVI_1 ? _taken_npc_T_6 : taken_pc_1; // @[Frontend.scala:234:31, :287:33, :290:{23,36}] wire [39:0] _taken_npc_T_8 = _taken_npc_T_7; // @[Frontend.scala:290:{23,59}] wire [31:0] _taken_npc_T_9 = taken_prevRVI_1 ? taken_rviImm_1 : {{11{taken_rvcImm_1[20]}}, taken_rvcImm_1}; // @[Frontend.scala:234:31, :247:23, :252:23, :290:71] wire [40:0] _taken_npc_T_10 = {_taken_npc_T_8[39], _taken_npc_T_8} + {{9{_taken_npc_T_9[31]}}, _taken_npc_T_9}; // @[Frontend.scala:290:{59,66,71}] wire [39:0] _taken_npc_T_11 = _taken_npc_T_10[39:0]; // @[Frontend.scala:290:66] wire [39:0] taken_npc_1 = _taken_npc_T_11; // @[Frontend.scala:290:66] wire [39:0] _taken_predicted_npc_T_1 = taken_npc_1; // @[Frontend.scala:290:66, :291:34] wire _taken_T_50 = _taken_T_48 | _taken_T_49; // @[Frontend.scala:294:{23,36,45}] wire _taken_btb_io_bht_advance_valid_T_4 = ~wrong_path; // @[Frontend.scala:126:27, :295:57, :319:52] wire _taken_btb_io_bht_advance_valid_T_5 = _taken_btb_io_bht_advance_valid_T_3 & _taken_btb_io_bht_advance_valid_T_4; // @[Decoupled.scala:51:35] wire _taken_T_51 = ~s2_btb_resp_valid; // @[Frontend.scala:118:44, :298:15] wire _taken_T_53 = taken_predictBranch_1 & _taken_T_52; // @[Frontend.scala:259:41, :298:52] wire _taken_T_54 = _taken_T_53 | taken_predictJump_1; // @[Frontend.scala:258:44, :298:{52,91}] wire _taken_T_55 = _taken_T_54 | taken_predictReturn_1; // @[Frontend.scala:257:49, :298:{91,106}] wire _taken_T_56 = _taken_T_51 & _taken_T_55; // @[Frontend.scala:298:{15,34,106}] assign updateBTB = _taken_T_35 & _taken_T_56 | _taken_T_27; // @[Frontend.scala:226:32, :270:{13,25}, :298:{34,125}, :299:21] wire _taken_T_58 = ~_taken_T_28; // @[Frontend.scala:270:13, :306:26, :313:51] wire _taken_T_59 = taken_valid_1 & _taken_T_58; // @[Frontend.scala:235:44, :306:{23,26}] wire _taken_T_60 = ~taken_rvc_1; // @[Frontend.scala:233:45, :261:91, :306:40] wire _taken_T_61 = _taken_T_59 & _taken_T_60; // @[Frontend.scala:306:{23,37,40}] wire [15:0] _taken_s2_partial_insn_T = {taken_bits_1[15:2], 2'h3}; // @[Frontend.scala:236:37, :308:37] wire taken = _taken_T_28 | taken_taken_1; // @[Frontend.scala:255:71, :311:19, :313:51] assign predicted_npc = useRAS ? {1'h0, _btb_io_ras_head_bits} : _taken_T_35 & _taken_T_36 & _taken_T_47 ? _taken_predicted_npc_T_1 : _taken_T_7 & _taken_T_18 ? _taken_predicted_npc_T : predicted_taken ? _predicted_npc_T_1 : ntpc; // @[package.scala:132:15] wire _GEN_11 = ~s2_btb_taken & taken; // @[Frontend.scala:120:40, :191:22, :311:19, :336:{11,26}, :337:20, :338:34] assign s2_redirect = ~s2_btb_taken & taken & _T_37 | io_cpu_req_valid_0; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_145 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_145( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_130 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_130( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PTW : input clock : Clock input reset : Reset output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}[20], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<8>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, dpath : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}} regreset state : UInt<3>, clock, reset, UInt<3>(0h0) wire l2_refill_wire : UInt<1> inst arb of Arbiter20_Valid_PTWReq connect arb.clock, clock connect arb.reset, reset connect arb.io.in[0], io.requestor[0].req connect arb.io.in[1], io.requestor[1].req connect arb.io.in[2], io.requestor[2].req connect arb.io.in[3], io.requestor[3].req connect arb.io.in[4], io.requestor[4].req connect arb.io.in[5], io.requestor[5].req connect arb.io.in[6], io.requestor[6].req connect arb.io.in[7], io.requestor[7].req connect arb.io.in[8], io.requestor[8].req connect arb.io.in[9], io.requestor[9].req connect arb.io.in[10], io.requestor[10].req connect arb.io.in[11], io.requestor[11].req connect arb.io.in[12], io.requestor[12].req connect arb.io.in[13], io.requestor[13].req connect arb.io.in[14], io.requestor[14].req connect arb.io.in[15], io.requestor[15].req connect arb.io.in[16], io.requestor[16].req connect arb.io.in[17], io.requestor[17].req connect arb.io.in[18], io.requestor[18].req connect arb.io.in[19], io.requestor[19].req node _arb_io_out_ready_T = eq(state, UInt<3>(0h0)) node _arb_io_out_ready_T_1 = eq(l2_refill_wire, UInt<1>(0h0)) node _arb_io_out_ready_T_2 = and(_arb_io_out_ready_T, _arb_io_out_ready_T_1) connect arb.io.out.ready, _arb_io_out_ready_T_2 wire _resp_valid_WIRE : UInt<1>[20] connect _resp_valid_WIRE[0], UInt<1>(0h0) connect _resp_valid_WIRE[1], UInt<1>(0h0) connect _resp_valid_WIRE[2], UInt<1>(0h0) connect _resp_valid_WIRE[3], UInt<1>(0h0) connect _resp_valid_WIRE[4], UInt<1>(0h0) connect _resp_valid_WIRE[5], UInt<1>(0h0) connect _resp_valid_WIRE[6], UInt<1>(0h0) connect _resp_valid_WIRE[7], UInt<1>(0h0) connect _resp_valid_WIRE[8], UInt<1>(0h0) connect _resp_valid_WIRE[9], UInt<1>(0h0) connect _resp_valid_WIRE[10], UInt<1>(0h0) connect _resp_valid_WIRE[11], UInt<1>(0h0) connect _resp_valid_WIRE[12], UInt<1>(0h0) connect _resp_valid_WIRE[13], UInt<1>(0h0) connect _resp_valid_WIRE[14], UInt<1>(0h0) connect _resp_valid_WIRE[15], UInt<1>(0h0) connect _resp_valid_WIRE[16], UInt<1>(0h0) connect _resp_valid_WIRE[17], UInt<1>(0h0) connect _resp_valid_WIRE[18], UInt<1>(0h0) connect _resp_valid_WIRE[19], UInt<1>(0h0) reg resp_valid : UInt<1>[20], clock connect resp_valid, _resp_valid_WIRE node _clock_en_T = neq(state, UInt<3>(0h0)) node _clock_en_T_1 = or(_clock_en_T, l2_refill_wire) node _clock_en_T_2 = or(_clock_en_T_1, arb.io.out.valid) node _clock_en_T_3 = or(_clock_en_T_2, io.dpath.sfence.valid) node _clock_en_T_4 = bits(io.dpath.customCSRs.csrs[0].value, 0, 0) node clock_en = or(_clock_en_T_3, _clock_en_T_4) node _io_dpath_clock_enabled_T = and(UInt<1>(0h1), clock_en) connect io.dpath.clock_enabled, _io_dpath_clock_enabled_T reg invalidated : UInt<1>, clock reg count : UInt<2>, clock reg resp_ae_ptw : UInt<1>, clock reg resp_ae_final : UInt<1>, clock reg resp_pf : UInt<1>, clock reg resp_gf : UInt<1>, clock reg resp_hr : UInt<1>, clock reg resp_hw : UInt<1>, clock reg resp_hx : UInt<1>, clock reg resp_fragmented_superpage : UInt<1>, clock reg r_req : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}, clock reg r_req_dest : UInt, clock reg r_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg r_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock reg aux_count : UInt<2>, clock reg aux_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, clock reg gpa_pgoff : UInt<12>, clock reg stage2 : UInt<1>, clock reg stage2_final : UInt<1>, clock node satp = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp, io.dpath.ptbr) node _r_hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_hgatp_initial_count_T_1 = tail(_r_hgatp_initial_count_T, 1) node _r_hgatp_initial_count_T_2 = sub(_r_hgatp_initial_count_T_1, UInt<1>(0h0)) node r_hgatp_initial_count = tail(_r_hgatp_initial_count_T_2, 1) node do_both_stages = and(r_req.vstage1, r_req.stage2) node _max_count_T = lt(count, aux_count) node max_count = mux(_max_count_T, aux_count, count) node _vpn_T = and(r_req.vstage1, stage2) node vpn = mux(_vpn_T, aux_pte.ppn, r_req.addr) reg mem_resp_valid : UInt<1>, clock connect mem_resp_valid, io.mem.resp.valid reg mem_resp_data : UInt, clock connect mem_resp_data, io.mem.resp.bits.data wire tmp : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} wire _tmp_WIRE : UInt<64> connect _tmp_WIRE, mem_resp_data node _tmp_T = bits(_tmp_WIRE, 0, 0) connect tmp.v, _tmp_T node _tmp_T_1 = bits(_tmp_WIRE, 1, 1) connect tmp.r, _tmp_T_1 node _tmp_T_2 = bits(_tmp_WIRE, 2, 2) connect tmp.w, _tmp_T_2 node _tmp_T_3 = bits(_tmp_WIRE, 3, 3) connect tmp.x, _tmp_T_3 node _tmp_T_4 = bits(_tmp_WIRE, 4, 4) connect tmp.u, _tmp_T_4 node _tmp_T_5 = bits(_tmp_WIRE, 5, 5) connect tmp.g, _tmp_T_5 node _tmp_T_6 = bits(_tmp_WIRE, 6, 6) connect tmp.a, _tmp_T_6 node _tmp_T_7 = bits(_tmp_WIRE, 7, 7) connect tmp.d, _tmp_T_7 node _tmp_T_8 = bits(_tmp_WIRE, 9, 8) connect tmp.reserved_for_software, _tmp_T_8 node _tmp_T_9 = bits(_tmp_WIRE, 53, 10) connect tmp.ppn, _tmp_T_9 node _tmp_T_10 = bits(_tmp_WIRE, 63, 54) connect tmp.reserved_for_future, _tmp_T_10 wire pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect pte, tmp node _res_ppn_T = eq(stage2, UInt<1>(0h0)) node _res_ppn_T_1 = and(do_both_stages, _res_ppn_T) node _res_ppn_T_2 = bits(tmp.ppn, 26, 0) node _res_ppn_T_3 = bits(tmp.ppn, 19, 0) node _res_ppn_T_4 = mux(_res_ppn_T_1, _res_ppn_T_2, _res_ppn_T_3) connect pte.ppn, _res_ppn_T_4 node _T = or(tmp.r, tmp.w) node _T_1 = or(_T, tmp.x) when _T_1 : node _T_2 = leq(count, UInt<1>(0h0)) node _T_3 = bits(tmp.ppn, 17, 9) node _T_4 = neq(_T_3, UInt<1>(0h0)) node _T_5 = and(_T_2, _T_4) when _T_5 : connect pte.v, UInt<1>(0h0) node _T_6 = leq(count, UInt<1>(0h1)) node _T_7 = bits(tmp.ppn, 8, 0) node _T_8 = neq(_T_7, UInt<1>(0h0)) node _T_9 = and(_T_6, _T_8) when _T_9 : connect pte.v, UInt<1>(0h0) node _T_10 = eq(stage2, UInt<1>(0h0)) node _T_11 = and(do_both_stages, _T_10) node _T_12 = shr(tmp.ppn, 27) node _T_13 = neq(_T_12, UInt<1>(0h0)) node _T_14 = shr(tmp.ppn, 20) node _T_15 = neq(_T_14, UInt<1>(0h0)) node invalid_paddr = mux(_T_11, _T_13, _T_15) node _T_16 = eq(stage2, UInt<1>(0h0)) node _T_17 = and(do_both_stages, _T_16) node _count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _count_T_1 = tail(_count_T, 1) node _count_T_2 = sub(_count_T_1, UInt<1>(0h0)) node count_1 = tail(_count_T_2, 1) node idxs_0 = shr(tmp.ppn, 29) wire _WIRE : UInt<15>[1] connect _WIRE[0], idxs_0 node _T_18 = or(count_1, UInt<0>(0h0)) node _T_19 = neq(_WIRE[0], UInt<1>(0h0)) node invalid_gpa = and(_T_17, _T_19) node _traverse_T = eq(pte.r, UInt<1>(0h0)) node _traverse_T_1 = and(pte.v, _traverse_T) node _traverse_T_2 = eq(pte.w, UInt<1>(0h0)) node _traverse_T_3 = and(_traverse_T_1, _traverse_T_2) node _traverse_T_4 = eq(pte.x, UInt<1>(0h0)) node _traverse_T_5 = and(_traverse_T_3, _traverse_T_4) node _traverse_T_6 = eq(pte.d, UInt<1>(0h0)) node _traverse_T_7 = and(_traverse_T_5, _traverse_T_6) node _traverse_T_8 = eq(pte.a, UInt<1>(0h0)) node _traverse_T_9 = and(_traverse_T_7, _traverse_T_8) node _traverse_T_10 = eq(pte.u, UInt<1>(0h0)) node _traverse_T_11 = and(_traverse_T_9, _traverse_T_10) node _traverse_T_12 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _traverse_T_13 = and(_traverse_T_11, _traverse_T_12) node _traverse_T_14 = eq(invalid_paddr, UInt<1>(0h0)) node _traverse_T_15 = and(_traverse_T_13, _traverse_T_14) node _traverse_T_16 = eq(invalid_gpa, UInt<1>(0h0)) node _traverse_T_17 = and(_traverse_T_15, _traverse_T_16) node _traverse_T_18 = lt(count, UInt<2>(0h2)) node traverse = and(_traverse_T_17, _traverse_T_18) node _pte_addr_vpn_idxs_T = shr(vpn, 18) node pte_addr_vpn_idxs_0 = bits(_pte_addr_vpn_idxs_T, 8, 0) node _pte_addr_vpn_idxs_T_1 = shr(vpn, 9) node pte_addr_vpn_idxs_1 = bits(_pte_addr_vpn_idxs_T_1, 8, 0) node _pte_addr_vpn_idxs_T_2 = shr(vpn, 0) node pte_addr_vpn_idxs_2 = bits(_pte_addr_vpn_idxs_T_2, 8, 0) node _pte_addr_mask_T = eq(count, r_hgatp_initial_count) node _pte_addr_mask_T_1 = and(stage2, _pte_addr_mask_T) node pte_addr_mask = mux(_pte_addr_mask_T_1, UInt<9>(0h1ff), UInt<9>(0h1ff)) node _pte_addr_vpn_idx_T = eq(count, UInt<1>(0h1)) node _pte_addr_vpn_idx_T_1 = mux(_pte_addr_vpn_idx_T, pte_addr_vpn_idxs_1, pte_addr_vpn_idxs_0) node _pte_addr_vpn_idx_T_2 = eq(count, UInt<2>(0h2)) node _pte_addr_vpn_idx_T_3 = mux(_pte_addr_vpn_idx_T_2, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_1) node _pte_addr_vpn_idx_T_4 = eq(count, UInt<2>(0h3)) node _pte_addr_vpn_idx_T_5 = mux(_pte_addr_vpn_idx_T_4, pte_addr_vpn_idxs_2, _pte_addr_vpn_idx_T_3) node pte_addr_vpn_idx = and(_pte_addr_vpn_idx_T_5, pte_addr_mask) node _pte_addr_raw_pte_addr_T = shl(r_pte.ppn, 9) node _pte_addr_raw_pte_addr_T_1 = or(_pte_addr_raw_pte_addr_T, pte_addr_vpn_idx) node pte_addr_raw_pte_addr = shl(_pte_addr_raw_pte_addr_T_1, 3) node pte_addr = bits(pte_addr_raw_pte_addr, 31, 0) regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0) regreset valid : UInt<8>, clock, reset, UInt<8>(0h0) reg tags : UInt<32>[8], clock reg data : UInt<20>[8], clock node _can_hit_T = lt(count, UInt<2>(0h2)) node _can_hit_T_1 = eq(r_req.stage2, UInt<1>(0h0)) node _can_hit_T_2 = mux(r_req.vstage1, stage2, _can_hit_T_1) node can_hit = and(_can_hit_T, _can_hit_T_2) node tag = cat(r_req.vstage1, pte_addr) node _hits_T = eq(tags[0], tag) node _hits_T_1 = eq(tags[1], tag) node _hits_T_2 = eq(tags[2], tag) node _hits_T_3 = eq(tags[3], tag) node _hits_T_4 = eq(tags[4], tag) node _hits_T_5 = eq(tags[5], tag) node _hits_T_6 = eq(tags[6], tag) node _hits_T_7 = eq(tags[7], tag) node hits_lo_lo = cat(_hits_T_1, _hits_T) node hits_lo_hi = cat(_hits_T_3, _hits_T_2) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo = cat(_hits_T_5, _hits_T_4) node hits_hi_hi = cat(_hits_T_7, _hits_T_6) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node _hits_T_8 = cat(hits_hi, hits_lo) node hits = and(_hits_T_8, valid) node _hit_T = orr(hits) node pte_cache_hit = and(_hit_T, can_hit) node _T_20 = and(mem_resp_valid, traverse) node _T_21 = and(_T_20, can_hit) node _T_22 = orr(hits) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = and(_T_21, _T_23) node _T_25 = eq(invalidated, UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) when _T_26 : node _r_T = andr(valid) node r_left_subtree_older = bits(state_reg, 6, 6) node r_left_subtree_state = bits(state_reg, 5, 3) node r_right_subtree_state = bits(state_reg, 2, 0) node r_left_subtree_older_1 = bits(r_left_subtree_state, 2, 2) node r_left_subtree_state_1 = bits(r_left_subtree_state, 1, 1) node r_right_subtree_state_1 = bits(r_left_subtree_state, 0, 0) node _r_T_1 = bits(r_left_subtree_state_1, 0, 0) node _r_T_2 = bits(r_right_subtree_state_1, 0, 0) node _r_T_3 = mux(r_left_subtree_older_1, _r_T_1, _r_T_2) node _r_T_4 = cat(r_left_subtree_older_1, _r_T_3) node r_left_subtree_older_2 = bits(r_right_subtree_state, 2, 2) node r_left_subtree_state_2 = bits(r_right_subtree_state, 1, 1) node r_right_subtree_state_2 = bits(r_right_subtree_state, 0, 0) node _r_T_5 = bits(r_left_subtree_state_2, 0, 0) node _r_T_6 = bits(r_right_subtree_state_2, 0, 0) node _r_T_7 = mux(r_left_subtree_older_2, _r_T_5, _r_T_6) node _r_T_8 = cat(r_left_subtree_older_2, _r_T_7) node _r_T_9 = mux(r_left_subtree_older, _r_T_4, _r_T_8) node _r_T_10 = cat(r_left_subtree_older, _r_T_9) node _r_T_11 = not(valid) node _r_T_12 = bits(_r_T_11, 0, 0) node _r_T_13 = bits(_r_T_11, 1, 1) node _r_T_14 = bits(_r_T_11, 2, 2) node _r_T_15 = bits(_r_T_11, 3, 3) node _r_T_16 = bits(_r_T_11, 4, 4) node _r_T_17 = bits(_r_T_11, 5, 5) node _r_T_18 = bits(_r_T_11, 6, 6) node _r_T_19 = bits(_r_T_11, 7, 7) node _r_T_20 = mux(_r_T_18, UInt<3>(0h6), UInt<3>(0h7)) node _r_T_21 = mux(_r_T_17, UInt<3>(0h5), _r_T_20) node _r_T_22 = mux(_r_T_16, UInt<3>(0h4), _r_T_21) node _r_T_23 = mux(_r_T_15, UInt<2>(0h3), _r_T_22) node _r_T_24 = mux(_r_T_14, UInt<2>(0h2), _r_T_23) node _r_T_25 = mux(_r_T_13, UInt<1>(0h1), _r_T_24) node _r_T_26 = mux(_r_T_12, UInt<1>(0h0), _r_T_25) node r = mux(_r_T, _r_T_10, _r_T_26) node _valid_T = dshl(UInt<1>(0h1), r) node _valid_T_1 = or(valid, _valid_T) connect valid, _valid_T_1 connect tags[r], tag connect data[r], pte.ppn node state_reg_touch_way_sized = bits(r, 2, 0) node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 2, 2) node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0)) node state_reg_left_subtree_state = bits(state_reg, 5, 3) node state_reg_right_subtree_state = bits(state_reg, 2, 0) node _state_reg_T = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_1 = bits(_state_reg_T, 1, 1) node state_reg_set_left_older_1 = eq(_state_reg_set_left_older_T_1, UInt<1>(0h0)) node state_reg_left_subtree_state_1 = bits(state_reg_left_subtree_state, 1, 1) node state_reg_right_subtree_state_1 = bits(state_reg_left_subtree_state, 0, 0) node _state_reg_T_1 = bits(_state_reg_T, 0, 0) node _state_reg_T_2 = bits(_state_reg_T_1, 0, 0) node _state_reg_T_3 = eq(_state_reg_T_2, UInt<1>(0h0)) node _state_reg_T_4 = mux(state_reg_set_left_older_1, state_reg_left_subtree_state_1, _state_reg_T_3) node _state_reg_T_5 = bits(_state_reg_T, 0, 0) node _state_reg_T_6 = bits(_state_reg_T_5, 0, 0) node _state_reg_T_7 = eq(_state_reg_T_6, UInt<1>(0h0)) node _state_reg_T_8 = mux(state_reg_set_left_older_1, _state_reg_T_7, state_reg_right_subtree_state_1) node state_reg_hi = cat(state_reg_set_left_older_1, _state_reg_T_4) node _state_reg_T_9 = cat(state_reg_hi, _state_reg_T_8) node _state_reg_T_10 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_9) node _state_reg_T_11 = bits(state_reg_touch_way_sized, 1, 0) node _state_reg_set_left_older_T_2 = bits(_state_reg_T_11, 1, 1) node state_reg_set_left_older_2 = eq(_state_reg_set_left_older_T_2, UInt<1>(0h0)) node state_reg_left_subtree_state_2 = bits(state_reg_right_subtree_state, 1, 1) node state_reg_right_subtree_state_2 = bits(state_reg_right_subtree_state, 0, 0) node _state_reg_T_12 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_13 = bits(_state_reg_T_12, 0, 0) node _state_reg_T_14 = eq(_state_reg_T_13, UInt<1>(0h0)) node _state_reg_T_15 = mux(state_reg_set_left_older_2, state_reg_left_subtree_state_2, _state_reg_T_14) node _state_reg_T_16 = bits(_state_reg_T_11, 0, 0) node _state_reg_T_17 = bits(_state_reg_T_16, 0, 0) node _state_reg_T_18 = eq(_state_reg_T_17, UInt<1>(0h0)) node _state_reg_T_19 = mux(state_reg_set_left_older_2, _state_reg_T_18, state_reg_right_subtree_state_2) node state_reg_hi_1 = cat(state_reg_set_left_older_2, _state_reg_T_15) node _state_reg_T_20 = cat(state_reg_hi_1, _state_reg_T_19) node _state_reg_T_21 = mux(state_reg_set_left_older, _state_reg_T_20, state_reg_right_subtree_state) node state_reg_hi_2 = cat(state_reg_set_left_older, _state_reg_T_10) node _state_reg_T_22 = cat(state_reg_hi_2, _state_reg_T_21) connect state_reg, _state_reg_T_22 node _T_27 = eq(state, UInt<3>(0h1)) node _T_28 = and(pte_cache_hit, _T_27) when _T_28 : node hi = bits(hits, 7, 4) node lo = bits(hits, 3, 0) node _T_29 = orr(hi) node _T_30 = or(hi, lo) node hi_1 = bits(_T_30, 3, 2) node lo_1 = bits(_T_30, 1, 0) node _T_31 = orr(hi_1) node _T_32 = or(hi_1, lo_1) node _T_33 = bits(_T_32, 1, 1) node _T_34 = cat(_T_31, _T_33) node _T_35 = cat(_T_29, _T_34) node state_reg_touch_way_sized_1 = bits(_T_35, 2, 0) node _state_reg_set_left_older_T_3 = bits(state_reg_touch_way_sized_1, 2, 2) node state_reg_set_left_older_3 = eq(_state_reg_set_left_older_T_3, UInt<1>(0h0)) node state_reg_left_subtree_state_3 = bits(state_reg, 5, 3) node state_reg_right_subtree_state_3 = bits(state_reg, 2, 0) node _state_reg_T_23 = bits(state_reg_touch_way_sized_1, 1, 0) node _state_reg_set_left_older_T_4 = bits(_state_reg_T_23, 1, 1) node state_reg_set_left_older_4 = eq(_state_reg_set_left_older_T_4, UInt<1>(0h0)) node state_reg_left_subtree_state_4 = bits(state_reg_left_subtree_state_3, 1, 1) node state_reg_right_subtree_state_4 = bits(state_reg_left_subtree_state_3, 0, 0) node _state_reg_T_24 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_25 = bits(_state_reg_T_24, 0, 0) node _state_reg_T_26 = eq(_state_reg_T_25, UInt<1>(0h0)) node _state_reg_T_27 = mux(state_reg_set_left_older_4, state_reg_left_subtree_state_4, _state_reg_T_26) node _state_reg_T_28 = bits(_state_reg_T_23, 0, 0) node _state_reg_T_29 = bits(_state_reg_T_28, 0, 0) node _state_reg_T_30 = eq(_state_reg_T_29, UInt<1>(0h0)) node _state_reg_T_31 = mux(state_reg_set_left_older_4, _state_reg_T_30, state_reg_right_subtree_state_4) node state_reg_hi_3 = cat(state_reg_set_left_older_4, _state_reg_T_27) node _state_reg_T_32 = cat(state_reg_hi_3, _state_reg_T_31) node _state_reg_T_33 = mux(state_reg_set_left_older_3, state_reg_left_subtree_state_3, _state_reg_T_32) node _state_reg_T_34 = bits(state_reg_touch_way_sized_1, 1, 0) node _state_reg_set_left_older_T_5 = bits(_state_reg_T_34, 1, 1) node state_reg_set_left_older_5 = eq(_state_reg_set_left_older_T_5, UInt<1>(0h0)) node state_reg_left_subtree_state_5 = bits(state_reg_right_subtree_state_3, 1, 1) node state_reg_right_subtree_state_5 = bits(state_reg_right_subtree_state_3, 0, 0) node _state_reg_T_35 = bits(_state_reg_T_34, 0, 0) node _state_reg_T_36 = bits(_state_reg_T_35, 0, 0) node _state_reg_T_37 = eq(_state_reg_T_36, UInt<1>(0h0)) node _state_reg_T_38 = mux(state_reg_set_left_older_5, state_reg_left_subtree_state_5, _state_reg_T_37) node _state_reg_T_39 = bits(_state_reg_T_34, 0, 0) node _state_reg_T_40 = bits(_state_reg_T_39, 0, 0) node _state_reg_T_41 = eq(_state_reg_T_40, UInt<1>(0h0)) node _state_reg_T_42 = mux(state_reg_set_left_older_5, _state_reg_T_41, state_reg_right_subtree_state_5) node state_reg_hi_4 = cat(state_reg_set_left_older_5, _state_reg_T_38) node _state_reg_T_43 = cat(state_reg_hi_4, _state_reg_T_42) node _state_reg_T_44 = mux(state_reg_set_left_older_3, _state_reg_T_43, state_reg_right_subtree_state_3) node state_reg_hi_5 = cat(state_reg_set_left_older_3, _state_reg_T_33) node _state_reg_T_45 = cat(state_reg_hi_5, _state_reg_T_44) connect state_reg, _state_reg_T_45 node _T_36 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) node _T_37 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _T_38 = or(_T_36, _T_37) node _T_39 = and(io.dpath.sfence.valid, _T_38) when _T_39 : connect valid, UInt<1>(0h0) node _T_40 = eq(state, UInt<3>(0h1)) node _T_41 = and(pte_cache_hit, _T_40) node _T_42 = eq(count, UInt<1>(0h0)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(state, UInt<3>(0h1)) node _T_45 = and(pte_cache_hit, _T_44) node _T_46 = eq(count, UInt<1>(0h1)) node _T_47 = and(_T_45, _T_46) node _T_48 = bits(hits, 0, 0) node _T_49 = bits(hits, 1, 1) node _T_50 = bits(hits, 2, 2) node _T_51 = bits(hits, 3, 3) node _T_52 = bits(hits, 4, 4) node _T_53 = bits(hits, 5, 5) node _T_54 = bits(hits, 6, 6) node _T_55 = bits(hits, 7, 7) node _T_56 = mux(_T_48, data[0], UInt<1>(0h0)) node _T_57 = mux(_T_49, data[1], UInt<1>(0h0)) node _T_58 = mux(_T_50, data[2], UInt<1>(0h0)) node _T_59 = mux(_T_51, data[3], UInt<1>(0h0)) node _T_60 = mux(_T_52, data[4], UInt<1>(0h0)) node _T_61 = mux(_T_53, data[5], UInt<1>(0h0)) node _T_62 = mux(_T_54, data[6], UInt<1>(0h0)) node _T_63 = mux(_T_55, data[7], UInt<1>(0h0)) node _T_64 = or(_T_56, _T_57) node _T_65 = or(_T_64, _T_58) node _T_66 = or(_T_65, _T_59) node _T_67 = or(_T_66, _T_60) node _T_68 = or(_T_67, _T_61) node _T_69 = or(_T_68, _T_62) node _T_70 = or(_T_69, _T_63) wire pte_cache_data : UInt<20> connect pte_cache_data, _T_70 regreset state_reg_1 : UInt<7>, clock, reset, UInt<7>(0h0) regreset valid_1 : UInt<8>, clock, reset, UInt<8>(0h0) reg tags_1 : UInt<32>[8], clock reg data_1 : UInt<20>[8], clock node _can_hit_T_3 = eq(count, r_hgatp_initial_count) node _can_hit_T_4 = lt(aux_count, UInt<2>(0h2)) node _can_hit_T_5 = and(_can_hit_T_3, _can_hit_T_4) node _can_hit_T_6 = and(_can_hit_T_5, r_req.vstage1) node _can_hit_T_7 = and(_can_hit_T_6, stage2) node _can_hit_T_8 = eq(stage2_final, UInt<1>(0h0)) node can_hit_1 = and(_can_hit_T_7, _can_hit_T_8) node _can_refill_T = eq(stage2, UInt<1>(0h0)) node _can_refill_T_1 = and(do_both_stages, _can_refill_T) node _can_refill_T_2 = eq(stage2_final, UInt<1>(0h0)) node can_refill = and(_can_refill_T_1, _can_refill_T_2) node _tag_T = cat(UInt<38>(0h0), UInt<1>(0h0)) node tag_1 = cat(UInt<1>(0h1), _tag_T) node _hits_T_9 = eq(tags_1[0], tag_1) node _hits_T_10 = eq(tags_1[1], tag_1) node _hits_T_11 = eq(tags_1[2], tag_1) node _hits_T_12 = eq(tags_1[3], tag_1) node _hits_T_13 = eq(tags_1[4], tag_1) node _hits_T_14 = eq(tags_1[5], tag_1) node _hits_T_15 = eq(tags_1[6], tag_1) node _hits_T_16 = eq(tags_1[7], tag_1) node hits_lo_lo_1 = cat(_hits_T_10, _hits_T_9) node hits_lo_hi_1 = cat(_hits_T_12, _hits_T_11) node hits_lo_1 = cat(hits_lo_hi_1, hits_lo_lo_1) node hits_hi_lo_1 = cat(_hits_T_14, _hits_T_13) node hits_hi_hi_1 = cat(_hits_T_16, _hits_T_15) node hits_hi_1 = cat(hits_hi_hi_1, hits_hi_lo_1) node _hits_T_17 = cat(hits_hi_1, hits_lo_1) node hits_1 = and(_hits_T_17, valid_1) node _hit_T_1 = orr(hits_1) node stage2_pte_cache_hit = and(_hit_T_1, can_hit_1) node _T_71 = and(mem_resp_valid, traverse) node _T_72 = and(_T_71, can_refill) node _T_73 = orr(hits_1) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = and(_T_72, _T_74) node _T_76 = eq(invalidated, UInt<1>(0h0)) node _T_77 = and(_T_75, _T_76) when _T_77 : node _r_T_27 = andr(valid_1) node r_left_subtree_older_3 = bits(state_reg_1, 6, 6) node r_left_subtree_state_3 = bits(state_reg_1, 5, 3) node r_right_subtree_state_3 = bits(state_reg_1, 2, 0) node r_left_subtree_older_4 = bits(r_left_subtree_state_3, 2, 2) node r_left_subtree_state_4 = bits(r_left_subtree_state_3, 1, 1) node r_right_subtree_state_4 = bits(r_left_subtree_state_3, 0, 0) node _r_T_28 = bits(r_left_subtree_state_4, 0, 0) node _r_T_29 = bits(r_right_subtree_state_4, 0, 0) node _r_T_30 = mux(r_left_subtree_older_4, _r_T_28, _r_T_29) node _r_T_31 = cat(r_left_subtree_older_4, _r_T_30) node r_left_subtree_older_5 = bits(r_right_subtree_state_3, 2, 2) node r_left_subtree_state_5 = bits(r_right_subtree_state_3, 1, 1) node r_right_subtree_state_5 = bits(r_right_subtree_state_3, 0, 0) node _r_T_32 = bits(r_left_subtree_state_5, 0, 0) node _r_T_33 = bits(r_right_subtree_state_5, 0, 0) node _r_T_34 = mux(r_left_subtree_older_5, _r_T_32, _r_T_33) node _r_T_35 = cat(r_left_subtree_older_5, _r_T_34) node _r_T_36 = mux(r_left_subtree_older_3, _r_T_31, _r_T_35) node _r_T_37 = cat(r_left_subtree_older_3, _r_T_36) node _r_T_38 = not(valid_1) node _r_T_39 = bits(_r_T_38, 0, 0) node _r_T_40 = bits(_r_T_38, 1, 1) node _r_T_41 = bits(_r_T_38, 2, 2) node _r_T_42 = bits(_r_T_38, 3, 3) node _r_T_43 = bits(_r_T_38, 4, 4) node _r_T_44 = bits(_r_T_38, 5, 5) node _r_T_45 = bits(_r_T_38, 6, 6) node _r_T_46 = bits(_r_T_38, 7, 7) node _r_T_47 = mux(_r_T_45, UInt<3>(0h6), UInt<3>(0h7)) node _r_T_48 = mux(_r_T_44, UInt<3>(0h5), _r_T_47) node _r_T_49 = mux(_r_T_43, UInt<3>(0h4), _r_T_48) node _r_T_50 = mux(_r_T_42, UInt<2>(0h3), _r_T_49) node _r_T_51 = mux(_r_T_41, UInt<2>(0h2), _r_T_50) node _r_T_52 = mux(_r_T_40, UInt<1>(0h1), _r_T_51) node _r_T_53 = mux(_r_T_39, UInt<1>(0h0), _r_T_52) node r_1 = mux(_r_T_27, _r_T_37, _r_T_53) node _valid_T_2 = dshl(UInt<1>(0h1), r_1) node _valid_T_3 = or(valid_1, _valid_T_2) connect valid_1, _valid_T_3 connect tags_1[r_1], tag_1 connect data_1[r_1], pte.ppn node state_reg_touch_way_sized_2 = bits(r_1, 2, 0) node _state_reg_set_left_older_T_6 = bits(state_reg_touch_way_sized_2, 2, 2) node state_reg_set_left_older_6 = eq(_state_reg_set_left_older_T_6, UInt<1>(0h0)) node state_reg_left_subtree_state_6 = bits(state_reg_1, 5, 3) node state_reg_right_subtree_state_6 = bits(state_reg_1, 2, 0) node _state_reg_T_46 = bits(state_reg_touch_way_sized_2, 1, 0) node _state_reg_set_left_older_T_7 = bits(_state_reg_T_46, 1, 1) node state_reg_set_left_older_7 = eq(_state_reg_set_left_older_T_7, UInt<1>(0h0)) node state_reg_left_subtree_state_7 = bits(state_reg_left_subtree_state_6, 1, 1) node state_reg_right_subtree_state_7 = bits(state_reg_left_subtree_state_6, 0, 0) node _state_reg_T_47 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_48 = bits(_state_reg_T_47, 0, 0) node _state_reg_T_49 = eq(_state_reg_T_48, UInt<1>(0h0)) node _state_reg_T_50 = mux(state_reg_set_left_older_7, state_reg_left_subtree_state_7, _state_reg_T_49) node _state_reg_T_51 = bits(_state_reg_T_46, 0, 0) node _state_reg_T_52 = bits(_state_reg_T_51, 0, 0) node _state_reg_T_53 = eq(_state_reg_T_52, UInt<1>(0h0)) node _state_reg_T_54 = mux(state_reg_set_left_older_7, _state_reg_T_53, state_reg_right_subtree_state_7) node state_reg_hi_6 = cat(state_reg_set_left_older_7, _state_reg_T_50) node _state_reg_T_55 = cat(state_reg_hi_6, _state_reg_T_54) node _state_reg_T_56 = mux(state_reg_set_left_older_6, state_reg_left_subtree_state_6, _state_reg_T_55) node _state_reg_T_57 = bits(state_reg_touch_way_sized_2, 1, 0) node _state_reg_set_left_older_T_8 = bits(_state_reg_T_57, 1, 1) node state_reg_set_left_older_8 = eq(_state_reg_set_left_older_T_8, UInt<1>(0h0)) node state_reg_left_subtree_state_8 = bits(state_reg_right_subtree_state_6, 1, 1) node state_reg_right_subtree_state_8 = bits(state_reg_right_subtree_state_6, 0, 0) node _state_reg_T_58 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_59 = bits(_state_reg_T_58, 0, 0) node _state_reg_T_60 = eq(_state_reg_T_59, UInt<1>(0h0)) node _state_reg_T_61 = mux(state_reg_set_left_older_8, state_reg_left_subtree_state_8, _state_reg_T_60) node _state_reg_T_62 = bits(_state_reg_T_57, 0, 0) node _state_reg_T_63 = bits(_state_reg_T_62, 0, 0) node _state_reg_T_64 = eq(_state_reg_T_63, UInt<1>(0h0)) node _state_reg_T_65 = mux(state_reg_set_left_older_8, _state_reg_T_64, state_reg_right_subtree_state_8) node state_reg_hi_7 = cat(state_reg_set_left_older_8, _state_reg_T_61) node _state_reg_T_66 = cat(state_reg_hi_7, _state_reg_T_65) node _state_reg_T_67 = mux(state_reg_set_left_older_6, _state_reg_T_66, state_reg_right_subtree_state_6) node state_reg_hi_8 = cat(state_reg_set_left_older_6, _state_reg_T_56) node _state_reg_T_68 = cat(state_reg_hi_8, _state_reg_T_67) connect state_reg_1, _state_reg_T_68 node _T_78 = eq(state, UInt<3>(0h1)) node _T_79 = and(stage2_pte_cache_hit, _T_78) when _T_79 : node hi_2 = bits(hits_1, 7, 4) node lo_2 = bits(hits_1, 3, 0) node _T_80 = orr(hi_2) node _T_81 = or(hi_2, lo_2) node hi_3 = bits(_T_81, 3, 2) node lo_3 = bits(_T_81, 1, 0) node _T_82 = orr(hi_3) node _T_83 = or(hi_3, lo_3) node _T_84 = bits(_T_83, 1, 1) node _T_85 = cat(_T_82, _T_84) node _T_86 = cat(_T_80, _T_85) node state_reg_touch_way_sized_3 = bits(_T_86, 2, 0) node _state_reg_set_left_older_T_9 = bits(state_reg_touch_way_sized_3, 2, 2) node state_reg_set_left_older_9 = eq(_state_reg_set_left_older_T_9, UInt<1>(0h0)) node state_reg_left_subtree_state_9 = bits(state_reg_1, 5, 3) node state_reg_right_subtree_state_9 = bits(state_reg_1, 2, 0) node _state_reg_T_69 = bits(state_reg_touch_way_sized_3, 1, 0) node _state_reg_set_left_older_T_10 = bits(_state_reg_T_69, 1, 1) node state_reg_set_left_older_10 = eq(_state_reg_set_left_older_T_10, UInt<1>(0h0)) node state_reg_left_subtree_state_10 = bits(state_reg_left_subtree_state_9, 1, 1) node state_reg_right_subtree_state_10 = bits(state_reg_left_subtree_state_9, 0, 0) node _state_reg_T_70 = bits(_state_reg_T_69, 0, 0) node _state_reg_T_71 = bits(_state_reg_T_70, 0, 0) node _state_reg_T_72 = eq(_state_reg_T_71, UInt<1>(0h0)) node _state_reg_T_73 = mux(state_reg_set_left_older_10, state_reg_left_subtree_state_10, _state_reg_T_72) node _state_reg_T_74 = bits(_state_reg_T_69, 0, 0) node _state_reg_T_75 = bits(_state_reg_T_74, 0, 0) node _state_reg_T_76 = eq(_state_reg_T_75, UInt<1>(0h0)) node _state_reg_T_77 = mux(state_reg_set_left_older_10, _state_reg_T_76, state_reg_right_subtree_state_10) node state_reg_hi_9 = cat(state_reg_set_left_older_10, _state_reg_T_73) node _state_reg_T_78 = cat(state_reg_hi_9, _state_reg_T_77) node _state_reg_T_79 = mux(state_reg_set_left_older_9, state_reg_left_subtree_state_9, _state_reg_T_78) node _state_reg_T_80 = bits(state_reg_touch_way_sized_3, 1, 0) node _state_reg_set_left_older_T_11 = bits(_state_reg_T_80, 1, 1) node state_reg_set_left_older_11 = eq(_state_reg_set_left_older_T_11, UInt<1>(0h0)) node state_reg_left_subtree_state_11 = bits(state_reg_right_subtree_state_9, 1, 1) node state_reg_right_subtree_state_11 = bits(state_reg_right_subtree_state_9, 0, 0) node _state_reg_T_81 = bits(_state_reg_T_80, 0, 0) node _state_reg_T_82 = bits(_state_reg_T_81, 0, 0) node _state_reg_T_83 = eq(_state_reg_T_82, UInt<1>(0h0)) node _state_reg_T_84 = mux(state_reg_set_left_older_11, state_reg_left_subtree_state_11, _state_reg_T_83) node _state_reg_T_85 = bits(_state_reg_T_80, 0, 0) node _state_reg_T_86 = bits(_state_reg_T_85, 0, 0) node _state_reg_T_87 = eq(_state_reg_T_86, UInt<1>(0h0)) node _state_reg_T_88 = mux(state_reg_set_left_older_11, _state_reg_T_87, state_reg_right_subtree_state_11) node state_reg_hi_10 = cat(state_reg_set_left_older_11, _state_reg_T_84) node _state_reg_T_89 = cat(state_reg_hi_10, _state_reg_T_88) node _state_reg_T_90 = mux(state_reg_set_left_older_9, _state_reg_T_89, state_reg_right_subtree_state_9) node state_reg_hi_11 = cat(state_reg_set_left_older_9, _state_reg_T_79) node _state_reg_T_91 = cat(state_reg_hi_11, _state_reg_T_90) connect state_reg_1, _state_reg_T_91 node _T_87 = eq(io.dpath.sfence.bits.rs1, UInt<1>(0h0)) node _T_88 = and(UInt<1>(0h0), io.dpath.sfence.bits.hg) node _T_89 = or(_T_87, _T_88) node _T_90 = and(io.dpath.sfence.valid, _T_89) when _T_90 : connect valid_1, UInt<1>(0h0) node _T_91 = eq(state, UInt<3>(0h1)) node _T_92 = and(stage2_pte_cache_hit, _T_91) node _T_93 = eq(aux_count, UInt<1>(0h0)) node _T_94 = and(_T_92, _T_93) node _T_95 = eq(state, UInt<3>(0h1)) node _T_96 = and(stage2_pte_cache_hit, _T_95) node _T_97 = eq(aux_count, UInt<1>(0h1)) node _T_98 = and(_T_96, _T_97) node _T_99 = bits(hits_1, 0, 0) node _T_100 = bits(hits_1, 1, 1) node _T_101 = bits(hits_1, 2, 2) node _T_102 = bits(hits_1, 3, 3) node _T_103 = bits(hits_1, 4, 4) node _T_104 = bits(hits_1, 5, 5) node _T_105 = bits(hits_1, 6, 6) node _T_106 = bits(hits_1, 7, 7) node _T_107 = mux(_T_99, data_1[0], UInt<1>(0h0)) node _T_108 = mux(_T_100, data_1[1], UInt<1>(0h0)) node _T_109 = mux(_T_101, data_1[2], UInt<1>(0h0)) node _T_110 = mux(_T_102, data_1[3], UInt<1>(0h0)) node _T_111 = mux(_T_103, data_1[4], UInt<1>(0h0)) node _T_112 = mux(_T_104, data_1[5], UInt<1>(0h0)) node _T_113 = mux(_T_105, data_1[6], UInt<1>(0h0)) node _T_114 = mux(_T_106, data_1[7], UInt<1>(0h0)) node _T_115 = or(_T_107, _T_108) node _T_116 = or(_T_115, _T_109) node _T_117 = or(_T_116, _T_110) node _T_118 = or(_T_117, _T_111) node _T_119 = or(_T_118, _T_112) node _T_120 = or(_T_119, _T_113) node _T_121 = or(_T_120, _T_114) wire stage2_pte_cache_data : UInt<20> connect stage2_pte_cache_data, _T_121 reg pte_hit : UInt<1>, clock connect pte_hit, UInt<1>(0h0) connect io.dpath.perf.pte_miss, UInt<1>(0h0) node _io_dpath_perf_pte_hit_T = eq(state, UInt<3>(0h1)) node _io_dpath_perf_pte_hit_T_1 = and(pte_hit, _io_dpath_perf_pte_hit_T) node _io_dpath_perf_pte_hit_T_2 = eq(io.dpath.perf.l2hit, UInt<1>(0h0)) node _io_dpath_perf_pte_hit_T_3 = and(_io_dpath_perf_pte_hit_T_1, _io_dpath_perf_pte_hit_T_2) connect io.dpath.perf.pte_hit, _io_dpath_perf_pte_hit_T_3 node _T_122 = or(io.dpath.perf.pte_miss, io.dpath.perf.pte_hit) node _T_123 = and(io.dpath.perf.l2hit, _T_122) node _T_124 = eq(_T_123, UInt<1>(0h0)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: PTE Cache Hit/Miss Performance Monitor Events are lower priority than L2TLB Hit event\n at PTW.scala:395 assert(!(io.dpath.perf.l2hit && (io.dpath.perf.pte_miss || io.dpath.perf.pte_hit)),\n") : printf assert(clock, _T_124, UInt<1>(0h1), "") : assert reg l2_refill : UInt<1>, clock connect l2_refill, UInt<1>(0h0) connect l2_refill_wire, l2_refill connect io.dpath.perf.l2miss, UInt<1>(0h0) connect io.dpath.perf.l2hit, UInt<1>(0h0) wire _WIRE_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect _WIRE_1.v, UInt<1>(0h0) connect _WIRE_1.r, UInt<1>(0h0) connect _WIRE_1.w, UInt<1>(0h0) connect _WIRE_1.x, UInt<1>(0h0) connect _WIRE_1.u, UInt<1>(0h0) connect _WIRE_1.g, UInt<1>(0h0) connect _WIRE_1.a, UInt<1>(0h0) connect _WIRE_1.d, UInt<1>(0h0) connect _WIRE_1.reserved_for_software, UInt<2>(0h0) connect _WIRE_1.ppn, UInt<44>(0h0) connect _WIRE_1.reserved_for_future, UInt<10>(0h0) wire l2_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect l2_pte, _WIRE_1 node _invalidated_T = neq(state, UInt<3>(0h0)) node _invalidated_T_1 = and(invalidated, _invalidated_T) node _invalidated_T_2 = or(io.dpath.sfence.valid, _invalidated_T_1) connect invalidated, _invalidated_T_2 connect io.mem.keep_clock_enabled, UInt<1>(0h0) node _io_mem_req_valid_T = eq(state, UInt<3>(0h1)) node _io_mem_req_valid_T_1 = eq(state, UInt<3>(0h3)) node _io_mem_req_valid_T_2 = or(_io_mem_req_valid_T, _io_mem_req_valid_T_1) connect io.mem.req.valid, _io_mem_req_valid_T_2 connect io.mem.req.bits.phys, UInt<1>(0h1) connect io.mem.req.bits.cmd, UInt<1>(0h0) connect io.mem.req.bits.size, UInt<2>(0h3) connect io.mem.req.bits.signed, UInt<1>(0h0) connect io.mem.req.bits.addr, pte_addr connect io.mem.req.bits.dprv, UInt<1>(0h1) node _io_mem_req_bits_dv_T = eq(stage2, UInt<1>(0h0)) node _io_mem_req_bits_dv_T_1 = and(do_both_stages, _io_mem_req_bits_dv_T) connect io.mem.req.bits.dv, _io_mem_req_bits_dv_T_1 invalidate io.mem.req.bits.tag connect io.mem.req.bits.no_resp, UInt<1>(0h0) invalidate io.mem.req.bits.no_alloc invalidate io.mem.req.bits.no_xcpt invalidate io.mem.req.bits.data invalidate io.mem.req.bits.mask node _io_mem_s1_kill_T = neq(state, UInt<3>(0h2)) node _io_mem_s1_kill_T_1 = or(UInt<1>(0h0), _io_mem_s1_kill_T) node _io_mem_s1_kill_T_2 = or(_io_mem_s1_kill_T_1, resp_gf) connect io.mem.s1_kill, _io_mem_s1_kill_T_2 invalidate io.mem.s1_data.mask invalidate io.mem.s1_data.data connect io.mem.s2_kill, UInt<1>(0h0) node _pmaPgLevelHomogeneous_T = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_3 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_5 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_6 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_7 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_8 = xor(_pmaPgLevelHomogeneous_T_7, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_9 = cvt(_pmaPgLevelHomogeneous_T_8) node _pmaPgLevelHomogeneous_T_10 = and(_pmaPgLevelHomogeneous_T_9, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_11 = asSInt(_pmaPgLevelHomogeneous_T_10) node _pmaPgLevelHomogeneous_T_12 = eq(_pmaPgLevelHomogeneous_T_11, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_13 = xor(_pmaPgLevelHomogeneous_T_7, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_14 = cvt(_pmaPgLevelHomogeneous_T_13) node _pmaPgLevelHomogeneous_T_15 = and(_pmaPgLevelHomogeneous_T_14, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_16 = asSInt(_pmaPgLevelHomogeneous_T_15) node _pmaPgLevelHomogeneous_T_17 = eq(_pmaPgLevelHomogeneous_T_16, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_18 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_12) node pmaPgLevelHomogeneous_1 = or(_pmaPgLevelHomogeneous_T_18, _pmaPgLevelHomogeneous_T_17) node _pmaPgLevelHomogeneous_T_19 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_20 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_21 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_22 = cvt(_pmaPgLevelHomogeneous_T_21) node _pmaPgLevelHomogeneous_T_23 = and(_pmaPgLevelHomogeneous_T_22, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_24 = asSInt(_pmaPgLevelHomogeneous_T_23) node _pmaPgLevelHomogeneous_T_25 = eq(_pmaPgLevelHomogeneous_T_24, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_26 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_25) node _pmaPgLevelHomogeneous_T_27 = eq(_pmaPgLevelHomogeneous_T_26, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_28 = xor(_pmaPgLevelHomogeneous_T_7, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_29 = cvt(_pmaPgLevelHomogeneous_T_28) node _pmaPgLevelHomogeneous_T_30 = and(_pmaPgLevelHomogeneous_T_29, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_31 = asSInt(_pmaPgLevelHomogeneous_T_30) node _pmaPgLevelHomogeneous_T_32 = eq(_pmaPgLevelHomogeneous_T_31, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_33 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_32) node _pmaPgLevelHomogeneous_T_34 = eq(_pmaPgLevelHomogeneous_T_33, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_36 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_37 = shl(r_pte.ppn, 12) node _pmaPgLevelHomogeneous_T_38 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_39 = cvt(_pmaPgLevelHomogeneous_T_38) node _pmaPgLevelHomogeneous_T_40 = and(_pmaPgLevelHomogeneous_T_39, asSInt(UInt<14>(0h2000))) node _pmaPgLevelHomogeneous_T_41 = asSInt(_pmaPgLevelHomogeneous_T_40) node _pmaPgLevelHomogeneous_T_42 = eq(_pmaPgLevelHomogeneous_T_41, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_43 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_44 = cvt(_pmaPgLevelHomogeneous_T_43) node _pmaPgLevelHomogeneous_T_45 = and(_pmaPgLevelHomogeneous_T_44, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_46 = asSInt(_pmaPgLevelHomogeneous_T_45) node _pmaPgLevelHomogeneous_T_47 = eq(_pmaPgLevelHomogeneous_T_46, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_48 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_49 = cvt(_pmaPgLevelHomogeneous_T_48) node _pmaPgLevelHomogeneous_T_50 = and(_pmaPgLevelHomogeneous_T_49, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_51 = asSInt(_pmaPgLevelHomogeneous_T_50) node _pmaPgLevelHomogeneous_T_52 = eq(_pmaPgLevelHomogeneous_T_51, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_53 = xor(_pmaPgLevelHomogeneous_T_37, UInt<21>(0h100000)) node _pmaPgLevelHomogeneous_T_54 = cvt(_pmaPgLevelHomogeneous_T_53) node _pmaPgLevelHomogeneous_T_55 = and(_pmaPgLevelHomogeneous_T_54, asSInt(UInt<18>(0h2f000))) node _pmaPgLevelHomogeneous_T_56 = asSInt(_pmaPgLevelHomogeneous_T_55) node _pmaPgLevelHomogeneous_T_57 = eq(_pmaPgLevelHomogeneous_T_56, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_58 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2000000)) node _pmaPgLevelHomogeneous_T_59 = cvt(_pmaPgLevelHomogeneous_T_58) node _pmaPgLevelHomogeneous_T_60 = and(_pmaPgLevelHomogeneous_T_59, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_61 = asSInt(_pmaPgLevelHomogeneous_T_60) node _pmaPgLevelHomogeneous_T_62 = eq(_pmaPgLevelHomogeneous_T_61, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_63 = xor(_pmaPgLevelHomogeneous_T_37, UInt<26>(0h2010000)) node _pmaPgLevelHomogeneous_T_64 = cvt(_pmaPgLevelHomogeneous_T_63) node _pmaPgLevelHomogeneous_T_65 = and(_pmaPgLevelHomogeneous_T_64, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_66 = asSInt(_pmaPgLevelHomogeneous_T_65) node _pmaPgLevelHomogeneous_T_67 = eq(_pmaPgLevelHomogeneous_T_66, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_68 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_69 = cvt(_pmaPgLevelHomogeneous_T_68) node _pmaPgLevelHomogeneous_T_70 = and(_pmaPgLevelHomogeneous_T_69, asSInt(UInt<17>(0h10000))) node _pmaPgLevelHomogeneous_T_71 = asSInt(_pmaPgLevelHomogeneous_T_70) node _pmaPgLevelHomogeneous_T_72 = eq(_pmaPgLevelHomogeneous_T_71, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_73 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0hc000000)) node _pmaPgLevelHomogeneous_T_74 = cvt(_pmaPgLevelHomogeneous_T_73) node _pmaPgLevelHomogeneous_T_75 = and(_pmaPgLevelHomogeneous_T_74, asSInt(UInt<27>(0h4000000))) node _pmaPgLevelHomogeneous_T_76 = asSInt(_pmaPgLevelHomogeneous_T_75) node _pmaPgLevelHomogeneous_T_77 = eq(_pmaPgLevelHomogeneous_T_76, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_78 = xor(_pmaPgLevelHomogeneous_T_37, UInt<29>(0h10020000)) node _pmaPgLevelHomogeneous_T_79 = cvt(_pmaPgLevelHomogeneous_T_78) node _pmaPgLevelHomogeneous_T_80 = and(_pmaPgLevelHomogeneous_T_79, asSInt(UInt<13>(0h1000))) node _pmaPgLevelHomogeneous_T_81 = asSInt(_pmaPgLevelHomogeneous_T_80) node _pmaPgLevelHomogeneous_T_82 = eq(_pmaPgLevelHomogeneous_T_81, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_83 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_84 = cvt(_pmaPgLevelHomogeneous_T_83) node _pmaPgLevelHomogeneous_T_85 = and(_pmaPgLevelHomogeneous_T_84, asSInt(UInt<29>(0h10000000))) node _pmaPgLevelHomogeneous_T_86 = asSInt(_pmaPgLevelHomogeneous_T_85) node _pmaPgLevelHomogeneous_T_87 = eq(_pmaPgLevelHomogeneous_T_86, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_88 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_42) node _pmaPgLevelHomogeneous_T_89 = or(_pmaPgLevelHomogeneous_T_88, _pmaPgLevelHomogeneous_T_47) node _pmaPgLevelHomogeneous_T_90 = or(_pmaPgLevelHomogeneous_T_89, _pmaPgLevelHomogeneous_T_52) node _pmaPgLevelHomogeneous_T_91 = or(_pmaPgLevelHomogeneous_T_90, _pmaPgLevelHomogeneous_T_57) node _pmaPgLevelHomogeneous_T_92 = or(_pmaPgLevelHomogeneous_T_91, _pmaPgLevelHomogeneous_T_62) node _pmaPgLevelHomogeneous_T_93 = or(_pmaPgLevelHomogeneous_T_92, _pmaPgLevelHomogeneous_T_67) node _pmaPgLevelHomogeneous_T_94 = or(_pmaPgLevelHomogeneous_T_93, _pmaPgLevelHomogeneous_T_72) node _pmaPgLevelHomogeneous_T_95 = or(_pmaPgLevelHomogeneous_T_94, _pmaPgLevelHomogeneous_T_77) node _pmaPgLevelHomogeneous_T_96 = or(_pmaPgLevelHomogeneous_T_95, _pmaPgLevelHomogeneous_T_82) node pmaPgLevelHomogeneous_2 = or(_pmaPgLevelHomogeneous_T_96, _pmaPgLevelHomogeneous_T_87) node _pmaPgLevelHomogeneous_T_97 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_98 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_99 = cvt(_pmaPgLevelHomogeneous_T_98) node _pmaPgLevelHomogeneous_T_100 = and(_pmaPgLevelHomogeneous_T_99, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_101 = asSInt(_pmaPgLevelHomogeneous_T_100) node _pmaPgLevelHomogeneous_T_102 = eq(_pmaPgLevelHomogeneous_T_101, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_103 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_102) node _pmaPgLevelHomogeneous_T_104 = eq(_pmaPgLevelHomogeneous_T_103, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_105 = xor(_pmaPgLevelHomogeneous_T_37, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_106 = cvt(_pmaPgLevelHomogeneous_T_105) node _pmaPgLevelHomogeneous_T_107 = and(_pmaPgLevelHomogeneous_T_106, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_108 = asSInt(_pmaPgLevelHomogeneous_T_107) node _pmaPgLevelHomogeneous_T_109 = eq(_pmaPgLevelHomogeneous_T_108, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_110 = xor(_pmaPgLevelHomogeneous_T_37, UInt<14>(0h3000)) node _pmaPgLevelHomogeneous_T_111 = cvt(_pmaPgLevelHomogeneous_T_110) node _pmaPgLevelHomogeneous_T_112 = and(_pmaPgLevelHomogeneous_T_111, asSInt(UInt<33>(0h9e113000))) node _pmaPgLevelHomogeneous_T_113 = asSInt(_pmaPgLevelHomogeneous_T_112) node _pmaPgLevelHomogeneous_T_114 = eq(_pmaPgLevelHomogeneous_T_113, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_115 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_116 = cvt(_pmaPgLevelHomogeneous_T_115) node _pmaPgLevelHomogeneous_T_117 = and(_pmaPgLevelHomogeneous_T_116, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_118 = asSInt(_pmaPgLevelHomogeneous_T_117) node _pmaPgLevelHomogeneous_T_119 = eq(_pmaPgLevelHomogeneous_T_118, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_120 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_121 = cvt(_pmaPgLevelHomogeneous_T_120) node _pmaPgLevelHomogeneous_T_122 = and(_pmaPgLevelHomogeneous_T_121, asSInt(UInt<33>(0h9e110000))) node _pmaPgLevelHomogeneous_T_123 = asSInt(_pmaPgLevelHomogeneous_T_122) node _pmaPgLevelHomogeneous_T_124 = eq(_pmaPgLevelHomogeneous_T_123, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_125 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_126 = cvt(_pmaPgLevelHomogeneous_T_125) node _pmaPgLevelHomogeneous_T_127 = and(_pmaPgLevelHomogeneous_T_126, asSInt(UInt<33>(0h90000000))) node _pmaPgLevelHomogeneous_T_128 = asSInt(_pmaPgLevelHomogeneous_T_127) node _pmaPgLevelHomogeneous_T_129 = eq(_pmaPgLevelHomogeneous_T_128, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_130 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_109) node _pmaPgLevelHomogeneous_T_131 = or(_pmaPgLevelHomogeneous_T_130, _pmaPgLevelHomogeneous_T_114) node _pmaPgLevelHomogeneous_T_132 = or(_pmaPgLevelHomogeneous_T_131, _pmaPgLevelHomogeneous_T_119) node _pmaPgLevelHomogeneous_T_133 = or(_pmaPgLevelHomogeneous_T_132, _pmaPgLevelHomogeneous_T_124) node _pmaPgLevelHomogeneous_T_134 = or(_pmaPgLevelHomogeneous_T_133, _pmaPgLevelHomogeneous_T_129) node _pmaPgLevelHomogeneous_T_135 = xor(_pmaPgLevelHomogeneous_T_37, UInt<28>(0h8000000)) node _pmaPgLevelHomogeneous_T_136 = cvt(_pmaPgLevelHomogeneous_T_135) node _pmaPgLevelHomogeneous_T_137 = and(_pmaPgLevelHomogeneous_T_136, asSInt(UInt<33>(0h8e000000))) node _pmaPgLevelHomogeneous_T_138 = asSInt(_pmaPgLevelHomogeneous_T_137) node _pmaPgLevelHomogeneous_T_139 = eq(_pmaPgLevelHomogeneous_T_138, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_140 = xor(_pmaPgLevelHomogeneous_T_37, UInt<32>(0h80000000)) node _pmaPgLevelHomogeneous_T_141 = cvt(_pmaPgLevelHomogeneous_T_140) node _pmaPgLevelHomogeneous_T_142 = and(_pmaPgLevelHomogeneous_T_141, asSInt(UInt<33>(0h80000000))) node _pmaPgLevelHomogeneous_T_143 = asSInt(_pmaPgLevelHomogeneous_T_142) node _pmaPgLevelHomogeneous_T_144 = eq(_pmaPgLevelHomogeneous_T_143, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_145 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_139) node _pmaPgLevelHomogeneous_T_146 = or(_pmaPgLevelHomogeneous_T_145, _pmaPgLevelHomogeneous_T_144) node _pmaPgLevelHomogeneous_T_147 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_148 = cvt(_pmaPgLevelHomogeneous_T_147) node _pmaPgLevelHomogeneous_T_149 = and(_pmaPgLevelHomogeneous_T_148, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_150 = asSInt(_pmaPgLevelHomogeneous_T_149) node _pmaPgLevelHomogeneous_T_151 = eq(_pmaPgLevelHomogeneous_T_150, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_152 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_151) node _pmaPgLevelHomogeneous_T_153 = eq(_pmaPgLevelHomogeneous_T_152, UInt<1>(0h0)) node _pmaPgLevelHomogeneous_T_154 = xor(_pmaPgLevelHomogeneous_T_37, UInt<17>(0h10000)) node _pmaPgLevelHomogeneous_T_155 = cvt(_pmaPgLevelHomogeneous_T_154) node _pmaPgLevelHomogeneous_T_156 = and(_pmaPgLevelHomogeneous_T_155, asSInt(UInt<33>(0h8a110000))) node _pmaPgLevelHomogeneous_T_157 = asSInt(_pmaPgLevelHomogeneous_T_156) node _pmaPgLevelHomogeneous_T_158 = eq(_pmaPgLevelHomogeneous_T_157, asSInt(UInt<1>(0h0))) node _pmaPgLevelHomogeneous_T_159 = or(UInt<1>(0h0), _pmaPgLevelHomogeneous_T_158) node _pmaPgLevelHomogeneous_T_160 = eq(_pmaPgLevelHomogeneous_T_159, UInt<1>(0h0)) node _pmaHomogeneous_T = eq(count, UInt<1>(0h1)) node _pmaHomogeneous_T_1 = mux(_pmaHomogeneous_T, pmaPgLevelHomogeneous_1, UInt<1>(0h0)) node _pmaHomogeneous_T_2 = eq(count, UInt<2>(0h2)) node _pmaHomogeneous_T_3 = mux(_pmaHomogeneous_T_2, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_1) node _pmaHomogeneous_T_4 = eq(count, UInt<2>(0h3)) node pmaHomogeneous = mux(_pmaHomogeneous_T_4, pmaPgLevelHomogeneous_2, _pmaHomogeneous_T_3) node _pmpHomogeneous_T = shl(r_pte.ppn, 12) wire _pmpHomogeneous_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmpHomogeneous_WIRE.mask, UInt<32>(0h0) connect _pmpHomogeneous_WIRE.addr, UInt<30>(0h0) connect _pmpHomogeneous_WIRE.cfg.r, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.w, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.x, UInt<1>(0h0) connect _pmpHomogeneous_WIRE.cfg.a, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.res, UInt<2>(0h0) connect _pmpHomogeneous_WIRE.cfg.l, UInt<1>(0h0) node _pmpHomogeneous_T_1 = bits(io.dpath.pmp[0].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T = bits(io.dpath.pmp[0].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_1 = bits(io.dpath.pmp[0].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_2 = bits(io.dpath.pmp[0].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_3 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_4 = mux(_pmpHomogeneous_maskHomogeneous_T_3, _pmpHomogeneous_maskHomogeneous_T_1, _pmpHomogeneous_maskHomogeneous_T) node _pmpHomogeneous_maskHomogeneous_T_5 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_6 = mux(_pmpHomogeneous_maskHomogeneous_T_5, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_4) node _pmpHomogeneous_maskHomogeneous_T_7 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous = mux(_pmpHomogeneous_maskHomogeneous_T_7, _pmpHomogeneous_maskHomogeneous_T_2, _pmpHomogeneous_maskHomogeneous_T_6) node _pmpHomogeneous_T_2 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_3 = not(_pmpHomogeneous_T_2) node _pmpHomogeneous_T_4 = or(_pmpHomogeneous_T_3, UInt<2>(0h3)) node _pmpHomogeneous_T_5 = not(_pmpHomogeneous_T_4) node _pmpHomogeneous_T_6 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_5) node _pmpHomogeneous_T_7 = shr(_pmpHomogeneous_T_6, 30) node _pmpHomogeneous_T_8 = neq(_pmpHomogeneous_T_7, UInt<1>(0h0)) node _pmpHomogeneous_T_9 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_10 = not(_pmpHomogeneous_T_9) node _pmpHomogeneous_T_11 = or(_pmpHomogeneous_T_10, UInt<2>(0h3)) node _pmpHomogeneous_T_12 = not(_pmpHomogeneous_T_11) node _pmpHomogeneous_T_13 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_12) node _pmpHomogeneous_T_14 = shr(_pmpHomogeneous_T_13, 21) node _pmpHomogeneous_T_15 = neq(_pmpHomogeneous_T_14, UInt<1>(0h0)) node _pmpHomogeneous_T_16 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_T_17 = not(_pmpHomogeneous_T_16) node _pmpHomogeneous_T_18 = or(_pmpHomogeneous_T_17, UInt<2>(0h3)) node _pmpHomogeneous_T_19 = not(_pmpHomogeneous_T_18) node _pmpHomogeneous_T_20 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_19) node _pmpHomogeneous_T_21 = shr(_pmpHomogeneous_T_20, 12) node _pmpHomogeneous_T_22 = neq(_pmpHomogeneous_T_21, UInt<1>(0h0)) node _pmpHomogeneous_T_23 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_24 = mux(_pmpHomogeneous_T_23, _pmpHomogeneous_T_15, _pmpHomogeneous_T_8) node _pmpHomogeneous_T_25 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_26 = mux(_pmpHomogeneous_T_25, _pmpHomogeneous_T_22, _pmpHomogeneous_T_24) node _pmpHomogeneous_T_27 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_28 = mux(_pmpHomogeneous_T_27, _pmpHomogeneous_T_22, _pmpHomogeneous_T_26) node _pmpHomogeneous_T_29 = or(pmpHomogeneous_maskHomogeneous, _pmpHomogeneous_T_28) node _pmpHomogeneous_T_30 = bits(io.dpath.pmp[0].cfg.a, 0, 0) node _pmpHomogeneous_T_31 = eq(_pmpHomogeneous_T_30, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_beginsAfterLower_T_1 = not(_pmpHomogeneous_beginsAfterLower_T) node _pmpHomogeneous_beginsAfterLower_T_2 = or(_pmpHomogeneous_beginsAfterLower_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_3 = not(_pmpHomogeneous_beginsAfterLower_T_2) node _pmpHomogeneous_beginsAfterLower_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_3) node pmpHomogeneous_beginsAfterLower = eq(_pmpHomogeneous_beginsAfterLower_T_4, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_1 = not(_pmpHomogeneous_beginsAfterUpper_T) node _pmpHomogeneous_beginsAfterUpper_T_2 = or(_pmpHomogeneous_beginsAfterUpper_T_1, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_3 = not(_pmpHomogeneous_beginsAfterUpper_T_2) node _pmpHomogeneous_beginsAfterUpper_T_4 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_3) node pmpHomogeneous_beginsAfterUpper = eq(_pmpHomogeneous_beginsAfterUpper_T_4, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_1 = mux(_pmpHomogeneous_pgMask_T, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_2 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_3 = mux(_pmpHomogeneous_pgMask_T_2, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_1) node _pmpHomogeneous_pgMask_T_4 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask = mux(_pmpHomogeneous_pgMask_T_4, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_3) node _pmpHomogeneous_endsBeforeLower_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeLower_T_1 = shl(_pmpHomogeneous_WIRE.addr, 2) node _pmpHomogeneous_endsBeforeLower_T_2 = not(_pmpHomogeneous_endsBeforeLower_T_1) node _pmpHomogeneous_endsBeforeLower_T_3 = or(_pmpHomogeneous_endsBeforeLower_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_4 = not(_pmpHomogeneous_endsBeforeLower_T_3) node _pmpHomogeneous_endsBeforeLower_T_5 = and(_pmpHomogeneous_endsBeforeLower_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeLower = lt(_pmpHomogeneous_endsBeforeLower_T, _pmpHomogeneous_endsBeforeLower_T_5) node _pmpHomogeneous_endsBeforeUpper_T = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask) node _pmpHomogeneous_endsBeforeUpper_T_1 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_2 = not(_pmpHomogeneous_endsBeforeUpper_T_1) node _pmpHomogeneous_endsBeforeUpper_T_3 = or(_pmpHomogeneous_endsBeforeUpper_T_2, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_4 = not(_pmpHomogeneous_endsBeforeUpper_T_3) node _pmpHomogeneous_endsBeforeUpper_T_5 = and(_pmpHomogeneous_endsBeforeUpper_T_4, pmpHomogeneous_pgMask) node pmpHomogeneous_endsBeforeUpper = lt(_pmpHomogeneous_endsBeforeUpper_T, _pmpHomogeneous_endsBeforeUpper_T_5) node _pmpHomogeneous_T_32 = or(pmpHomogeneous_endsBeforeLower, pmpHomogeneous_beginsAfterUpper) node _pmpHomogeneous_T_33 = and(pmpHomogeneous_beginsAfterLower, pmpHomogeneous_endsBeforeUpper) node _pmpHomogeneous_T_34 = or(_pmpHomogeneous_T_32, _pmpHomogeneous_T_33) node _pmpHomogeneous_T_35 = or(_pmpHomogeneous_T_31, _pmpHomogeneous_T_34) node _pmpHomogeneous_T_36 = mux(_pmpHomogeneous_T_1, _pmpHomogeneous_T_29, _pmpHomogeneous_T_35) node _pmpHomogeneous_T_37 = and(UInt<1>(0h1), _pmpHomogeneous_T_36) node _pmpHomogeneous_T_38 = bits(io.dpath.pmp[1].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_8 = bits(io.dpath.pmp[1].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_9 = bits(io.dpath.pmp[1].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_10 = bits(io.dpath.pmp[1].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_11 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_12 = mux(_pmpHomogeneous_maskHomogeneous_T_11, _pmpHomogeneous_maskHomogeneous_T_9, _pmpHomogeneous_maskHomogeneous_T_8) node _pmpHomogeneous_maskHomogeneous_T_13 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_14 = mux(_pmpHomogeneous_maskHomogeneous_T_13, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_12) node _pmpHomogeneous_maskHomogeneous_T_15 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_1 = mux(_pmpHomogeneous_maskHomogeneous_T_15, _pmpHomogeneous_maskHomogeneous_T_10, _pmpHomogeneous_maskHomogeneous_T_14) node _pmpHomogeneous_T_39 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_40 = not(_pmpHomogeneous_T_39) node _pmpHomogeneous_T_41 = or(_pmpHomogeneous_T_40, UInt<2>(0h3)) node _pmpHomogeneous_T_42 = not(_pmpHomogeneous_T_41) node _pmpHomogeneous_T_43 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_42) node _pmpHomogeneous_T_44 = shr(_pmpHomogeneous_T_43, 30) node _pmpHomogeneous_T_45 = neq(_pmpHomogeneous_T_44, UInt<1>(0h0)) node _pmpHomogeneous_T_46 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_47 = not(_pmpHomogeneous_T_46) node _pmpHomogeneous_T_48 = or(_pmpHomogeneous_T_47, UInt<2>(0h3)) node _pmpHomogeneous_T_49 = not(_pmpHomogeneous_T_48) node _pmpHomogeneous_T_50 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_49) node _pmpHomogeneous_T_51 = shr(_pmpHomogeneous_T_50, 21) node _pmpHomogeneous_T_52 = neq(_pmpHomogeneous_T_51, UInt<1>(0h0)) node _pmpHomogeneous_T_53 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_T_54 = not(_pmpHomogeneous_T_53) node _pmpHomogeneous_T_55 = or(_pmpHomogeneous_T_54, UInt<2>(0h3)) node _pmpHomogeneous_T_56 = not(_pmpHomogeneous_T_55) node _pmpHomogeneous_T_57 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_56) node _pmpHomogeneous_T_58 = shr(_pmpHomogeneous_T_57, 12) node _pmpHomogeneous_T_59 = neq(_pmpHomogeneous_T_58, UInt<1>(0h0)) node _pmpHomogeneous_T_60 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_61 = mux(_pmpHomogeneous_T_60, _pmpHomogeneous_T_52, _pmpHomogeneous_T_45) node _pmpHomogeneous_T_62 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_63 = mux(_pmpHomogeneous_T_62, _pmpHomogeneous_T_59, _pmpHomogeneous_T_61) node _pmpHomogeneous_T_64 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_65 = mux(_pmpHomogeneous_T_64, _pmpHomogeneous_T_59, _pmpHomogeneous_T_63) node _pmpHomogeneous_T_66 = or(pmpHomogeneous_maskHomogeneous_1, _pmpHomogeneous_T_65) node _pmpHomogeneous_T_67 = bits(io.dpath.pmp[1].cfg.a, 0, 0) node _pmpHomogeneous_T_68 = eq(_pmpHomogeneous_T_67, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_5 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_6 = not(_pmpHomogeneous_beginsAfterLower_T_5) node _pmpHomogeneous_beginsAfterLower_T_7 = or(_pmpHomogeneous_beginsAfterLower_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_8 = not(_pmpHomogeneous_beginsAfterLower_T_7) node _pmpHomogeneous_beginsAfterLower_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_8) node pmpHomogeneous_beginsAfterLower_1 = eq(_pmpHomogeneous_beginsAfterLower_T_9, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_5 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_6 = not(_pmpHomogeneous_beginsAfterUpper_T_5) node _pmpHomogeneous_beginsAfterUpper_T_7 = or(_pmpHomogeneous_beginsAfterUpper_T_6, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_8 = not(_pmpHomogeneous_beginsAfterUpper_T_7) node _pmpHomogeneous_beginsAfterUpper_T_9 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_8) node pmpHomogeneous_beginsAfterUpper_1 = eq(_pmpHomogeneous_beginsAfterUpper_T_9, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_5 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_6 = mux(_pmpHomogeneous_pgMask_T_5, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_7 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_8 = mux(_pmpHomogeneous_pgMask_T_7, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_6) node _pmpHomogeneous_pgMask_T_9 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_1 = mux(_pmpHomogeneous_pgMask_T_9, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_8) node _pmpHomogeneous_endsBeforeLower_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeLower_T_7 = shl(io.dpath.pmp[0].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_8 = not(_pmpHomogeneous_endsBeforeLower_T_7) node _pmpHomogeneous_endsBeforeLower_T_9 = or(_pmpHomogeneous_endsBeforeLower_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_10 = not(_pmpHomogeneous_endsBeforeLower_T_9) node _pmpHomogeneous_endsBeforeLower_T_11 = and(_pmpHomogeneous_endsBeforeLower_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeLower_1 = lt(_pmpHomogeneous_endsBeforeLower_T_6, _pmpHomogeneous_endsBeforeLower_T_11) node _pmpHomogeneous_endsBeforeUpper_T_6 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_1) node _pmpHomogeneous_endsBeforeUpper_T_7 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_8 = not(_pmpHomogeneous_endsBeforeUpper_T_7) node _pmpHomogeneous_endsBeforeUpper_T_9 = or(_pmpHomogeneous_endsBeforeUpper_T_8, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_10 = not(_pmpHomogeneous_endsBeforeUpper_T_9) node _pmpHomogeneous_endsBeforeUpper_T_11 = and(_pmpHomogeneous_endsBeforeUpper_T_10, pmpHomogeneous_pgMask_1) node pmpHomogeneous_endsBeforeUpper_1 = lt(_pmpHomogeneous_endsBeforeUpper_T_6, _pmpHomogeneous_endsBeforeUpper_T_11) node _pmpHomogeneous_T_69 = or(pmpHomogeneous_endsBeforeLower_1, pmpHomogeneous_beginsAfterUpper_1) node _pmpHomogeneous_T_70 = and(pmpHomogeneous_beginsAfterLower_1, pmpHomogeneous_endsBeforeUpper_1) node _pmpHomogeneous_T_71 = or(_pmpHomogeneous_T_69, _pmpHomogeneous_T_70) node _pmpHomogeneous_T_72 = or(_pmpHomogeneous_T_68, _pmpHomogeneous_T_71) node _pmpHomogeneous_T_73 = mux(_pmpHomogeneous_T_38, _pmpHomogeneous_T_66, _pmpHomogeneous_T_72) node _pmpHomogeneous_T_74 = and(_pmpHomogeneous_T_37, _pmpHomogeneous_T_73) node _pmpHomogeneous_T_75 = bits(io.dpath.pmp[2].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_16 = bits(io.dpath.pmp[2].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_17 = bits(io.dpath.pmp[2].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_18 = bits(io.dpath.pmp[2].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_19 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_20 = mux(_pmpHomogeneous_maskHomogeneous_T_19, _pmpHomogeneous_maskHomogeneous_T_17, _pmpHomogeneous_maskHomogeneous_T_16) node _pmpHomogeneous_maskHomogeneous_T_21 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_22 = mux(_pmpHomogeneous_maskHomogeneous_T_21, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_20) node _pmpHomogeneous_maskHomogeneous_T_23 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_2 = mux(_pmpHomogeneous_maskHomogeneous_T_23, _pmpHomogeneous_maskHomogeneous_T_18, _pmpHomogeneous_maskHomogeneous_T_22) node _pmpHomogeneous_T_76 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_77 = not(_pmpHomogeneous_T_76) node _pmpHomogeneous_T_78 = or(_pmpHomogeneous_T_77, UInt<2>(0h3)) node _pmpHomogeneous_T_79 = not(_pmpHomogeneous_T_78) node _pmpHomogeneous_T_80 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_79) node _pmpHomogeneous_T_81 = shr(_pmpHomogeneous_T_80, 30) node _pmpHomogeneous_T_82 = neq(_pmpHomogeneous_T_81, UInt<1>(0h0)) node _pmpHomogeneous_T_83 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_84 = not(_pmpHomogeneous_T_83) node _pmpHomogeneous_T_85 = or(_pmpHomogeneous_T_84, UInt<2>(0h3)) node _pmpHomogeneous_T_86 = not(_pmpHomogeneous_T_85) node _pmpHomogeneous_T_87 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_86) node _pmpHomogeneous_T_88 = shr(_pmpHomogeneous_T_87, 21) node _pmpHomogeneous_T_89 = neq(_pmpHomogeneous_T_88, UInt<1>(0h0)) node _pmpHomogeneous_T_90 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_T_91 = not(_pmpHomogeneous_T_90) node _pmpHomogeneous_T_92 = or(_pmpHomogeneous_T_91, UInt<2>(0h3)) node _pmpHomogeneous_T_93 = not(_pmpHomogeneous_T_92) node _pmpHomogeneous_T_94 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_93) node _pmpHomogeneous_T_95 = shr(_pmpHomogeneous_T_94, 12) node _pmpHomogeneous_T_96 = neq(_pmpHomogeneous_T_95, UInt<1>(0h0)) node _pmpHomogeneous_T_97 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_98 = mux(_pmpHomogeneous_T_97, _pmpHomogeneous_T_89, _pmpHomogeneous_T_82) node _pmpHomogeneous_T_99 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_100 = mux(_pmpHomogeneous_T_99, _pmpHomogeneous_T_96, _pmpHomogeneous_T_98) node _pmpHomogeneous_T_101 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_102 = mux(_pmpHomogeneous_T_101, _pmpHomogeneous_T_96, _pmpHomogeneous_T_100) node _pmpHomogeneous_T_103 = or(pmpHomogeneous_maskHomogeneous_2, _pmpHomogeneous_T_102) node _pmpHomogeneous_T_104 = bits(io.dpath.pmp[2].cfg.a, 0, 0) node _pmpHomogeneous_T_105 = eq(_pmpHomogeneous_T_104, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_10 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_11 = not(_pmpHomogeneous_beginsAfterLower_T_10) node _pmpHomogeneous_beginsAfterLower_T_12 = or(_pmpHomogeneous_beginsAfterLower_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_13 = not(_pmpHomogeneous_beginsAfterLower_T_12) node _pmpHomogeneous_beginsAfterLower_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_13) node pmpHomogeneous_beginsAfterLower_2 = eq(_pmpHomogeneous_beginsAfterLower_T_14, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_10 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_11 = not(_pmpHomogeneous_beginsAfterUpper_T_10) node _pmpHomogeneous_beginsAfterUpper_T_12 = or(_pmpHomogeneous_beginsAfterUpper_T_11, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_13 = not(_pmpHomogeneous_beginsAfterUpper_T_12) node _pmpHomogeneous_beginsAfterUpper_T_14 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_13) node pmpHomogeneous_beginsAfterUpper_2 = eq(_pmpHomogeneous_beginsAfterUpper_T_14, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_10 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_11 = mux(_pmpHomogeneous_pgMask_T_10, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_12 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_13 = mux(_pmpHomogeneous_pgMask_T_12, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_11) node _pmpHomogeneous_pgMask_T_14 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_2 = mux(_pmpHomogeneous_pgMask_T_14, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_13) node _pmpHomogeneous_endsBeforeLower_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeLower_T_13 = shl(io.dpath.pmp[1].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_14 = not(_pmpHomogeneous_endsBeforeLower_T_13) node _pmpHomogeneous_endsBeforeLower_T_15 = or(_pmpHomogeneous_endsBeforeLower_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_16 = not(_pmpHomogeneous_endsBeforeLower_T_15) node _pmpHomogeneous_endsBeforeLower_T_17 = and(_pmpHomogeneous_endsBeforeLower_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeLower_2 = lt(_pmpHomogeneous_endsBeforeLower_T_12, _pmpHomogeneous_endsBeforeLower_T_17) node _pmpHomogeneous_endsBeforeUpper_T_12 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_2) node _pmpHomogeneous_endsBeforeUpper_T_13 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_14 = not(_pmpHomogeneous_endsBeforeUpper_T_13) node _pmpHomogeneous_endsBeforeUpper_T_15 = or(_pmpHomogeneous_endsBeforeUpper_T_14, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_16 = not(_pmpHomogeneous_endsBeforeUpper_T_15) node _pmpHomogeneous_endsBeforeUpper_T_17 = and(_pmpHomogeneous_endsBeforeUpper_T_16, pmpHomogeneous_pgMask_2) node pmpHomogeneous_endsBeforeUpper_2 = lt(_pmpHomogeneous_endsBeforeUpper_T_12, _pmpHomogeneous_endsBeforeUpper_T_17) node _pmpHomogeneous_T_106 = or(pmpHomogeneous_endsBeforeLower_2, pmpHomogeneous_beginsAfterUpper_2) node _pmpHomogeneous_T_107 = and(pmpHomogeneous_beginsAfterLower_2, pmpHomogeneous_endsBeforeUpper_2) node _pmpHomogeneous_T_108 = or(_pmpHomogeneous_T_106, _pmpHomogeneous_T_107) node _pmpHomogeneous_T_109 = or(_pmpHomogeneous_T_105, _pmpHomogeneous_T_108) node _pmpHomogeneous_T_110 = mux(_pmpHomogeneous_T_75, _pmpHomogeneous_T_103, _pmpHomogeneous_T_109) node _pmpHomogeneous_T_111 = and(_pmpHomogeneous_T_74, _pmpHomogeneous_T_110) node _pmpHomogeneous_T_112 = bits(io.dpath.pmp[3].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_24 = bits(io.dpath.pmp[3].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_25 = bits(io.dpath.pmp[3].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_26 = bits(io.dpath.pmp[3].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_27 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_28 = mux(_pmpHomogeneous_maskHomogeneous_T_27, _pmpHomogeneous_maskHomogeneous_T_25, _pmpHomogeneous_maskHomogeneous_T_24) node _pmpHomogeneous_maskHomogeneous_T_29 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_30 = mux(_pmpHomogeneous_maskHomogeneous_T_29, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_28) node _pmpHomogeneous_maskHomogeneous_T_31 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_3 = mux(_pmpHomogeneous_maskHomogeneous_T_31, _pmpHomogeneous_maskHomogeneous_T_26, _pmpHomogeneous_maskHomogeneous_T_30) node _pmpHomogeneous_T_113 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_114 = not(_pmpHomogeneous_T_113) node _pmpHomogeneous_T_115 = or(_pmpHomogeneous_T_114, UInt<2>(0h3)) node _pmpHomogeneous_T_116 = not(_pmpHomogeneous_T_115) node _pmpHomogeneous_T_117 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_116) node _pmpHomogeneous_T_118 = shr(_pmpHomogeneous_T_117, 30) node _pmpHomogeneous_T_119 = neq(_pmpHomogeneous_T_118, UInt<1>(0h0)) node _pmpHomogeneous_T_120 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_121 = not(_pmpHomogeneous_T_120) node _pmpHomogeneous_T_122 = or(_pmpHomogeneous_T_121, UInt<2>(0h3)) node _pmpHomogeneous_T_123 = not(_pmpHomogeneous_T_122) node _pmpHomogeneous_T_124 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_123) node _pmpHomogeneous_T_125 = shr(_pmpHomogeneous_T_124, 21) node _pmpHomogeneous_T_126 = neq(_pmpHomogeneous_T_125, UInt<1>(0h0)) node _pmpHomogeneous_T_127 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_T_128 = not(_pmpHomogeneous_T_127) node _pmpHomogeneous_T_129 = or(_pmpHomogeneous_T_128, UInt<2>(0h3)) node _pmpHomogeneous_T_130 = not(_pmpHomogeneous_T_129) node _pmpHomogeneous_T_131 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_130) node _pmpHomogeneous_T_132 = shr(_pmpHomogeneous_T_131, 12) node _pmpHomogeneous_T_133 = neq(_pmpHomogeneous_T_132, UInt<1>(0h0)) node _pmpHomogeneous_T_134 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_135 = mux(_pmpHomogeneous_T_134, _pmpHomogeneous_T_126, _pmpHomogeneous_T_119) node _pmpHomogeneous_T_136 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_137 = mux(_pmpHomogeneous_T_136, _pmpHomogeneous_T_133, _pmpHomogeneous_T_135) node _pmpHomogeneous_T_138 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_139 = mux(_pmpHomogeneous_T_138, _pmpHomogeneous_T_133, _pmpHomogeneous_T_137) node _pmpHomogeneous_T_140 = or(pmpHomogeneous_maskHomogeneous_3, _pmpHomogeneous_T_139) node _pmpHomogeneous_T_141 = bits(io.dpath.pmp[3].cfg.a, 0, 0) node _pmpHomogeneous_T_142 = eq(_pmpHomogeneous_T_141, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_15 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_16 = not(_pmpHomogeneous_beginsAfterLower_T_15) node _pmpHomogeneous_beginsAfterLower_T_17 = or(_pmpHomogeneous_beginsAfterLower_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_18 = not(_pmpHomogeneous_beginsAfterLower_T_17) node _pmpHomogeneous_beginsAfterLower_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_18) node pmpHomogeneous_beginsAfterLower_3 = eq(_pmpHomogeneous_beginsAfterLower_T_19, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_15 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_16 = not(_pmpHomogeneous_beginsAfterUpper_T_15) node _pmpHomogeneous_beginsAfterUpper_T_17 = or(_pmpHomogeneous_beginsAfterUpper_T_16, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_18 = not(_pmpHomogeneous_beginsAfterUpper_T_17) node _pmpHomogeneous_beginsAfterUpper_T_19 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_18) node pmpHomogeneous_beginsAfterUpper_3 = eq(_pmpHomogeneous_beginsAfterUpper_T_19, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_15 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_16 = mux(_pmpHomogeneous_pgMask_T_15, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_17 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_18 = mux(_pmpHomogeneous_pgMask_T_17, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_16) node _pmpHomogeneous_pgMask_T_19 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_3 = mux(_pmpHomogeneous_pgMask_T_19, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_18) node _pmpHomogeneous_endsBeforeLower_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeLower_T_19 = shl(io.dpath.pmp[2].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_20 = not(_pmpHomogeneous_endsBeforeLower_T_19) node _pmpHomogeneous_endsBeforeLower_T_21 = or(_pmpHomogeneous_endsBeforeLower_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_22 = not(_pmpHomogeneous_endsBeforeLower_T_21) node _pmpHomogeneous_endsBeforeLower_T_23 = and(_pmpHomogeneous_endsBeforeLower_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeLower_3 = lt(_pmpHomogeneous_endsBeforeLower_T_18, _pmpHomogeneous_endsBeforeLower_T_23) node _pmpHomogeneous_endsBeforeUpper_T_18 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_3) node _pmpHomogeneous_endsBeforeUpper_T_19 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_20 = not(_pmpHomogeneous_endsBeforeUpper_T_19) node _pmpHomogeneous_endsBeforeUpper_T_21 = or(_pmpHomogeneous_endsBeforeUpper_T_20, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_22 = not(_pmpHomogeneous_endsBeforeUpper_T_21) node _pmpHomogeneous_endsBeforeUpper_T_23 = and(_pmpHomogeneous_endsBeforeUpper_T_22, pmpHomogeneous_pgMask_3) node pmpHomogeneous_endsBeforeUpper_3 = lt(_pmpHomogeneous_endsBeforeUpper_T_18, _pmpHomogeneous_endsBeforeUpper_T_23) node _pmpHomogeneous_T_143 = or(pmpHomogeneous_endsBeforeLower_3, pmpHomogeneous_beginsAfterUpper_3) node _pmpHomogeneous_T_144 = and(pmpHomogeneous_beginsAfterLower_3, pmpHomogeneous_endsBeforeUpper_3) node _pmpHomogeneous_T_145 = or(_pmpHomogeneous_T_143, _pmpHomogeneous_T_144) node _pmpHomogeneous_T_146 = or(_pmpHomogeneous_T_142, _pmpHomogeneous_T_145) node _pmpHomogeneous_T_147 = mux(_pmpHomogeneous_T_112, _pmpHomogeneous_T_140, _pmpHomogeneous_T_146) node _pmpHomogeneous_T_148 = and(_pmpHomogeneous_T_111, _pmpHomogeneous_T_147) node _pmpHomogeneous_T_149 = bits(io.dpath.pmp[4].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_32 = bits(io.dpath.pmp[4].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_33 = bits(io.dpath.pmp[4].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_34 = bits(io.dpath.pmp[4].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_36 = mux(_pmpHomogeneous_maskHomogeneous_T_35, _pmpHomogeneous_maskHomogeneous_T_33, _pmpHomogeneous_maskHomogeneous_T_32) node _pmpHomogeneous_maskHomogeneous_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_38 = mux(_pmpHomogeneous_maskHomogeneous_T_37, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_36) node _pmpHomogeneous_maskHomogeneous_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_4 = mux(_pmpHomogeneous_maskHomogeneous_T_39, _pmpHomogeneous_maskHomogeneous_T_34, _pmpHomogeneous_maskHomogeneous_T_38) node _pmpHomogeneous_T_150 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_151 = not(_pmpHomogeneous_T_150) node _pmpHomogeneous_T_152 = or(_pmpHomogeneous_T_151, UInt<2>(0h3)) node _pmpHomogeneous_T_153 = not(_pmpHomogeneous_T_152) node _pmpHomogeneous_T_154 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_153) node _pmpHomogeneous_T_155 = shr(_pmpHomogeneous_T_154, 30) node _pmpHomogeneous_T_156 = neq(_pmpHomogeneous_T_155, UInt<1>(0h0)) node _pmpHomogeneous_T_157 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_158 = not(_pmpHomogeneous_T_157) node _pmpHomogeneous_T_159 = or(_pmpHomogeneous_T_158, UInt<2>(0h3)) node _pmpHomogeneous_T_160 = not(_pmpHomogeneous_T_159) node _pmpHomogeneous_T_161 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_160) node _pmpHomogeneous_T_162 = shr(_pmpHomogeneous_T_161, 21) node _pmpHomogeneous_T_163 = neq(_pmpHomogeneous_T_162, UInt<1>(0h0)) node _pmpHomogeneous_T_164 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_T_165 = not(_pmpHomogeneous_T_164) node _pmpHomogeneous_T_166 = or(_pmpHomogeneous_T_165, UInt<2>(0h3)) node _pmpHomogeneous_T_167 = not(_pmpHomogeneous_T_166) node _pmpHomogeneous_T_168 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_167) node _pmpHomogeneous_T_169 = shr(_pmpHomogeneous_T_168, 12) node _pmpHomogeneous_T_170 = neq(_pmpHomogeneous_T_169, UInt<1>(0h0)) node _pmpHomogeneous_T_171 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_172 = mux(_pmpHomogeneous_T_171, _pmpHomogeneous_T_163, _pmpHomogeneous_T_156) node _pmpHomogeneous_T_173 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_174 = mux(_pmpHomogeneous_T_173, _pmpHomogeneous_T_170, _pmpHomogeneous_T_172) node _pmpHomogeneous_T_175 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_176 = mux(_pmpHomogeneous_T_175, _pmpHomogeneous_T_170, _pmpHomogeneous_T_174) node _pmpHomogeneous_T_177 = or(pmpHomogeneous_maskHomogeneous_4, _pmpHomogeneous_T_176) node _pmpHomogeneous_T_178 = bits(io.dpath.pmp[4].cfg.a, 0, 0) node _pmpHomogeneous_T_179 = eq(_pmpHomogeneous_T_178, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_20 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_21 = not(_pmpHomogeneous_beginsAfterLower_T_20) node _pmpHomogeneous_beginsAfterLower_T_22 = or(_pmpHomogeneous_beginsAfterLower_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_23 = not(_pmpHomogeneous_beginsAfterLower_T_22) node _pmpHomogeneous_beginsAfterLower_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_23) node pmpHomogeneous_beginsAfterLower_4 = eq(_pmpHomogeneous_beginsAfterLower_T_24, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_20 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_21 = not(_pmpHomogeneous_beginsAfterUpper_T_20) node _pmpHomogeneous_beginsAfterUpper_T_22 = or(_pmpHomogeneous_beginsAfterUpper_T_21, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_23 = not(_pmpHomogeneous_beginsAfterUpper_T_22) node _pmpHomogeneous_beginsAfterUpper_T_24 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_23) node pmpHomogeneous_beginsAfterUpper_4 = eq(_pmpHomogeneous_beginsAfterUpper_T_24, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_20 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_21 = mux(_pmpHomogeneous_pgMask_T_20, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_22 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_23 = mux(_pmpHomogeneous_pgMask_T_22, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_21) node _pmpHomogeneous_pgMask_T_24 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_4 = mux(_pmpHomogeneous_pgMask_T_24, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_23) node _pmpHomogeneous_endsBeforeLower_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeLower_T_25 = shl(io.dpath.pmp[3].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_26 = not(_pmpHomogeneous_endsBeforeLower_T_25) node _pmpHomogeneous_endsBeforeLower_T_27 = or(_pmpHomogeneous_endsBeforeLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_28 = not(_pmpHomogeneous_endsBeforeLower_T_27) node _pmpHomogeneous_endsBeforeLower_T_29 = and(_pmpHomogeneous_endsBeforeLower_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeLower_4 = lt(_pmpHomogeneous_endsBeforeLower_T_24, _pmpHomogeneous_endsBeforeLower_T_29) node _pmpHomogeneous_endsBeforeUpper_T_24 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_4) node _pmpHomogeneous_endsBeforeUpper_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_26 = not(_pmpHomogeneous_endsBeforeUpper_T_25) node _pmpHomogeneous_endsBeforeUpper_T_27 = or(_pmpHomogeneous_endsBeforeUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_28 = not(_pmpHomogeneous_endsBeforeUpper_T_27) node _pmpHomogeneous_endsBeforeUpper_T_29 = and(_pmpHomogeneous_endsBeforeUpper_T_28, pmpHomogeneous_pgMask_4) node pmpHomogeneous_endsBeforeUpper_4 = lt(_pmpHomogeneous_endsBeforeUpper_T_24, _pmpHomogeneous_endsBeforeUpper_T_29) node _pmpHomogeneous_T_180 = or(pmpHomogeneous_endsBeforeLower_4, pmpHomogeneous_beginsAfterUpper_4) node _pmpHomogeneous_T_181 = and(pmpHomogeneous_beginsAfterLower_4, pmpHomogeneous_endsBeforeUpper_4) node _pmpHomogeneous_T_182 = or(_pmpHomogeneous_T_180, _pmpHomogeneous_T_181) node _pmpHomogeneous_T_183 = or(_pmpHomogeneous_T_179, _pmpHomogeneous_T_182) node _pmpHomogeneous_T_184 = mux(_pmpHomogeneous_T_149, _pmpHomogeneous_T_177, _pmpHomogeneous_T_183) node _pmpHomogeneous_T_185 = and(_pmpHomogeneous_T_148, _pmpHomogeneous_T_184) node _pmpHomogeneous_T_186 = bits(io.dpath.pmp[5].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_40 = bits(io.dpath.pmp[5].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_41 = bits(io.dpath.pmp[5].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_42 = bits(io.dpath.pmp[5].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_43 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_44 = mux(_pmpHomogeneous_maskHomogeneous_T_43, _pmpHomogeneous_maskHomogeneous_T_41, _pmpHomogeneous_maskHomogeneous_T_40) node _pmpHomogeneous_maskHomogeneous_T_45 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_46 = mux(_pmpHomogeneous_maskHomogeneous_T_45, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_44) node _pmpHomogeneous_maskHomogeneous_T_47 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_5 = mux(_pmpHomogeneous_maskHomogeneous_T_47, _pmpHomogeneous_maskHomogeneous_T_42, _pmpHomogeneous_maskHomogeneous_T_46) node _pmpHomogeneous_T_187 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_188 = not(_pmpHomogeneous_T_187) node _pmpHomogeneous_T_189 = or(_pmpHomogeneous_T_188, UInt<2>(0h3)) node _pmpHomogeneous_T_190 = not(_pmpHomogeneous_T_189) node _pmpHomogeneous_T_191 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_190) node _pmpHomogeneous_T_192 = shr(_pmpHomogeneous_T_191, 30) node _pmpHomogeneous_T_193 = neq(_pmpHomogeneous_T_192, UInt<1>(0h0)) node _pmpHomogeneous_T_194 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_195 = not(_pmpHomogeneous_T_194) node _pmpHomogeneous_T_196 = or(_pmpHomogeneous_T_195, UInt<2>(0h3)) node _pmpHomogeneous_T_197 = not(_pmpHomogeneous_T_196) node _pmpHomogeneous_T_198 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_197) node _pmpHomogeneous_T_199 = shr(_pmpHomogeneous_T_198, 21) node _pmpHomogeneous_T_200 = neq(_pmpHomogeneous_T_199, UInt<1>(0h0)) node _pmpHomogeneous_T_201 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_T_202 = not(_pmpHomogeneous_T_201) node _pmpHomogeneous_T_203 = or(_pmpHomogeneous_T_202, UInt<2>(0h3)) node _pmpHomogeneous_T_204 = not(_pmpHomogeneous_T_203) node _pmpHomogeneous_T_205 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_204) node _pmpHomogeneous_T_206 = shr(_pmpHomogeneous_T_205, 12) node _pmpHomogeneous_T_207 = neq(_pmpHomogeneous_T_206, UInt<1>(0h0)) node _pmpHomogeneous_T_208 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_209 = mux(_pmpHomogeneous_T_208, _pmpHomogeneous_T_200, _pmpHomogeneous_T_193) node _pmpHomogeneous_T_210 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_211 = mux(_pmpHomogeneous_T_210, _pmpHomogeneous_T_207, _pmpHomogeneous_T_209) node _pmpHomogeneous_T_212 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_213 = mux(_pmpHomogeneous_T_212, _pmpHomogeneous_T_207, _pmpHomogeneous_T_211) node _pmpHomogeneous_T_214 = or(pmpHomogeneous_maskHomogeneous_5, _pmpHomogeneous_T_213) node _pmpHomogeneous_T_215 = bits(io.dpath.pmp[5].cfg.a, 0, 0) node _pmpHomogeneous_T_216 = eq(_pmpHomogeneous_T_215, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_25 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_26 = not(_pmpHomogeneous_beginsAfterLower_T_25) node _pmpHomogeneous_beginsAfterLower_T_27 = or(_pmpHomogeneous_beginsAfterLower_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_28 = not(_pmpHomogeneous_beginsAfterLower_T_27) node _pmpHomogeneous_beginsAfterLower_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_28) node pmpHomogeneous_beginsAfterLower_5 = eq(_pmpHomogeneous_beginsAfterLower_T_29, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_25 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_26 = not(_pmpHomogeneous_beginsAfterUpper_T_25) node _pmpHomogeneous_beginsAfterUpper_T_27 = or(_pmpHomogeneous_beginsAfterUpper_T_26, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_28 = not(_pmpHomogeneous_beginsAfterUpper_T_27) node _pmpHomogeneous_beginsAfterUpper_T_29 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_28) node pmpHomogeneous_beginsAfterUpper_5 = eq(_pmpHomogeneous_beginsAfterUpper_T_29, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_25 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_26 = mux(_pmpHomogeneous_pgMask_T_25, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_27 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_28 = mux(_pmpHomogeneous_pgMask_T_27, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_26) node _pmpHomogeneous_pgMask_T_29 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_5 = mux(_pmpHomogeneous_pgMask_T_29, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_28) node _pmpHomogeneous_endsBeforeLower_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeLower_T_31 = shl(io.dpath.pmp[4].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_32 = not(_pmpHomogeneous_endsBeforeLower_T_31) node _pmpHomogeneous_endsBeforeLower_T_33 = or(_pmpHomogeneous_endsBeforeLower_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_34 = not(_pmpHomogeneous_endsBeforeLower_T_33) node _pmpHomogeneous_endsBeforeLower_T_35 = and(_pmpHomogeneous_endsBeforeLower_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeLower_5 = lt(_pmpHomogeneous_endsBeforeLower_T_30, _pmpHomogeneous_endsBeforeLower_T_35) node _pmpHomogeneous_endsBeforeUpper_T_30 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_5) node _pmpHomogeneous_endsBeforeUpper_T_31 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_32 = not(_pmpHomogeneous_endsBeforeUpper_T_31) node _pmpHomogeneous_endsBeforeUpper_T_33 = or(_pmpHomogeneous_endsBeforeUpper_T_32, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_34 = not(_pmpHomogeneous_endsBeforeUpper_T_33) node _pmpHomogeneous_endsBeforeUpper_T_35 = and(_pmpHomogeneous_endsBeforeUpper_T_34, pmpHomogeneous_pgMask_5) node pmpHomogeneous_endsBeforeUpper_5 = lt(_pmpHomogeneous_endsBeforeUpper_T_30, _pmpHomogeneous_endsBeforeUpper_T_35) node _pmpHomogeneous_T_217 = or(pmpHomogeneous_endsBeforeLower_5, pmpHomogeneous_beginsAfterUpper_5) node _pmpHomogeneous_T_218 = and(pmpHomogeneous_beginsAfterLower_5, pmpHomogeneous_endsBeforeUpper_5) node _pmpHomogeneous_T_219 = or(_pmpHomogeneous_T_217, _pmpHomogeneous_T_218) node _pmpHomogeneous_T_220 = or(_pmpHomogeneous_T_216, _pmpHomogeneous_T_219) node _pmpHomogeneous_T_221 = mux(_pmpHomogeneous_T_186, _pmpHomogeneous_T_214, _pmpHomogeneous_T_220) node _pmpHomogeneous_T_222 = and(_pmpHomogeneous_T_185, _pmpHomogeneous_T_221) node _pmpHomogeneous_T_223 = bits(io.dpath.pmp[6].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_48 = bits(io.dpath.pmp[6].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_49 = bits(io.dpath.pmp[6].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_50 = bits(io.dpath.pmp[6].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_51 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_52 = mux(_pmpHomogeneous_maskHomogeneous_T_51, _pmpHomogeneous_maskHomogeneous_T_49, _pmpHomogeneous_maskHomogeneous_T_48) node _pmpHomogeneous_maskHomogeneous_T_53 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_54 = mux(_pmpHomogeneous_maskHomogeneous_T_53, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_52) node _pmpHomogeneous_maskHomogeneous_T_55 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_6 = mux(_pmpHomogeneous_maskHomogeneous_T_55, _pmpHomogeneous_maskHomogeneous_T_50, _pmpHomogeneous_maskHomogeneous_T_54) node _pmpHomogeneous_T_224 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_225 = not(_pmpHomogeneous_T_224) node _pmpHomogeneous_T_226 = or(_pmpHomogeneous_T_225, UInt<2>(0h3)) node _pmpHomogeneous_T_227 = not(_pmpHomogeneous_T_226) node _pmpHomogeneous_T_228 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_227) node _pmpHomogeneous_T_229 = shr(_pmpHomogeneous_T_228, 30) node _pmpHomogeneous_T_230 = neq(_pmpHomogeneous_T_229, UInt<1>(0h0)) node _pmpHomogeneous_T_231 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_232 = not(_pmpHomogeneous_T_231) node _pmpHomogeneous_T_233 = or(_pmpHomogeneous_T_232, UInt<2>(0h3)) node _pmpHomogeneous_T_234 = not(_pmpHomogeneous_T_233) node _pmpHomogeneous_T_235 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_234) node _pmpHomogeneous_T_236 = shr(_pmpHomogeneous_T_235, 21) node _pmpHomogeneous_T_237 = neq(_pmpHomogeneous_T_236, UInt<1>(0h0)) node _pmpHomogeneous_T_238 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_T_239 = not(_pmpHomogeneous_T_238) node _pmpHomogeneous_T_240 = or(_pmpHomogeneous_T_239, UInt<2>(0h3)) node _pmpHomogeneous_T_241 = not(_pmpHomogeneous_T_240) node _pmpHomogeneous_T_242 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_241) node _pmpHomogeneous_T_243 = shr(_pmpHomogeneous_T_242, 12) node _pmpHomogeneous_T_244 = neq(_pmpHomogeneous_T_243, UInt<1>(0h0)) node _pmpHomogeneous_T_245 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_246 = mux(_pmpHomogeneous_T_245, _pmpHomogeneous_T_237, _pmpHomogeneous_T_230) node _pmpHomogeneous_T_247 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_248 = mux(_pmpHomogeneous_T_247, _pmpHomogeneous_T_244, _pmpHomogeneous_T_246) node _pmpHomogeneous_T_249 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_250 = mux(_pmpHomogeneous_T_249, _pmpHomogeneous_T_244, _pmpHomogeneous_T_248) node _pmpHomogeneous_T_251 = or(pmpHomogeneous_maskHomogeneous_6, _pmpHomogeneous_T_250) node _pmpHomogeneous_T_252 = bits(io.dpath.pmp[6].cfg.a, 0, 0) node _pmpHomogeneous_T_253 = eq(_pmpHomogeneous_T_252, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_30 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_31 = not(_pmpHomogeneous_beginsAfterLower_T_30) node _pmpHomogeneous_beginsAfterLower_T_32 = or(_pmpHomogeneous_beginsAfterLower_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_33 = not(_pmpHomogeneous_beginsAfterLower_T_32) node _pmpHomogeneous_beginsAfterLower_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_33) node pmpHomogeneous_beginsAfterLower_6 = eq(_pmpHomogeneous_beginsAfterLower_T_34, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_30 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_31 = not(_pmpHomogeneous_beginsAfterUpper_T_30) node _pmpHomogeneous_beginsAfterUpper_T_32 = or(_pmpHomogeneous_beginsAfterUpper_T_31, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_33 = not(_pmpHomogeneous_beginsAfterUpper_T_32) node _pmpHomogeneous_beginsAfterUpper_T_34 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_33) node pmpHomogeneous_beginsAfterUpper_6 = eq(_pmpHomogeneous_beginsAfterUpper_T_34, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_30 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_31 = mux(_pmpHomogeneous_pgMask_T_30, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_32 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_33 = mux(_pmpHomogeneous_pgMask_T_32, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_31) node _pmpHomogeneous_pgMask_T_34 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_6 = mux(_pmpHomogeneous_pgMask_T_34, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_33) node _pmpHomogeneous_endsBeforeLower_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeLower_T_37 = shl(io.dpath.pmp[5].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_38 = not(_pmpHomogeneous_endsBeforeLower_T_37) node _pmpHomogeneous_endsBeforeLower_T_39 = or(_pmpHomogeneous_endsBeforeLower_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_40 = not(_pmpHomogeneous_endsBeforeLower_T_39) node _pmpHomogeneous_endsBeforeLower_T_41 = and(_pmpHomogeneous_endsBeforeLower_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeLower_6 = lt(_pmpHomogeneous_endsBeforeLower_T_36, _pmpHomogeneous_endsBeforeLower_T_41) node _pmpHomogeneous_endsBeforeUpper_T_36 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_6) node _pmpHomogeneous_endsBeforeUpper_T_37 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_38 = not(_pmpHomogeneous_endsBeforeUpper_T_37) node _pmpHomogeneous_endsBeforeUpper_T_39 = or(_pmpHomogeneous_endsBeforeUpper_T_38, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_40 = not(_pmpHomogeneous_endsBeforeUpper_T_39) node _pmpHomogeneous_endsBeforeUpper_T_41 = and(_pmpHomogeneous_endsBeforeUpper_T_40, pmpHomogeneous_pgMask_6) node pmpHomogeneous_endsBeforeUpper_6 = lt(_pmpHomogeneous_endsBeforeUpper_T_36, _pmpHomogeneous_endsBeforeUpper_T_41) node _pmpHomogeneous_T_254 = or(pmpHomogeneous_endsBeforeLower_6, pmpHomogeneous_beginsAfterUpper_6) node _pmpHomogeneous_T_255 = and(pmpHomogeneous_beginsAfterLower_6, pmpHomogeneous_endsBeforeUpper_6) node _pmpHomogeneous_T_256 = or(_pmpHomogeneous_T_254, _pmpHomogeneous_T_255) node _pmpHomogeneous_T_257 = or(_pmpHomogeneous_T_253, _pmpHomogeneous_T_256) node _pmpHomogeneous_T_258 = mux(_pmpHomogeneous_T_223, _pmpHomogeneous_T_251, _pmpHomogeneous_T_257) node _pmpHomogeneous_T_259 = and(_pmpHomogeneous_T_222, _pmpHomogeneous_T_258) node _pmpHomogeneous_T_260 = bits(io.dpath.pmp[7].cfg.a, 1, 1) node _pmpHomogeneous_maskHomogeneous_T_56 = bits(io.dpath.pmp[7].mask, 29, 29) node _pmpHomogeneous_maskHomogeneous_T_57 = bits(io.dpath.pmp[7].mask, 20, 20) node _pmpHomogeneous_maskHomogeneous_T_58 = bits(io.dpath.pmp[7].mask, 11, 11) node _pmpHomogeneous_maskHomogeneous_T_59 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_maskHomogeneous_T_60 = mux(_pmpHomogeneous_maskHomogeneous_T_59, _pmpHomogeneous_maskHomogeneous_T_57, _pmpHomogeneous_maskHomogeneous_T_56) node _pmpHomogeneous_maskHomogeneous_T_61 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_maskHomogeneous_T_62 = mux(_pmpHomogeneous_maskHomogeneous_T_61, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_60) node _pmpHomogeneous_maskHomogeneous_T_63 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_maskHomogeneous_7 = mux(_pmpHomogeneous_maskHomogeneous_T_63, _pmpHomogeneous_maskHomogeneous_T_58, _pmpHomogeneous_maskHomogeneous_T_62) node _pmpHomogeneous_T_261 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_262 = not(_pmpHomogeneous_T_261) node _pmpHomogeneous_T_263 = or(_pmpHomogeneous_T_262, UInt<2>(0h3)) node _pmpHomogeneous_T_264 = not(_pmpHomogeneous_T_263) node _pmpHomogeneous_T_265 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_264) node _pmpHomogeneous_T_266 = shr(_pmpHomogeneous_T_265, 30) node _pmpHomogeneous_T_267 = neq(_pmpHomogeneous_T_266, UInt<1>(0h0)) node _pmpHomogeneous_T_268 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_269 = not(_pmpHomogeneous_T_268) node _pmpHomogeneous_T_270 = or(_pmpHomogeneous_T_269, UInt<2>(0h3)) node _pmpHomogeneous_T_271 = not(_pmpHomogeneous_T_270) node _pmpHomogeneous_T_272 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_271) node _pmpHomogeneous_T_273 = shr(_pmpHomogeneous_T_272, 21) node _pmpHomogeneous_T_274 = neq(_pmpHomogeneous_T_273, UInt<1>(0h0)) node _pmpHomogeneous_T_275 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_T_276 = not(_pmpHomogeneous_T_275) node _pmpHomogeneous_T_277 = or(_pmpHomogeneous_T_276, UInt<2>(0h3)) node _pmpHomogeneous_T_278 = not(_pmpHomogeneous_T_277) node _pmpHomogeneous_T_279 = xor(_pmpHomogeneous_T, _pmpHomogeneous_T_278) node _pmpHomogeneous_T_280 = shr(_pmpHomogeneous_T_279, 12) node _pmpHomogeneous_T_281 = neq(_pmpHomogeneous_T_280, UInt<1>(0h0)) node _pmpHomogeneous_T_282 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_T_283 = mux(_pmpHomogeneous_T_282, _pmpHomogeneous_T_274, _pmpHomogeneous_T_267) node _pmpHomogeneous_T_284 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_T_285 = mux(_pmpHomogeneous_T_284, _pmpHomogeneous_T_281, _pmpHomogeneous_T_283) node _pmpHomogeneous_T_286 = eq(count, UInt<2>(0h3)) node _pmpHomogeneous_T_287 = mux(_pmpHomogeneous_T_286, _pmpHomogeneous_T_281, _pmpHomogeneous_T_285) node _pmpHomogeneous_T_288 = or(pmpHomogeneous_maskHomogeneous_7, _pmpHomogeneous_T_287) node _pmpHomogeneous_T_289 = bits(io.dpath.pmp[7].cfg.a, 0, 0) node _pmpHomogeneous_T_290 = eq(_pmpHomogeneous_T_289, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterLower_T_35 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_beginsAfterLower_T_36 = not(_pmpHomogeneous_beginsAfterLower_T_35) node _pmpHomogeneous_beginsAfterLower_T_37 = or(_pmpHomogeneous_beginsAfterLower_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterLower_T_38 = not(_pmpHomogeneous_beginsAfterLower_T_37) node _pmpHomogeneous_beginsAfterLower_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterLower_T_38) node pmpHomogeneous_beginsAfterLower_7 = eq(_pmpHomogeneous_beginsAfterLower_T_39, UInt<1>(0h0)) node _pmpHomogeneous_beginsAfterUpper_T_35 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_beginsAfterUpper_T_36 = not(_pmpHomogeneous_beginsAfterUpper_T_35) node _pmpHomogeneous_beginsAfterUpper_T_37 = or(_pmpHomogeneous_beginsAfterUpper_T_36, UInt<2>(0h3)) node _pmpHomogeneous_beginsAfterUpper_T_38 = not(_pmpHomogeneous_beginsAfterUpper_T_37) node _pmpHomogeneous_beginsAfterUpper_T_39 = lt(_pmpHomogeneous_T, _pmpHomogeneous_beginsAfterUpper_T_38) node pmpHomogeneous_beginsAfterUpper_7 = eq(_pmpHomogeneous_beginsAfterUpper_T_39, UInt<1>(0h0)) node _pmpHomogeneous_pgMask_T_35 = eq(count, UInt<1>(0h1)) node _pmpHomogeneous_pgMask_T_36 = mux(_pmpHomogeneous_pgMask_T_35, UInt<32>(0hffe00000), UInt<32>(0hc0000000)) node _pmpHomogeneous_pgMask_T_37 = eq(count, UInt<2>(0h2)) node _pmpHomogeneous_pgMask_T_38 = mux(_pmpHomogeneous_pgMask_T_37, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_36) node _pmpHomogeneous_pgMask_T_39 = eq(count, UInt<2>(0h3)) node pmpHomogeneous_pgMask_7 = mux(_pmpHomogeneous_pgMask_T_39, UInt<32>(0hfffff000), _pmpHomogeneous_pgMask_T_38) node _pmpHomogeneous_endsBeforeLower_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeLower_T_43 = shl(io.dpath.pmp[6].addr, 2) node _pmpHomogeneous_endsBeforeLower_T_44 = not(_pmpHomogeneous_endsBeforeLower_T_43) node _pmpHomogeneous_endsBeforeLower_T_45 = or(_pmpHomogeneous_endsBeforeLower_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeLower_T_46 = not(_pmpHomogeneous_endsBeforeLower_T_45) node _pmpHomogeneous_endsBeforeLower_T_47 = and(_pmpHomogeneous_endsBeforeLower_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeLower_7 = lt(_pmpHomogeneous_endsBeforeLower_T_42, _pmpHomogeneous_endsBeforeLower_T_47) node _pmpHomogeneous_endsBeforeUpper_T_42 = and(_pmpHomogeneous_T, pmpHomogeneous_pgMask_7) node _pmpHomogeneous_endsBeforeUpper_T_43 = shl(io.dpath.pmp[7].addr, 2) node _pmpHomogeneous_endsBeforeUpper_T_44 = not(_pmpHomogeneous_endsBeforeUpper_T_43) node _pmpHomogeneous_endsBeforeUpper_T_45 = or(_pmpHomogeneous_endsBeforeUpper_T_44, UInt<2>(0h3)) node _pmpHomogeneous_endsBeforeUpper_T_46 = not(_pmpHomogeneous_endsBeforeUpper_T_45) node _pmpHomogeneous_endsBeforeUpper_T_47 = and(_pmpHomogeneous_endsBeforeUpper_T_46, pmpHomogeneous_pgMask_7) node pmpHomogeneous_endsBeforeUpper_7 = lt(_pmpHomogeneous_endsBeforeUpper_T_42, _pmpHomogeneous_endsBeforeUpper_T_47) node _pmpHomogeneous_T_291 = or(pmpHomogeneous_endsBeforeLower_7, pmpHomogeneous_beginsAfterUpper_7) node _pmpHomogeneous_T_292 = and(pmpHomogeneous_beginsAfterLower_7, pmpHomogeneous_endsBeforeUpper_7) node _pmpHomogeneous_T_293 = or(_pmpHomogeneous_T_291, _pmpHomogeneous_T_292) node _pmpHomogeneous_T_294 = or(_pmpHomogeneous_T_290, _pmpHomogeneous_T_293) node _pmpHomogeneous_T_295 = mux(_pmpHomogeneous_T_260, _pmpHomogeneous_T_288, _pmpHomogeneous_T_294) node pmpHomogeneous = and(_pmpHomogeneous_T_259, _pmpHomogeneous_T_295) node homogeneous = and(pmaHomogeneous, pmpHomogeneous) connect io.requestor[0].resp.valid, resp_valid[0] connect io.requestor[0].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[0].resp.bits.ae_final, resp_ae_final connect io.requestor[0].resp.bits.pf, resp_pf connect io.requestor[0].resp.bits.gf, resp_gf connect io.requestor[0].resp.bits.hr, resp_hr connect io.requestor[0].resp.bits.hw, resp_hw connect io.requestor[0].resp.bits.hx, resp_hx connect io.requestor[0].resp.bits.pte, r_pte connect io.requestor[0].resp.bits.level, max_count node _io_requestor_0_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[0].resp.bits.homogeneous, _io_requestor_0_resp_bits_homogeneous_T node _io_requestor_0_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[0].resp.bits.fragmented_superpage, _io_requestor_0_resp_bits_fragmented_superpage_T connect io.requestor[0].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_0_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_0_resp_bits_gpa_bits_T_2 = or(_io_requestor_0_resp_bits_gpa_bits_T, _io_requestor_0_resp_bits_gpa_bits_T_1) node _io_requestor_0_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_0_resp_bits_gpa_bits_T_4 = or(_io_requestor_0_resp_bits_gpa_bits_T_2, _io_requestor_0_resp_bits_gpa_bits_T_3) node _io_requestor_0_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_0_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_0_resp_bits_gpa_bits_T_7 = cat(_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6) node _io_requestor_0_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_0_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_0_resp_bits_gpa_bits_T_10 = cat(_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9) node _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_0_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_0_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_0_resp_bits_gpa_bits_T_11 = eq(io_requestor_0_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_0_resp_bits_gpa_bits_T_12 = mux(_io_requestor_0_resp_bits_gpa_bits_T_11, _io_requestor_0_resp_bits_gpa_bits_T_10, _io_requestor_0_resp_bits_gpa_bits_T_7) node _io_requestor_0_resp_bits_gpa_bits_T_13 = mux(_io_requestor_0_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_0_resp_bits_gpa_bits_T_12) node _io_requestor_0_resp_bits_gpa_bits_T_14 = cat(_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[0].resp.bits.gpa.bits, _io_requestor_0_resp_bits_gpa_bits_T_14 node _io_requestor_0_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[0].resp.bits.gpa_is_pte, _io_requestor_0_resp_bits_gpa_is_pte_T connect io.requestor[0].ptbr, io.dpath.ptbr connect io.requestor[0].hgatp, io.dpath.hgatp connect io.requestor[0].vsatp, io.dpath.vsatp connect io.requestor[0].customCSRs, io.dpath.customCSRs connect io.requestor[0].status, io.dpath.status connect io.requestor[0].hstatus, io.dpath.hstatus connect io.requestor[0].gstatus, io.dpath.gstatus connect io.requestor[0].pmp, io.dpath.pmp connect io.requestor[1].resp.valid, resp_valid[1] connect io.requestor[1].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[1].resp.bits.ae_final, resp_ae_final connect io.requestor[1].resp.bits.pf, resp_pf connect io.requestor[1].resp.bits.gf, resp_gf connect io.requestor[1].resp.bits.hr, resp_hr connect io.requestor[1].resp.bits.hw, resp_hw connect io.requestor[1].resp.bits.hx, resp_hx connect io.requestor[1].resp.bits.pte, r_pte connect io.requestor[1].resp.bits.level, max_count node _io_requestor_1_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[1].resp.bits.homogeneous, _io_requestor_1_resp_bits_homogeneous_T node _io_requestor_1_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[1].resp.bits.fragmented_superpage, _io_requestor_1_resp_bits_fragmented_superpage_T connect io.requestor[1].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_1_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_1_resp_bits_gpa_bits_T_2 = or(_io_requestor_1_resp_bits_gpa_bits_T, _io_requestor_1_resp_bits_gpa_bits_T_1) node _io_requestor_1_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_1_resp_bits_gpa_bits_T_4 = or(_io_requestor_1_resp_bits_gpa_bits_T_2, _io_requestor_1_resp_bits_gpa_bits_T_3) node _io_requestor_1_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_1_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_1_resp_bits_gpa_bits_T_7 = cat(_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6) node _io_requestor_1_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_1_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_1_resp_bits_gpa_bits_T_10 = cat(_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9) node _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_1_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_1_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_1_resp_bits_gpa_bits_T_11 = eq(io_requestor_1_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_1_resp_bits_gpa_bits_T_12 = mux(_io_requestor_1_resp_bits_gpa_bits_T_11, _io_requestor_1_resp_bits_gpa_bits_T_10, _io_requestor_1_resp_bits_gpa_bits_T_7) node _io_requestor_1_resp_bits_gpa_bits_T_13 = mux(_io_requestor_1_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_1_resp_bits_gpa_bits_T_12) node _io_requestor_1_resp_bits_gpa_bits_T_14 = cat(_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[1].resp.bits.gpa.bits, _io_requestor_1_resp_bits_gpa_bits_T_14 node _io_requestor_1_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[1].resp.bits.gpa_is_pte, _io_requestor_1_resp_bits_gpa_is_pte_T connect io.requestor[1].ptbr, io.dpath.ptbr connect io.requestor[1].hgatp, io.dpath.hgatp connect io.requestor[1].vsatp, io.dpath.vsatp connect io.requestor[1].customCSRs, io.dpath.customCSRs connect io.requestor[1].status, io.dpath.status connect io.requestor[1].hstatus, io.dpath.hstatus connect io.requestor[1].gstatus, io.dpath.gstatus connect io.requestor[1].pmp, io.dpath.pmp connect io.requestor[2].resp.valid, resp_valid[2] connect io.requestor[2].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[2].resp.bits.ae_final, resp_ae_final connect io.requestor[2].resp.bits.pf, resp_pf connect io.requestor[2].resp.bits.gf, resp_gf connect io.requestor[2].resp.bits.hr, resp_hr connect io.requestor[2].resp.bits.hw, resp_hw connect io.requestor[2].resp.bits.hx, resp_hx connect io.requestor[2].resp.bits.pte, r_pte connect io.requestor[2].resp.bits.level, max_count node _io_requestor_2_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[2].resp.bits.homogeneous, _io_requestor_2_resp_bits_homogeneous_T node _io_requestor_2_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[2].resp.bits.fragmented_superpage, _io_requestor_2_resp_bits_fragmented_superpage_T connect io.requestor[2].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_2_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_2_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_2_resp_bits_gpa_bits_T_2 = or(_io_requestor_2_resp_bits_gpa_bits_T, _io_requestor_2_resp_bits_gpa_bits_T_1) node _io_requestor_2_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_2_resp_bits_gpa_bits_T_4 = or(_io_requestor_2_resp_bits_gpa_bits_T_2, _io_requestor_2_resp_bits_gpa_bits_T_3) node _io_requestor_2_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_2_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_2_resp_bits_gpa_bits_T_7 = cat(_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6) node _io_requestor_2_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_2_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_2_resp_bits_gpa_bits_T_10 = cat(_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9) node _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_2_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_2_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_2_resp_bits_gpa_bits_T_11 = eq(io_requestor_2_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_2_resp_bits_gpa_bits_T_12 = mux(_io_requestor_2_resp_bits_gpa_bits_T_11, _io_requestor_2_resp_bits_gpa_bits_T_10, _io_requestor_2_resp_bits_gpa_bits_T_7) node _io_requestor_2_resp_bits_gpa_bits_T_13 = mux(_io_requestor_2_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_2_resp_bits_gpa_bits_T_12) node _io_requestor_2_resp_bits_gpa_bits_T_14 = cat(_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[2].resp.bits.gpa.bits, _io_requestor_2_resp_bits_gpa_bits_T_14 node _io_requestor_2_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[2].resp.bits.gpa_is_pte, _io_requestor_2_resp_bits_gpa_is_pte_T connect io.requestor[2].ptbr, io.dpath.ptbr connect io.requestor[2].hgatp, io.dpath.hgatp connect io.requestor[2].vsatp, io.dpath.vsatp connect io.requestor[2].customCSRs, io.dpath.customCSRs connect io.requestor[2].status, io.dpath.status connect io.requestor[2].hstatus, io.dpath.hstatus connect io.requestor[2].gstatus, io.dpath.gstatus connect io.requestor[2].pmp, io.dpath.pmp connect io.requestor[3].resp.valid, resp_valid[3] connect io.requestor[3].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[3].resp.bits.ae_final, resp_ae_final connect io.requestor[3].resp.bits.pf, resp_pf connect io.requestor[3].resp.bits.gf, resp_gf connect io.requestor[3].resp.bits.hr, resp_hr connect io.requestor[3].resp.bits.hw, resp_hw connect io.requestor[3].resp.bits.hx, resp_hx connect io.requestor[3].resp.bits.pte, r_pte connect io.requestor[3].resp.bits.level, max_count node _io_requestor_3_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[3].resp.bits.homogeneous, _io_requestor_3_resp_bits_homogeneous_T node _io_requestor_3_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[3].resp.bits.fragmented_superpage, _io_requestor_3_resp_bits_fragmented_superpage_T connect io.requestor[3].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_3_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_3_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_3_resp_bits_gpa_bits_T_2 = or(_io_requestor_3_resp_bits_gpa_bits_T, _io_requestor_3_resp_bits_gpa_bits_T_1) node _io_requestor_3_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_3_resp_bits_gpa_bits_T_4 = or(_io_requestor_3_resp_bits_gpa_bits_T_2, _io_requestor_3_resp_bits_gpa_bits_T_3) node _io_requestor_3_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_3_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_3_resp_bits_gpa_bits_T_7 = cat(_io_requestor_3_resp_bits_gpa_bits_T_5, _io_requestor_3_resp_bits_gpa_bits_T_6) node _io_requestor_3_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_3_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_3_resp_bits_gpa_bits_T_10 = cat(_io_requestor_3_resp_bits_gpa_bits_T_8, _io_requestor_3_resp_bits_gpa_bits_T_9) node _io_requestor_3_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_3_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_3_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_3_resp_bits_gpa_bits_T_11 = eq(io_requestor_3_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_3_resp_bits_gpa_bits_T_12 = mux(_io_requestor_3_resp_bits_gpa_bits_T_11, _io_requestor_3_resp_bits_gpa_bits_T_10, _io_requestor_3_resp_bits_gpa_bits_T_7) node _io_requestor_3_resp_bits_gpa_bits_T_13 = mux(_io_requestor_3_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_3_resp_bits_gpa_bits_T_12) node _io_requestor_3_resp_bits_gpa_bits_T_14 = cat(_io_requestor_3_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[3].resp.bits.gpa.bits, _io_requestor_3_resp_bits_gpa_bits_T_14 node _io_requestor_3_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[3].resp.bits.gpa_is_pte, _io_requestor_3_resp_bits_gpa_is_pte_T connect io.requestor[3].ptbr, io.dpath.ptbr connect io.requestor[3].hgatp, io.dpath.hgatp connect io.requestor[3].vsatp, io.dpath.vsatp connect io.requestor[3].customCSRs, io.dpath.customCSRs connect io.requestor[3].status, io.dpath.status connect io.requestor[3].hstatus, io.dpath.hstatus connect io.requestor[3].gstatus, io.dpath.gstatus connect io.requestor[3].pmp, io.dpath.pmp connect io.requestor[4].resp.valid, resp_valid[4] connect io.requestor[4].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[4].resp.bits.ae_final, resp_ae_final connect io.requestor[4].resp.bits.pf, resp_pf connect io.requestor[4].resp.bits.gf, resp_gf connect io.requestor[4].resp.bits.hr, resp_hr connect io.requestor[4].resp.bits.hw, resp_hw connect io.requestor[4].resp.bits.hx, resp_hx connect io.requestor[4].resp.bits.pte, r_pte connect io.requestor[4].resp.bits.level, max_count node _io_requestor_4_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[4].resp.bits.homogeneous, _io_requestor_4_resp_bits_homogeneous_T node _io_requestor_4_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[4].resp.bits.fragmented_superpage, _io_requestor_4_resp_bits_fragmented_superpage_T connect io.requestor[4].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_4_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_4_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_4_resp_bits_gpa_bits_T_2 = or(_io_requestor_4_resp_bits_gpa_bits_T, _io_requestor_4_resp_bits_gpa_bits_T_1) node _io_requestor_4_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_4_resp_bits_gpa_bits_T_4 = or(_io_requestor_4_resp_bits_gpa_bits_T_2, _io_requestor_4_resp_bits_gpa_bits_T_3) node _io_requestor_4_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_4_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_4_resp_bits_gpa_bits_T_7 = cat(_io_requestor_4_resp_bits_gpa_bits_T_5, _io_requestor_4_resp_bits_gpa_bits_T_6) node _io_requestor_4_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_4_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_4_resp_bits_gpa_bits_T_10 = cat(_io_requestor_4_resp_bits_gpa_bits_T_8, _io_requestor_4_resp_bits_gpa_bits_T_9) node _io_requestor_4_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_4_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_4_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_4_resp_bits_gpa_bits_T_11 = eq(io_requestor_4_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_4_resp_bits_gpa_bits_T_12 = mux(_io_requestor_4_resp_bits_gpa_bits_T_11, _io_requestor_4_resp_bits_gpa_bits_T_10, _io_requestor_4_resp_bits_gpa_bits_T_7) node _io_requestor_4_resp_bits_gpa_bits_T_13 = mux(_io_requestor_4_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_4_resp_bits_gpa_bits_T_12) node _io_requestor_4_resp_bits_gpa_bits_T_14 = cat(_io_requestor_4_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[4].resp.bits.gpa.bits, _io_requestor_4_resp_bits_gpa_bits_T_14 node _io_requestor_4_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[4].resp.bits.gpa_is_pte, _io_requestor_4_resp_bits_gpa_is_pte_T connect io.requestor[4].ptbr, io.dpath.ptbr connect io.requestor[4].hgatp, io.dpath.hgatp connect io.requestor[4].vsatp, io.dpath.vsatp connect io.requestor[4].customCSRs, io.dpath.customCSRs connect io.requestor[4].status, io.dpath.status connect io.requestor[4].hstatus, io.dpath.hstatus connect io.requestor[4].gstatus, io.dpath.gstatus connect io.requestor[4].pmp, io.dpath.pmp connect io.requestor[5].resp.valid, resp_valid[5] connect io.requestor[5].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[5].resp.bits.ae_final, resp_ae_final connect io.requestor[5].resp.bits.pf, resp_pf connect io.requestor[5].resp.bits.gf, resp_gf connect io.requestor[5].resp.bits.hr, resp_hr connect io.requestor[5].resp.bits.hw, resp_hw connect io.requestor[5].resp.bits.hx, resp_hx connect io.requestor[5].resp.bits.pte, r_pte connect io.requestor[5].resp.bits.level, max_count node _io_requestor_5_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[5].resp.bits.homogeneous, _io_requestor_5_resp_bits_homogeneous_T node _io_requestor_5_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[5].resp.bits.fragmented_superpage, _io_requestor_5_resp_bits_fragmented_superpage_T connect io.requestor[5].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_5_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_5_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_5_resp_bits_gpa_bits_T_2 = or(_io_requestor_5_resp_bits_gpa_bits_T, _io_requestor_5_resp_bits_gpa_bits_T_1) node _io_requestor_5_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_5_resp_bits_gpa_bits_T_4 = or(_io_requestor_5_resp_bits_gpa_bits_T_2, _io_requestor_5_resp_bits_gpa_bits_T_3) node _io_requestor_5_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_5_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_5_resp_bits_gpa_bits_T_7 = cat(_io_requestor_5_resp_bits_gpa_bits_T_5, _io_requestor_5_resp_bits_gpa_bits_T_6) node _io_requestor_5_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_5_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_5_resp_bits_gpa_bits_T_10 = cat(_io_requestor_5_resp_bits_gpa_bits_T_8, _io_requestor_5_resp_bits_gpa_bits_T_9) node _io_requestor_5_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_5_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_5_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_5_resp_bits_gpa_bits_T_11 = eq(io_requestor_5_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_5_resp_bits_gpa_bits_T_12 = mux(_io_requestor_5_resp_bits_gpa_bits_T_11, _io_requestor_5_resp_bits_gpa_bits_T_10, _io_requestor_5_resp_bits_gpa_bits_T_7) node _io_requestor_5_resp_bits_gpa_bits_T_13 = mux(_io_requestor_5_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_5_resp_bits_gpa_bits_T_12) node _io_requestor_5_resp_bits_gpa_bits_T_14 = cat(_io_requestor_5_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[5].resp.bits.gpa.bits, _io_requestor_5_resp_bits_gpa_bits_T_14 node _io_requestor_5_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[5].resp.bits.gpa_is_pte, _io_requestor_5_resp_bits_gpa_is_pte_T connect io.requestor[5].ptbr, io.dpath.ptbr connect io.requestor[5].hgatp, io.dpath.hgatp connect io.requestor[5].vsatp, io.dpath.vsatp connect io.requestor[5].customCSRs, io.dpath.customCSRs connect io.requestor[5].status, io.dpath.status connect io.requestor[5].hstatus, io.dpath.hstatus connect io.requestor[5].gstatus, io.dpath.gstatus connect io.requestor[5].pmp, io.dpath.pmp connect io.requestor[6].resp.valid, resp_valid[6] connect io.requestor[6].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[6].resp.bits.ae_final, resp_ae_final connect io.requestor[6].resp.bits.pf, resp_pf connect io.requestor[6].resp.bits.gf, resp_gf connect io.requestor[6].resp.bits.hr, resp_hr connect io.requestor[6].resp.bits.hw, resp_hw connect io.requestor[6].resp.bits.hx, resp_hx connect io.requestor[6].resp.bits.pte, r_pte connect io.requestor[6].resp.bits.level, max_count node _io_requestor_6_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[6].resp.bits.homogeneous, _io_requestor_6_resp_bits_homogeneous_T node _io_requestor_6_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[6].resp.bits.fragmented_superpage, _io_requestor_6_resp_bits_fragmented_superpage_T connect io.requestor[6].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_6_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_6_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_6_resp_bits_gpa_bits_T_2 = or(_io_requestor_6_resp_bits_gpa_bits_T, _io_requestor_6_resp_bits_gpa_bits_T_1) node _io_requestor_6_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_6_resp_bits_gpa_bits_T_4 = or(_io_requestor_6_resp_bits_gpa_bits_T_2, _io_requestor_6_resp_bits_gpa_bits_T_3) node _io_requestor_6_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_6_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_6_resp_bits_gpa_bits_T_7 = cat(_io_requestor_6_resp_bits_gpa_bits_T_5, _io_requestor_6_resp_bits_gpa_bits_T_6) node _io_requestor_6_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_6_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_6_resp_bits_gpa_bits_T_10 = cat(_io_requestor_6_resp_bits_gpa_bits_T_8, _io_requestor_6_resp_bits_gpa_bits_T_9) node _io_requestor_6_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_6_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_6_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_6_resp_bits_gpa_bits_T_11 = eq(io_requestor_6_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_6_resp_bits_gpa_bits_T_12 = mux(_io_requestor_6_resp_bits_gpa_bits_T_11, _io_requestor_6_resp_bits_gpa_bits_T_10, _io_requestor_6_resp_bits_gpa_bits_T_7) node _io_requestor_6_resp_bits_gpa_bits_T_13 = mux(_io_requestor_6_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_6_resp_bits_gpa_bits_T_12) node _io_requestor_6_resp_bits_gpa_bits_T_14 = cat(_io_requestor_6_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[6].resp.bits.gpa.bits, _io_requestor_6_resp_bits_gpa_bits_T_14 node _io_requestor_6_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[6].resp.bits.gpa_is_pte, _io_requestor_6_resp_bits_gpa_is_pte_T connect io.requestor[6].ptbr, io.dpath.ptbr connect io.requestor[6].hgatp, io.dpath.hgatp connect io.requestor[6].vsatp, io.dpath.vsatp connect io.requestor[6].customCSRs, io.dpath.customCSRs connect io.requestor[6].status, io.dpath.status connect io.requestor[6].hstatus, io.dpath.hstatus connect io.requestor[6].gstatus, io.dpath.gstatus connect io.requestor[6].pmp, io.dpath.pmp connect io.requestor[7].resp.valid, resp_valid[7] connect io.requestor[7].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[7].resp.bits.ae_final, resp_ae_final connect io.requestor[7].resp.bits.pf, resp_pf connect io.requestor[7].resp.bits.gf, resp_gf connect io.requestor[7].resp.bits.hr, resp_hr connect io.requestor[7].resp.bits.hw, resp_hw connect io.requestor[7].resp.bits.hx, resp_hx connect io.requestor[7].resp.bits.pte, r_pte connect io.requestor[7].resp.bits.level, max_count node _io_requestor_7_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[7].resp.bits.homogeneous, _io_requestor_7_resp_bits_homogeneous_T node _io_requestor_7_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[7].resp.bits.fragmented_superpage, _io_requestor_7_resp_bits_fragmented_superpage_T connect io.requestor[7].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_7_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_7_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_7_resp_bits_gpa_bits_T_2 = or(_io_requestor_7_resp_bits_gpa_bits_T, _io_requestor_7_resp_bits_gpa_bits_T_1) node _io_requestor_7_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_7_resp_bits_gpa_bits_T_4 = or(_io_requestor_7_resp_bits_gpa_bits_T_2, _io_requestor_7_resp_bits_gpa_bits_T_3) node _io_requestor_7_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_7_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_7_resp_bits_gpa_bits_T_7 = cat(_io_requestor_7_resp_bits_gpa_bits_T_5, _io_requestor_7_resp_bits_gpa_bits_T_6) node _io_requestor_7_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_7_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_7_resp_bits_gpa_bits_T_10 = cat(_io_requestor_7_resp_bits_gpa_bits_T_8, _io_requestor_7_resp_bits_gpa_bits_T_9) node _io_requestor_7_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_7_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_7_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_7_resp_bits_gpa_bits_T_11 = eq(io_requestor_7_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_7_resp_bits_gpa_bits_T_12 = mux(_io_requestor_7_resp_bits_gpa_bits_T_11, _io_requestor_7_resp_bits_gpa_bits_T_10, _io_requestor_7_resp_bits_gpa_bits_T_7) node _io_requestor_7_resp_bits_gpa_bits_T_13 = mux(_io_requestor_7_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_7_resp_bits_gpa_bits_T_12) node _io_requestor_7_resp_bits_gpa_bits_T_14 = cat(_io_requestor_7_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[7].resp.bits.gpa.bits, _io_requestor_7_resp_bits_gpa_bits_T_14 node _io_requestor_7_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[7].resp.bits.gpa_is_pte, _io_requestor_7_resp_bits_gpa_is_pte_T connect io.requestor[7].ptbr, io.dpath.ptbr connect io.requestor[7].hgatp, io.dpath.hgatp connect io.requestor[7].vsatp, io.dpath.vsatp connect io.requestor[7].customCSRs, io.dpath.customCSRs connect io.requestor[7].status, io.dpath.status connect io.requestor[7].hstatus, io.dpath.hstatus connect io.requestor[7].gstatus, io.dpath.gstatus connect io.requestor[7].pmp, io.dpath.pmp connect io.requestor[8].resp.valid, resp_valid[8] connect io.requestor[8].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[8].resp.bits.ae_final, resp_ae_final connect io.requestor[8].resp.bits.pf, resp_pf connect io.requestor[8].resp.bits.gf, resp_gf connect io.requestor[8].resp.bits.hr, resp_hr connect io.requestor[8].resp.bits.hw, resp_hw connect io.requestor[8].resp.bits.hx, resp_hx connect io.requestor[8].resp.bits.pte, r_pte connect io.requestor[8].resp.bits.level, max_count node _io_requestor_8_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[8].resp.bits.homogeneous, _io_requestor_8_resp_bits_homogeneous_T node _io_requestor_8_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[8].resp.bits.fragmented_superpage, _io_requestor_8_resp_bits_fragmented_superpage_T connect io.requestor[8].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_8_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_8_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_8_resp_bits_gpa_bits_T_2 = or(_io_requestor_8_resp_bits_gpa_bits_T, _io_requestor_8_resp_bits_gpa_bits_T_1) node _io_requestor_8_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_8_resp_bits_gpa_bits_T_4 = or(_io_requestor_8_resp_bits_gpa_bits_T_2, _io_requestor_8_resp_bits_gpa_bits_T_3) node _io_requestor_8_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_8_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_8_resp_bits_gpa_bits_T_7 = cat(_io_requestor_8_resp_bits_gpa_bits_T_5, _io_requestor_8_resp_bits_gpa_bits_T_6) node _io_requestor_8_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_8_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_8_resp_bits_gpa_bits_T_10 = cat(_io_requestor_8_resp_bits_gpa_bits_T_8, _io_requestor_8_resp_bits_gpa_bits_T_9) node _io_requestor_8_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_8_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_8_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_8_resp_bits_gpa_bits_T_11 = eq(io_requestor_8_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_8_resp_bits_gpa_bits_T_12 = mux(_io_requestor_8_resp_bits_gpa_bits_T_11, _io_requestor_8_resp_bits_gpa_bits_T_10, _io_requestor_8_resp_bits_gpa_bits_T_7) node _io_requestor_8_resp_bits_gpa_bits_T_13 = mux(_io_requestor_8_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_8_resp_bits_gpa_bits_T_12) node _io_requestor_8_resp_bits_gpa_bits_T_14 = cat(_io_requestor_8_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[8].resp.bits.gpa.bits, _io_requestor_8_resp_bits_gpa_bits_T_14 node _io_requestor_8_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[8].resp.bits.gpa_is_pte, _io_requestor_8_resp_bits_gpa_is_pte_T connect io.requestor[8].ptbr, io.dpath.ptbr connect io.requestor[8].hgatp, io.dpath.hgatp connect io.requestor[8].vsatp, io.dpath.vsatp connect io.requestor[8].customCSRs, io.dpath.customCSRs connect io.requestor[8].status, io.dpath.status connect io.requestor[8].hstatus, io.dpath.hstatus connect io.requestor[8].gstatus, io.dpath.gstatus connect io.requestor[8].pmp, io.dpath.pmp connect io.requestor[9].resp.valid, resp_valid[9] connect io.requestor[9].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[9].resp.bits.ae_final, resp_ae_final connect io.requestor[9].resp.bits.pf, resp_pf connect io.requestor[9].resp.bits.gf, resp_gf connect io.requestor[9].resp.bits.hr, resp_hr connect io.requestor[9].resp.bits.hw, resp_hw connect io.requestor[9].resp.bits.hx, resp_hx connect io.requestor[9].resp.bits.pte, r_pte connect io.requestor[9].resp.bits.level, max_count node _io_requestor_9_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[9].resp.bits.homogeneous, _io_requestor_9_resp_bits_homogeneous_T node _io_requestor_9_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[9].resp.bits.fragmented_superpage, _io_requestor_9_resp_bits_fragmented_superpage_T connect io.requestor[9].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_9_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_9_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_9_resp_bits_gpa_bits_T_2 = or(_io_requestor_9_resp_bits_gpa_bits_T, _io_requestor_9_resp_bits_gpa_bits_T_1) node _io_requestor_9_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_9_resp_bits_gpa_bits_T_4 = or(_io_requestor_9_resp_bits_gpa_bits_T_2, _io_requestor_9_resp_bits_gpa_bits_T_3) node _io_requestor_9_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_9_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_9_resp_bits_gpa_bits_T_7 = cat(_io_requestor_9_resp_bits_gpa_bits_T_5, _io_requestor_9_resp_bits_gpa_bits_T_6) node _io_requestor_9_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_9_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_9_resp_bits_gpa_bits_T_10 = cat(_io_requestor_9_resp_bits_gpa_bits_T_8, _io_requestor_9_resp_bits_gpa_bits_T_9) node _io_requestor_9_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_9_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_9_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_9_resp_bits_gpa_bits_T_11 = eq(io_requestor_9_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_9_resp_bits_gpa_bits_T_12 = mux(_io_requestor_9_resp_bits_gpa_bits_T_11, _io_requestor_9_resp_bits_gpa_bits_T_10, _io_requestor_9_resp_bits_gpa_bits_T_7) node _io_requestor_9_resp_bits_gpa_bits_T_13 = mux(_io_requestor_9_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_9_resp_bits_gpa_bits_T_12) node _io_requestor_9_resp_bits_gpa_bits_T_14 = cat(_io_requestor_9_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[9].resp.bits.gpa.bits, _io_requestor_9_resp_bits_gpa_bits_T_14 node _io_requestor_9_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[9].resp.bits.gpa_is_pte, _io_requestor_9_resp_bits_gpa_is_pte_T connect io.requestor[9].ptbr, io.dpath.ptbr connect io.requestor[9].hgatp, io.dpath.hgatp connect io.requestor[9].vsatp, io.dpath.vsatp connect io.requestor[9].customCSRs, io.dpath.customCSRs connect io.requestor[9].status, io.dpath.status connect io.requestor[9].hstatus, io.dpath.hstatus connect io.requestor[9].gstatus, io.dpath.gstatus connect io.requestor[9].pmp, io.dpath.pmp connect io.requestor[10].resp.valid, resp_valid[10] connect io.requestor[10].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[10].resp.bits.ae_final, resp_ae_final connect io.requestor[10].resp.bits.pf, resp_pf connect io.requestor[10].resp.bits.gf, resp_gf connect io.requestor[10].resp.bits.hr, resp_hr connect io.requestor[10].resp.bits.hw, resp_hw connect io.requestor[10].resp.bits.hx, resp_hx connect io.requestor[10].resp.bits.pte, r_pte connect io.requestor[10].resp.bits.level, max_count node _io_requestor_10_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[10].resp.bits.homogeneous, _io_requestor_10_resp_bits_homogeneous_T node _io_requestor_10_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[10].resp.bits.fragmented_superpage, _io_requestor_10_resp_bits_fragmented_superpage_T connect io.requestor[10].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_10_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_10_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_10_resp_bits_gpa_bits_T_2 = or(_io_requestor_10_resp_bits_gpa_bits_T, _io_requestor_10_resp_bits_gpa_bits_T_1) node _io_requestor_10_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_10_resp_bits_gpa_bits_T_4 = or(_io_requestor_10_resp_bits_gpa_bits_T_2, _io_requestor_10_resp_bits_gpa_bits_T_3) node _io_requestor_10_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_10_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_10_resp_bits_gpa_bits_T_7 = cat(_io_requestor_10_resp_bits_gpa_bits_T_5, _io_requestor_10_resp_bits_gpa_bits_T_6) node _io_requestor_10_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_10_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_10_resp_bits_gpa_bits_T_10 = cat(_io_requestor_10_resp_bits_gpa_bits_T_8, _io_requestor_10_resp_bits_gpa_bits_T_9) node _io_requestor_10_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_10_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_10_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_10_resp_bits_gpa_bits_T_11 = eq(io_requestor_10_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_10_resp_bits_gpa_bits_T_12 = mux(_io_requestor_10_resp_bits_gpa_bits_T_11, _io_requestor_10_resp_bits_gpa_bits_T_10, _io_requestor_10_resp_bits_gpa_bits_T_7) node _io_requestor_10_resp_bits_gpa_bits_T_13 = mux(_io_requestor_10_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_10_resp_bits_gpa_bits_T_12) node _io_requestor_10_resp_bits_gpa_bits_T_14 = cat(_io_requestor_10_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[10].resp.bits.gpa.bits, _io_requestor_10_resp_bits_gpa_bits_T_14 node _io_requestor_10_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[10].resp.bits.gpa_is_pte, _io_requestor_10_resp_bits_gpa_is_pte_T connect io.requestor[10].ptbr, io.dpath.ptbr connect io.requestor[10].hgatp, io.dpath.hgatp connect io.requestor[10].vsatp, io.dpath.vsatp connect io.requestor[10].customCSRs, io.dpath.customCSRs connect io.requestor[10].status, io.dpath.status connect io.requestor[10].hstatus, io.dpath.hstatus connect io.requestor[10].gstatus, io.dpath.gstatus connect io.requestor[10].pmp, io.dpath.pmp connect io.requestor[11].resp.valid, resp_valid[11] connect io.requestor[11].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[11].resp.bits.ae_final, resp_ae_final connect io.requestor[11].resp.bits.pf, resp_pf connect io.requestor[11].resp.bits.gf, resp_gf connect io.requestor[11].resp.bits.hr, resp_hr connect io.requestor[11].resp.bits.hw, resp_hw connect io.requestor[11].resp.bits.hx, resp_hx connect io.requestor[11].resp.bits.pte, r_pte connect io.requestor[11].resp.bits.level, max_count node _io_requestor_11_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[11].resp.bits.homogeneous, _io_requestor_11_resp_bits_homogeneous_T node _io_requestor_11_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[11].resp.bits.fragmented_superpage, _io_requestor_11_resp_bits_fragmented_superpage_T connect io.requestor[11].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_11_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_11_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_11_resp_bits_gpa_bits_T_2 = or(_io_requestor_11_resp_bits_gpa_bits_T, _io_requestor_11_resp_bits_gpa_bits_T_1) node _io_requestor_11_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_11_resp_bits_gpa_bits_T_4 = or(_io_requestor_11_resp_bits_gpa_bits_T_2, _io_requestor_11_resp_bits_gpa_bits_T_3) node _io_requestor_11_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_11_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_11_resp_bits_gpa_bits_T_7 = cat(_io_requestor_11_resp_bits_gpa_bits_T_5, _io_requestor_11_resp_bits_gpa_bits_T_6) node _io_requestor_11_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_11_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_11_resp_bits_gpa_bits_T_10 = cat(_io_requestor_11_resp_bits_gpa_bits_T_8, _io_requestor_11_resp_bits_gpa_bits_T_9) node _io_requestor_11_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_11_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_11_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_11_resp_bits_gpa_bits_T_11 = eq(io_requestor_11_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_11_resp_bits_gpa_bits_T_12 = mux(_io_requestor_11_resp_bits_gpa_bits_T_11, _io_requestor_11_resp_bits_gpa_bits_T_10, _io_requestor_11_resp_bits_gpa_bits_T_7) node _io_requestor_11_resp_bits_gpa_bits_T_13 = mux(_io_requestor_11_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_11_resp_bits_gpa_bits_T_12) node _io_requestor_11_resp_bits_gpa_bits_T_14 = cat(_io_requestor_11_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[11].resp.bits.gpa.bits, _io_requestor_11_resp_bits_gpa_bits_T_14 node _io_requestor_11_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[11].resp.bits.gpa_is_pte, _io_requestor_11_resp_bits_gpa_is_pte_T connect io.requestor[11].ptbr, io.dpath.ptbr connect io.requestor[11].hgatp, io.dpath.hgatp connect io.requestor[11].vsatp, io.dpath.vsatp connect io.requestor[11].customCSRs, io.dpath.customCSRs connect io.requestor[11].status, io.dpath.status connect io.requestor[11].hstatus, io.dpath.hstatus connect io.requestor[11].gstatus, io.dpath.gstatus connect io.requestor[11].pmp, io.dpath.pmp connect io.requestor[12].resp.valid, resp_valid[12] connect io.requestor[12].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[12].resp.bits.ae_final, resp_ae_final connect io.requestor[12].resp.bits.pf, resp_pf connect io.requestor[12].resp.bits.gf, resp_gf connect io.requestor[12].resp.bits.hr, resp_hr connect io.requestor[12].resp.bits.hw, resp_hw connect io.requestor[12].resp.bits.hx, resp_hx connect io.requestor[12].resp.bits.pte, r_pte connect io.requestor[12].resp.bits.level, max_count node _io_requestor_12_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[12].resp.bits.homogeneous, _io_requestor_12_resp_bits_homogeneous_T node _io_requestor_12_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[12].resp.bits.fragmented_superpage, _io_requestor_12_resp_bits_fragmented_superpage_T connect io.requestor[12].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_12_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_12_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_12_resp_bits_gpa_bits_T_2 = or(_io_requestor_12_resp_bits_gpa_bits_T, _io_requestor_12_resp_bits_gpa_bits_T_1) node _io_requestor_12_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_12_resp_bits_gpa_bits_T_4 = or(_io_requestor_12_resp_bits_gpa_bits_T_2, _io_requestor_12_resp_bits_gpa_bits_T_3) node _io_requestor_12_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_12_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_12_resp_bits_gpa_bits_T_7 = cat(_io_requestor_12_resp_bits_gpa_bits_T_5, _io_requestor_12_resp_bits_gpa_bits_T_6) node _io_requestor_12_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_12_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_12_resp_bits_gpa_bits_T_10 = cat(_io_requestor_12_resp_bits_gpa_bits_T_8, _io_requestor_12_resp_bits_gpa_bits_T_9) node _io_requestor_12_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_12_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_12_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_12_resp_bits_gpa_bits_T_11 = eq(io_requestor_12_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_12_resp_bits_gpa_bits_T_12 = mux(_io_requestor_12_resp_bits_gpa_bits_T_11, _io_requestor_12_resp_bits_gpa_bits_T_10, _io_requestor_12_resp_bits_gpa_bits_T_7) node _io_requestor_12_resp_bits_gpa_bits_T_13 = mux(_io_requestor_12_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_12_resp_bits_gpa_bits_T_12) node _io_requestor_12_resp_bits_gpa_bits_T_14 = cat(_io_requestor_12_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[12].resp.bits.gpa.bits, _io_requestor_12_resp_bits_gpa_bits_T_14 node _io_requestor_12_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[12].resp.bits.gpa_is_pte, _io_requestor_12_resp_bits_gpa_is_pte_T connect io.requestor[12].ptbr, io.dpath.ptbr connect io.requestor[12].hgatp, io.dpath.hgatp connect io.requestor[12].vsatp, io.dpath.vsatp connect io.requestor[12].customCSRs, io.dpath.customCSRs connect io.requestor[12].status, io.dpath.status connect io.requestor[12].hstatus, io.dpath.hstatus connect io.requestor[12].gstatus, io.dpath.gstatus connect io.requestor[12].pmp, io.dpath.pmp connect io.requestor[13].resp.valid, resp_valid[13] connect io.requestor[13].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[13].resp.bits.ae_final, resp_ae_final connect io.requestor[13].resp.bits.pf, resp_pf connect io.requestor[13].resp.bits.gf, resp_gf connect io.requestor[13].resp.bits.hr, resp_hr connect io.requestor[13].resp.bits.hw, resp_hw connect io.requestor[13].resp.bits.hx, resp_hx connect io.requestor[13].resp.bits.pte, r_pte connect io.requestor[13].resp.bits.level, max_count node _io_requestor_13_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[13].resp.bits.homogeneous, _io_requestor_13_resp_bits_homogeneous_T node _io_requestor_13_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[13].resp.bits.fragmented_superpage, _io_requestor_13_resp_bits_fragmented_superpage_T connect io.requestor[13].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_13_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_13_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_13_resp_bits_gpa_bits_T_2 = or(_io_requestor_13_resp_bits_gpa_bits_T, _io_requestor_13_resp_bits_gpa_bits_T_1) node _io_requestor_13_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_13_resp_bits_gpa_bits_T_4 = or(_io_requestor_13_resp_bits_gpa_bits_T_2, _io_requestor_13_resp_bits_gpa_bits_T_3) node _io_requestor_13_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_13_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_13_resp_bits_gpa_bits_T_7 = cat(_io_requestor_13_resp_bits_gpa_bits_T_5, _io_requestor_13_resp_bits_gpa_bits_T_6) node _io_requestor_13_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_13_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_13_resp_bits_gpa_bits_T_10 = cat(_io_requestor_13_resp_bits_gpa_bits_T_8, _io_requestor_13_resp_bits_gpa_bits_T_9) node _io_requestor_13_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_13_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_13_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_13_resp_bits_gpa_bits_T_11 = eq(io_requestor_13_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_13_resp_bits_gpa_bits_T_12 = mux(_io_requestor_13_resp_bits_gpa_bits_T_11, _io_requestor_13_resp_bits_gpa_bits_T_10, _io_requestor_13_resp_bits_gpa_bits_T_7) node _io_requestor_13_resp_bits_gpa_bits_T_13 = mux(_io_requestor_13_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_13_resp_bits_gpa_bits_T_12) node _io_requestor_13_resp_bits_gpa_bits_T_14 = cat(_io_requestor_13_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[13].resp.bits.gpa.bits, _io_requestor_13_resp_bits_gpa_bits_T_14 node _io_requestor_13_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[13].resp.bits.gpa_is_pte, _io_requestor_13_resp_bits_gpa_is_pte_T connect io.requestor[13].ptbr, io.dpath.ptbr connect io.requestor[13].hgatp, io.dpath.hgatp connect io.requestor[13].vsatp, io.dpath.vsatp connect io.requestor[13].customCSRs, io.dpath.customCSRs connect io.requestor[13].status, io.dpath.status connect io.requestor[13].hstatus, io.dpath.hstatus connect io.requestor[13].gstatus, io.dpath.gstatus connect io.requestor[13].pmp, io.dpath.pmp connect io.requestor[14].resp.valid, resp_valid[14] connect io.requestor[14].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[14].resp.bits.ae_final, resp_ae_final connect io.requestor[14].resp.bits.pf, resp_pf connect io.requestor[14].resp.bits.gf, resp_gf connect io.requestor[14].resp.bits.hr, resp_hr connect io.requestor[14].resp.bits.hw, resp_hw connect io.requestor[14].resp.bits.hx, resp_hx connect io.requestor[14].resp.bits.pte, r_pte connect io.requestor[14].resp.bits.level, max_count node _io_requestor_14_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[14].resp.bits.homogeneous, _io_requestor_14_resp_bits_homogeneous_T node _io_requestor_14_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[14].resp.bits.fragmented_superpage, _io_requestor_14_resp_bits_fragmented_superpage_T connect io.requestor[14].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_14_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_14_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_14_resp_bits_gpa_bits_T_2 = or(_io_requestor_14_resp_bits_gpa_bits_T, _io_requestor_14_resp_bits_gpa_bits_T_1) node _io_requestor_14_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_14_resp_bits_gpa_bits_T_4 = or(_io_requestor_14_resp_bits_gpa_bits_T_2, _io_requestor_14_resp_bits_gpa_bits_T_3) node _io_requestor_14_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_14_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_14_resp_bits_gpa_bits_T_7 = cat(_io_requestor_14_resp_bits_gpa_bits_T_5, _io_requestor_14_resp_bits_gpa_bits_T_6) node _io_requestor_14_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_14_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_14_resp_bits_gpa_bits_T_10 = cat(_io_requestor_14_resp_bits_gpa_bits_T_8, _io_requestor_14_resp_bits_gpa_bits_T_9) node _io_requestor_14_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_14_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_14_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_14_resp_bits_gpa_bits_T_11 = eq(io_requestor_14_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_14_resp_bits_gpa_bits_T_12 = mux(_io_requestor_14_resp_bits_gpa_bits_T_11, _io_requestor_14_resp_bits_gpa_bits_T_10, _io_requestor_14_resp_bits_gpa_bits_T_7) node _io_requestor_14_resp_bits_gpa_bits_T_13 = mux(_io_requestor_14_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_14_resp_bits_gpa_bits_T_12) node _io_requestor_14_resp_bits_gpa_bits_T_14 = cat(_io_requestor_14_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[14].resp.bits.gpa.bits, _io_requestor_14_resp_bits_gpa_bits_T_14 node _io_requestor_14_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[14].resp.bits.gpa_is_pte, _io_requestor_14_resp_bits_gpa_is_pte_T connect io.requestor[14].ptbr, io.dpath.ptbr connect io.requestor[14].hgatp, io.dpath.hgatp connect io.requestor[14].vsatp, io.dpath.vsatp connect io.requestor[14].customCSRs, io.dpath.customCSRs connect io.requestor[14].status, io.dpath.status connect io.requestor[14].hstatus, io.dpath.hstatus connect io.requestor[14].gstatus, io.dpath.gstatus connect io.requestor[14].pmp, io.dpath.pmp connect io.requestor[15].resp.valid, resp_valid[15] connect io.requestor[15].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[15].resp.bits.ae_final, resp_ae_final connect io.requestor[15].resp.bits.pf, resp_pf connect io.requestor[15].resp.bits.gf, resp_gf connect io.requestor[15].resp.bits.hr, resp_hr connect io.requestor[15].resp.bits.hw, resp_hw connect io.requestor[15].resp.bits.hx, resp_hx connect io.requestor[15].resp.bits.pte, r_pte connect io.requestor[15].resp.bits.level, max_count node _io_requestor_15_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[15].resp.bits.homogeneous, _io_requestor_15_resp_bits_homogeneous_T node _io_requestor_15_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[15].resp.bits.fragmented_superpage, _io_requestor_15_resp_bits_fragmented_superpage_T connect io.requestor[15].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_15_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_15_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_15_resp_bits_gpa_bits_T_2 = or(_io_requestor_15_resp_bits_gpa_bits_T, _io_requestor_15_resp_bits_gpa_bits_T_1) node _io_requestor_15_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_15_resp_bits_gpa_bits_T_4 = or(_io_requestor_15_resp_bits_gpa_bits_T_2, _io_requestor_15_resp_bits_gpa_bits_T_3) node _io_requestor_15_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_15_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_15_resp_bits_gpa_bits_T_7 = cat(_io_requestor_15_resp_bits_gpa_bits_T_5, _io_requestor_15_resp_bits_gpa_bits_T_6) node _io_requestor_15_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_15_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_15_resp_bits_gpa_bits_T_10 = cat(_io_requestor_15_resp_bits_gpa_bits_T_8, _io_requestor_15_resp_bits_gpa_bits_T_9) node _io_requestor_15_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_15_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_15_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_15_resp_bits_gpa_bits_T_11 = eq(io_requestor_15_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_15_resp_bits_gpa_bits_T_12 = mux(_io_requestor_15_resp_bits_gpa_bits_T_11, _io_requestor_15_resp_bits_gpa_bits_T_10, _io_requestor_15_resp_bits_gpa_bits_T_7) node _io_requestor_15_resp_bits_gpa_bits_T_13 = mux(_io_requestor_15_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_15_resp_bits_gpa_bits_T_12) node _io_requestor_15_resp_bits_gpa_bits_T_14 = cat(_io_requestor_15_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[15].resp.bits.gpa.bits, _io_requestor_15_resp_bits_gpa_bits_T_14 node _io_requestor_15_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[15].resp.bits.gpa_is_pte, _io_requestor_15_resp_bits_gpa_is_pte_T connect io.requestor[15].ptbr, io.dpath.ptbr connect io.requestor[15].hgatp, io.dpath.hgatp connect io.requestor[15].vsatp, io.dpath.vsatp connect io.requestor[15].customCSRs, io.dpath.customCSRs connect io.requestor[15].status, io.dpath.status connect io.requestor[15].hstatus, io.dpath.hstatus connect io.requestor[15].gstatus, io.dpath.gstatus connect io.requestor[15].pmp, io.dpath.pmp connect io.requestor[16].resp.valid, resp_valid[16] connect io.requestor[16].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[16].resp.bits.ae_final, resp_ae_final connect io.requestor[16].resp.bits.pf, resp_pf connect io.requestor[16].resp.bits.gf, resp_gf connect io.requestor[16].resp.bits.hr, resp_hr connect io.requestor[16].resp.bits.hw, resp_hw connect io.requestor[16].resp.bits.hx, resp_hx connect io.requestor[16].resp.bits.pte, r_pte connect io.requestor[16].resp.bits.level, max_count node _io_requestor_16_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[16].resp.bits.homogeneous, _io_requestor_16_resp_bits_homogeneous_T node _io_requestor_16_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[16].resp.bits.fragmented_superpage, _io_requestor_16_resp_bits_fragmented_superpage_T connect io.requestor[16].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_16_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_16_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_16_resp_bits_gpa_bits_T_2 = or(_io_requestor_16_resp_bits_gpa_bits_T, _io_requestor_16_resp_bits_gpa_bits_T_1) node _io_requestor_16_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_16_resp_bits_gpa_bits_T_4 = or(_io_requestor_16_resp_bits_gpa_bits_T_2, _io_requestor_16_resp_bits_gpa_bits_T_3) node _io_requestor_16_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_16_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_16_resp_bits_gpa_bits_T_7 = cat(_io_requestor_16_resp_bits_gpa_bits_T_5, _io_requestor_16_resp_bits_gpa_bits_T_6) node _io_requestor_16_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_16_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_16_resp_bits_gpa_bits_T_10 = cat(_io_requestor_16_resp_bits_gpa_bits_T_8, _io_requestor_16_resp_bits_gpa_bits_T_9) node _io_requestor_16_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_16_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_16_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_16_resp_bits_gpa_bits_T_11 = eq(io_requestor_16_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_16_resp_bits_gpa_bits_T_12 = mux(_io_requestor_16_resp_bits_gpa_bits_T_11, _io_requestor_16_resp_bits_gpa_bits_T_10, _io_requestor_16_resp_bits_gpa_bits_T_7) node _io_requestor_16_resp_bits_gpa_bits_T_13 = mux(_io_requestor_16_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_16_resp_bits_gpa_bits_T_12) node _io_requestor_16_resp_bits_gpa_bits_T_14 = cat(_io_requestor_16_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[16].resp.bits.gpa.bits, _io_requestor_16_resp_bits_gpa_bits_T_14 node _io_requestor_16_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[16].resp.bits.gpa_is_pte, _io_requestor_16_resp_bits_gpa_is_pte_T connect io.requestor[16].ptbr, io.dpath.ptbr connect io.requestor[16].hgatp, io.dpath.hgatp connect io.requestor[16].vsatp, io.dpath.vsatp connect io.requestor[16].customCSRs, io.dpath.customCSRs connect io.requestor[16].status, io.dpath.status connect io.requestor[16].hstatus, io.dpath.hstatus connect io.requestor[16].gstatus, io.dpath.gstatus connect io.requestor[16].pmp, io.dpath.pmp connect io.requestor[17].resp.valid, resp_valid[17] connect io.requestor[17].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[17].resp.bits.ae_final, resp_ae_final connect io.requestor[17].resp.bits.pf, resp_pf connect io.requestor[17].resp.bits.gf, resp_gf connect io.requestor[17].resp.bits.hr, resp_hr connect io.requestor[17].resp.bits.hw, resp_hw connect io.requestor[17].resp.bits.hx, resp_hx connect io.requestor[17].resp.bits.pte, r_pte connect io.requestor[17].resp.bits.level, max_count node _io_requestor_17_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[17].resp.bits.homogeneous, _io_requestor_17_resp_bits_homogeneous_T node _io_requestor_17_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[17].resp.bits.fragmented_superpage, _io_requestor_17_resp_bits_fragmented_superpage_T connect io.requestor[17].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_17_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_17_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_17_resp_bits_gpa_bits_T_2 = or(_io_requestor_17_resp_bits_gpa_bits_T, _io_requestor_17_resp_bits_gpa_bits_T_1) node _io_requestor_17_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_17_resp_bits_gpa_bits_T_4 = or(_io_requestor_17_resp_bits_gpa_bits_T_2, _io_requestor_17_resp_bits_gpa_bits_T_3) node _io_requestor_17_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_17_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_17_resp_bits_gpa_bits_T_7 = cat(_io_requestor_17_resp_bits_gpa_bits_T_5, _io_requestor_17_resp_bits_gpa_bits_T_6) node _io_requestor_17_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_17_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_17_resp_bits_gpa_bits_T_10 = cat(_io_requestor_17_resp_bits_gpa_bits_T_8, _io_requestor_17_resp_bits_gpa_bits_T_9) node _io_requestor_17_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_17_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_17_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_17_resp_bits_gpa_bits_T_11 = eq(io_requestor_17_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_17_resp_bits_gpa_bits_T_12 = mux(_io_requestor_17_resp_bits_gpa_bits_T_11, _io_requestor_17_resp_bits_gpa_bits_T_10, _io_requestor_17_resp_bits_gpa_bits_T_7) node _io_requestor_17_resp_bits_gpa_bits_T_13 = mux(_io_requestor_17_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_17_resp_bits_gpa_bits_T_12) node _io_requestor_17_resp_bits_gpa_bits_T_14 = cat(_io_requestor_17_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[17].resp.bits.gpa.bits, _io_requestor_17_resp_bits_gpa_bits_T_14 node _io_requestor_17_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[17].resp.bits.gpa_is_pte, _io_requestor_17_resp_bits_gpa_is_pte_T connect io.requestor[17].ptbr, io.dpath.ptbr connect io.requestor[17].hgatp, io.dpath.hgatp connect io.requestor[17].vsatp, io.dpath.vsatp connect io.requestor[17].customCSRs, io.dpath.customCSRs connect io.requestor[17].status, io.dpath.status connect io.requestor[17].hstatus, io.dpath.hstatus connect io.requestor[17].gstatus, io.dpath.gstatus connect io.requestor[17].pmp, io.dpath.pmp connect io.requestor[18].resp.valid, resp_valid[18] connect io.requestor[18].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[18].resp.bits.ae_final, resp_ae_final connect io.requestor[18].resp.bits.pf, resp_pf connect io.requestor[18].resp.bits.gf, resp_gf connect io.requestor[18].resp.bits.hr, resp_hr connect io.requestor[18].resp.bits.hw, resp_hw connect io.requestor[18].resp.bits.hx, resp_hx connect io.requestor[18].resp.bits.pte, r_pte connect io.requestor[18].resp.bits.level, max_count node _io_requestor_18_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[18].resp.bits.homogeneous, _io_requestor_18_resp_bits_homogeneous_T node _io_requestor_18_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[18].resp.bits.fragmented_superpage, _io_requestor_18_resp_bits_fragmented_superpage_T connect io.requestor[18].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_18_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_18_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_18_resp_bits_gpa_bits_T_2 = or(_io_requestor_18_resp_bits_gpa_bits_T, _io_requestor_18_resp_bits_gpa_bits_T_1) node _io_requestor_18_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_18_resp_bits_gpa_bits_T_4 = or(_io_requestor_18_resp_bits_gpa_bits_T_2, _io_requestor_18_resp_bits_gpa_bits_T_3) node _io_requestor_18_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_18_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_18_resp_bits_gpa_bits_T_7 = cat(_io_requestor_18_resp_bits_gpa_bits_T_5, _io_requestor_18_resp_bits_gpa_bits_T_6) node _io_requestor_18_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_18_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_18_resp_bits_gpa_bits_T_10 = cat(_io_requestor_18_resp_bits_gpa_bits_T_8, _io_requestor_18_resp_bits_gpa_bits_T_9) node _io_requestor_18_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_18_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_18_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_18_resp_bits_gpa_bits_T_11 = eq(io_requestor_18_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_18_resp_bits_gpa_bits_T_12 = mux(_io_requestor_18_resp_bits_gpa_bits_T_11, _io_requestor_18_resp_bits_gpa_bits_T_10, _io_requestor_18_resp_bits_gpa_bits_T_7) node _io_requestor_18_resp_bits_gpa_bits_T_13 = mux(_io_requestor_18_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_18_resp_bits_gpa_bits_T_12) node _io_requestor_18_resp_bits_gpa_bits_T_14 = cat(_io_requestor_18_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[18].resp.bits.gpa.bits, _io_requestor_18_resp_bits_gpa_bits_T_14 node _io_requestor_18_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[18].resp.bits.gpa_is_pte, _io_requestor_18_resp_bits_gpa_is_pte_T connect io.requestor[18].ptbr, io.dpath.ptbr connect io.requestor[18].hgatp, io.dpath.hgatp connect io.requestor[18].vsatp, io.dpath.vsatp connect io.requestor[18].customCSRs, io.dpath.customCSRs connect io.requestor[18].status, io.dpath.status connect io.requestor[18].hstatus, io.dpath.hstatus connect io.requestor[18].gstatus, io.dpath.gstatus connect io.requestor[18].pmp, io.dpath.pmp connect io.requestor[19].resp.valid, resp_valid[19] connect io.requestor[19].resp.bits.ae_ptw, resp_ae_ptw connect io.requestor[19].resp.bits.ae_final, resp_ae_final connect io.requestor[19].resp.bits.pf, resp_pf connect io.requestor[19].resp.bits.gf, resp_gf connect io.requestor[19].resp.bits.hr, resp_hr connect io.requestor[19].resp.bits.hw, resp_hw connect io.requestor[19].resp.bits.hx, resp_hx connect io.requestor[19].resp.bits.pte, r_pte connect io.requestor[19].resp.bits.level, max_count node _io_requestor_19_resp_bits_homogeneous_T = or(homogeneous, UInt<1>(0h0)) connect io.requestor[19].resp.bits.homogeneous, _io_requestor_19_resp_bits_homogeneous_T node _io_requestor_19_resp_bits_fragmented_superpage_T = and(resp_fragmented_superpage, UInt<1>(0h0)) connect io.requestor[19].resp.bits.fragmented_superpage, _io_requestor_19_resp_bits_fragmented_superpage_T connect io.requestor[19].resp.bits.gpa.valid, r_req.need_gpa node _io_requestor_19_resp_bits_gpa_bits_T = eq(stage2_final, UInt<1>(0h0)) node _io_requestor_19_resp_bits_gpa_bits_T_1 = eq(r_req.vstage1, UInt<1>(0h0)) node _io_requestor_19_resp_bits_gpa_bits_T_2 = or(_io_requestor_19_resp_bits_gpa_bits_T, _io_requestor_19_resp_bits_gpa_bits_T_1) node _io_requestor_19_resp_bits_gpa_bits_T_3 = eq(aux_count, UInt<2>(0h2)) node _io_requestor_19_resp_bits_gpa_bits_T_4 = or(_io_requestor_19_resp_bits_gpa_bits_T_2, _io_requestor_19_resp_bits_gpa_bits_T_3) node _io_requestor_19_resp_bits_gpa_bits_T_5 = shr(aux_pte.ppn, 18) node _io_requestor_19_resp_bits_gpa_bits_T_6 = bits(r_req.addr, 17, 0) node _io_requestor_19_resp_bits_gpa_bits_T_7 = cat(_io_requestor_19_resp_bits_gpa_bits_T_5, _io_requestor_19_resp_bits_gpa_bits_T_6) node _io_requestor_19_resp_bits_gpa_bits_T_8 = shr(aux_pte.ppn, 9) node _io_requestor_19_resp_bits_gpa_bits_T_9 = bits(r_req.addr, 8, 0) node _io_requestor_19_resp_bits_gpa_bits_T_10 = cat(_io_requestor_19_resp_bits_gpa_bits_T_8, _io_requestor_19_resp_bits_gpa_bits_T_9) node _io_requestor_19_resp_bits_gpa_bits_truncIdx_T = or(aux_count, UInt<1>(0h0)) node io_requestor_19_resp_bits_gpa_bits_truncIdx = bits(_io_requestor_19_resp_bits_gpa_bits_truncIdx_T, 0, 0) node _io_requestor_19_resp_bits_gpa_bits_T_11 = eq(io_requestor_19_resp_bits_gpa_bits_truncIdx, UInt<1>(0h1)) node _io_requestor_19_resp_bits_gpa_bits_T_12 = mux(_io_requestor_19_resp_bits_gpa_bits_T_11, _io_requestor_19_resp_bits_gpa_bits_T_10, _io_requestor_19_resp_bits_gpa_bits_T_7) node _io_requestor_19_resp_bits_gpa_bits_T_13 = mux(_io_requestor_19_resp_bits_gpa_bits_T_4, aux_pte.ppn, _io_requestor_19_resp_bits_gpa_bits_T_12) node _io_requestor_19_resp_bits_gpa_bits_T_14 = cat(_io_requestor_19_resp_bits_gpa_bits_T_13, gpa_pgoff) connect io.requestor[19].resp.bits.gpa.bits, _io_requestor_19_resp_bits_gpa_bits_T_14 node _io_requestor_19_resp_bits_gpa_is_pte_T = eq(stage2_final, UInt<1>(0h0)) connect io.requestor[19].resp.bits.gpa_is_pte, _io_requestor_19_resp_bits_gpa_is_pte_T connect io.requestor[19].ptbr, io.dpath.ptbr connect io.requestor[19].hgatp, io.dpath.hgatp connect io.requestor[19].vsatp, io.dpath.vsatp connect io.requestor[19].customCSRs, io.dpath.customCSRs connect io.requestor[19].status, io.dpath.status connect io.requestor[19].hstatus, io.dpath.hstatus connect io.requestor[19].gstatus, io.dpath.gstatus connect io.requestor[19].pmp, io.dpath.pmp wire next_state : UInt connect next_state, state inst state_barrier of OptimizationBarrier_UInt connect state_barrier.clock, clock connect state_barrier.reset, reset connect state_barrier.io.x, next_state connect state, state_barrier.io.y wire do_switch : UInt<1> connect do_switch, UInt<1>(0h0) node _T_128 = eq(UInt<3>(0h0), state) when _T_128 : node _T_129 = and(arb.io.out.ready, arb.io.out.valid) when _T_129 : node _satp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _satp_initial_count_T_1 = tail(_satp_initial_count_T, 1) node _satp_initial_count_T_2 = sub(_satp_initial_count_T_1, UInt<1>(0h0)) node satp_initial_count = tail(_satp_initial_count_T_2, 1) node _vsatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _vsatp_initial_count_T_1 = tail(_vsatp_initial_count_T, 1) node _vsatp_initial_count_T_2 = sub(_vsatp_initial_count_T_1, UInt<1>(0h0)) node vsatp_initial_count = tail(_vsatp_initial_count_T_2, 1) node _hgatp_initial_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _hgatp_initial_count_T_1 = tail(_hgatp_initial_count_T, 1) node _hgatp_initial_count_T_2 = sub(_hgatp_initial_count_T_1, UInt<1>(0h0)) node hgatp_initial_count = tail(_hgatp_initial_count_T_2, 1) node aux_ppn = mux(arb.io.out.bits.bits.vstage1, io.dpath.vsatp.ppn, arb.io.out.bits.bits.addr) connect r_req, arb.io.out.bits.bits connect r_req_dest, arb.io.chosen node _next_state_T = mux(arb.io.out.bits.valid, UInt<3>(0h1), UInt<3>(0h0)) connect next_state, _next_state_T connect stage2, arb.io.out.bits.bits.stage2 node _stage2_final_T = eq(arb.io.out.bits.bits.vstage1, UInt<1>(0h0)) node _stage2_final_T_1 = and(arb.io.out.bits.bits.stage2, _stage2_final_T) connect stage2_final, _stage2_final_T_1 node _count_T_3 = mux(arb.io.out.bits.bits.stage2, hgatp_initial_count, satp_initial_count) connect count, _count_T_3 node _aux_count_T = mux(arb.io.out.bits.bits.vstage1, vsatp_initial_count, UInt<1>(0h0)) connect aux_count, _aux_count_T connect aux_pte.ppn, aux_ppn connect aux_pte.reserved_for_future, UInt<1>(0h0) connect resp_ae_ptw, UInt<1>(0h0) connect resp_ae_final, UInt<1>(0h0) connect resp_pf, UInt<1>(0h0) node _resp_gf_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _resp_gf_count_T_1 = tail(_resp_gf_count_T, 1) node _resp_gf_count_T_2 = sub(_resp_gf_count_T_1, UInt<1>(0h0)) node resp_gf_count = tail(_resp_gf_count_T_2, 1) node resp_gf_idxs_0 = shr(aux_ppn, 29) wire _resp_gf_WIRE : UInt<15>[1] connect _resp_gf_WIRE[0], resp_gf_idxs_0 node _resp_gf_T = or(resp_gf_count, UInt<0>(0h0)) node _resp_gf_T_1 = neq(_resp_gf_WIRE[0], UInt<1>(0h0)) node _resp_gf_T_2 = and(_resp_gf_T_1, arb.io.out.bits.bits.stage2) connect resp_gf, _resp_gf_T_2 connect resp_hr, UInt<1>(0h1) connect resp_hw, UInt<1>(0h1) connect resp_hx, UInt<1>(0h1) connect resp_fragmented_superpage, UInt<1>(0h0) connect r_hgatp, io.dpath.hgatp node _T_130 = eq(arb.io.out.bits.bits.need_gpa, UInt<1>(0h0)) node _T_131 = or(_T_130, arb.io.out.bits.bits.stage2) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:610 assert(!arb.io.out.bits.bits.need_gpa || arb.io.out.bits.bits.stage2)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 else : node _T_135 = eq(UInt<3>(0h1), state) when _T_135 : node _T_136 = eq(count, r_hgatp_initial_count) node _T_137 = and(stage2, _T_136) when _T_137 : node _gpa_pgoff_T = eq(aux_count, UInt<2>(0h2)) node _gpa_pgoff_T_1 = shl(r_req.addr, 3) node _gpa_pgoff_T_2 = mux(_gpa_pgoff_T, _gpa_pgoff_T_1, UInt<1>(0h0)) connect gpa_pgoff, _gpa_pgoff_T_2 when stage2_pte_cache_hit : node _aux_count_T_1 = add(aux_count, UInt<1>(0h1)) node _aux_count_T_2 = tail(_aux_count_T_1, 1) connect aux_count, _aux_count_T_2 connect aux_pte.ppn, stage2_pte_cache_data connect aux_pte.reserved_for_future, UInt<1>(0h0) connect pte_hit, UInt<1>(0h1) else : when pte_cache_hit : node _count_T_4 = add(count, UInt<1>(0h1)) node _count_T_5 = tail(_count_T_4, 1) connect count, _count_T_5 connect pte_hit, UInt<1>(0h1) else : node _next_state_T_1 = mux(io.mem.req.ready, UInt<3>(0h2), UInt<3>(0h1)) connect next_state, _next_state_T_1 when resp_gf : connect next_state, UInt<3>(0h0) node _T_138 = or(r_req_dest, UInt<5>(0h0)) node _T_139 = bits(_T_138, 4, 0) connect resp_valid[_T_139], UInt<1>(0h1) else : node _T_140 = eq(UInt<3>(0h2), state) when _T_140 : node _next_state_T_2 = mux(UInt<1>(0h0), UInt<3>(0h1), UInt<3>(0h4)) connect next_state, _next_state_T_2 else : node _T_141 = eq(UInt<3>(0h4), state) when _T_141 : connect next_state, UInt<3>(0h5) node _io_dpath_perf_pte_miss_T = lt(count, UInt<2>(0h2)) connect io.dpath.perf.pte_miss, _io_dpath_perf_pte_miss_T when io.mem.s2_xcpt.ae.ld : connect resp_ae_ptw, UInt<1>(0h1) connect next_state, UInt<3>(0h0) node _T_142 = or(r_req_dest, UInt<5>(0h0)) node _T_143 = bits(_T_142, 4, 0) connect resp_valid[_T_143], UInt<1>(0h1) else : node _T_144 = eq(UInt<3>(0h7), state) when _T_144 : connect next_state, UInt<3>(0h0) node _T_145 = or(r_req_dest, UInt<5>(0h0)) node _T_146 = bits(_T_145, 4, 0) connect resp_valid[_T_146], UInt<1>(0h1) node _T_147 = eq(homogeneous, UInt<1>(0h0)) when _T_147 : connect count, UInt<2>(0h2) connect resp_fragmented_superpage, UInt<1>(0h1) when do_both_stages : connect resp_fragmented_superpage, UInt<1>(0h1) node _merged_pte_superpage_mask_T = mux(stage2_final, max_count, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_1 = eq(_merged_pte_superpage_mask_T, UInt<1>(0h1)) node _merged_pte_superpage_mask_T_2 = mux(_merged_pte_superpage_mask_T_1, UInt<44>(0hffffffffe00), UInt<44>(0hffffffc0000)) node _merged_pte_superpage_mask_T_3 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h2)) node _merged_pte_superpage_mask_T_4 = mux(_merged_pte_superpage_mask_T_3, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_2) node _merged_pte_superpage_mask_T_5 = eq(_merged_pte_superpage_mask_T, UInt<2>(0h3)) node merged_pte_superpage_mask = mux(_merged_pte_superpage_mask_T_5, UInt<44>(0hfffffffffff), _merged_pte_superpage_mask_T_4) node _merged_pte_stage1_ppns_T = bits(pte.ppn, 43, 18) node _merged_pte_stage1_ppns_T_1 = bits(aux_pte.ppn, 17, 0) node merged_pte_stage1_ppns_0 = cat(_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1) node _merged_pte_stage1_ppns_T_2 = bits(pte.ppn, 43, 9) node _merged_pte_stage1_ppns_T_3 = bits(aux_pte.ppn, 8, 0) node merged_pte_stage1_ppns_1 = cat(_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3) node _merged_pte_stage1_ppn_T = eq(count, UInt<1>(0h1)) node _merged_pte_stage1_ppn_T_1 = mux(_merged_pte_stage1_ppn_T, merged_pte_stage1_ppns_1, merged_pte_stage1_ppns_0) node _merged_pte_stage1_ppn_T_2 = eq(count, UInt<2>(0h2)) node _merged_pte_stage1_ppn_T_3 = mux(_merged_pte_stage1_ppn_T_2, pte.ppn, _merged_pte_stage1_ppn_T_1) node _merged_pte_stage1_ppn_T_4 = eq(count, UInt<2>(0h3)) node merged_pte_stage1_ppn = mux(_merged_pte_stage1_ppn_T_4, pte.ppn, _merged_pte_stage1_ppn_T_3) node _merged_pte_T = and(merged_pte_stage1_ppn, merged_pte_superpage_mask) wire merged_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect merged_pte, aux_pte connect merged_pte.ppn, _merged_pte_T node _r_pte_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _r_pte_T_1 = and(UInt<1>(0h0), _r_pte_T) node _r_pte_T_2 = eq(resp_gf, UInt<1>(0h0)) node _r_pte_T_3 = and(_r_pte_T_1, _r_pte_T_2) node _r_pte_T_4 = eq(state, UInt<3>(0h1)) node _r_pte_T_5 = and(_r_pte_T_4, stage2_pte_cache_hit) node _r_pte_count_T = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_1 = tail(_r_pte_count_T, 1) node _r_pte_count_T_2 = sub(_r_pte_count_T_1, UInt<1>(0h0)) node r_pte_count = tail(_r_pte_count_T_2, 1) node r_pte_idxs_0 = shr(stage2_pte_cache_data, 27) wire r_pte_lsbs : UInt<2> connect r_pte_lsbs, r_pte_idxs_0 wire r_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte, l2_pte node _r_pte_pte_ppn_T = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_1 = cat(_r_pte_pte_ppn_T, r_pte_lsbs) connect r_pte_pte.ppn, _r_pte_pte_ppn_T_1 node _r_pte_T_6 = eq(state, UInt<3>(0h1)) node _r_pte_T_7 = and(_r_pte_T_6, pte_cache_hit) wire r_pte_pte_1 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_1, l2_pte connect r_pte_pte_1.ppn, pte_cache_data node _r_pte_count_T_3 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_4 = tail(_r_pte_count_T_3, 1) node _r_pte_count_T_5 = sub(_r_pte_count_T_4, UInt<1>(0h0)) node r_pte_count_1 = tail(_r_pte_count_T_5, 1) node r_pte_idxs_0_1 = shr(pte.ppn, 27) wire r_pte_lsbs_1 : UInt<2> connect r_pte_lsbs_1, r_pte_idxs_0_1 wire r_pte_pte_2 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_2, r_pte node _r_pte_pte_ppn_T_2 = shr(r_hgatp.ppn, 2) node _r_pte_pte_ppn_T_3 = cat(_r_pte_pte_ppn_T_2, r_pte_lsbs_1) connect r_pte_pte_2.ppn, _r_pte_pte_ppn_T_3 node _r_pte_T_8 = eq(traverse, UInt<1>(0h0)) node _r_pte_T_9 = and(_r_pte_T_8, r_req.vstage1) node _r_pte_T_10 = and(_r_pte_T_9, stage2) node _r_pte_T_11 = mux(_r_pte_T_10, merged_pte, pte) node _r_pte_T_12 = eq(state, UInt<3>(0h7)) node _r_pte_T_13 = eq(homogeneous, UInt<1>(0h0)) node _r_pte_T_14 = and(_r_pte_T_12, _r_pte_T_13) node _r_pte_T_15 = neq(count, UInt<2>(0h2)) node _r_pte_T_16 = and(_r_pte_T_14, _r_pte_T_15) node _r_pte_T_17 = shr(r_pte.ppn, 18) node _r_pte_T_18 = bits(r_req.addr, 17, 0) node _r_pte_T_19 = cat(_r_pte_T_17, _r_pte_T_18) node _r_pte_T_20 = shr(r_pte.ppn, 9) node _r_pte_T_21 = bits(r_req.addr, 8, 0) node _r_pte_T_22 = cat(_r_pte_T_20, _r_pte_T_21) node _r_pte_truncIdx_T = or(count, UInt<1>(0h0)) node r_pte_truncIdx = bits(_r_pte_truncIdx_T, 0, 0) node _r_pte_T_23 = eq(r_pte_truncIdx, UInt<1>(0h1)) node _r_pte_T_24 = mux(_r_pte_T_23, _r_pte_T_22, _r_pte_T_19) wire r_pte_pte_3 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_3, r_pte connect r_pte_pte_3.ppn, _r_pte_T_24 node _r_pte_T_25 = and(arb.io.out.ready, arb.io.out.valid) node _r_pte_count_T_6 = sub(UInt<2>(0h3), UInt<2>(0h3)) node _r_pte_count_T_7 = tail(_r_pte_count_T_6, 1) node _r_pte_count_T_8 = sub(_r_pte_count_T_7, UInt<1>(0h0)) node r_pte_count_2 = tail(_r_pte_count_T_8, 1) node r_pte_idxs_0_2 = shr(io.dpath.vsatp.ppn, 27) wire r_pte_lsbs_2 : UInt<2> connect r_pte_lsbs_2, r_pte_idxs_0_2 wire r_pte_pte_4 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_4, r_pte node _r_pte_pte_ppn_T_4 = shr(io.dpath.hgatp.ppn, 2) node _r_pte_pte_ppn_T_5 = cat(_r_pte_pte_ppn_T_4, r_pte_lsbs_2) connect r_pte_pte_4.ppn, _r_pte_pte_ppn_T_5 wire r_pte_pte_5 : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect r_pte_pte_5, r_pte connect r_pte_pte_5.ppn, satp.ppn node _r_pte_T_26 = mux(arb.io.out.bits.bits.stage2, r_pte_pte_4, r_pte_pte_5) node _r_pte_T_27 = mux(_r_pte_T_25, _r_pte_T_26, r_pte) node _r_pte_T_28 = mux(_r_pte_T_16, r_pte_pte_3, _r_pte_T_27) node _r_pte_T_29 = mux(mem_resp_valid, _r_pte_T_11, _r_pte_T_28) node _r_pte_T_30 = mux(do_switch, r_pte_pte_2, _r_pte_T_29) node _r_pte_T_31 = mux(_r_pte_T_7, r_pte_pte_1, _r_pte_T_30) node _r_pte_T_32 = mux(_r_pte_T_5, r_pte_pte, _r_pte_T_31) node _r_pte_T_33 = mux(_r_pte_T_3, l2_pte, _r_pte_T_32) inst r_pte_barrier of OptimizationBarrier_PTE connect r_pte_barrier.clock, clock connect r_pte_barrier.reset, reset connect r_pte_barrier.io.x.v, _r_pte_T_33.v connect r_pte_barrier.io.x.r, _r_pte_T_33.r connect r_pte_barrier.io.x.w, _r_pte_T_33.w connect r_pte_barrier.io.x.x, _r_pte_T_33.x connect r_pte_barrier.io.x.u, _r_pte_T_33.u connect r_pte_barrier.io.x.g, _r_pte_T_33.g connect r_pte_barrier.io.x.a, _r_pte_T_33.a connect r_pte_barrier.io.x.d, _r_pte_T_33.d connect r_pte_barrier.io.x.reserved_for_software, _r_pte_T_33.reserved_for_software connect r_pte_barrier.io.x.ppn, _r_pte_T_33.ppn connect r_pte_barrier.io.x.reserved_for_future, _r_pte_T_33.reserved_for_future connect r_pte, r_pte_barrier.io.y node _T_148 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_149 = and(UInt<1>(0h0), _T_148) node _T_150 = eq(resp_gf, UInt<1>(0h0)) node _T_151 = and(_T_149, _T_150) when _T_151 : node _T_152 = eq(state, UInt<3>(0h1)) node _T_153 = eq(state, UInt<3>(0h2)) node _T_154 = or(_T_152, _T_153) node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_T_154, UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:686 assert(state === s_req || state === s_wait1)\n") : printf_2 assert(clock, _T_154, UInt<1>(0h1), "") : assert_2 connect next_state, UInt<3>(0h0) node _T_158 = or(r_req_dest, UInt<5>(0h0)) node _T_159 = bits(_T_158, 4, 0) connect resp_valid[_T_159], UInt<1>(0h1) connect count, UInt<2>(0h2) when mem_resp_valid : node _T_160 = eq(state, UInt<3>(0h5)) node _T_161 = asUInt(reset) node _T_162 = eq(_T_161, UInt<1>(0h0)) when _T_162 : node _T_163 = eq(_T_160, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:692 assert(state === s_wait3)\n") : printf_3 assert(clock, _T_160, UInt<1>(0h1), "") : assert_3 connect next_state, UInt<3>(0h1) when traverse : node _T_164 = eq(stage2, UInt<1>(0h0)) node _T_165 = and(do_both_stages, _T_164) when _T_165 : connect do_switch, UInt<1>(0h1) node _count_T_6 = add(count, UInt<1>(0h1)) node _count_T_7 = tail(_count_T_6, 1) connect count, _count_T_7 else : node _gf_T = eq(stage2_final, UInt<1>(0h0)) node _gf_T_1 = and(stage2, _gf_T) node _gf_T_2 = eq(pte.w, UInt<1>(0h0)) node _gf_T_3 = and(pte.x, _gf_T_2) node _gf_T_4 = or(pte.r, _gf_T_3) node _gf_T_5 = and(pte.v, _gf_T_4) node _gf_T_6 = and(_gf_T_5, pte.a) node _gf_T_7 = and(_gf_T_6, pte.r) node _gf_T_8 = and(_gf_T_7, pte.u) node _gf_T_9 = eq(_gf_T_8, UInt<1>(0h0)) node _gf_T_10 = and(_gf_T_1, _gf_T_9) node _gf_T_11 = eq(pte.w, UInt<1>(0h0)) node _gf_T_12 = and(pte.x, _gf_T_11) node _gf_T_13 = or(pte.r, _gf_T_12) node _gf_T_14 = and(pte.v, _gf_T_13) node _gf_T_15 = and(_gf_T_14, pte.a) node _gf_T_16 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _gf_T_17 = and(_gf_T_15, _gf_T_16) node _gf_T_18 = and(_gf_T_17, invalid_gpa) node gf = or(_gf_T_10, _gf_T_18) node ae = and(pte.v, invalid_paddr) node _pf_T = neq(pte.reserved_for_future, UInt<1>(0h0)) node pf = and(pte.v, _pf_T) node _success_T = eq(ae, UInt<1>(0h0)) node _success_T_1 = and(pte.v, _success_T) node _success_T_2 = eq(pf, UInt<1>(0h0)) node _success_T_3 = and(_success_T_1, _success_T_2) node _success_T_4 = eq(gf, UInt<1>(0h0)) node success = and(_success_T_3, _success_T_4) node _T_166 = eq(stage2_final, UInt<1>(0h0)) node _T_167 = and(do_both_stages, _T_166) node _T_168 = and(_T_167, success) when _T_168 : when stage2 : connect stage2, UInt<1>(0h0) connect count, aux_count else : connect stage2_final, UInt<1>(0h1) connect do_switch, UInt<1>(0h1) else : node _l2_refill_T = eq(count, UInt<2>(0h2)) node _l2_refill_T_1 = and(success, _l2_refill_T) node _l2_refill_T_2 = eq(r_req.need_gpa, UInt<1>(0h0)) node _l2_refill_T_3 = and(_l2_refill_T_1, _l2_refill_T_2) node _l2_refill_T_4 = eq(r_req.vstage1, UInt<1>(0h0)) node _l2_refill_T_5 = eq(r_req.stage2, UInt<1>(0h0)) node _l2_refill_T_6 = and(_l2_refill_T_4, _l2_refill_T_5) node _l2_refill_T_7 = eq(aux_count, UInt<2>(0h2)) node _l2_refill_T_8 = and(do_both_stages, _l2_refill_T_7) node _l2_refill_T_9 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_10 = and(pte.x, _l2_refill_T_9) node _l2_refill_T_11 = or(pte.r, _l2_refill_T_10) node _l2_refill_T_12 = and(pte.v, _l2_refill_T_11) node _l2_refill_T_13 = and(_l2_refill_T_12, pte.a) node _l2_refill_T_14 = and(_l2_refill_T_13, pte.w) node _l2_refill_T_15 = and(_l2_refill_T_14, pte.d) node _l2_refill_T_16 = and(_l2_refill_T_15, pte.u) node _l2_refill_T_17 = eq(pte.w, UInt<1>(0h0)) node _l2_refill_T_18 = and(pte.x, _l2_refill_T_17) node _l2_refill_T_19 = or(pte.r, _l2_refill_T_18) node _l2_refill_T_20 = and(pte.v, _l2_refill_T_19) node _l2_refill_T_21 = and(_l2_refill_T_20, pte.a) node _l2_refill_T_22 = and(_l2_refill_T_21, pte.x) node _l2_refill_T_23 = and(_l2_refill_T_22, pte.u) node _l2_refill_T_24 = and(_l2_refill_T_16, _l2_refill_T_23) node _l2_refill_T_25 = and(_l2_refill_T_8, _l2_refill_T_24) node _l2_refill_T_26 = or(_l2_refill_T_6, _l2_refill_T_25) node _l2_refill_T_27 = and(_l2_refill_T_3, _l2_refill_T_26) connect l2_refill, _l2_refill_T_27 connect count, max_count node _T_169 = eq(count, UInt<2>(0h2)) node _T_170 = eq(do_both_stages, UInt<1>(0h0)) node _T_171 = eq(aux_count, UInt<2>(0h2)) node _T_172 = or(_T_170, _T_171) node _T_173 = and(_T_169, _T_172) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = and(UInt<1>(0h0), _T_174) when _T_175 : connect next_state, UInt<3>(0h7) else : connect next_state, UInt<3>(0h0) node _T_176 = or(r_req_dest, UInt<5>(0h0)) node _T_177 = bits(_T_176, 4, 0) connect resp_valid[_T_177], UInt<1>(0h1) node _resp_ae_ptw_T = lt(count, UInt<2>(0h2)) node _resp_ae_ptw_T_1 = and(ae, _resp_ae_ptw_T) node _resp_ae_ptw_T_2 = eq(pte.r, UInt<1>(0h0)) node _resp_ae_ptw_T_3 = and(pte.v, _resp_ae_ptw_T_2) node _resp_ae_ptw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_ae_ptw_T_5 = and(_resp_ae_ptw_T_3, _resp_ae_ptw_T_4) node _resp_ae_ptw_T_6 = eq(pte.x, UInt<1>(0h0)) node _resp_ae_ptw_T_7 = and(_resp_ae_ptw_T_5, _resp_ae_ptw_T_6) node _resp_ae_ptw_T_8 = eq(pte.d, UInt<1>(0h0)) node _resp_ae_ptw_T_9 = and(_resp_ae_ptw_T_7, _resp_ae_ptw_T_8) node _resp_ae_ptw_T_10 = eq(pte.a, UInt<1>(0h0)) node _resp_ae_ptw_T_11 = and(_resp_ae_ptw_T_9, _resp_ae_ptw_T_10) node _resp_ae_ptw_T_12 = eq(pte.u, UInt<1>(0h0)) node _resp_ae_ptw_T_13 = and(_resp_ae_ptw_T_11, _resp_ae_ptw_T_12) node _resp_ae_ptw_T_14 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _resp_ae_ptw_T_15 = and(_resp_ae_ptw_T_13, _resp_ae_ptw_T_14) node _resp_ae_ptw_T_16 = and(_resp_ae_ptw_T_1, _resp_ae_ptw_T_15) connect resp_ae_ptw, _resp_ae_ptw_T_16 node _resp_ae_final_T = eq(pte.w, UInt<1>(0h0)) node _resp_ae_final_T_1 = and(pte.x, _resp_ae_final_T) node _resp_ae_final_T_2 = or(pte.r, _resp_ae_final_T_1) node _resp_ae_final_T_3 = and(pte.v, _resp_ae_final_T_2) node _resp_ae_final_T_4 = and(_resp_ae_final_T_3, pte.a) node _resp_ae_final_T_5 = and(ae, _resp_ae_final_T_4) connect resp_ae_final, _resp_ae_final_T_5 node _resp_pf_T = eq(stage2, UInt<1>(0h0)) node _resp_pf_T_1 = and(pf, _resp_pf_T) connect resp_pf, _resp_pf_T_1 node _resp_gf_T_3 = and(pf, stage2) node _resp_gf_T_4 = or(gf, _resp_gf_T_3) connect resp_gf, _resp_gf_T_4 node _resp_hr_T = eq(stage2, UInt<1>(0h0)) node _resp_hr_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hr_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hr_T_3 = and(_resp_hr_T_1, _resp_hr_T_2) node _resp_hr_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hr_T_5 = and(pte.x, _resp_hr_T_4) node _resp_hr_T_6 = or(pte.r, _resp_hr_T_5) node _resp_hr_T_7 = and(pte.v, _resp_hr_T_6) node _resp_hr_T_8 = and(_resp_hr_T_7, pte.a) node _resp_hr_T_9 = and(_resp_hr_T_8, pte.r) node _resp_hr_T_10 = and(_resp_hr_T_9, pte.u) node _resp_hr_T_11 = and(_resp_hr_T_3, _resp_hr_T_10) node _resp_hr_T_12 = or(_resp_hr_T, _resp_hr_T_11) connect resp_hr, _resp_hr_T_12 node _resp_hw_T = eq(stage2, UInt<1>(0h0)) node _resp_hw_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hw_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hw_T_3 = and(_resp_hw_T_1, _resp_hw_T_2) node _resp_hw_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hw_T_5 = and(pte.x, _resp_hw_T_4) node _resp_hw_T_6 = or(pte.r, _resp_hw_T_5) node _resp_hw_T_7 = and(pte.v, _resp_hw_T_6) node _resp_hw_T_8 = and(_resp_hw_T_7, pte.a) node _resp_hw_T_9 = and(_resp_hw_T_8, pte.w) node _resp_hw_T_10 = and(_resp_hw_T_9, pte.d) node _resp_hw_T_11 = and(_resp_hw_T_10, pte.u) node _resp_hw_T_12 = and(_resp_hw_T_3, _resp_hw_T_11) node _resp_hw_T_13 = or(_resp_hw_T, _resp_hw_T_12) connect resp_hw, _resp_hw_T_13 node _resp_hx_T = eq(stage2, UInt<1>(0h0)) node _resp_hx_T_1 = eq(pf, UInt<1>(0h0)) node _resp_hx_T_2 = eq(gf, UInt<1>(0h0)) node _resp_hx_T_3 = and(_resp_hx_T_1, _resp_hx_T_2) node _resp_hx_T_4 = eq(pte.w, UInt<1>(0h0)) node _resp_hx_T_5 = and(pte.x, _resp_hx_T_4) node _resp_hx_T_6 = or(pte.r, _resp_hx_T_5) node _resp_hx_T_7 = and(pte.v, _resp_hx_T_6) node _resp_hx_T_8 = and(_resp_hx_T_7, pte.a) node _resp_hx_T_9 = and(_resp_hx_T_8, pte.x) node _resp_hx_T_10 = and(_resp_hx_T_9, pte.u) node _resp_hx_T_11 = and(_resp_hx_T_3, _resp_hx_T_10) node _resp_hx_T_12 = or(_resp_hx_T, _resp_hx_T_11) connect resp_hx, _resp_hx_T_12 when io.mem.s2_nack : node _T_178 = eq(state, UInt<3>(0h4)) node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_T_178, UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed\n at PTW.scala:736 assert(state === s_wait2)\n") : printf_4 assert(clock, _T_178, UInt<1>(0h1), "") : assert_4 connect next_state, UInt<3>(0h1) when do_switch : node _aux_count_T_3 = add(count, UInt<1>(0h1)) node _aux_count_T_4 = tail(_aux_count_T_3, 1) node _aux_count_T_5 = mux(traverse, _aux_count_T_4, count) connect aux_count, _aux_count_T_5 connect count, r_hgatp_initial_count node _aux_pte_s1_ppns_T = bits(pte.ppn, 43, 18) node _aux_pte_s1_ppns_T_1 = bits(r_req.addr, 17, 0) node aux_pte_s1_ppns_0 = cat(_aux_pte_s1_ppns_T, _aux_pte_s1_ppns_T_1) node _aux_pte_s1_ppns_T_2 = bits(pte.ppn, 43, 9) node _aux_pte_s1_ppns_T_3 = bits(r_req.addr, 8, 0) node aux_pte_s1_ppns_1 = cat(_aux_pte_s1_ppns_T_2, _aux_pte_s1_ppns_T_3) node _aux_pte_T = eq(count, UInt<1>(0h1)) node _aux_pte_T_1 = mux(_aux_pte_T, aux_pte_s1_ppns_1, aux_pte_s1_ppns_0) node _aux_pte_T_2 = eq(count, UInt<2>(0h2)) node _aux_pte_T_3 = mux(_aux_pte_T_2, pte.ppn, _aux_pte_T_1) node _aux_pte_T_4 = eq(count, UInt<2>(0h3)) node _aux_pte_T_5 = mux(_aux_pte_T_4, pte.ppn, _aux_pte_T_3) wire aux_pte_pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>} connect aux_pte_pte, pte connect aux_pte_pte.ppn, _aux_pte_T_5 node _aux_pte_T_6 = mux(traverse, pte, aux_pte_pte) connect aux_pte, _aux_pte_T_6 connect stage2, UInt<1>(0h1) node _leaf_T = eq(traverse, UInt<1>(0h0)) node _leaf_T_1 = and(mem_resp_valid, _leaf_T) node _leaf_T_2 = eq(count, UInt<1>(0h0)) node leaf = and(_leaf_T_1, _leaf_T_2) node _T_182 = and(leaf, pte.v) node _T_183 = eq(invalid_paddr, UInt<1>(0h0)) node _T_184 = and(_T_182, _T_183) node _T_185 = eq(invalid_gpa, UInt<1>(0h0)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = and(leaf, pte.v) node _T_190 = and(_T_189, invalid_paddr) node _T_191 = and(leaf, pte.v) node _T_192 = and(_T_191, invalid_gpa) node _T_193 = and(leaf, pte.v) node _T_194 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_195 = and(_T_193, _T_194) node _T_196 = bits(mem_resp_data, 0, 0) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = and(leaf, _T_197) node _T_199 = eq(pte.v, UInt<1>(0h0)) node _T_200 = and(leaf, _T_199) node _T_201 = bits(mem_resp_data, 0, 0) node _T_202 = and(_T_200, _T_201) node _leaf_T_3 = eq(traverse, UInt<1>(0h0)) node _leaf_T_4 = and(mem_resp_valid, _leaf_T_3) node _leaf_T_5 = eq(count, UInt<1>(0h1)) node leaf_1 = and(_leaf_T_4, _leaf_T_5) node _T_203 = and(leaf_1, pte.v) node _T_204 = eq(invalid_paddr, UInt<1>(0h0)) node _T_205 = and(_T_203, _T_204) node _T_206 = eq(invalid_gpa, UInt<1>(0h0)) node _T_207 = and(_T_205, _T_206) node _T_208 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_209 = and(_T_207, _T_208) node _T_210 = and(leaf_1, pte.v) node _T_211 = and(_T_210, invalid_paddr) node _T_212 = and(leaf_1, pte.v) node _T_213 = and(_T_212, invalid_gpa) node _T_214 = and(leaf_1, pte.v) node _T_215 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_216 = and(_T_214, _T_215) node _T_217 = bits(mem_resp_data, 0, 0) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = and(leaf_1, _T_218) node _T_220 = eq(pte.v, UInt<1>(0h0)) node _T_221 = and(leaf_1, _T_220) node _T_222 = bits(mem_resp_data, 0, 0) node _T_223 = and(_T_221, _T_222) node _leaf_T_6 = eq(traverse, UInt<1>(0h0)) node _leaf_T_7 = and(mem_resp_valid, _leaf_T_6) node _leaf_T_8 = eq(count, UInt<2>(0h2)) node leaf_2 = and(_leaf_T_7, _leaf_T_8) node _T_224 = and(leaf_2, pte.v) node _T_225 = eq(invalid_paddr, UInt<1>(0h0)) node _T_226 = and(_T_224, _T_225) node _T_227 = eq(invalid_gpa, UInt<1>(0h0)) node _T_228 = and(_T_226, _T_227) node _T_229 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_230 = and(_T_228, _T_229) node _T_231 = and(leaf_2, pte.v) node _T_232 = and(_T_231, invalid_paddr) node _T_233 = and(leaf_2, pte.v) node _T_234 = and(_T_233, invalid_gpa) node _T_235 = and(leaf_2, pte.v) node _T_236 = neq(pte.reserved_for_future, UInt<1>(0h0)) node _T_237 = and(_T_235, _T_236) node _T_238 = bits(mem_resp_data, 0, 0) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = and(leaf_2, _T_239) node _T_241 = eq(count, UInt<2>(0h2)) node _T_242 = and(mem_resp_valid, _T_241) node _T_243 = eq(pte.r, UInt<1>(0h0)) node _T_244 = and(pte.v, _T_243) node _T_245 = eq(pte.w, UInt<1>(0h0)) node _T_246 = and(_T_244, _T_245) node _T_247 = eq(pte.x, UInt<1>(0h0)) node _T_248 = and(_T_246, _T_247) node _T_249 = eq(pte.d, UInt<1>(0h0)) node _T_250 = and(_T_248, _T_249) node _T_251 = eq(pte.a, UInt<1>(0h0)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(pte.u, UInt<1>(0h0)) node _T_254 = and(_T_252, _T_253) node _T_255 = eq(pte.reserved_for_future, UInt<1>(0h0)) node _T_256 = and(_T_254, _T_255) node _T_257 = and(_T_242, _T_256) node _T_258 = eq(state, UInt<3>(0h4)) node _T_259 = and(_T_258, io.mem.s2_xcpt.ae.ld)
module PTW( // @[PTW.scala:219:7] input clock, // @[PTW.scala:219:7] input reset, // @[PTW.scala:219:7] output io_requestor_0_req_ready, // @[PTW.scala:220:14] input io_requestor_0_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_0_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_0_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_0_resp_valid, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_0_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_0_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_0_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_0_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_0_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_0_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_0_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_0_status_debug, // @[PTW.scala:220:14] output io_requestor_0_status_cease, // @[PTW.scala:220:14] output io_requestor_0_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_dprv, // @[PTW.scala:220:14] output io_requestor_0_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_prv, // @[PTW.scala:220:14] output io_requestor_0_status_v, // @[PTW.scala:220:14] output io_requestor_0_status_mpv, // @[PTW.scala:220:14] output io_requestor_0_status_gva, // @[PTW.scala:220:14] output io_requestor_0_status_tsr, // @[PTW.scala:220:14] output io_requestor_0_status_tw, // @[PTW.scala:220:14] output io_requestor_0_status_tvm, // @[PTW.scala:220:14] output io_requestor_0_status_mxr, // @[PTW.scala:220:14] output io_requestor_0_status_sum, // @[PTW.scala:220:14] output io_requestor_0_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_status_mpp, // @[PTW.scala:220:14] output io_requestor_0_status_spp, // @[PTW.scala:220:14] output io_requestor_0_status_mpie, // @[PTW.scala:220:14] output io_requestor_0_status_spie, // @[PTW.scala:220:14] output io_requestor_0_status_mie, // @[PTW.scala:220:14] output io_requestor_0_status_sie, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_0_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_0_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_0_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_0_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_0_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_0_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_0_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_0_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_0_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_0_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_0_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_0_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_0_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_0_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_0_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_0_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_0_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_0_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_1_req_ready, // @[PTW.scala:220:14] input io_requestor_1_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_1_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_1_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_1_resp_valid, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_1_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_1_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_1_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_1_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_1_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_1_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_1_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_1_status_debug, // @[PTW.scala:220:14] output io_requestor_1_status_cease, // @[PTW.scala:220:14] output io_requestor_1_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_dprv, // @[PTW.scala:220:14] output io_requestor_1_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_prv, // @[PTW.scala:220:14] output io_requestor_1_status_v, // @[PTW.scala:220:14] output io_requestor_1_status_mpv, // @[PTW.scala:220:14] output io_requestor_1_status_gva, // @[PTW.scala:220:14] output io_requestor_1_status_tsr, // @[PTW.scala:220:14] output io_requestor_1_status_tw, // @[PTW.scala:220:14] output io_requestor_1_status_tvm, // @[PTW.scala:220:14] output io_requestor_1_status_mxr, // @[PTW.scala:220:14] output io_requestor_1_status_sum, // @[PTW.scala:220:14] output io_requestor_1_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_status_mpp, // @[PTW.scala:220:14] output io_requestor_1_status_spp, // @[PTW.scala:220:14] output io_requestor_1_status_mpie, // @[PTW.scala:220:14] output io_requestor_1_status_spie, // @[PTW.scala:220:14] output io_requestor_1_status_mie, // @[PTW.scala:220:14] output io_requestor_1_status_sie, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_1_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_1_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_1_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_1_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_1_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_1_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_1_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_1_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_1_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_1_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_1_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_1_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_1_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_1_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_1_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_1_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_1_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_1_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_2_req_ready, // @[PTW.scala:220:14] input io_requestor_2_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_2_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_2_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_2_resp_valid, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_2_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_2_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_2_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_2_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_2_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_2_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_2_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_2_status_debug, // @[PTW.scala:220:14] output io_requestor_2_status_cease, // @[PTW.scala:220:14] output io_requestor_2_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_2_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_dprv, // @[PTW.scala:220:14] output io_requestor_2_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_prv, // @[PTW.scala:220:14] output io_requestor_2_status_v, // @[PTW.scala:220:14] output io_requestor_2_status_mpv, // @[PTW.scala:220:14] output io_requestor_2_status_gva, // @[PTW.scala:220:14] output io_requestor_2_status_tsr, // @[PTW.scala:220:14] output io_requestor_2_status_tw, // @[PTW.scala:220:14] output io_requestor_2_status_tvm, // @[PTW.scala:220:14] output io_requestor_2_status_mxr, // @[PTW.scala:220:14] output io_requestor_2_status_sum, // @[PTW.scala:220:14] output io_requestor_2_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_status_mpp, // @[PTW.scala:220:14] output io_requestor_2_status_spp, // @[PTW.scala:220:14] output io_requestor_2_status_mpie, // @[PTW.scala:220:14] output io_requestor_2_status_spie, // @[PTW.scala:220:14] output io_requestor_2_status_mie, // @[PTW.scala:220:14] output io_requestor_2_status_sie, // @[PTW.scala:220:14] output io_requestor_2_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_2_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_2_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_2_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_2_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_2_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_2_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_2_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_2_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_2_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_2_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_2_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_2_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_2_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_2_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_2_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_2_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_2_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_2_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_2_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_2_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_2_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_2_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_2_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_2_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_2_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_2_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_3_req_ready, // @[PTW.scala:220:14] input io_requestor_3_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_3_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_3_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_3_resp_valid, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_3_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_3_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_3_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_3_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_3_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_3_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_3_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_3_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_3_status_debug, // @[PTW.scala:220:14] output io_requestor_3_status_cease, // @[PTW.scala:220:14] output io_requestor_3_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_3_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_dprv, // @[PTW.scala:220:14] output io_requestor_3_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_prv, // @[PTW.scala:220:14] output io_requestor_3_status_v, // @[PTW.scala:220:14] output io_requestor_3_status_mpv, // @[PTW.scala:220:14] output io_requestor_3_status_gva, // @[PTW.scala:220:14] output io_requestor_3_status_tsr, // @[PTW.scala:220:14] output io_requestor_3_status_tw, // @[PTW.scala:220:14] output io_requestor_3_status_tvm, // @[PTW.scala:220:14] output io_requestor_3_status_mxr, // @[PTW.scala:220:14] output io_requestor_3_status_sum, // @[PTW.scala:220:14] output io_requestor_3_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_3_status_mpp, // @[PTW.scala:220:14] output io_requestor_3_status_spp, // @[PTW.scala:220:14] output io_requestor_3_status_mpie, // @[PTW.scala:220:14] output io_requestor_3_status_spie, // @[PTW.scala:220:14] output io_requestor_3_status_mie, // @[PTW.scala:220:14] output io_requestor_3_status_sie, // @[PTW.scala:220:14] output io_requestor_3_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_3_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_3_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_3_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_3_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_3_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_3_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_3_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_3_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_3_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_3_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_3_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_3_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_3_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_3_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_3_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_3_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_3_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_3_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_3_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_3_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_3_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_3_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_3_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_3_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_3_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_3_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_4_req_ready, // @[PTW.scala:220:14] input io_requestor_4_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_4_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_4_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_4_resp_valid, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_4_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_4_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_4_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_4_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_4_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_4_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_4_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_4_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_4_status_debug, // @[PTW.scala:220:14] output io_requestor_4_status_cease, // @[PTW.scala:220:14] output io_requestor_4_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_4_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_4_status_dprv, // @[PTW.scala:220:14] output io_requestor_4_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_4_status_prv, // @[PTW.scala:220:14] output io_requestor_4_status_v, // @[PTW.scala:220:14] output io_requestor_4_status_mpv, // @[PTW.scala:220:14] output io_requestor_4_status_gva, // @[PTW.scala:220:14] output io_requestor_4_status_tsr, // @[PTW.scala:220:14] output io_requestor_4_status_tw, // @[PTW.scala:220:14] output io_requestor_4_status_tvm, // @[PTW.scala:220:14] output io_requestor_4_status_mxr, // @[PTW.scala:220:14] output io_requestor_4_status_sum, // @[PTW.scala:220:14] output io_requestor_4_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_4_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_4_status_mpp, // @[PTW.scala:220:14] output io_requestor_4_status_spp, // @[PTW.scala:220:14] output io_requestor_4_status_mpie, // @[PTW.scala:220:14] output io_requestor_4_status_spie, // @[PTW.scala:220:14] output io_requestor_4_status_mie, // @[PTW.scala:220:14] output io_requestor_4_status_sie, // @[PTW.scala:220:14] output io_requestor_4_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_4_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_4_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_4_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_4_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_4_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_4_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_4_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_4_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_4_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_4_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_4_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_4_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_4_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_4_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_4_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_4_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_4_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_4_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_4_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_4_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_4_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_4_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_4_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_4_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_4_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_4_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_4_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_4_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_4_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_4_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_4_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_4_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_4_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_4_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_4_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_4_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_4_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_4_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_4_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_4_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_4_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_4_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_4_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_4_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_4_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_5_req_ready, // @[PTW.scala:220:14] input io_requestor_5_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_5_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_5_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_5_resp_valid, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_5_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_5_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_5_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_5_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_5_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_5_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_5_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_5_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_5_status_debug, // @[PTW.scala:220:14] output io_requestor_5_status_cease, // @[PTW.scala:220:14] output io_requestor_5_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_5_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_5_status_dprv, // @[PTW.scala:220:14] output io_requestor_5_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_5_status_prv, // @[PTW.scala:220:14] output io_requestor_5_status_v, // @[PTW.scala:220:14] output io_requestor_5_status_mpv, // @[PTW.scala:220:14] output io_requestor_5_status_gva, // @[PTW.scala:220:14] output io_requestor_5_status_tsr, // @[PTW.scala:220:14] output io_requestor_5_status_tw, // @[PTW.scala:220:14] output io_requestor_5_status_tvm, // @[PTW.scala:220:14] output io_requestor_5_status_mxr, // @[PTW.scala:220:14] output io_requestor_5_status_sum, // @[PTW.scala:220:14] output io_requestor_5_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_5_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_5_status_mpp, // @[PTW.scala:220:14] output io_requestor_5_status_spp, // @[PTW.scala:220:14] output io_requestor_5_status_mpie, // @[PTW.scala:220:14] output io_requestor_5_status_spie, // @[PTW.scala:220:14] output io_requestor_5_status_mie, // @[PTW.scala:220:14] output io_requestor_5_status_sie, // @[PTW.scala:220:14] output io_requestor_5_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_5_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_5_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_5_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_5_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_5_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_5_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_5_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_5_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_5_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_5_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_5_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_5_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_5_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_5_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_5_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_5_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_5_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_5_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_5_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_5_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_5_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_5_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_5_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_5_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_5_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_5_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_5_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_5_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_5_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_5_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_5_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_5_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_5_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_5_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_5_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_5_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_5_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_5_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_5_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_5_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_5_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_5_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_5_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_5_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_5_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_6_req_ready, // @[PTW.scala:220:14] input io_requestor_6_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_6_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_6_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_6_resp_valid, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_6_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_6_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_6_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_6_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_6_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_6_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_6_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_6_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_6_status_debug, // @[PTW.scala:220:14] output io_requestor_6_status_cease, // @[PTW.scala:220:14] output io_requestor_6_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_6_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_6_status_dprv, // @[PTW.scala:220:14] output io_requestor_6_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_6_status_prv, // @[PTW.scala:220:14] output io_requestor_6_status_v, // @[PTW.scala:220:14] output io_requestor_6_status_mpv, // @[PTW.scala:220:14] output io_requestor_6_status_gva, // @[PTW.scala:220:14] output io_requestor_6_status_tsr, // @[PTW.scala:220:14] output io_requestor_6_status_tw, // @[PTW.scala:220:14] output io_requestor_6_status_tvm, // @[PTW.scala:220:14] output io_requestor_6_status_mxr, // @[PTW.scala:220:14] output io_requestor_6_status_sum, // @[PTW.scala:220:14] output io_requestor_6_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_6_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_6_status_mpp, // @[PTW.scala:220:14] output io_requestor_6_status_spp, // @[PTW.scala:220:14] output io_requestor_6_status_mpie, // @[PTW.scala:220:14] output io_requestor_6_status_spie, // @[PTW.scala:220:14] output io_requestor_6_status_mie, // @[PTW.scala:220:14] output io_requestor_6_status_sie, // @[PTW.scala:220:14] output io_requestor_6_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_6_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_6_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_6_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_6_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_6_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_6_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_6_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_6_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_6_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_6_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_6_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_6_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_6_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_6_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_6_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_6_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_6_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_6_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_6_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_6_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_6_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_6_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_6_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_6_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_6_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_6_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_6_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_6_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_6_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_6_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_6_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_6_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_6_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_6_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_6_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_6_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_6_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_6_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_6_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_6_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_6_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_6_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_6_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_6_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_6_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_7_req_ready, // @[PTW.scala:220:14] input io_requestor_7_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_7_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_7_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_7_resp_valid, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_7_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_7_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_7_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_7_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_7_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_7_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_7_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_7_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_7_status_debug, // @[PTW.scala:220:14] output io_requestor_7_status_cease, // @[PTW.scala:220:14] output io_requestor_7_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_7_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_7_status_dprv, // @[PTW.scala:220:14] output io_requestor_7_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_7_status_prv, // @[PTW.scala:220:14] output io_requestor_7_status_v, // @[PTW.scala:220:14] output io_requestor_7_status_mpv, // @[PTW.scala:220:14] output io_requestor_7_status_gva, // @[PTW.scala:220:14] output io_requestor_7_status_tsr, // @[PTW.scala:220:14] output io_requestor_7_status_tw, // @[PTW.scala:220:14] output io_requestor_7_status_tvm, // @[PTW.scala:220:14] output io_requestor_7_status_mxr, // @[PTW.scala:220:14] output io_requestor_7_status_sum, // @[PTW.scala:220:14] output io_requestor_7_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_7_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_7_status_mpp, // @[PTW.scala:220:14] output io_requestor_7_status_spp, // @[PTW.scala:220:14] output io_requestor_7_status_mpie, // @[PTW.scala:220:14] output io_requestor_7_status_spie, // @[PTW.scala:220:14] output io_requestor_7_status_mie, // @[PTW.scala:220:14] output io_requestor_7_status_sie, // @[PTW.scala:220:14] output io_requestor_7_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_7_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_7_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_7_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_7_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_7_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_7_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_7_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_7_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_7_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_7_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_7_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_7_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_7_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_7_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_7_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_7_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_7_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_7_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_7_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_7_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_7_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_7_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_7_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_7_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_7_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_7_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_7_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_7_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_7_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_7_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_7_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_7_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_7_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_7_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_7_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_7_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_7_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_7_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_7_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_7_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_7_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_7_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_7_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_7_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_7_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_8_req_ready, // @[PTW.scala:220:14] input io_requestor_8_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_8_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_8_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_8_resp_valid, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_8_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_8_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_8_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_8_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_8_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_8_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_8_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_8_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_8_status_debug, // @[PTW.scala:220:14] output io_requestor_8_status_cease, // @[PTW.scala:220:14] output io_requestor_8_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_8_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_8_status_dprv, // @[PTW.scala:220:14] output io_requestor_8_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_8_status_prv, // @[PTW.scala:220:14] output io_requestor_8_status_v, // @[PTW.scala:220:14] output io_requestor_8_status_mpv, // @[PTW.scala:220:14] output io_requestor_8_status_gva, // @[PTW.scala:220:14] output io_requestor_8_status_tsr, // @[PTW.scala:220:14] output io_requestor_8_status_tw, // @[PTW.scala:220:14] output io_requestor_8_status_tvm, // @[PTW.scala:220:14] output io_requestor_8_status_mxr, // @[PTW.scala:220:14] output io_requestor_8_status_sum, // @[PTW.scala:220:14] output io_requestor_8_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_8_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_8_status_mpp, // @[PTW.scala:220:14] output io_requestor_8_status_spp, // @[PTW.scala:220:14] output io_requestor_8_status_mpie, // @[PTW.scala:220:14] output io_requestor_8_status_spie, // @[PTW.scala:220:14] output io_requestor_8_status_mie, // @[PTW.scala:220:14] output io_requestor_8_status_sie, // @[PTW.scala:220:14] output io_requestor_8_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_8_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_8_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_8_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_8_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_8_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_8_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_8_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_8_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_8_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_8_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_8_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_8_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_8_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_8_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_8_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_8_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_8_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_8_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_8_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_8_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_8_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_8_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_8_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_8_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_8_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_8_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_8_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_8_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_8_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_8_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_8_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_8_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_8_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_8_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_8_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_8_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_8_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_8_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_8_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_8_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_8_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_8_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_8_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_8_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_8_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_9_req_ready, // @[PTW.scala:220:14] input io_requestor_9_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_9_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_9_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_9_resp_valid, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_9_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_9_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_9_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_9_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_9_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_9_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_9_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_9_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_9_status_debug, // @[PTW.scala:220:14] output io_requestor_9_status_cease, // @[PTW.scala:220:14] output io_requestor_9_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_9_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_9_status_dprv, // @[PTW.scala:220:14] output io_requestor_9_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_9_status_prv, // @[PTW.scala:220:14] output io_requestor_9_status_v, // @[PTW.scala:220:14] output io_requestor_9_status_mpv, // @[PTW.scala:220:14] output io_requestor_9_status_gva, // @[PTW.scala:220:14] output io_requestor_9_status_tsr, // @[PTW.scala:220:14] output io_requestor_9_status_tw, // @[PTW.scala:220:14] output io_requestor_9_status_tvm, // @[PTW.scala:220:14] output io_requestor_9_status_mxr, // @[PTW.scala:220:14] output io_requestor_9_status_sum, // @[PTW.scala:220:14] output io_requestor_9_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_9_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_9_status_mpp, // @[PTW.scala:220:14] output io_requestor_9_status_spp, // @[PTW.scala:220:14] output io_requestor_9_status_mpie, // @[PTW.scala:220:14] output io_requestor_9_status_spie, // @[PTW.scala:220:14] output io_requestor_9_status_mie, // @[PTW.scala:220:14] output io_requestor_9_status_sie, // @[PTW.scala:220:14] output io_requestor_9_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_9_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_9_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_9_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_9_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_9_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_9_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_9_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_9_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_9_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_9_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_9_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_9_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_9_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_9_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_9_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_9_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_9_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_9_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_9_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_9_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_9_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_9_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_9_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_9_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_9_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_9_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_9_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_9_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_9_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_9_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_9_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_9_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_9_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_9_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_9_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_9_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_9_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_9_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_9_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_9_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_9_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_9_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_9_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_9_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_9_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_10_req_ready, // @[PTW.scala:220:14] input io_requestor_10_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_10_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_10_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_10_resp_valid, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_10_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_10_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_10_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_10_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_10_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_10_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_10_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_10_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_10_status_debug, // @[PTW.scala:220:14] output io_requestor_10_status_cease, // @[PTW.scala:220:14] output io_requestor_10_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_10_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_10_status_dprv, // @[PTW.scala:220:14] output io_requestor_10_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_10_status_prv, // @[PTW.scala:220:14] output io_requestor_10_status_v, // @[PTW.scala:220:14] output io_requestor_10_status_mpv, // @[PTW.scala:220:14] output io_requestor_10_status_gva, // @[PTW.scala:220:14] output io_requestor_10_status_tsr, // @[PTW.scala:220:14] output io_requestor_10_status_tw, // @[PTW.scala:220:14] output io_requestor_10_status_tvm, // @[PTW.scala:220:14] output io_requestor_10_status_mxr, // @[PTW.scala:220:14] output io_requestor_10_status_sum, // @[PTW.scala:220:14] output io_requestor_10_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_10_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_10_status_mpp, // @[PTW.scala:220:14] output io_requestor_10_status_spp, // @[PTW.scala:220:14] output io_requestor_10_status_mpie, // @[PTW.scala:220:14] output io_requestor_10_status_spie, // @[PTW.scala:220:14] output io_requestor_10_status_mie, // @[PTW.scala:220:14] output io_requestor_10_status_sie, // @[PTW.scala:220:14] output io_requestor_10_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_10_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_10_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_10_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_10_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_10_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_10_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_10_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_10_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_10_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_10_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_10_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_10_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_10_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_10_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_10_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_10_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_10_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_10_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_10_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_10_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_10_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_10_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_10_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_10_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_10_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_10_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_10_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_10_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_10_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_10_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_10_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_10_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_10_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_10_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_10_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_10_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_10_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_10_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_10_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_10_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_10_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_10_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_10_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_10_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_10_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_11_req_ready, // @[PTW.scala:220:14] input io_requestor_11_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_11_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_11_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_11_resp_valid, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_11_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_11_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_11_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_11_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_11_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_11_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_11_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_11_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_11_status_debug, // @[PTW.scala:220:14] output io_requestor_11_status_cease, // @[PTW.scala:220:14] output io_requestor_11_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_11_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_11_status_dprv, // @[PTW.scala:220:14] output io_requestor_11_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_11_status_prv, // @[PTW.scala:220:14] output io_requestor_11_status_v, // @[PTW.scala:220:14] output io_requestor_11_status_mpv, // @[PTW.scala:220:14] output io_requestor_11_status_gva, // @[PTW.scala:220:14] output io_requestor_11_status_tsr, // @[PTW.scala:220:14] output io_requestor_11_status_tw, // @[PTW.scala:220:14] output io_requestor_11_status_tvm, // @[PTW.scala:220:14] output io_requestor_11_status_mxr, // @[PTW.scala:220:14] output io_requestor_11_status_sum, // @[PTW.scala:220:14] output io_requestor_11_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_11_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_11_status_mpp, // @[PTW.scala:220:14] output io_requestor_11_status_spp, // @[PTW.scala:220:14] output io_requestor_11_status_mpie, // @[PTW.scala:220:14] output io_requestor_11_status_spie, // @[PTW.scala:220:14] output io_requestor_11_status_mie, // @[PTW.scala:220:14] output io_requestor_11_status_sie, // @[PTW.scala:220:14] output io_requestor_11_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_11_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_11_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_11_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_11_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_11_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_11_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_11_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_11_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_11_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_11_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_11_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_11_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_11_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_11_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_11_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_11_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_11_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_11_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_11_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_11_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_11_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_11_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_11_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_11_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_11_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_11_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_11_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_11_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_11_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_11_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_11_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_11_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_11_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_11_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_11_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_11_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_11_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_11_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_11_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_11_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_11_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_11_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_11_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_11_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_11_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_12_req_ready, // @[PTW.scala:220:14] input io_requestor_12_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_12_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_12_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_12_resp_valid, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_12_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_12_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_12_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_12_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_12_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_12_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_12_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_12_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_12_status_debug, // @[PTW.scala:220:14] output io_requestor_12_status_cease, // @[PTW.scala:220:14] output io_requestor_12_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_12_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_12_status_dprv, // @[PTW.scala:220:14] output io_requestor_12_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_12_status_prv, // @[PTW.scala:220:14] output io_requestor_12_status_v, // @[PTW.scala:220:14] output io_requestor_12_status_mpv, // @[PTW.scala:220:14] output io_requestor_12_status_gva, // @[PTW.scala:220:14] output io_requestor_12_status_tsr, // @[PTW.scala:220:14] output io_requestor_12_status_tw, // @[PTW.scala:220:14] output io_requestor_12_status_tvm, // @[PTW.scala:220:14] output io_requestor_12_status_mxr, // @[PTW.scala:220:14] output io_requestor_12_status_sum, // @[PTW.scala:220:14] output io_requestor_12_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_12_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_12_status_mpp, // @[PTW.scala:220:14] output io_requestor_12_status_spp, // @[PTW.scala:220:14] output io_requestor_12_status_mpie, // @[PTW.scala:220:14] output io_requestor_12_status_spie, // @[PTW.scala:220:14] output io_requestor_12_status_mie, // @[PTW.scala:220:14] output io_requestor_12_status_sie, // @[PTW.scala:220:14] output io_requestor_12_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_12_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_12_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_12_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_12_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_12_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_12_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_12_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_12_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_12_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_12_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_12_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_12_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_12_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_12_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_12_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_12_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_12_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_12_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_12_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_12_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_12_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_12_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_12_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_12_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_12_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_12_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_12_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_12_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_12_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_12_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_12_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_12_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_12_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_12_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_12_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_12_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_12_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_12_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_12_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_12_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_12_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_12_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_12_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_12_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_12_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_13_req_ready, // @[PTW.scala:220:14] input io_requestor_13_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_13_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_13_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_13_resp_valid, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_13_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_13_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_13_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_13_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_13_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_13_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_13_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_13_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_13_status_debug, // @[PTW.scala:220:14] output io_requestor_13_status_cease, // @[PTW.scala:220:14] output io_requestor_13_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_13_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_13_status_dprv, // @[PTW.scala:220:14] output io_requestor_13_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_13_status_prv, // @[PTW.scala:220:14] output io_requestor_13_status_v, // @[PTW.scala:220:14] output io_requestor_13_status_mpv, // @[PTW.scala:220:14] output io_requestor_13_status_gva, // @[PTW.scala:220:14] output io_requestor_13_status_tsr, // @[PTW.scala:220:14] output io_requestor_13_status_tw, // @[PTW.scala:220:14] output io_requestor_13_status_tvm, // @[PTW.scala:220:14] output io_requestor_13_status_mxr, // @[PTW.scala:220:14] output io_requestor_13_status_sum, // @[PTW.scala:220:14] output io_requestor_13_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_13_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_13_status_mpp, // @[PTW.scala:220:14] output io_requestor_13_status_spp, // @[PTW.scala:220:14] output io_requestor_13_status_mpie, // @[PTW.scala:220:14] output io_requestor_13_status_spie, // @[PTW.scala:220:14] output io_requestor_13_status_mie, // @[PTW.scala:220:14] output io_requestor_13_status_sie, // @[PTW.scala:220:14] output io_requestor_13_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_13_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_13_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_13_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_13_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_13_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_13_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_13_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_13_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_13_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_13_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_13_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_13_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_13_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_13_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_13_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_13_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_13_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_13_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_13_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_13_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_13_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_13_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_13_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_13_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_13_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_13_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_13_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_13_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_13_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_13_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_13_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_13_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_13_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_13_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_13_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_13_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_13_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_13_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_13_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_13_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_13_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_13_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_13_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_13_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_13_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_14_req_ready, // @[PTW.scala:220:14] input io_requestor_14_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_14_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_14_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_14_resp_valid, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_14_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_14_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_14_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_14_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_14_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_14_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_14_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_14_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_14_status_debug, // @[PTW.scala:220:14] output io_requestor_14_status_cease, // @[PTW.scala:220:14] output io_requestor_14_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_14_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_14_status_dprv, // @[PTW.scala:220:14] output io_requestor_14_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_14_status_prv, // @[PTW.scala:220:14] output io_requestor_14_status_v, // @[PTW.scala:220:14] output io_requestor_14_status_mpv, // @[PTW.scala:220:14] output io_requestor_14_status_gva, // @[PTW.scala:220:14] output io_requestor_14_status_tsr, // @[PTW.scala:220:14] output io_requestor_14_status_tw, // @[PTW.scala:220:14] output io_requestor_14_status_tvm, // @[PTW.scala:220:14] output io_requestor_14_status_mxr, // @[PTW.scala:220:14] output io_requestor_14_status_sum, // @[PTW.scala:220:14] output io_requestor_14_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_14_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_14_status_mpp, // @[PTW.scala:220:14] output io_requestor_14_status_spp, // @[PTW.scala:220:14] output io_requestor_14_status_mpie, // @[PTW.scala:220:14] output io_requestor_14_status_spie, // @[PTW.scala:220:14] output io_requestor_14_status_mie, // @[PTW.scala:220:14] output io_requestor_14_status_sie, // @[PTW.scala:220:14] output io_requestor_14_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_14_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_14_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_14_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_14_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_14_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_14_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_14_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_14_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_14_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_14_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_14_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_14_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_14_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_14_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_14_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_14_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_14_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_14_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_14_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_14_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_14_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_14_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_14_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_14_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_14_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_14_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_14_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_14_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_14_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_14_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_14_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_14_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_14_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_14_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_14_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_14_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_14_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_14_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_14_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_14_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_14_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_14_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_14_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_14_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_14_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_15_req_ready, // @[PTW.scala:220:14] input io_requestor_15_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_15_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_15_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_15_resp_valid, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_15_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_15_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_15_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_15_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_15_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_15_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_15_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_15_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_15_status_debug, // @[PTW.scala:220:14] output io_requestor_15_status_cease, // @[PTW.scala:220:14] output io_requestor_15_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_15_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_15_status_dprv, // @[PTW.scala:220:14] output io_requestor_15_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_15_status_prv, // @[PTW.scala:220:14] output io_requestor_15_status_v, // @[PTW.scala:220:14] output io_requestor_15_status_mpv, // @[PTW.scala:220:14] output io_requestor_15_status_gva, // @[PTW.scala:220:14] output io_requestor_15_status_tsr, // @[PTW.scala:220:14] output io_requestor_15_status_tw, // @[PTW.scala:220:14] output io_requestor_15_status_tvm, // @[PTW.scala:220:14] output io_requestor_15_status_mxr, // @[PTW.scala:220:14] output io_requestor_15_status_sum, // @[PTW.scala:220:14] output io_requestor_15_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_15_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_15_status_mpp, // @[PTW.scala:220:14] output io_requestor_15_status_spp, // @[PTW.scala:220:14] output io_requestor_15_status_mpie, // @[PTW.scala:220:14] output io_requestor_15_status_spie, // @[PTW.scala:220:14] output io_requestor_15_status_mie, // @[PTW.scala:220:14] output io_requestor_15_status_sie, // @[PTW.scala:220:14] output io_requestor_15_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_15_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_15_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_15_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_15_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_15_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_15_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_15_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_15_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_15_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_15_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_15_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_15_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_15_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_15_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_15_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_15_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_15_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_15_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_15_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_15_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_15_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_15_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_15_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_15_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_15_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_15_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_15_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_15_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_15_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_15_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_15_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_15_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_15_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_15_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_15_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_15_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_15_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_15_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_15_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_15_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_15_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_15_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_15_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_15_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_15_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_16_req_ready, // @[PTW.scala:220:14] input io_requestor_16_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_16_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_16_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_16_resp_valid, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_16_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_16_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_16_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_16_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_16_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_16_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_16_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_16_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_16_status_debug, // @[PTW.scala:220:14] output io_requestor_16_status_cease, // @[PTW.scala:220:14] output io_requestor_16_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_16_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_16_status_dprv, // @[PTW.scala:220:14] output io_requestor_16_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_16_status_prv, // @[PTW.scala:220:14] output io_requestor_16_status_v, // @[PTW.scala:220:14] output io_requestor_16_status_mpv, // @[PTW.scala:220:14] output io_requestor_16_status_gva, // @[PTW.scala:220:14] output io_requestor_16_status_tsr, // @[PTW.scala:220:14] output io_requestor_16_status_tw, // @[PTW.scala:220:14] output io_requestor_16_status_tvm, // @[PTW.scala:220:14] output io_requestor_16_status_mxr, // @[PTW.scala:220:14] output io_requestor_16_status_sum, // @[PTW.scala:220:14] output io_requestor_16_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_16_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_16_status_mpp, // @[PTW.scala:220:14] output io_requestor_16_status_spp, // @[PTW.scala:220:14] output io_requestor_16_status_mpie, // @[PTW.scala:220:14] output io_requestor_16_status_spie, // @[PTW.scala:220:14] output io_requestor_16_status_mie, // @[PTW.scala:220:14] output io_requestor_16_status_sie, // @[PTW.scala:220:14] output io_requestor_16_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_16_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_16_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_16_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_16_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_16_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_16_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_16_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_16_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_16_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_16_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_16_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_16_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_16_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_16_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_16_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_16_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_16_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_16_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_16_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_16_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_16_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_16_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_16_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_16_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_16_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_16_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_16_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_16_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_16_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_16_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_16_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_16_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_16_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_16_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_16_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_16_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_16_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_16_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_16_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_16_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_16_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_16_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_16_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_16_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_16_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_17_req_ready, // @[PTW.scala:220:14] input io_requestor_17_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_17_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_17_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_17_resp_valid, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_17_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_17_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_17_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_17_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_17_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_17_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_17_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_17_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_17_status_debug, // @[PTW.scala:220:14] output io_requestor_17_status_cease, // @[PTW.scala:220:14] output io_requestor_17_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_17_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_17_status_dprv, // @[PTW.scala:220:14] output io_requestor_17_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_17_status_prv, // @[PTW.scala:220:14] output io_requestor_17_status_v, // @[PTW.scala:220:14] output io_requestor_17_status_mpv, // @[PTW.scala:220:14] output io_requestor_17_status_gva, // @[PTW.scala:220:14] output io_requestor_17_status_tsr, // @[PTW.scala:220:14] output io_requestor_17_status_tw, // @[PTW.scala:220:14] output io_requestor_17_status_tvm, // @[PTW.scala:220:14] output io_requestor_17_status_mxr, // @[PTW.scala:220:14] output io_requestor_17_status_sum, // @[PTW.scala:220:14] output io_requestor_17_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_17_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_17_status_mpp, // @[PTW.scala:220:14] output io_requestor_17_status_spp, // @[PTW.scala:220:14] output io_requestor_17_status_mpie, // @[PTW.scala:220:14] output io_requestor_17_status_spie, // @[PTW.scala:220:14] output io_requestor_17_status_mie, // @[PTW.scala:220:14] output io_requestor_17_status_sie, // @[PTW.scala:220:14] output io_requestor_17_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_17_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_17_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_17_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_17_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_17_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_17_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_17_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_17_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_17_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_17_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_17_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_17_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_17_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_17_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_17_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_17_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_17_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_17_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_17_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_17_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_17_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_17_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_17_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_17_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_17_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_17_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_17_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_17_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_17_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_17_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_17_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_17_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_17_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_17_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_17_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_17_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_17_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_17_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_17_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_17_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_17_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_17_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_17_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_17_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_17_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_18_req_ready, // @[PTW.scala:220:14] input io_requestor_18_req_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_18_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_18_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_18_resp_valid, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_18_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_18_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_18_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_18_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_18_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_18_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_18_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_18_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_18_status_debug, // @[PTW.scala:220:14] output io_requestor_18_status_cease, // @[PTW.scala:220:14] output io_requestor_18_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_18_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_18_status_dprv, // @[PTW.scala:220:14] output io_requestor_18_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_18_status_prv, // @[PTW.scala:220:14] output io_requestor_18_status_v, // @[PTW.scala:220:14] output io_requestor_18_status_mpv, // @[PTW.scala:220:14] output io_requestor_18_status_gva, // @[PTW.scala:220:14] output io_requestor_18_status_tsr, // @[PTW.scala:220:14] output io_requestor_18_status_tw, // @[PTW.scala:220:14] output io_requestor_18_status_tvm, // @[PTW.scala:220:14] output io_requestor_18_status_mxr, // @[PTW.scala:220:14] output io_requestor_18_status_sum, // @[PTW.scala:220:14] output io_requestor_18_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_18_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_18_status_mpp, // @[PTW.scala:220:14] output io_requestor_18_status_spp, // @[PTW.scala:220:14] output io_requestor_18_status_mpie, // @[PTW.scala:220:14] output io_requestor_18_status_spie, // @[PTW.scala:220:14] output io_requestor_18_status_mie, // @[PTW.scala:220:14] output io_requestor_18_status_sie, // @[PTW.scala:220:14] output io_requestor_18_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_18_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_18_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_18_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_18_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_18_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_18_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_18_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_18_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_18_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_18_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_18_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_18_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_18_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_18_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_18_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_18_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_18_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_18_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_18_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_18_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_18_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_18_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_18_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_18_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_18_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_18_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_18_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_18_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_18_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_18_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_18_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_18_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_18_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_18_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_18_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_18_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_18_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_18_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_18_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_18_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_18_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_18_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_18_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_18_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_18_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_requestor_19_req_ready, // @[PTW.scala:220:14] input io_requestor_19_req_valid, // @[PTW.scala:220:14] input io_requestor_19_req_bits_valid, // @[PTW.scala:220:14] input [26:0] io_requestor_19_req_bits_bits_addr, // @[PTW.scala:220:14] input io_requestor_19_req_bits_bits_need_gpa, // @[PTW.scala:220:14] output io_requestor_19_resp_valid, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_ae_ptw, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_ae_final, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pf, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_gf, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_hr, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_hw, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_hx, // @[PTW.scala:220:14] output [9:0] io_requestor_19_resp_bits_pte_reserved_for_future, // @[PTW.scala:220:14] output [43:0] io_requestor_19_resp_bits_pte_ppn, // @[PTW.scala:220:14] output [1:0] io_requestor_19_resp_bits_pte_reserved_for_software, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_d, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_a, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_g, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_u, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_x, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_w, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_r, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_pte_v, // @[PTW.scala:220:14] output [1:0] io_requestor_19_resp_bits_level, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_homogeneous, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_gpa_valid, // @[PTW.scala:220:14] output [38:0] io_requestor_19_resp_bits_gpa_bits, // @[PTW.scala:220:14] output io_requestor_19_resp_bits_gpa_is_pte, // @[PTW.scala:220:14] output [3:0] io_requestor_19_ptbr_mode, // @[PTW.scala:220:14] output [43:0] io_requestor_19_ptbr_ppn, // @[PTW.scala:220:14] output io_requestor_19_status_debug, // @[PTW.scala:220:14] output io_requestor_19_status_cease, // @[PTW.scala:220:14] output io_requestor_19_status_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_19_status_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_19_status_dprv, // @[PTW.scala:220:14] output io_requestor_19_status_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_19_status_prv, // @[PTW.scala:220:14] output io_requestor_19_status_v, // @[PTW.scala:220:14] output io_requestor_19_status_mpv, // @[PTW.scala:220:14] output io_requestor_19_status_gva, // @[PTW.scala:220:14] output io_requestor_19_status_tsr, // @[PTW.scala:220:14] output io_requestor_19_status_tw, // @[PTW.scala:220:14] output io_requestor_19_status_tvm, // @[PTW.scala:220:14] output io_requestor_19_status_mxr, // @[PTW.scala:220:14] output io_requestor_19_status_sum, // @[PTW.scala:220:14] output io_requestor_19_status_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_19_status_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_19_status_mpp, // @[PTW.scala:220:14] output io_requestor_19_status_spp, // @[PTW.scala:220:14] output io_requestor_19_status_mpie, // @[PTW.scala:220:14] output io_requestor_19_status_spie, // @[PTW.scala:220:14] output io_requestor_19_status_mie, // @[PTW.scala:220:14] output io_requestor_19_status_sie, // @[PTW.scala:220:14] output io_requestor_19_hstatus_spvp, // @[PTW.scala:220:14] output io_requestor_19_hstatus_spv, // @[PTW.scala:220:14] output io_requestor_19_hstatus_gva, // @[PTW.scala:220:14] output io_requestor_19_gstatus_debug, // @[PTW.scala:220:14] output io_requestor_19_gstatus_cease, // @[PTW.scala:220:14] output io_requestor_19_gstatus_wfi, // @[PTW.scala:220:14] output [31:0] io_requestor_19_gstatus_isa, // @[PTW.scala:220:14] output [1:0] io_requestor_19_gstatus_dprv, // @[PTW.scala:220:14] output io_requestor_19_gstatus_dv, // @[PTW.scala:220:14] output [1:0] io_requestor_19_gstatus_prv, // @[PTW.scala:220:14] output io_requestor_19_gstatus_v, // @[PTW.scala:220:14] output [22:0] io_requestor_19_gstatus_zero2, // @[PTW.scala:220:14] output io_requestor_19_gstatus_mpv, // @[PTW.scala:220:14] output io_requestor_19_gstatus_gva, // @[PTW.scala:220:14] output io_requestor_19_gstatus_mbe, // @[PTW.scala:220:14] output io_requestor_19_gstatus_sbe, // @[PTW.scala:220:14] output [1:0] io_requestor_19_gstatus_sxl, // @[PTW.scala:220:14] output [7:0] io_requestor_19_gstatus_zero1, // @[PTW.scala:220:14] output io_requestor_19_gstatus_tsr, // @[PTW.scala:220:14] output io_requestor_19_gstatus_tw, // @[PTW.scala:220:14] output io_requestor_19_gstatus_tvm, // @[PTW.scala:220:14] output io_requestor_19_gstatus_mxr, // @[PTW.scala:220:14] output io_requestor_19_gstatus_sum, // @[PTW.scala:220:14] output io_requestor_19_gstatus_mprv, // @[PTW.scala:220:14] output [1:0] io_requestor_19_gstatus_fs, // @[PTW.scala:220:14] output [1:0] io_requestor_19_gstatus_mpp, // @[PTW.scala:220:14] output [1:0] io_requestor_19_gstatus_vs, // @[PTW.scala:220:14] output io_requestor_19_gstatus_spp, // @[PTW.scala:220:14] output io_requestor_19_gstatus_mpie, // @[PTW.scala:220:14] output io_requestor_19_gstatus_ube, // @[PTW.scala:220:14] output io_requestor_19_gstatus_spie, // @[PTW.scala:220:14] output io_requestor_19_gstatus_upie, // @[PTW.scala:220:14] output io_requestor_19_gstatus_mie, // @[PTW.scala:220:14] output io_requestor_19_gstatus_hie, // @[PTW.scala:220:14] output io_requestor_19_gstatus_sie, // @[PTW.scala:220:14] output io_requestor_19_gstatus_uie, // @[PTW.scala:220:14] output io_requestor_19_pmp_0_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_0_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_0_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_0_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_0_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_0_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_0_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_1_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_1_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_1_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_1_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_1_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_1_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_1_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_2_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_2_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_2_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_2_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_2_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_2_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_2_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_3_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_3_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_3_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_3_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_3_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_3_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_3_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_4_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_4_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_4_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_4_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_4_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_4_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_4_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_5_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_5_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_5_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_5_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_5_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_5_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_5_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_6_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_6_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_6_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_6_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_6_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_6_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_6_mask, // @[PTW.scala:220:14] output io_requestor_19_pmp_7_cfg_l, // @[PTW.scala:220:14] output [1:0] io_requestor_19_pmp_7_cfg_a, // @[PTW.scala:220:14] output io_requestor_19_pmp_7_cfg_x, // @[PTW.scala:220:14] output io_requestor_19_pmp_7_cfg_w, // @[PTW.scala:220:14] output io_requestor_19_pmp_7_cfg_r, // @[PTW.scala:220:14] output [29:0] io_requestor_19_pmp_7_addr, // @[PTW.scala:220:14] output [31:0] io_requestor_19_pmp_7_mask, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_0_value, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_1_value, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_2_value, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] output io_requestor_19_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] output [63:0] io_requestor_19_customCSRs_csrs_3_value, // @[PTW.scala:220:14] input io_mem_req_ready, // @[PTW.scala:220:14] output io_mem_req_valid, // @[PTW.scala:220:14] output [39:0] io_mem_req_bits_addr, // @[PTW.scala:220:14] output io_mem_req_bits_dv, // @[PTW.scala:220:14] output io_mem_s1_kill, // @[PTW.scala:220:14] input io_mem_s2_nack, // @[PTW.scala:220:14] input io_mem_s2_nack_cause_raw, // @[PTW.scala:220:14] input io_mem_s2_uncached, // @[PTW.scala:220:14] input [31:0] io_mem_s2_paddr, // @[PTW.scala:220:14] input io_mem_resp_valid, // @[PTW.scala:220:14] input [39:0] io_mem_resp_bits_addr, // @[PTW.scala:220:14] input [7:0] io_mem_resp_bits_tag, // @[PTW.scala:220:14] input [4:0] io_mem_resp_bits_cmd, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_size, // @[PTW.scala:220:14] input io_mem_resp_bits_signed, // @[PTW.scala:220:14] input [1:0] io_mem_resp_bits_dprv, // @[PTW.scala:220:14] input io_mem_resp_bits_dv, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data, // @[PTW.scala:220:14] input [7:0] io_mem_resp_bits_mask, // @[PTW.scala:220:14] input io_mem_resp_bits_replay, // @[PTW.scala:220:14] input io_mem_resp_bits_has_data, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_word_bypass, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_data_raw, // @[PTW.scala:220:14] input [63:0] io_mem_resp_bits_store_data, // @[PTW.scala:220:14] input io_mem_replay_next, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ma_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_pf_st, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_ld, // @[PTW.scala:220:14] input io_mem_s2_xcpt_ae_st, // @[PTW.scala:220:14] input [39:0] io_mem_s2_gpa, // @[PTW.scala:220:14] input io_mem_ordered, // @[PTW.scala:220:14] input io_mem_store_pending, // @[PTW.scala:220:14] input io_mem_perf_acquire, // @[PTW.scala:220:14] input io_mem_perf_release, // @[PTW.scala:220:14] input io_mem_perf_grant, // @[PTW.scala:220:14] input io_mem_perf_tlbMiss, // @[PTW.scala:220:14] input io_mem_perf_blocked, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenLoad, // @[PTW.scala:220:14] input io_mem_perf_canAcceptStoreThenRMW, // @[PTW.scala:220:14] input io_mem_perf_canAcceptLoadThenLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterLoad, // @[PTW.scala:220:14] input io_mem_perf_storeBufferEmptyAfterStore, // @[PTW.scala:220:14] input [3:0] io_dpath_ptbr_mode, // @[PTW.scala:220:14] input [43:0] io_dpath_ptbr_ppn, // @[PTW.scala:220:14] input io_dpath_sfence_valid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs1, // @[PTW.scala:220:14] input io_dpath_sfence_bits_rs2, // @[PTW.scala:220:14] input [38:0] io_dpath_sfence_bits_addr, // @[PTW.scala:220:14] input io_dpath_sfence_bits_asid, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hv, // @[PTW.scala:220:14] input io_dpath_sfence_bits_hg, // @[PTW.scala:220:14] input io_dpath_status_debug, // @[PTW.scala:220:14] input io_dpath_status_cease, // @[PTW.scala:220:14] input io_dpath_status_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_status_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_status_dprv, // @[PTW.scala:220:14] input io_dpath_status_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_prv, // @[PTW.scala:220:14] input io_dpath_status_v, // @[PTW.scala:220:14] input io_dpath_status_mpv, // @[PTW.scala:220:14] input io_dpath_status_gva, // @[PTW.scala:220:14] input io_dpath_status_tsr, // @[PTW.scala:220:14] input io_dpath_status_tw, // @[PTW.scala:220:14] input io_dpath_status_tvm, // @[PTW.scala:220:14] input io_dpath_status_mxr, // @[PTW.scala:220:14] input io_dpath_status_sum, // @[PTW.scala:220:14] input io_dpath_status_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_status_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_status_mpp, // @[PTW.scala:220:14] input io_dpath_status_spp, // @[PTW.scala:220:14] input io_dpath_status_mpie, // @[PTW.scala:220:14] input io_dpath_status_spie, // @[PTW.scala:220:14] input io_dpath_status_mie, // @[PTW.scala:220:14] input io_dpath_status_sie, // @[PTW.scala:220:14] input io_dpath_hstatus_spvp, // @[PTW.scala:220:14] input io_dpath_hstatus_spv, // @[PTW.scala:220:14] input io_dpath_hstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_debug, // @[PTW.scala:220:14] input io_dpath_gstatus_cease, // @[PTW.scala:220:14] input io_dpath_gstatus_wfi, // @[PTW.scala:220:14] input [31:0] io_dpath_gstatus_isa, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_dprv, // @[PTW.scala:220:14] input io_dpath_gstatus_dv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_prv, // @[PTW.scala:220:14] input io_dpath_gstatus_v, // @[PTW.scala:220:14] input [22:0] io_dpath_gstatus_zero2, // @[PTW.scala:220:14] input io_dpath_gstatus_mpv, // @[PTW.scala:220:14] input io_dpath_gstatus_gva, // @[PTW.scala:220:14] input io_dpath_gstatus_mbe, // @[PTW.scala:220:14] input io_dpath_gstatus_sbe, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_sxl, // @[PTW.scala:220:14] input [7:0] io_dpath_gstatus_zero1, // @[PTW.scala:220:14] input io_dpath_gstatus_tsr, // @[PTW.scala:220:14] input io_dpath_gstatus_tw, // @[PTW.scala:220:14] input io_dpath_gstatus_tvm, // @[PTW.scala:220:14] input io_dpath_gstatus_mxr, // @[PTW.scala:220:14] input io_dpath_gstatus_sum, // @[PTW.scala:220:14] input io_dpath_gstatus_mprv, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_fs, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_mpp, // @[PTW.scala:220:14] input [1:0] io_dpath_gstatus_vs, // @[PTW.scala:220:14] input io_dpath_gstatus_spp, // @[PTW.scala:220:14] input io_dpath_gstatus_mpie, // @[PTW.scala:220:14] input io_dpath_gstatus_ube, // @[PTW.scala:220:14] input io_dpath_gstatus_spie, // @[PTW.scala:220:14] input io_dpath_gstatus_upie, // @[PTW.scala:220:14] input io_dpath_gstatus_mie, // @[PTW.scala:220:14] input io_dpath_gstatus_hie, // @[PTW.scala:220:14] input io_dpath_gstatus_sie, // @[PTW.scala:220:14] input io_dpath_gstatus_uie, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_0_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_0_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_0_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_0_mask, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_1_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_1_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_1_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_1_mask, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_2_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_2_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_2_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_2_mask, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_3_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_3_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_3_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_3_mask, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_4_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_4_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_4_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_4_mask, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_5_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_5_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_5_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_5_mask, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_6_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_6_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_6_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_6_mask, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_l, // @[PTW.scala:220:14] input [1:0] io_dpath_pmp_7_cfg_a, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_x, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_w, // @[PTW.scala:220:14] input io_dpath_pmp_7_cfg_r, // @[PTW.scala:220:14] input [29:0] io_dpath_pmp_7_addr, // @[PTW.scala:220:14] input [31:0] io_dpath_pmp_7_mask, // @[PTW.scala:220:14] output io_dpath_perf_pte_miss, // @[PTW.scala:220:14] output io_dpath_perf_pte_hit, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_0_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_0_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_1_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_1_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_2_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_2_value, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_ren, // @[PTW.scala:220:14] input io_dpath_customCSRs_csrs_3_wen, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_wdata, // @[PTW.scala:220:14] input [63:0] io_dpath_customCSRs_csrs_3_value, // @[PTW.scala:220:14] output io_dpath_clock_enabled // @[PTW.scala:220:14] ); wire tmp_r; // @[PTW.scala:304:37] wire tmp_w; // @[PTW.scala:304:37] wire tmp_x; // @[PTW.scala:304:37] wire tmp_u; // @[PTW.scala:304:37] wire tmp_g; // @[PTW.scala:304:37] wire tmp_a; // @[PTW.scala:304:37] wire tmp_d; // @[PTW.scala:304:37] wire [1:0] tmp_reserved_for_software; // @[PTW.scala:304:37] wire [9:0] tmp_reserved_for_future; // @[PTW.scala:304:37] wire [9:0] _r_pte_barrier_io_y_reserved_for_future; // @[package.scala:267:25] wire [43:0] _r_pte_barrier_io_y_ppn; // @[package.scala:267:25] wire [1:0] _r_pte_barrier_io_y_reserved_for_software; // @[package.scala:267:25] wire _r_pte_barrier_io_y_d; // @[package.scala:267:25] wire _r_pte_barrier_io_y_a; // @[package.scala:267:25] wire _r_pte_barrier_io_y_g; // @[package.scala:267:25] wire _r_pte_barrier_io_y_u; // @[package.scala:267:25] wire _r_pte_barrier_io_y_x; // @[package.scala:267:25] wire _r_pte_barrier_io_y_w; // @[package.scala:267:25] wire _r_pte_barrier_io_y_r; // @[package.scala:267:25] wire _r_pte_barrier_io_y_v; // @[package.scala:267:25] wire [2:0] _state_barrier_io_y; // @[package.scala:267:25] wire _arb_io_out_valid; // @[PTW.scala:236:19] wire _arb_io_out_bits_valid; // @[PTW.scala:236:19] wire [26:0] _arb_io_out_bits_bits_addr; // @[PTW.scala:236:19] wire _arb_io_out_bits_bits_need_gpa; // @[PTW.scala:236:19] wire [4:0] _arb_io_chosen; // @[PTW.scala:236:19] wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_0_req_bits_bits_addr_0 = io_requestor_0_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_need_gpa_0 = io_requestor_0_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_1_req_bits_bits_addr_0 = io_requestor_1_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_need_gpa_0 = io_requestor_1_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_2_req_valid_0 = io_requestor_2_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_2_req_bits_bits_addr_0 = io_requestor_2_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_need_gpa_0 = io_requestor_2_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_3_req_valid_0 = io_requestor_3_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_3_req_bits_bits_addr_0 = io_requestor_3_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_bits_need_gpa_0 = io_requestor_3_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_4_req_valid_0 = io_requestor_4_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_4_req_bits_bits_addr_0 = io_requestor_4_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_4_req_bits_bits_need_gpa_0 = io_requestor_4_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_5_req_valid_0 = io_requestor_5_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_5_req_bits_bits_addr_0 = io_requestor_5_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_5_req_bits_bits_need_gpa_0 = io_requestor_5_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_6_req_valid_0 = io_requestor_6_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_6_req_bits_bits_addr_0 = io_requestor_6_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_6_req_bits_bits_need_gpa_0 = io_requestor_6_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_7_req_valid_0 = io_requestor_7_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_7_req_bits_bits_addr_0 = io_requestor_7_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_7_req_bits_bits_need_gpa_0 = io_requestor_7_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_8_req_valid_0 = io_requestor_8_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_8_req_bits_bits_addr_0 = io_requestor_8_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_8_req_bits_bits_need_gpa_0 = io_requestor_8_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_9_req_valid_0 = io_requestor_9_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_9_req_bits_bits_addr_0 = io_requestor_9_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_9_req_bits_bits_need_gpa_0 = io_requestor_9_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_10_req_valid_0 = io_requestor_10_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_10_req_bits_bits_addr_0 = io_requestor_10_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_10_req_bits_bits_need_gpa_0 = io_requestor_10_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_11_req_valid_0 = io_requestor_11_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_11_req_bits_bits_addr_0 = io_requestor_11_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_11_req_bits_bits_need_gpa_0 = io_requestor_11_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_12_req_valid_0 = io_requestor_12_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_12_req_bits_bits_addr_0 = io_requestor_12_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_12_req_bits_bits_need_gpa_0 = io_requestor_12_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_13_req_valid_0 = io_requestor_13_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_13_req_bits_bits_addr_0 = io_requestor_13_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_13_req_bits_bits_need_gpa_0 = io_requestor_13_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_14_req_valid_0 = io_requestor_14_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_14_req_bits_bits_addr_0 = io_requestor_14_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_14_req_bits_bits_need_gpa_0 = io_requestor_14_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_15_req_valid_0 = io_requestor_15_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_15_req_bits_bits_addr_0 = io_requestor_15_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_15_req_bits_bits_need_gpa_0 = io_requestor_15_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_16_req_valid_0 = io_requestor_16_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_16_req_bits_bits_addr_0 = io_requestor_16_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_16_req_bits_bits_need_gpa_0 = io_requestor_16_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_17_req_valid_0 = io_requestor_17_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_17_req_bits_bits_addr_0 = io_requestor_17_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_17_req_bits_bits_need_gpa_0 = io_requestor_17_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_18_req_valid_0 = io_requestor_18_req_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_18_req_bits_bits_addr_0 = io_requestor_18_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_18_req_bits_bits_need_gpa_0 = io_requestor_18_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_requestor_19_req_valid_0 = io_requestor_19_req_valid; // @[PTW.scala:219:7] wire io_requestor_19_req_bits_valid_0 = io_requestor_19_req_bits_valid; // @[PTW.scala:219:7] wire [26:0] io_requestor_19_req_bits_bits_addr_0 = io_requestor_19_req_bits_bits_addr; // @[PTW.scala:219:7] wire io_requestor_19_req_bits_bits_need_gpa_0 = io_requestor_19_req_bits_bits_need_gpa; // @[PTW.scala:219:7] wire io_mem_req_ready_0 = io_mem_req_ready; // @[PTW.scala:219:7] wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[PTW.scala:219:7] wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[PTW.scala:219:7] wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[PTW.scala:219:7] wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[PTW.scala:219:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[PTW.scala:219:7] wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[PTW.scala:219:7] wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[PTW.scala:219:7] wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[PTW.scala:219:7] wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[PTW.scala:219:7] wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[PTW.scala:219:7] wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[PTW.scala:219:7] wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[PTW.scala:219:7] wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[PTW.scala:219:7] wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[PTW.scala:219:7] wire io_mem_replay_next_0 = io_mem_replay_next; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[PTW.scala:219:7] wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[PTW.scala:219:7] wire io_mem_ordered_0 = io_mem_ordered; // @[PTW.scala:219:7] wire io_mem_store_pending_0 = io_mem_store_pending; // @[PTW.scala:219:7] wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[PTW.scala:219:7] wire io_mem_perf_release_0 = io_mem_perf_release; // @[PTW.scala:219:7] wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[PTW.scala:219:7] wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[PTW.scala:219:7] wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[PTW.scala:219:7] wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[PTW.scala:219:7] wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[PTW.scala:219:7] wire [3:0] io_dpath_ptbr_mode_0 = io_dpath_ptbr_mode; // @[PTW.scala:219:7] wire [43:0] io_dpath_ptbr_ppn_0 = io_dpath_ptbr_ppn; // @[PTW.scala:219:7] wire io_dpath_sfence_valid_0 = io_dpath_sfence_valid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs1_0 = io_dpath_sfence_bits_rs1; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_rs2_0 = io_dpath_sfence_bits_rs2; // @[PTW.scala:219:7] wire [38:0] io_dpath_sfence_bits_addr_0 = io_dpath_sfence_bits_addr; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_asid_0 = io_dpath_sfence_bits_asid; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hv_0 = io_dpath_sfence_bits_hv; // @[PTW.scala:219:7] wire io_dpath_sfence_bits_hg_0 = io_dpath_sfence_bits_hg; // @[PTW.scala:219:7] wire io_dpath_status_debug_0 = io_dpath_status_debug; // @[PTW.scala:219:7] wire io_dpath_status_cease_0 = io_dpath_status_cease; // @[PTW.scala:219:7] wire io_dpath_status_wfi_0 = io_dpath_status_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_status_isa_0 = io_dpath_status_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_dprv_0 = io_dpath_status_dprv; // @[PTW.scala:219:7] wire io_dpath_status_dv_0 = io_dpath_status_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_prv_0 = io_dpath_status_prv; // @[PTW.scala:219:7] wire io_dpath_status_v_0 = io_dpath_status_v; // @[PTW.scala:219:7] wire io_dpath_status_mpv_0 = io_dpath_status_mpv; // @[PTW.scala:219:7] wire io_dpath_status_gva_0 = io_dpath_status_gva; // @[PTW.scala:219:7] wire io_dpath_status_tsr_0 = io_dpath_status_tsr; // @[PTW.scala:219:7] wire io_dpath_status_tw_0 = io_dpath_status_tw; // @[PTW.scala:219:7] wire io_dpath_status_tvm_0 = io_dpath_status_tvm; // @[PTW.scala:219:7] wire io_dpath_status_mxr_0 = io_dpath_status_mxr; // @[PTW.scala:219:7] wire io_dpath_status_sum_0 = io_dpath_status_sum; // @[PTW.scala:219:7] wire io_dpath_status_mprv_0 = io_dpath_status_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_fs_0 = io_dpath_status_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_mpp_0 = io_dpath_status_mpp; // @[PTW.scala:219:7] wire io_dpath_status_spp_0 = io_dpath_status_spp; // @[PTW.scala:219:7] wire io_dpath_status_mpie_0 = io_dpath_status_mpie; // @[PTW.scala:219:7] wire io_dpath_status_spie_0 = io_dpath_status_spie; // @[PTW.scala:219:7] wire io_dpath_status_mie_0 = io_dpath_status_mie; // @[PTW.scala:219:7] wire io_dpath_status_sie_0 = io_dpath_status_sie; // @[PTW.scala:219:7] wire io_dpath_hstatus_spvp_0 = io_dpath_hstatus_spvp; // @[PTW.scala:219:7] wire io_dpath_hstatus_spv_0 = io_dpath_hstatus_spv; // @[PTW.scala:219:7] wire io_dpath_hstatus_gva_0 = io_dpath_hstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_debug_0 = io_dpath_gstatus_debug; // @[PTW.scala:219:7] wire io_dpath_gstatus_cease_0 = io_dpath_gstatus_cease; // @[PTW.scala:219:7] wire io_dpath_gstatus_wfi_0 = io_dpath_gstatus_wfi; // @[PTW.scala:219:7] wire [31:0] io_dpath_gstatus_isa_0 = io_dpath_gstatus_isa; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_dprv_0 = io_dpath_gstatus_dprv; // @[PTW.scala:219:7] wire io_dpath_gstatus_dv_0 = io_dpath_gstatus_dv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_prv_0 = io_dpath_gstatus_prv; // @[PTW.scala:219:7] wire io_dpath_gstatus_v_0 = io_dpath_gstatus_v; // @[PTW.scala:219:7] wire [22:0] io_dpath_gstatus_zero2_0 = io_dpath_gstatus_zero2; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpv_0 = io_dpath_gstatus_mpv; // @[PTW.scala:219:7] wire io_dpath_gstatus_gva_0 = io_dpath_gstatus_gva; // @[PTW.scala:219:7] wire io_dpath_gstatus_mbe_0 = io_dpath_gstatus_mbe; // @[PTW.scala:219:7] wire io_dpath_gstatus_sbe_0 = io_dpath_gstatus_sbe; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_sxl_0 = io_dpath_gstatus_sxl; // @[PTW.scala:219:7] wire [7:0] io_dpath_gstatus_zero1_0 = io_dpath_gstatus_zero1; // @[PTW.scala:219:7] wire io_dpath_gstatus_tsr_0 = io_dpath_gstatus_tsr; // @[PTW.scala:219:7] wire io_dpath_gstatus_tw_0 = io_dpath_gstatus_tw; // @[PTW.scala:219:7] wire io_dpath_gstatus_tvm_0 = io_dpath_gstatus_tvm; // @[PTW.scala:219:7] wire io_dpath_gstatus_mxr_0 = io_dpath_gstatus_mxr; // @[PTW.scala:219:7] wire io_dpath_gstatus_sum_0 = io_dpath_gstatus_sum; // @[PTW.scala:219:7] wire io_dpath_gstatus_mprv_0 = io_dpath_gstatus_mprv; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_fs_0 = io_dpath_gstatus_fs; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_mpp_0 = io_dpath_gstatus_mpp; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_vs_0 = io_dpath_gstatus_vs; // @[PTW.scala:219:7] wire io_dpath_gstatus_spp_0 = io_dpath_gstatus_spp; // @[PTW.scala:219:7] wire io_dpath_gstatus_mpie_0 = io_dpath_gstatus_mpie; // @[PTW.scala:219:7] wire io_dpath_gstatus_ube_0 = io_dpath_gstatus_ube; // @[PTW.scala:219:7] wire io_dpath_gstatus_spie_0 = io_dpath_gstatus_spie; // @[PTW.scala:219:7] wire io_dpath_gstatus_upie_0 = io_dpath_gstatus_upie; // @[PTW.scala:219:7] wire io_dpath_gstatus_mie_0 = io_dpath_gstatus_mie; // @[PTW.scala:219:7] wire io_dpath_gstatus_hie_0 = io_dpath_gstatus_hie; // @[PTW.scala:219:7] wire io_dpath_gstatus_sie_0 = io_dpath_gstatus_sie; // @[PTW.scala:219:7] wire io_dpath_gstatus_uie_0 = io_dpath_gstatus_uie; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_0_addr_0 = io_dpath_pmp_0_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_0_mask_0 = io_dpath_pmp_0_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_1_addr_0 = io_dpath_pmp_1_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_1_mask_0 = io_dpath_pmp_1_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_2_addr_0 = io_dpath_pmp_2_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_2_mask_0 = io_dpath_pmp_2_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_3_addr_0 = io_dpath_pmp_3_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_3_mask_0 = io_dpath_pmp_3_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_4_addr_0 = io_dpath_pmp_4_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_4_mask_0 = io_dpath_pmp_4_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_5_addr_0 = io_dpath_pmp_5_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_5_mask_0 = io_dpath_pmp_5_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_6_addr_0 = io_dpath_pmp_6_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_6_mask_0 = io_dpath_pmp_6_mask; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w; // @[PTW.scala:219:7] wire io_dpath_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r; // @[PTW.scala:219:7] wire [29:0] io_dpath_pmp_7_addr_0 = io_dpath_pmp_7_addr; // @[PTW.scala:219:7] wire [31:0] io_dpath_pmp_7_mask_0 = io_dpath_pmp_7_mask; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_req_bits_bits_vstage1 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_req_bits_bits_stage2 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_fragmented_superpage = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_signed = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_resp = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_alloc = 1'h0; // @[PTW.scala:219:7] wire io_mem_req_bits_no_xcpt = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_kill = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_xcpt_gf_st = 1'h0; // @[PTW.scala:219:7] wire io_mem_s2_gpa_is_pte = 1'h0; // @[PTW.scala:219:7] wire io_mem_keep_clock_enabled = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_mbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_ube = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_upie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_hie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_status_uie = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtsr = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtw = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vtvm = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_hu = 1'h0; // @[PTW.scala:219:7] wire io_dpath_hstatus_vsbe = 1'h0; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd_rv32 = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2miss = 1'h0; // @[PTW.scala:219:7] wire io_dpath_perf_l2hit = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_0_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_1_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_2_set = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_stall = 1'h0; // @[PTW.scala:219:7] wire io_dpath_customCSRs_csrs_3_set = 1'h0; // @[PTW.scala:219:7] wire _resp_valid_WIRE_0 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_1 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_2 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_3 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_4 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_5 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_6 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_7 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_8 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_9 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_10 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_11 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_12 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_13 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_14 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_15 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_16 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_17 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_18 = 1'h0; // @[PTW.scala:242:35] wire _resp_valid_WIRE_19 = 1'h0; // @[PTW.scala:242:35] wire _hits_T_9 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_10 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_11 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_12 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_13 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_14 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_15 = 1'h0; // @[PTW.scala:366:27] wire _hits_T_16 = 1'h0; // @[PTW.scala:366:27] wire _hit_T_1 = 1'h0; // @[PTW.scala:367:20] wire stage2_pte_cache_hit = 1'h0; // @[PTW.scala:367:24] wire _state_reg_set_left_older_T_9 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_set_left_older_T_10 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_70 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_71 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_74 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_75 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_set_left_older_T_11 = 1'h0; // @[Replacement.scala:196:43] wire _state_reg_T_81 = 1'h0; // @[package.scala:163:13] wire _state_reg_T_82 = 1'h0; // @[Replacement.scala:218:17] wire _state_reg_T_85 = 1'h0; // @[Replacement.scala:207:62] wire _state_reg_T_86 = 1'h0; // @[Replacement.scala:218:17] wire l2_pte_d = 1'h0; // @[PTW.scala:403:113] wire l2_pte_a = 1'h0; // @[PTW.scala:403:113] wire l2_pte_g = 1'h0; // @[PTW.scala:403:113] wire l2_pte_u = 1'h0; // @[PTW.scala:403:113] wire l2_pte_x = 1'h0; // @[PTW.scala:403:113] wire l2_pte_w = 1'h0; // @[PTW.scala:403:113] wire l2_pte_r = 1'h0; // @[PTW.scala:403:113] wire l2_pte_v = 1'h0; // @[PTW.scala:403:113] wire _pmpHomogeneous_WIRE_cfg_l = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_x = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_w = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_WIRE_cfg_r = 1'h0; // @[PMP.scala:137:40] wire _pmpHomogeneous_beginsAfterLower_T_4 = 1'h0; // @[PMP.scala:106:32] wire pmpHomogeneous_endsBeforeLower = 1'h0; // @[PMP.scala:110:40] wire _io_requestor_0_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_1_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_2_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_3_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_4_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_5_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_6_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_7_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_8_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_9_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_10_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_11_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_12_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_13_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_14_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_15_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_16_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_17_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_18_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _io_requestor_19_resp_bits_fragmented_superpage_T = 1'h0; // @[PTW.scala:563:81] wire _stage2_final_T_1 = 1'h0; // @[PTW.scala:595:53] wire _resp_gf_T_2 = 1'h0; // @[PTW.scala:603:71] wire _r_pte_T_1 = 1'h0; // @[PTW.scala:670:16] wire _r_pte_T_3 = 1'h0; // @[PTW.scala:670:29] wire _r_pte_T_5 = 1'h0; // @[PTW.scala:672:25] wire r_pte_idxs_0 = 1'h0; // @[PTW.scala:778:58] wire r_pte_pte_d = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_a = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_g = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_u = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_x = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_w = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_r = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_v = 1'h0; // @[PTW.scala:780:26] wire r_pte_pte_1_d = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_a = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_g = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_u = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_x = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_w = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_r = 1'h0; // @[PTW.scala:771:26] wire r_pte_pte_1_v = 1'h0; // @[PTW.scala:771:26] wire [15:0] io_requestor_0_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_0_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_1_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_2_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_3_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_3_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_3_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_4_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_4_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_4_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_5_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_5_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_5_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_6_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_6_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_6_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_7_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_7_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_7_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_8_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_8_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_8_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_9_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_9_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_9_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_10_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_10_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_10_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_11_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_11_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_11_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_12_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_12_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_12_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_13_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_13_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_13_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_14_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_14_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_14_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_15_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_15_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_15_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_16_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_16_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_16_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_17_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_17_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_17_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_18_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_18_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_18_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_19_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_19_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_requestor_19_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_ptbr_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_hgatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] io_dpath_vsatp_asid = 16'h0; // @[PTW.scala:219:7] wire [15:0] satp_asid = 16'h0; // @[PTW.scala:285:17] wire [3:0] io_requestor_0_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_0_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_3_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_3_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_4_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_4_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_5_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_5_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_6_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_6_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_7_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_7_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_8_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_8_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_9_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_9_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_10_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_10_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_11_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_11_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_12_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_12_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_13_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_13_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_14_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_14_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_15_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_15_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_16_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_16_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_17_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_17_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_18_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_18_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_19_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_requestor_19_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_hgatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] io_dpath_vsatp_mode = 4'h0; // @[PTW.scala:219:7] wire [3:0] hits_lo_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hits_hi_1 = 4'h0; // @[package.scala:45:27] wire [3:0] hi_2 = 4'h0; // @[OneHot.scala:30:18] wire [3:0] lo_2 = 4'h0; // @[OneHot.scala:31:18] wire [43:0] io_requestor_0_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_4_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_4_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_5_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_5_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_6_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_6_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_7_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_7_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_8_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_8_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_9_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_9_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_10_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_10_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_11_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_11_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_12_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_12_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_13_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_13_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_14_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_14_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_15_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_15_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_16_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_16_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_17_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_17_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_18_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_18_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_19_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_requestor_19_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_hgatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] io_dpath_vsatp_ppn = 44'h0; // @[PTW.scala:219:7] wire [43:0] l2_pte_ppn = 44'h0; // @[PTW.scala:403:113] wire [43:0] r_pte_pte_4_ppn = 44'h0; // @[PTW.scala:780:26] wire [43:0] _r_pte_pte_ppn_T_5 = 44'h0; // @[PTW.scala:781:19] wire io_requestor_0_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_0_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_2_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_2_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_3_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_3_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_4_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_4_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_5_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_5_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_6_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_6_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_7_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_7_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_8_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_8_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_9_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_9_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_10_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_10_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_11_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_11_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_12_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_12_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_13_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_13_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_14_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_14_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_15_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_15_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_16_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_16_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_17_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_17_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_18_req_bits_valid = 1'h1; // @[PTW.scala:219:7] wire io_requestor_18_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_19_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire io_mem_req_bits_phys = 1'h1; // @[PTW.scala:219:7] wire io_mem_clock_enabled = 1'h1; // @[PTW.scala:219:7] wire io_dpath_status_sd = 1'h1; // @[PTW.scala:219:7] wire io_dpath_gstatus_sd = 1'h1; // @[PTW.scala:219:7] wire state_reg_set_left_older_9 = 1'h1; // @[Replacement.scala:196:33] wire state_reg_set_left_older_10 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_72 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_76 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_77 = 1'h1; // @[Replacement.scala:206:16] wire state_reg_set_left_older_11 = 1'h1; // @[Replacement.scala:196:33] wire _state_reg_T_83 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_87 = 1'h1; // @[Replacement.scala:218:7] wire _state_reg_T_88 = 1'h1; // @[Replacement.scala:206:16] wire _io_dpath_perf_pte_hit_T_2 = 1'h1; // @[PTW.scala:394:60] wire _pmaPgLevelHomogeneous_T_1 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_2 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_3 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_4 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_5 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_6 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_19 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_20 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_35 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_36 = 1'h1; // @[TLBPermissions.scala:87:22] wire _pmaPgLevelHomogeneous_T_97 = 1'h1; // @[TLBPermissions.scala:87:22] wire pmpHomogeneous_beginsAfterLower = 1'h1; // @[PMP.scala:106:28] wire _stage2_final_T = 1'h1; // @[PTW.scala:595:56] wire _r_pte_T = 1'h1; // @[PTW.scala:670:19] wire [22:0] io_requestor_0_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_3_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_4_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_5_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_6_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_7_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_8_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_9_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_10_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_11_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_12_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_13_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_14_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_15_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_16_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_17_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_18_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_requestor_19_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [22:0] io_dpath_status_zero2 = 23'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_3_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_4_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_5_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_6_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_7_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_8_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_9_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_10_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_11_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_12_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_13_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_14_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_15_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_16_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_17_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_18_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_requestor_19_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_tag = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_req_bits_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_mem_s1_data_mask = 8'h0; // @[PTW.scala:219:7] wire [7:0] io_dpath_status_zero1 = 8'h0; // @[PTW.scala:219:7] wire [7:0] _hits_T_17 = 8'h0; // @[package.scala:45:27] wire [7:0] hits_1 = 8'h0; // @[PTW.scala:366:43] wire [1:0] io_requestor_0_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_size = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_xs = 2'h3; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_vs = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero3 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_zero2 = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_0_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_1_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_2_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_3_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_4_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_5_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_6_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] io_dpath_pmp_7_cfg_res = 2'h0; // @[PTW.scala:219:7] wire [1:0] _r_hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:286:42] wire [1:0] r_hgatp_initial_count = 2'h0; // @[PTW.scala:286:58] wire [1:0] _count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] count_1 = 2'h0; // @[PTW.scala:786:44] wire [1:0] hits_lo_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_lo_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_lo_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hits_hi_hi_1 = 2'h0; // @[package.scala:45:27] wire [1:0] hi_3 = 2'h0; // @[OneHot.scala:30:18] wire [1:0] lo_3 = 2'h0; // @[OneHot.scala:31:18] wire [1:0] _state_reg_T_69 = 2'h0; // @[package.scala:163:13] wire [1:0] _state_reg_T_80 = 2'h0; // @[Replacement.scala:207:62] wire [1:0] l2_pte_reserved_for_software = 2'h0; // @[PTW.scala:403:113] wire [1:0] _pmpHomogeneous_WIRE_cfg_res = 2'h0; // @[PMP.scala:137:40] wire [1:0] _pmpHomogeneous_WIRE_cfg_a = 2'h0; // @[PMP.scala:137:40] wire [1:0] _satp_initial_count_T_1 = 2'h0; // @[PTW.scala:586:45] wire [1:0] satp_initial_count = 2'h0; // @[PTW.scala:586:61] wire [1:0] _vsatp_initial_count_T_1 = 2'h0; // @[PTW.scala:587:46] wire [1:0] vsatp_initial_count = 2'h0; // @[PTW.scala:587:62] wire [1:0] _hgatp_initial_count_T_1 = 2'h0; // @[PTW.scala:588:46] wire [1:0] hgatp_initial_count = 2'h0; // @[PTW.scala:588:62] wire [1:0] _count_T_3 = 2'h0; // @[PTW.scala:596:27] wire [1:0] _aux_count_T = 2'h0; // @[PTW.scala:597:27] wire [1:0] _resp_gf_count_T_1 = 2'h0; // @[PTW.scala:786:28] wire [1:0] resp_gf_count = 2'h0; // @[PTW.scala:786:44] wire [1:0] _resp_gf_T = 2'h0; // @[package.scala:24:40] wire [1:0] _r_pte_count_T_1 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs = 2'h0; // @[PTW.scala:779:27] wire [1:0] r_pte_pte_reserved_for_software = 2'h0; // @[PTW.scala:780:26] wire [1:0] r_pte_pte_1_reserved_for_software = 2'h0; // @[PTW.scala:771:26] wire [1:0] _r_pte_count_T_4 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_1 = 2'h0; // @[PTW.scala:777:44] wire [1:0] _r_pte_count_T_7 = 2'h0; // @[PTW.scala:777:28] wire [1:0] r_pte_count_2 = 2'h0; // @[PTW.scala:777:44] wire [1:0] r_pte_lsbs_2 = 2'h0; // @[PTW.scala:779:27] wire [29:0] io_requestor_0_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] io_dpath_hstatus_zero6 = 30'h0; // @[PTW.scala:219:7] wire [29:0] _pmpHomogeneous_WIRE_addr = 30'h0; // @[PMP.scala:137:40] wire [8:0] io_requestor_0_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_1_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_2_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_3_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_4_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_5_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_6_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_7_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_8_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_9_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_10_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_11_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_12_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_13_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_14_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_15_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_16_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_17_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_18_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_requestor_19_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [8:0] io_dpath_hstatus_zero5 = 9'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_0_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_1_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_2_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_3_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_4_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_5_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_6_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_7_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_8_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_9_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_10_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_11_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_12_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_13_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_14_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_15_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_16_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_17_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_18_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_requestor_19_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [5:0] io_dpath_hstatus_vgein = 6'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_0_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_1_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_2_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_3_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_4_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_5_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_6_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_7_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_8_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_9_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_10_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_11_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_12_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_13_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_14_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_15_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_16_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_17_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_18_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_requestor_19_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_mem_req_bits_cmd = 5'h0; // @[PTW.scala:219:7] wire [4:0] io_dpath_hstatus_zero1 = 5'h0; // @[PTW.scala:219:7] wire [41:0] _r_pte_pte_ppn_T_4 = 42'h0; // @[PTW.scala:781:30] wire [16:0] r_pte_idxs_0_2 = 17'h0; // @[PTW.scala:778:58] wire [2:0] _r_hgatp_initial_count_T = 3'h0; // @[PTW.scala:286:42] wire [2:0] _r_hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:286:58] wire [2:0] _count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] state_reg_touch_way_sized_3 = 3'h0; // @[package.scala:163:13] wire [2:0] _satp_initial_count_T = 3'h0; // @[PTW.scala:586:45] wire [2:0] _satp_initial_count_T_2 = 3'h0; // @[PTW.scala:586:61] wire [2:0] _vsatp_initial_count_T = 3'h0; // @[PTW.scala:587:46] wire [2:0] _vsatp_initial_count_T_2 = 3'h0; // @[PTW.scala:587:62] wire [2:0] _hgatp_initial_count_T = 3'h0; // @[PTW.scala:588:46] wire [2:0] _hgatp_initial_count_T_2 = 3'h0; // @[PTW.scala:588:62] wire [2:0] _resp_gf_count_T = 3'h0; // @[PTW.scala:786:28] wire [2:0] _resp_gf_count_T_2 = 3'h0; // @[PTW.scala:786:44] wire [2:0] _r_pte_count_T = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_2 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_3 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_5 = 3'h0; // @[PTW.scala:777:44] wire [2:0] _r_pte_count_T_6 = 3'h0; // @[PTW.scala:777:28] wire [2:0] _r_pte_count_T_8 = 3'h0; // @[PTW.scala:777:44] wire [19:0] stage2_pte_cache_data = 20'h0; // @[Mux.scala:30:73] wire [31:0] _pmpHomogeneous_WIRE_mask = 32'h0; // @[PMP.scala:137:40] wire [31:0] _pmpHomogeneous_beginsAfterLower_T = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_3 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_5 = 32'h0; // @[PMP.scala:110:58] wire [1:0] io_requestor_0_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_sxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_status_uxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_hstatus_vsxl = 2'h2; // @[PTW.scala:219:7] wire [1:0] io_dpath_gstatus_uxl = 2'h2; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_req_bits_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_mem_s1_data_data = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_0_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_1_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_2_sdata = 64'h0; // @[PTW.scala:219:7] wire [63:0] io_dpath_customCSRs_csrs_3_sdata = 64'h0; // @[PTW.scala:219:7] wire [1:0] io_mem_req_bits_dprv = 2'h1; // @[PTW.scala:219:7] wire [9:0] l2_pte_reserved_for_future = 10'h0; // @[PTW.scala:403:113] wire [9:0] r_pte_pte_reserved_for_future = 10'h0; // @[PTW.scala:780:26] wire [9:0] r_pte_pte_1_reserved_for_future = 10'h0; // @[PTW.scala:771:26] wire [2:0] _next_state_T_2 = 3'h4; // @[PTW.scala:636:24] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_1 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:29] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:48] wire [39:0] tag_1 = 40'h8000000000; // @[PTW.scala:363:18] wire [8:0] pte_addr_mask = 9'h1FF; // @[PTW.scala:324:23] wire [38:0] _tag_T = 39'h0; // @[package.scala:138:15] wire [1:0] max_count; // @[PTW.scala:289:25] wire _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_3_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_3_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_4_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_4_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_5_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_5_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_6_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_6_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_7_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_7_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_8_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_8_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_9_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_9_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_10_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_10_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_11_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_11_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_12_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_12_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_13_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_13_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_14_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_14_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_15_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_15_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_16_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_16_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_17_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_17_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_18_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_18_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_requestor_19_resp_bits_homogeneous_T; // @[PTW.scala:562:58] wire _io_requestor_19_resp_bits_gpa_is_pte_T; // @[PTW.scala:567:45] wire _io_mem_req_valid_T_2; // @[PTW.scala:515:39] wire _io_mem_req_bits_dv_T_1; // @[PTW.scala:523:40] wire _io_mem_s1_kill_T_2; // @[PTW.scala:531:51] wire [3:0] io_requestor_0_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_1_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_2_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_3_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_4_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_5_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_6_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_7_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_8_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_9_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_10_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_11_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_12_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_13_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_14_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_15_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_16_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_17_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_18_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] io_requestor_19_ptbr_mode_0 = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7] wire [3:0] satp_mode = io_dpath_ptbr_mode_0; // @[PTW.scala:219:7, :285:17] wire [43:0] io_requestor_0_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_4_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_5_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_6_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_7_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_8_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_9_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_10_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_11_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_12_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_13_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_14_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_15_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_16_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_17_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_18_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_19_ptbr_ppn_0 = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7] wire [43:0] satp_ppn = io_dpath_ptbr_ppn_0; // @[PTW.scala:219:7, :285:17] wire io_requestor_0_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_3_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_4_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_5_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_6_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_7_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_8_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_9_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_10_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_11_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_12_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_13_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_14_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_15_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_16_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_17_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_18_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_19_status_debug_0 = io_dpath_status_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_3_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_4_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_5_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_6_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_7_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_8_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_9_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_10_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_11_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_12_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_13_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_14_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_15_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_16_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_17_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_18_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_19_status_cease_0 = io_dpath_status_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_3_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_4_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_5_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_6_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_7_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_8_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_9_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_10_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_11_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_12_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_13_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_14_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_15_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_16_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_17_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_18_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire io_requestor_19_status_wfi_0 = io_dpath_status_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_status_isa_0 = io_dpath_status_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_dprv_0 = io_dpath_status_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_3_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_4_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_5_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_6_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_7_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_8_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_9_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_10_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_11_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_12_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_13_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_14_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_15_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_16_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_17_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_18_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire io_requestor_19_status_dv_0 = io_dpath_status_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_prv_0 = io_dpath_status_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_1_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_2_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_3_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_4_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_5_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_6_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_7_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_8_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_9_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_10_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_11_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_12_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_13_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_14_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_15_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_16_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_17_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_18_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_19_status_v_0 = io_dpath_status_v_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_4_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_5_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_6_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_7_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_8_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_9_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_10_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_11_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_12_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_13_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_14_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_15_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_16_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_17_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_18_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_19_status_mpv_0 = io_dpath_status_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_3_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_4_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_5_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_6_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_7_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_8_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_9_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_10_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_11_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_12_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_13_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_14_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_15_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_16_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_17_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_18_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_19_status_gva_0 = io_dpath_status_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_3_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_4_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_5_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_6_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_7_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_8_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_9_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_10_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_11_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_12_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_13_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_14_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_15_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_16_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_17_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_18_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_19_status_tsr_0 = io_dpath_status_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_3_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_4_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_5_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_6_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_7_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_8_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_9_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_10_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_11_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_12_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_13_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_14_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_15_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_16_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_17_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_18_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_19_status_tw_0 = io_dpath_status_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_3_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_4_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_5_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_6_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_7_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_8_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_9_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_10_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_11_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_12_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_13_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_14_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_15_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_16_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_17_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_18_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_19_status_tvm_0 = io_dpath_status_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_4_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_5_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_6_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_7_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_8_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_9_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_10_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_11_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_12_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_13_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_14_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_15_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_16_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_17_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_18_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_19_status_mxr_0 = io_dpath_status_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_3_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_4_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_5_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_6_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_7_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_8_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_9_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_10_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_11_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_12_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_13_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_14_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_15_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_16_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_17_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_18_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_19_status_sum_0 = io_dpath_status_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_4_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_5_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_6_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_7_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_8_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_9_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_10_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_11_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_12_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_13_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_14_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_15_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_16_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_17_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_18_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire io_requestor_19_status_mprv_0 = io_dpath_status_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_fs_0 = io_dpath_status_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_status_mpp_0 = io_dpath_status_mpp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_3_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_4_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_5_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_6_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_7_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_8_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_9_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_10_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_11_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_12_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_13_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_14_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_15_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_16_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_17_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_18_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_19_status_spp_0 = io_dpath_status_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_4_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_5_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_6_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_7_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_8_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_9_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_10_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_11_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_12_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_13_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_14_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_15_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_16_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_17_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_18_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_19_status_mpie_0 = io_dpath_status_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_4_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_5_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_6_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_7_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_8_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_9_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_10_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_11_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_12_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_13_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_14_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_15_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_16_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_17_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_18_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_19_status_spie_0 = io_dpath_status_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_4_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_5_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_6_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_7_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_8_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_9_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_10_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_11_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_12_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_13_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_14_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_15_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_16_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_17_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_18_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_19_status_mie_0 = io_dpath_status_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_3_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_4_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_5_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_6_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_7_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_8_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_9_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_10_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_11_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_12_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_13_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_14_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_15_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_16_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_17_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_18_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_19_status_sie_0 = io_dpath_status_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_spvp_0 = io_dpath_hstatus_spvp_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_spv_0 = io_dpath_hstatus_spv_0; // @[PTW.scala:219:7] wire io_requestor_0_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_3_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_4_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_5_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_6_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_7_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_8_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_9_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_10_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_11_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_12_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_13_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_14_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_15_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_16_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_17_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_18_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_19_hstatus_gva_0 = io_dpath_hstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_debug_0 = io_dpath_gstatus_debug_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_cease_0 = io_dpath_gstatus_cease_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_wfi_0 = io_dpath_gstatus_wfi_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_gstatus_isa_0 = io_dpath_gstatus_isa_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_dprv_0 = io_dpath_gstatus_dprv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_dv_0 = io_dpath_gstatus_dv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_prv_0 = io_dpath_gstatus_prv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_v_0 = io_dpath_gstatus_v_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_0_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_1_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_2_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_3_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_4_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_5_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_6_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_7_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_8_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_9_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_10_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_11_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_12_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_13_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_14_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_15_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_16_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_17_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_18_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire [22:0] io_requestor_19_gstatus_zero2_0 = io_dpath_gstatus_zero2_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_mpv_0 = io_dpath_gstatus_mpv_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_gva_0 = io_dpath_gstatus_gva_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_mbe_0 = io_dpath_gstatus_mbe_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_sbe_0 = io_dpath_gstatus_sbe_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_sxl_0 = io_dpath_gstatus_sxl_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_0_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_1_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_2_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_3_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_4_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_5_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_6_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_7_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_8_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_9_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_10_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_11_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_12_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_13_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_14_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_15_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_16_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_17_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_18_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire [7:0] io_requestor_19_gstatus_zero1_0 = io_dpath_gstatus_zero1_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_tsr_0 = io_dpath_gstatus_tsr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_tw_0 = io_dpath_gstatus_tw_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_tvm_0 = io_dpath_gstatus_tvm_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_mxr_0 = io_dpath_gstatus_mxr_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_sum_0 = io_dpath_gstatus_sum_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_mprv_0 = io_dpath_gstatus_mprv_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_fs_0 = io_dpath_gstatus_fs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_mpp_0 = io_dpath_gstatus_mpp_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_gstatus_vs_0 = io_dpath_gstatus_vs_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_spp_0 = io_dpath_gstatus_spp_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_mpie_0 = io_dpath_gstatus_mpie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_ube_0 = io_dpath_gstatus_ube_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_spie_0 = io_dpath_gstatus_spie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_upie_0 = io_dpath_gstatus_upie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_mie_0 = io_dpath_gstatus_mie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_hie_0 = io_dpath_gstatus_hie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_sie_0 = io_dpath_gstatus_sie_0; // @[PTW.scala:219:7] wire io_requestor_0_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_1_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_2_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_3_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_4_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_5_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_6_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_7_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_8_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_9_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_10_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_11_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_12_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_13_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_14_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_15_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_16_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_17_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_18_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_19_gstatus_uie_0 = io_dpath_gstatus_uie_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_0_cfg_l_0 = io_dpath_pmp_0_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_0_cfg_a_0 = io_dpath_pmp_0_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_0_cfg_x_0 = io_dpath_pmp_0_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_0_cfg_w_0 = io_dpath_pmp_0_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_0_cfg_r_0 = io_dpath_pmp_0_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_0_addr_0 = io_dpath_pmp_0_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_0_mask_0 = io_dpath_pmp_0_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_1_cfg_l_0 = io_dpath_pmp_1_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_1_cfg_a_0 = io_dpath_pmp_1_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_1_cfg_x_0 = io_dpath_pmp_1_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_1_cfg_w_0 = io_dpath_pmp_1_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_1_cfg_r_0 = io_dpath_pmp_1_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_1_addr_0 = io_dpath_pmp_1_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_1_mask_0 = io_dpath_pmp_1_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_2_cfg_l_0 = io_dpath_pmp_2_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_2_cfg_a_0 = io_dpath_pmp_2_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_2_cfg_x_0 = io_dpath_pmp_2_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_2_cfg_w_0 = io_dpath_pmp_2_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_2_cfg_r_0 = io_dpath_pmp_2_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_2_addr_0 = io_dpath_pmp_2_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_2_mask_0 = io_dpath_pmp_2_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_3_cfg_l_0 = io_dpath_pmp_3_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_3_cfg_a_0 = io_dpath_pmp_3_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_3_cfg_x_0 = io_dpath_pmp_3_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_3_cfg_w_0 = io_dpath_pmp_3_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_3_cfg_r_0 = io_dpath_pmp_3_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_3_addr_0 = io_dpath_pmp_3_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_3_mask_0 = io_dpath_pmp_3_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_4_cfg_l_0 = io_dpath_pmp_4_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_4_cfg_a_0 = io_dpath_pmp_4_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_4_cfg_x_0 = io_dpath_pmp_4_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_4_cfg_w_0 = io_dpath_pmp_4_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_4_cfg_r_0 = io_dpath_pmp_4_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_4_addr_0 = io_dpath_pmp_4_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_4_mask_0 = io_dpath_pmp_4_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_5_cfg_l_0 = io_dpath_pmp_5_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_5_cfg_a_0 = io_dpath_pmp_5_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_5_cfg_x_0 = io_dpath_pmp_5_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_5_cfg_w_0 = io_dpath_pmp_5_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_5_cfg_r_0 = io_dpath_pmp_5_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_5_addr_0 = io_dpath_pmp_5_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_5_mask_0 = io_dpath_pmp_5_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_6_cfg_l_0 = io_dpath_pmp_6_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_6_cfg_a_0 = io_dpath_pmp_6_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_6_cfg_x_0 = io_dpath_pmp_6_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_6_cfg_w_0 = io_dpath_pmp_6_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_6_cfg_r_0 = io_dpath_pmp_6_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_6_addr_0 = io_dpath_pmp_6_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_6_mask_0 = io_dpath_pmp_6_mask_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_7_cfg_l_0 = io_dpath_pmp_7_cfg_l_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_pmp_7_cfg_a_0 = io_dpath_pmp_7_cfg_a_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_7_cfg_x_0 = io_dpath_pmp_7_cfg_x_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_7_cfg_w_0 = io_dpath_pmp_7_cfg_w_0; // @[PTW.scala:219:7] wire io_requestor_0_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_1_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_2_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_3_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_4_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_5_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_6_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_7_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_8_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_9_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_10_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_11_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_12_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_13_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_14_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_15_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_16_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_17_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_18_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire io_requestor_19_pmp_7_cfg_r_0 = io_dpath_pmp_7_cfg_r_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_0_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_1_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_2_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_3_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_4_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_5_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_6_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_7_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_8_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_9_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_10_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_11_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_12_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_13_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_14_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_15_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_16_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_17_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_18_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [29:0] io_requestor_19_pmp_7_addr_0 = io_dpath_pmp_7_addr_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_0_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_1_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_2_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_3_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_4_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_5_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_6_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_7_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_8_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_9_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_10_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_11_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_12_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_13_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_14_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_15_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_16_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_17_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_18_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire [31:0] io_requestor_19_pmp_7_mask_0 = io_dpath_pmp_7_mask_0; // @[PTW.scala:219:7] wire _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:394:57] wire io_requestor_0_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_0_ren_0 = io_dpath_customCSRs_csrs_0_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_0_wen_0 = io_dpath_customCSRs_csrs_0_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_0_wdata_0 = io_dpath_customCSRs_csrs_0_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_0_value_0 = io_dpath_customCSRs_csrs_0_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_1_ren_0 = io_dpath_customCSRs_csrs_1_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_1_wen_0 = io_dpath_customCSRs_csrs_1_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_1_wdata_0 = io_dpath_customCSRs_csrs_1_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_1_value_0 = io_dpath_customCSRs_csrs_1_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_2_ren_0 = io_dpath_customCSRs_csrs_2_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_2_wen_0 = io_dpath_customCSRs_csrs_2_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_2_wdata_0 = io_dpath_customCSRs_csrs_2_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_2_value_0 = io_dpath_customCSRs_csrs_2_value_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_3_ren_0 = io_dpath_customCSRs_csrs_3_ren_0; // @[PTW.scala:219:7] wire io_requestor_0_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_1_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_2_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_3_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_4_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_5_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_6_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_7_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_8_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_9_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_10_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_11_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_12_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_13_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_14_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_15_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_16_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_17_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_18_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire io_requestor_19_customCSRs_csrs_3_wen_0 = io_dpath_customCSRs_csrs_3_wen_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_3_wdata_0 = io_dpath_customCSRs_csrs_3_wdata_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_0_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_1_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_2_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_3_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_4_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_5_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_6_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_7_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_8_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_9_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_10_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_11_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_12_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_13_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_14_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_15_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_16_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_17_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_18_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire [63:0] io_requestor_19_customCSRs_csrs_3_value_0 = io_dpath_customCSRs_csrs_3_value_0; // @[PTW.scala:219:7] wire _io_dpath_clock_enabled_T; // @[PTW.scala:245:39] wire io_requestor_0_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_0_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_0_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_0_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_0_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_0_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_1_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_1_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_1_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_1_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_1_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_1_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_2_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_2_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_2_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_2_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_2_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_2_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_3_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_3_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_3_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_3_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_3_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_3_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_4_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_4_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_4_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_4_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_4_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_4_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_5_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_5_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_5_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_5_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_5_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_5_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_6_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_6_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_6_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_6_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_6_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_6_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_7_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_7_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_7_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_7_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_7_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_7_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_8_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_8_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_8_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_8_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_8_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_8_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_9_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_9_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_9_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_9_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_9_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_9_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_10_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_10_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_10_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_10_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_10_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_10_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_11_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_11_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_11_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_11_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_11_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_11_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_12_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_12_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_12_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_12_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_12_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_12_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_13_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_13_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_13_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_13_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_13_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_13_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_14_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_14_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_14_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_14_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_14_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_14_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_15_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_15_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_15_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_15_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_15_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_15_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_16_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_16_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_16_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_16_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_16_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_16_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_17_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_17_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_17_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_17_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_17_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_17_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_18_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_18_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_18_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_18_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_18_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_18_resp_valid_0; // @[PTW.scala:219:7] wire io_requestor_19_req_ready_0; // @[PTW.scala:219:7] wire [9:0] io_requestor_19_resp_bits_pte_reserved_for_future_0; // @[PTW.scala:219:7] wire [43:0] io_requestor_19_resp_bits_pte_ppn_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_resp_bits_pte_reserved_for_software_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_d_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_a_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_g_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_u_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_x_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_w_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_r_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pte_v_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_gpa_valid_0; // @[PTW.scala:219:7] wire [38:0] io_requestor_19_resp_bits_gpa_bits_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_ae_ptw_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_ae_final_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_pf_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_gf_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_hr_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_hw_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_hx_0; // @[PTW.scala:219:7] wire [1:0] io_requestor_19_resp_bits_level_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_homogeneous_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_bits_gpa_is_pte_0; // @[PTW.scala:219:7] wire io_requestor_19_resp_valid_0; // @[PTW.scala:219:7] wire [39:0] io_mem_req_bits_addr_0; // @[PTW.scala:219:7] wire io_mem_req_bits_dv_0; // @[PTW.scala:219:7] wire io_mem_req_valid_0; // @[PTW.scala:219:7] wire io_mem_s1_kill_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_miss_0; // @[PTW.scala:219:7] wire io_dpath_perf_pte_hit_0; // @[PTW.scala:219:7] wire io_dpath_clock_enabled_0; // @[PTW.scala:219:7] reg [2:0] state; // @[PTW.scala:233:22] wire l2_refill_wire; // @[PTW.scala:234:28] wire _arb_io_out_ready_T = ~(|state); // @[PTW.scala:233:22, :240:30] wire _arb_io_out_ready_T_1 = ~l2_refill_wire; // @[PTW.scala:234:28, :240:46] wire _arb_io_out_ready_T_2 = _arb_io_out_ready_T & _arb_io_out_ready_T_1; // @[PTW.scala:240:{30,43,46}] reg resp_valid_0; // @[PTW.scala:242:27] assign io_requestor_0_resp_valid_0 = resp_valid_0; // @[PTW.scala:219:7, :242:27] reg resp_valid_1; // @[PTW.scala:242:27] assign io_requestor_1_resp_valid_0 = resp_valid_1; // @[PTW.scala:219:7, :242:27] reg resp_valid_2; // @[PTW.scala:242:27] assign io_requestor_2_resp_valid_0 = resp_valid_2; // @[PTW.scala:219:7, :242:27] reg resp_valid_3; // @[PTW.scala:242:27] assign io_requestor_3_resp_valid_0 = resp_valid_3; // @[PTW.scala:219:7, :242:27] reg resp_valid_4; // @[PTW.scala:242:27] assign io_requestor_4_resp_valid_0 = resp_valid_4; // @[PTW.scala:219:7, :242:27] reg resp_valid_5; // @[PTW.scala:242:27] assign io_requestor_5_resp_valid_0 = resp_valid_5; // @[PTW.scala:219:7, :242:27] reg resp_valid_6; // @[PTW.scala:242:27] assign io_requestor_6_resp_valid_0 = resp_valid_6; // @[PTW.scala:219:7, :242:27] reg resp_valid_7; // @[PTW.scala:242:27] assign io_requestor_7_resp_valid_0 = resp_valid_7; // @[PTW.scala:219:7, :242:27] reg resp_valid_8; // @[PTW.scala:242:27] assign io_requestor_8_resp_valid_0 = resp_valid_8; // @[PTW.scala:219:7, :242:27] reg resp_valid_9; // @[PTW.scala:242:27] assign io_requestor_9_resp_valid_0 = resp_valid_9; // @[PTW.scala:219:7, :242:27] reg resp_valid_10; // @[PTW.scala:242:27] assign io_requestor_10_resp_valid_0 = resp_valid_10; // @[PTW.scala:219:7, :242:27] reg resp_valid_11; // @[PTW.scala:242:27] assign io_requestor_11_resp_valid_0 = resp_valid_11; // @[PTW.scala:219:7, :242:27] reg resp_valid_12; // @[PTW.scala:242:27] assign io_requestor_12_resp_valid_0 = resp_valid_12; // @[PTW.scala:219:7, :242:27] reg resp_valid_13; // @[PTW.scala:242:27] assign io_requestor_13_resp_valid_0 = resp_valid_13; // @[PTW.scala:219:7, :242:27] reg resp_valid_14; // @[PTW.scala:242:27] assign io_requestor_14_resp_valid_0 = resp_valid_14; // @[PTW.scala:219:7, :242:27] reg resp_valid_15; // @[PTW.scala:242:27] assign io_requestor_15_resp_valid_0 = resp_valid_15; // @[PTW.scala:219:7, :242:27] reg resp_valid_16; // @[PTW.scala:242:27] assign io_requestor_16_resp_valid_0 = resp_valid_16; // @[PTW.scala:219:7, :242:27] reg resp_valid_17; // @[PTW.scala:242:27] assign io_requestor_17_resp_valid_0 = resp_valid_17; // @[PTW.scala:219:7, :242:27] reg resp_valid_18; // @[PTW.scala:242:27] assign io_requestor_18_resp_valid_0 = resp_valid_18; // @[PTW.scala:219:7, :242:27] reg resp_valid_19; // @[PTW.scala:242:27] assign io_requestor_19_resp_valid_0 = resp_valid_19; // @[PTW.scala:219:7, :242:27] wire _clock_en_T = |state; // @[PTW.scala:233:22, :240:30, :244:24] wire _clock_en_T_1 = _clock_en_T | l2_refill_wire; // @[PTW.scala:234:28, :244:{24,36}] wire _clock_en_T_2 = _clock_en_T_1 | _arb_io_out_valid; // @[PTW.scala:236:19, :244:{36,54}] wire _clock_en_T_3 = _clock_en_T_2 | io_dpath_sfence_valid_0; // @[PTW.scala:219:7, :244:{54,74}] wire _clock_en_T_4 = io_dpath_customCSRs_csrs_0_value_0[0]; // @[CustomCSRs.scala:43:61] wire clock_en = _clock_en_T_3 | _clock_en_T_4; // @[CustomCSRs.scala:43:61] assign _io_dpath_clock_enabled_T = clock_en; // @[PTW.scala:244:99, :245:39] assign io_dpath_clock_enabled_0 = _io_dpath_clock_enabled_T; // @[PTW.scala:219:7, :245:39] reg invalidated; // @[PTW.scala:251:24] reg [1:0] count; // @[PTW.scala:259:18] wire [1:0] _r_pte_truncIdx_T = count; // @[package.scala:38:21] reg resp_ae_ptw; // @[PTW.scala:260:24] assign io_requestor_0_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_1_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_2_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_3_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_4_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_5_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_6_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_7_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_8_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_9_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_10_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_11_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_12_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_13_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_14_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_15_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_16_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_17_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_18_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] assign io_requestor_19_resp_bits_ae_ptw_0 = resp_ae_ptw; // @[PTW.scala:219:7, :260:24] reg resp_ae_final; // @[PTW.scala:261:26] assign io_requestor_0_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_1_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_2_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_3_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_4_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_5_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_6_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_7_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_8_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_9_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_10_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_11_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_12_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_13_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_14_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_15_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_16_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_17_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_18_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] assign io_requestor_19_resp_bits_ae_final_0 = resp_ae_final; // @[PTW.scala:219:7, :261:26] reg resp_pf; // @[PTW.scala:262:20] assign io_requestor_0_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_1_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_2_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_3_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_4_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_5_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_6_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_7_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_8_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_9_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_10_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_11_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_12_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_13_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_14_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_15_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_16_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_17_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_18_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] assign io_requestor_19_resp_bits_pf_0 = resp_pf; // @[PTW.scala:219:7, :262:20] reg resp_gf; // @[PTW.scala:263:20] assign io_requestor_0_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_1_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_2_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_3_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_4_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_5_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_6_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_7_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_8_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_9_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_10_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_11_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_12_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_13_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_14_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_15_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_16_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_17_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_18_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] assign io_requestor_19_resp_bits_gf_0 = resp_gf; // @[PTW.scala:219:7, :263:20] reg resp_hr; // @[PTW.scala:264:20] assign io_requestor_0_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_1_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_2_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_3_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_4_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_5_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_6_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_7_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_8_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_9_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_10_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_11_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_12_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_13_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_14_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_15_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_16_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_17_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_18_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] assign io_requestor_19_resp_bits_hr_0 = resp_hr; // @[PTW.scala:219:7, :264:20] reg resp_hw; // @[PTW.scala:265:20] assign io_requestor_0_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_1_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_2_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_3_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_4_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_5_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_6_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_7_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_8_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_9_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_10_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_11_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_12_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_13_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_14_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_15_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_16_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_17_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_18_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] assign io_requestor_19_resp_bits_hw_0 = resp_hw; // @[PTW.scala:219:7, :265:20] reg resp_hx; // @[PTW.scala:266:20] assign io_requestor_0_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_1_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_2_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_3_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_4_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_5_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_6_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_7_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_8_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_9_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_10_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_11_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_12_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_13_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_14_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_15_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_16_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_17_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_18_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] assign io_requestor_19_resp_bits_hx_0 = resp_hx; // @[PTW.scala:219:7, :266:20] reg resp_fragmented_superpage; // @[PTW.scala:267:38] reg [26:0] r_req_addr; // @[PTW.scala:270:18] reg r_req_need_gpa; // @[PTW.scala:270:18] assign io_requestor_0_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_1_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_2_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_3_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_4_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_5_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_6_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_7_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_8_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_9_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_10_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_11_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_12_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_13_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_14_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_15_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_16_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_17_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_18_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] assign io_requestor_19_resp_bits_gpa_valid_0 = r_req_need_gpa; // @[PTW.scala:219:7, :270:18] reg r_req_vstage1; // @[PTW.scala:270:18] reg r_req_stage2; // @[PTW.scala:270:18] reg [4:0] r_req_dest; // @[PTW.scala:272:23] reg [9:0] r_pte_reserved_for_future; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_reserved_for_future_0 = r_pte_reserved_for_future; // @[PTW.scala:219:7, :275:18] wire [9:0] r_pte_pte_2_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_3_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] wire [9:0] r_pte_pte_4_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :780:26] wire [9:0] r_pte_pte_5_reserved_for_future = r_pte_reserved_for_future; // @[PTW.scala:275:18, :771:26] reg [43:0] r_pte_ppn; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_ppn_0 = r_pte_ppn; // @[PTW.scala:219:7, :275:18] reg [1:0] r_pte_reserved_for_software; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_reserved_for_software_0 = r_pte_reserved_for_software; // @[PTW.scala:219:7, :275:18] wire [1:0] r_pte_pte_2_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_3_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] wire [1:0] r_pte_pte_4_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :780:26] wire [1:0] r_pte_pte_5_reserved_for_software = r_pte_reserved_for_software; // @[PTW.scala:275:18, :771:26] reg r_pte_d; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_d_0 = r_pte_d; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_d = r_pte_d; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_d = r_pte_d; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_d = r_pte_d; // @[PTW.scala:275:18, :771:26] reg r_pte_a; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_a_0 = r_pte_a; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_a = r_pte_a; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_a = r_pte_a; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_a = r_pte_a; // @[PTW.scala:275:18, :771:26] reg r_pte_g; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_g_0 = r_pte_g; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_g = r_pte_g; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_g = r_pte_g; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_g = r_pte_g; // @[PTW.scala:275:18, :771:26] reg r_pte_u; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_u_0 = r_pte_u; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_u = r_pte_u; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_u = r_pte_u; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_u = r_pte_u; // @[PTW.scala:275:18, :771:26] reg r_pte_x; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_x_0 = r_pte_x; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_x = r_pte_x; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_x = r_pte_x; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_x = r_pte_x; // @[PTW.scala:275:18, :771:26] reg r_pte_w; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_w_0 = r_pte_w; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_w = r_pte_w; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_w = r_pte_w; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_w = r_pte_w; // @[PTW.scala:275:18, :771:26] reg r_pte_r; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_r_0 = r_pte_r; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_r = r_pte_r; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_r = r_pte_r; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_r = r_pte_r; // @[PTW.scala:275:18, :771:26] reg r_pte_v; // @[PTW.scala:275:18] assign io_requestor_0_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_1_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_2_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_3_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_4_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_5_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_6_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_7_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_8_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_9_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_10_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_11_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_12_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_13_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_14_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_15_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_16_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_17_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_18_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] assign io_requestor_19_resp_bits_pte_v_0 = r_pte_v; // @[PTW.scala:219:7, :275:18] wire r_pte_pte_2_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_3_v = r_pte_v; // @[PTW.scala:275:18, :771:26] wire r_pte_pte_4_v = r_pte_v; // @[PTW.scala:275:18, :780:26] wire r_pte_pte_5_v = r_pte_v; // @[PTW.scala:275:18, :771:26] reg [3:0] r_hgatp_mode; // @[PTW.scala:276:20] reg [15:0] r_hgatp_asid; // @[PTW.scala:276:20] reg [43:0] r_hgatp_ppn; // @[PTW.scala:276:20] reg [1:0] aux_count; // @[PTW.scala:278:22] wire [1:0] _io_requestor_0_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_1_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_2_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_3_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_4_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_5_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_6_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_7_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_8_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_9_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_10_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_11_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_12_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_13_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_14_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_15_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_16_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_17_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_18_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] wire [1:0] _io_requestor_19_resp_bits_gpa_bits_truncIdx_T = aux_count; // @[package.scala:38:21] reg [9:0] aux_pte_reserved_for_future; // @[PTW.scala:280:20] wire [9:0] merged_pte_reserved_for_future = aux_pte_reserved_for_future; // @[PTW.scala:280:20, :771:26] reg [43:0] aux_pte_ppn; // @[PTW.scala:280:20] reg [1:0] aux_pte_reserved_for_software; // @[PTW.scala:280:20] wire [1:0] merged_pte_reserved_for_software = aux_pte_reserved_for_software; // @[PTW.scala:280:20, :771:26] reg aux_pte_d; // @[PTW.scala:280:20] wire merged_pte_d = aux_pte_d; // @[PTW.scala:280:20, :771:26] reg aux_pte_a; // @[PTW.scala:280:20] wire merged_pte_a = aux_pte_a; // @[PTW.scala:280:20, :771:26] reg aux_pte_g; // @[PTW.scala:280:20] wire merged_pte_g = aux_pte_g; // @[PTW.scala:280:20, :771:26] reg aux_pte_u; // @[PTW.scala:280:20] wire merged_pte_u = aux_pte_u; // @[PTW.scala:280:20, :771:26] reg aux_pte_x; // @[PTW.scala:280:20] wire merged_pte_x = aux_pte_x; // @[PTW.scala:280:20, :771:26] reg aux_pte_w; // @[PTW.scala:280:20] wire merged_pte_w = aux_pte_w; // @[PTW.scala:280:20, :771:26] reg aux_pte_r; // @[PTW.scala:280:20] wire merged_pte_r = aux_pte_r; // @[PTW.scala:280:20, :771:26] reg aux_pte_v; // @[PTW.scala:280:20] wire merged_pte_v = aux_pte_v; // @[PTW.scala:280:20, :771:26] reg [11:0] gpa_pgoff; // @[PTW.scala:281:22] reg stage2; // @[PTW.scala:282:19] reg stage2_final; // @[PTW.scala:283:25] wire [43:0] r_pte_pte_5_ppn = satp_ppn; // @[PTW.scala:285:17, :771:26] wire do_both_stages = r_req_vstage1 & r_req_stage2; // @[PTW.scala:270:18, :288:38] wire _max_count_T = count < aux_count; // @[PTW.scala:259:18, :278:22, :289:25] assign max_count = _max_count_T ? aux_count : count; // @[PTW.scala:259:18, :278:22, :289:25] assign io_requestor_0_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_1_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_2_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_3_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_4_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_5_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_6_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_7_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_8_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_9_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_10_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_11_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_12_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_13_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_14_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_15_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_16_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_17_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_18_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] assign io_requestor_19_resp_bits_level_0 = max_count; // @[PTW.scala:219:7, :289:25] wire _vpn_T = r_req_vstage1 & stage2; // @[PTW.scala:270:18, :282:19, :290:31] wire [43:0] vpn = _vpn_T ? aux_pte_ppn : {17'h0, r_req_addr}; // @[PTW.scala:270:18, :280:20, :290:{16,31}] wire [43:0] _pte_addr_vpn_idxs_T_2 = vpn; // @[PTW.scala:290:16, :322:12] reg mem_resp_valid; // @[PTW.scala:292:31] reg [63:0] mem_resp_data; // @[PTW.scala:293:30] wire [63:0] _tmp_WIRE = mem_resp_data; // @[PTW.scala:293:30, :304:37] wire [9:0] _tmp_T_10; // @[PTW.scala:304:37] wire [43:0] _tmp_T_9; // @[PTW.scala:304:37] wire [9:0] pte_reserved_for_future = tmp_reserved_for_future; // @[PTW.scala:304:37, :305:26] wire [1:0] _tmp_T_8; // @[PTW.scala:304:37] wire _tmp_T_7; // @[PTW.scala:304:37] wire [1:0] pte_reserved_for_software = tmp_reserved_for_software; // @[PTW.scala:304:37, :305:26] wire _tmp_T_6; // @[PTW.scala:304:37] wire pte_d = tmp_d; // @[PTW.scala:304:37, :305:26] wire _tmp_T_5; // @[PTW.scala:304:37] wire pte_a = tmp_a; // @[PTW.scala:304:37, :305:26] wire _tmp_T_4; // @[PTW.scala:304:37] wire pte_g = tmp_g; // @[PTW.scala:304:37, :305:26] wire _tmp_T_3; // @[PTW.scala:304:37] wire pte_u = tmp_u; // @[PTW.scala:304:37, :305:26] wire _tmp_T_2; // @[PTW.scala:304:37] wire pte_x = tmp_x; // @[PTW.scala:304:37, :305:26] wire _tmp_T_1; // @[PTW.scala:304:37] wire pte_w = tmp_w; // @[PTW.scala:304:37, :305:26] wire _tmp_T; // @[PTW.scala:304:37] wire pte_r = tmp_r; // @[PTW.scala:304:37, :305:26] wire [43:0] tmp_ppn; // @[PTW.scala:304:37] wire tmp_v; // @[PTW.scala:304:37] assign _tmp_T = _tmp_WIRE[0]; // @[PTW.scala:304:37] assign tmp_v = _tmp_T; // @[PTW.scala:304:37] assign _tmp_T_1 = _tmp_WIRE[1]; // @[PTW.scala:304:37] assign tmp_r = _tmp_T_1; // @[PTW.scala:304:37] assign _tmp_T_2 = _tmp_WIRE[2]; // @[PTW.scala:304:37] assign tmp_w = _tmp_T_2; // @[PTW.scala:304:37] assign _tmp_T_3 = _tmp_WIRE[3]; // @[PTW.scala:304:37] assign tmp_x = _tmp_T_3; // @[PTW.scala:304:37] assign _tmp_T_4 = _tmp_WIRE[4]; // @[PTW.scala:304:37] assign tmp_u = _tmp_T_4; // @[PTW.scala:304:37] assign _tmp_T_5 = _tmp_WIRE[5]; // @[PTW.scala:304:37] assign tmp_g = _tmp_T_5; // @[PTW.scala:304:37] assign _tmp_T_6 = _tmp_WIRE[6]; // @[PTW.scala:304:37] assign tmp_a = _tmp_T_6; // @[PTW.scala:304:37] assign _tmp_T_7 = _tmp_WIRE[7]; // @[PTW.scala:304:37] assign tmp_d = _tmp_T_7; // @[PTW.scala:304:37] assign _tmp_T_8 = _tmp_WIRE[9:8]; // @[PTW.scala:304:37] assign tmp_reserved_for_software = _tmp_T_8; // @[PTW.scala:304:37] assign _tmp_T_9 = _tmp_WIRE[53:10]; // @[PTW.scala:304:37] assign tmp_ppn = _tmp_T_9; // @[PTW.scala:304:37] assign _tmp_T_10 = _tmp_WIRE[63:54]; // @[PTW.scala:304:37] assign tmp_reserved_for_future = _tmp_T_10; // @[PTW.scala:304:37] wire [9:0] aux_pte_pte_reserved_for_future = pte_reserved_for_future; // @[PTW.scala:305:26, :771:26] wire [1:0] aux_pte_pte_reserved_for_software = pte_reserved_for_software; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_d = pte_d; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_a = pte_a; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_g = pte_g; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_u = pte_u; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_x = pte_x; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_w = pte_w; // @[PTW.scala:305:26, :771:26] wire aux_pte_pte_r = pte_r; // @[PTW.scala:305:26, :771:26] wire [43:0] pte_ppn; // @[PTW.scala:305:26] wire pte_v; // @[PTW.scala:305:26] wire aux_pte_pte_v = pte_v; // @[PTW.scala:305:26, :771:26] wire _res_ppn_T = ~stage2; // @[PTW.scala:282:19, :306:38] wire _res_ppn_T_1 = do_both_stages & _res_ppn_T; // @[PTW.scala:288:38, :306:{35,38}] wire [26:0] _res_ppn_T_2 = tmp_ppn[26:0]; // @[PTW.scala:304:37, :306:54] wire [19:0] _res_ppn_T_3 = tmp_ppn[19:0]; // @[PTW.scala:304:37, :306:99] wire [26:0] _res_ppn_T_4 = _res_ppn_T_1 ? _res_ppn_T_2 : {7'h0, _res_ppn_T_3}; // @[PTW.scala:306:{19,35,54,99}] assign pte_ppn = {17'h0, _res_ppn_T_4}; // @[PTW.scala:305:26, :306:{13,19}] assign pte_v = ~((tmp_r | tmp_w | tmp_x) & (~(count[1]) & (|(tmp_ppn[8:0])) | count == 2'h0 & (|(tmp_ppn[17:9])))) & tmp_v; // @[PTW.scala:259:18, :304:37, :305:26, :307:{17,26,36}, :310:{21,28,38,97,106,114}] wire invalid_paddr = do_both_stages & ~stage2 ? (|(tmp_ppn[43:27])) : (|(tmp_ppn[43:20])); // @[PTW.scala:282:19, :288:38, :304:37, :306:38, :313:{9,25,46,58,76,88}] wire [14:0] idxs_0 = tmp_ppn[43:29]; // @[PTW.scala:304:37, :787:58] wire invalid_gpa = do_both_stages & ~stage2 & (|idxs_0); // @[PTW.scala:282:19, :288:38, :306:38, :314:{21,32}, :787:58, :788:25] wire _traverse_T = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _traverse_T_1 = pte_v & _traverse_T; // @[PTW.scala:139:{33,36}, :305:26] wire _traverse_T_2 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _traverse_T_3 = _traverse_T_1 & _traverse_T_2; // @[PTW.scala:139:{33,39,42}] wire _traverse_T_4 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _traverse_T_5 = _traverse_T_3 & _traverse_T_4; // @[PTW.scala:139:{39,45,48}] wire _traverse_T_6 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _traverse_T_7 = _traverse_T_5 & _traverse_T_6; // @[PTW.scala:139:{45,51,54}] wire _traverse_T_8 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _traverse_T_9 = _traverse_T_7 & _traverse_T_8; // @[PTW.scala:139:{51,57,60}] wire _traverse_T_10 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _traverse_T_11 = _traverse_T_9 & _traverse_T_10; // @[PTW.scala:139:{57,63,66}] wire _traverse_T_12 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _traverse_T_13 = _traverse_T_11 & _traverse_T_12; // @[PTW.scala:139:{63,69,92}] wire _traverse_T_14 = ~invalid_paddr; // @[PTW.scala:313:9, :317:33] wire _traverse_T_15 = _traverse_T_13 & _traverse_T_14; // @[PTW.scala:139:69, :317:{30,33}] wire _traverse_T_16 = ~invalid_gpa; // @[PTW.scala:314:32, :317:51] wire _traverse_T_17 = _traverse_T_15 & _traverse_T_16; // @[PTW.scala:317:{30,48,51}] wire _traverse_T_18 = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73] wire traverse = _traverse_T_17 & _traverse_T_18; // @[PTW.scala:317:{48,64,73}] wire [25:0] _pte_addr_vpn_idxs_T = vpn[43:18]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_0 = _pte_addr_vpn_idxs_T[8:0]; // @[PTW.scala:322:{12,48}] wire [34:0] _pte_addr_vpn_idxs_T_1 = vpn[43:9]; // @[PTW.scala:290:16, :322:12] wire [8:0] pte_addr_vpn_idxs_1 = _pte_addr_vpn_idxs_T_1[8:0]; // @[PTW.scala:322:{12,48}] wire [8:0] pte_addr_vpn_idxs_2 = _pte_addr_vpn_idxs_T_2[8:0]; // @[PTW.scala:322:{12,48}] wire _pte_addr_mask_T = ~(|count); // @[PTW.scala:259:18, :324:40] wire _pte_addr_mask_T_1 = stage2 & _pte_addr_mask_T; // @[PTW.scala:282:19, :324:{31,40}] wire _T_46 = count == 2'h1; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T = _T_46; // @[package.scala:39:86] wire _pmaHomogeneous_T; // @[package.scala:39:86] assign _pmaHomogeneous_T = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_3; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_3 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_23; // @[package.scala:39:86] assign _pmpHomogeneous_T_23 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_11; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_11 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_60; // @[package.scala:39:86] assign _pmpHomogeneous_T_60 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_5 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_19; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_19 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_97; // @[package.scala:39:86] assign _pmpHomogeneous_T_97 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_10; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_10 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_27 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_134; // @[package.scala:39:86] assign _pmpHomogeneous_T_134 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_15; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_15 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_35 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_171; // @[package.scala:39:86] assign _pmpHomogeneous_T_171 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_20; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_20 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_43; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_43 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_208; // @[package.scala:39:86] assign _pmpHomogeneous_T_208 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_25 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_51; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_51 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_245; // @[package.scala:39:86] assign _pmpHomogeneous_T_245 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_30; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_30 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_59; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_59 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_T_282; // @[package.scala:39:86] assign _pmpHomogeneous_T_282 = _T_46; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_35; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_35 = _T_46; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T = _T_46; // @[package.scala:39:86] wire _aux_pte_T; // @[package.scala:39:86] assign _aux_pte_T = _T_46; // @[package.scala:39:86] wire _leaf_T_5; // @[PTW.scala:751:53] assign _leaf_T_5 = _T_46; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_1 = _pte_addr_vpn_idx_T ? pte_addr_vpn_idxs_1 : pte_addr_vpn_idxs_0; // @[package.scala:39:{76,86}] wire _T_241 = count == 2'h2; // @[package.scala:39:86] wire _pte_addr_vpn_idx_T_2; // @[package.scala:39:86] assign _pte_addr_vpn_idx_T_2 = _T_241; // @[package.scala:39:86] wire _pmaHomogeneous_T_2; // @[package.scala:39:86] assign _pmaHomogeneous_T_2 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_5; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_5 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_25; // @[package.scala:39:86] assign _pmpHomogeneous_T_25 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_2; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_2 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_13; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_13 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_62; // @[package.scala:39:86] assign _pmpHomogeneous_T_62 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_7; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_7 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_21; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_21 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_99; // @[package.scala:39:86] assign _pmpHomogeneous_T_99 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_12; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_12 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_29; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_29 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_136; // @[package.scala:39:86] assign _pmpHomogeneous_T_136 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_17; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_17 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_37 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_173; // @[package.scala:39:86] assign _pmpHomogeneous_T_173 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_22; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_22 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_45; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_45 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_210; // @[package.scala:39:86] assign _pmpHomogeneous_T_210 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_27; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_27 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_53; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_53 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_247; // @[package.scala:39:86] assign _pmpHomogeneous_T_247 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_32; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_32 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_maskHomogeneous_T_61; // @[package.scala:39:86] assign _pmpHomogeneous_maskHomogeneous_T_61 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_T_284; // @[package.scala:39:86] assign _pmpHomogeneous_T_284 = _T_241; // @[package.scala:39:86] wire _pmpHomogeneous_pgMask_T_37; // @[package.scala:39:86] assign _pmpHomogeneous_pgMask_T_37 = _T_241; // @[package.scala:39:86] wire _merged_pte_stage1_ppn_T_2; // @[package.scala:39:86] assign _merged_pte_stage1_ppn_T_2 = _T_241; // @[package.scala:39:86] wire _l2_refill_T; // @[PTW.scala:713:39] assign _l2_refill_T = _T_241; // @[package.scala:39:86] wire _aux_pte_T_2; // @[package.scala:39:86] assign _aux_pte_T_2 = _T_241; // @[package.scala:39:86] wire _leaf_T_8; // @[PTW.scala:751:53] assign _leaf_T_8 = _T_241; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_3 = _pte_addr_vpn_idx_T_2 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_1; // @[package.scala:39:{76,86}] wire _pte_addr_vpn_idx_T_4 = &count; // @[package.scala:39:86] wire [8:0] _pte_addr_vpn_idx_T_5 = _pte_addr_vpn_idx_T_4 ? pte_addr_vpn_idxs_2 : _pte_addr_vpn_idx_T_3; // @[package.scala:39:{76,86}] wire [8:0] pte_addr_vpn_idx = _pte_addr_vpn_idx_T_5; // @[package.scala:39:76] wire [52:0] _pte_addr_raw_pte_addr_T = {r_pte_ppn, 9'h0}; // @[PTW.scala:275:18, :326:36] wire [52:0] _pte_addr_raw_pte_addr_T_1 = {_pte_addr_raw_pte_addr_T[52:9], _pte_addr_raw_pte_addr_T[8:0] | pte_addr_vpn_idx}; // @[PTW.scala:325:36, :326:{36,52}] wire [55:0] pte_addr_raw_pte_addr = {_pte_addr_raw_pte_addr_T_1, 3'h0}; // @[PTW.scala:326:{52,63}] wire [31:0] pte_addr = pte_addr_raw_pte_addr[31:0]; // @[PTW.scala:326:63, :330:23] reg [6:0] state_reg; // @[Replacement.scala:168:70] reg [7:0] valid; // @[PTW.scala:352:24] reg [31:0] tags_0; // @[PTW.scala:353:19] reg [31:0] tags_1; // @[PTW.scala:353:19] reg [31:0] tags_2; // @[PTW.scala:353:19] reg [31:0] tags_3; // @[PTW.scala:353:19] reg [31:0] tags_4; // @[PTW.scala:353:19] reg [31:0] tags_5; // @[PTW.scala:353:19] reg [31:0] tags_6; // @[PTW.scala:353:19] reg [31:0] tags_7; // @[PTW.scala:353:19] reg [19:0] data_0; // @[PTW.scala:355:19] reg [19:0] data_1; // @[PTW.scala:355:19] reg [19:0] data_2; // @[PTW.scala:355:19] reg [19:0] data_3; // @[PTW.scala:355:19] reg [19:0] data_4; // @[PTW.scala:355:19] reg [19:0] data_5; // @[PTW.scala:355:19] reg [19:0] data_6; // @[PTW.scala:355:19] reg [19:0] data_7; // @[PTW.scala:355:19] wire _can_hit_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :358:18] wire _can_hit_T_1 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65] wire _can_hit_T_2 = r_req_vstage1 ? stage2 : _can_hit_T_1; // @[PTW.scala:270:18, :282:19, :358:{41,65}] wire can_hit = _can_hit_T & _can_hit_T_2; // @[PTW.scala:358:{18,35,41}] wire [32:0] tag = {r_req_vstage1, pte_addr}; // @[PTW.scala:270:18, :330:23, :364:15] wire _hits_T = {1'h0, tags_0} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_1 = {1'h0, tags_1} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_2 = {1'h0, tags_2} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_3 = {1'h0, tags_3} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_4 = {1'h0, tags_4} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_5 = {1'h0, tags_5} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_6 = {1'h0, tags_6} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire _hits_T_7 = {1'h0, tags_7} == tag; // @[PTW.scala:353:19, :364:15, :366:27] wire [1:0] hits_lo_lo = {_hits_T_1, _hits_T}; // @[package.scala:45:27] wire [1:0] hits_lo_hi = {_hits_T_3, _hits_T_2}; // @[package.scala:45:27] wire [3:0] hits_lo = {hits_lo_hi, hits_lo_lo}; // @[package.scala:45:27] wire [1:0] hits_hi_lo = {_hits_T_5, _hits_T_4}; // @[package.scala:45:27] wire [1:0] hits_hi_hi = {_hits_T_7, _hits_T_6}; // @[package.scala:45:27] wire [3:0] hits_hi = {hits_hi_hi, hits_hi_lo}; // @[package.scala:45:27] wire [7:0] _hits_T_8 = {hits_hi, hits_lo}; // @[package.scala:45:27] wire [7:0] hits = _hits_T_8 & valid; // @[package.scala:45:27] wire _hit_T = |hits; // @[PTW.scala:366:43, :367:20] wire pte_cache_hit = _hit_T & can_hit; // @[PTW.scala:358:35, :367:{20,24}] wire _r_T = &valid; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older = state_reg[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_3 = state_reg[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_3 = state_reg[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_1 = r_left_subtree_state[2]; // @[package.scala:163:13] wire r_left_subtree_state_1 = r_left_subtree_state[1]; // @[package.scala:163:13] wire _r_T_1 = r_left_subtree_state_1; // @[package.scala:163:13] wire r_right_subtree_state_1 = r_left_subtree_state[0]; // @[package.scala:163:13] wire _r_T_2 = r_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12] wire _r_T_3 = r_left_subtree_older_1 ? _r_T_1 : _r_T_2; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_4 = {r_left_subtree_older_1, _r_T_3}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_2 = r_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_2 = r_right_subtree_state[1]; // @[package.scala:163:13] wire _r_T_5 = r_left_subtree_state_2; // @[package.scala:163:13] wire r_right_subtree_state_2 = r_right_subtree_state[0]; // @[Replacement.scala:245:38] wire _r_T_6 = r_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12] wire _r_T_7 = r_left_subtree_older_2 ? _r_T_5 : _r_T_6; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_8 = {r_left_subtree_older_2, _r_T_7}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_9 = r_left_subtree_older ? _r_T_4 : _r_T_8; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_10 = {r_left_subtree_older, _r_T_9}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_11 = ~valid; // @[PTW.scala:352:24, :370:57] wire _r_T_12 = _r_T_11[0]; // @[OneHot.scala:48:45] wire _r_T_13 = _r_T_11[1]; // @[OneHot.scala:48:45] wire _r_T_14 = _r_T_11[2]; // @[OneHot.scala:48:45] wire _r_T_15 = _r_T_11[3]; // @[OneHot.scala:48:45] wire _r_T_16 = _r_T_11[4]; // @[OneHot.scala:48:45] wire _r_T_17 = _r_T_11[5]; // @[OneHot.scala:48:45] wire _r_T_18 = _r_T_11[6]; // @[OneHot.scala:48:45] wire _r_T_19 = _r_T_11[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_20 = {2'h3, ~_r_T_18}; // @[OneHot.scala:48:45] wire [2:0] _r_T_21 = _r_T_17 ? 3'h5 : _r_T_20; // @[OneHot.scala:48:45] wire [2:0] _r_T_22 = _r_T_16 ? 3'h4 : _r_T_21; // @[OneHot.scala:48:45] wire [2:0] _r_T_23 = _r_T_15 ? 3'h3 : _r_T_22; // @[OneHot.scala:48:45] wire [2:0] _r_T_24 = _r_T_14 ? 3'h2 : _r_T_23; // @[OneHot.scala:48:45] wire [2:0] _r_T_25 = _r_T_13 ? 3'h1 : _r_T_24; // @[OneHot.scala:48:45] wire [2:0] _r_T_26 = _r_T_12 ? 3'h0 : _r_T_25; // @[OneHot.scala:48:45] wire [2:0] r = _r_T ? _r_T_10 : _r_T_26; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized = r; // @[package.scala:163:13] wire [7:0] _valid_T = 8'h1 << r; // @[OneHot.scala:58:35] wire [7:0] _valid_T_1 = valid | _valid_T; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T = state_reg_touch_way_sized[2]; // @[package.scala:163:13] wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_11 = state_reg_touch_way_sized[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_1 = _state_reg_T[1]; // @[package.scala:163:13] wire state_reg_set_left_older_1 = ~_state_reg_set_left_older_T_1; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_1 = state_reg_left_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_1 = state_reg_left_subtree_state[0]; // @[package.scala:163:13] wire _state_reg_T_1 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_5 = _state_reg_T[0]; // @[package.scala:163:13] wire _state_reg_T_2 = _state_reg_T_1; // @[package.scala:163:13] wire _state_reg_T_3 = ~_state_reg_T_2; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_4 = state_reg_set_left_older_1 ? state_reg_left_subtree_state_1 : _state_reg_T_3; // @[package.scala:163:13] wire _state_reg_T_6 = _state_reg_T_5; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_7 = ~_state_reg_T_6; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_8 = state_reg_set_left_older_1 ? _state_reg_T_7 : state_reg_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi = {state_reg_set_left_older_1, _state_reg_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_9 = {state_reg_hi, _state_reg_T_8}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_10 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_9; // @[package.scala:163:13] wire _state_reg_set_left_older_T_2 = _state_reg_T_11[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_2 = ~_state_reg_set_left_older_T_2; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_2 = state_reg_right_subtree_state[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_2 = state_reg_right_subtree_state[0]; // @[Replacement.scala:198:38] wire _state_reg_T_12 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_16 = _state_reg_T_11[0]; // @[package.scala:163:13] wire _state_reg_T_13 = _state_reg_T_12; // @[package.scala:163:13] wire _state_reg_T_14 = ~_state_reg_T_13; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_15 = state_reg_set_left_older_2 ? state_reg_left_subtree_state_2 : _state_reg_T_14; // @[package.scala:163:13] wire _state_reg_T_17 = _state_reg_T_16; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_18 = ~_state_reg_T_17; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_19 = state_reg_set_left_older_2 ? _state_reg_T_18 : state_reg_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_1 = {state_reg_set_left_older_2, _state_reg_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_20 = {state_reg_hi_1, _state_reg_T_19}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_21 = state_reg_set_left_older ? _state_reg_T_20 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_2 = {state_reg_set_left_older, _state_reg_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_22 = {state_reg_hi_2, _state_reg_T_21}; // @[Replacement.scala:202:12, :206:16] wire _T_152 = state == 3'h1; // @[PTW.scala:233:22, :377:24] wire _io_dpath_perf_pte_hit_T; // @[PTW.scala:394:46] assign _io_dpath_perf_pte_hit_T = _T_152; // @[PTW.scala:377:24, :394:46] wire _io_mem_req_valid_T; // @[PTW.scala:515:29] assign _io_mem_req_valid_T = _T_152; // @[PTW.scala:377:24, :515:29] wire _r_pte_T_4; // @[PTW.scala:672:15] assign _r_pte_T_4 = _T_152; // @[PTW.scala:377:24, :672:15] wire _r_pte_T_6; // @[PTW.scala:674:15] assign _r_pte_T_6 = _T_152; // @[PTW.scala:377:24, :674:15] wire [3:0] hi = hits[7:4]; // @[OneHot.scala:30:18] wire [3:0] lo = hits[3:0]; // @[OneHot.scala:31:18] wire [3:0] _T_30 = hi | lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] hi_1 = _T_30[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] lo_1 = _T_30[1:0]; // @[OneHot.scala:31:18, :32:28] wire [2:0] state_reg_touch_way_sized_1 = {|hi, |hi_1, hi_1[1] | lo_1[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire _state_reg_set_left_older_T_3 = state_reg_touch_way_sized_1[2]; // @[package.scala:163:13] wire state_reg_set_left_older_3 = ~_state_reg_set_left_older_T_3; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_23 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_34 = state_reg_touch_way_sized_1[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_4 = _state_reg_T_23[1]; // @[package.scala:163:13] wire state_reg_set_left_older_4 = ~_state_reg_set_left_older_T_4; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_4 = state_reg_left_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_4 = state_reg_left_subtree_state_3[0]; // @[package.scala:163:13] wire _state_reg_T_24 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_28 = _state_reg_T_23[0]; // @[package.scala:163:13] wire _state_reg_T_25 = _state_reg_T_24; // @[package.scala:163:13] wire _state_reg_T_26 = ~_state_reg_T_25; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_27 = state_reg_set_left_older_4 ? state_reg_left_subtree_state_4 : _state_reg_T_26; // @[package.scala:163:13] wire _state_reg_T_29 = _state_reg_T_28; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_30 = ~_state_reg_T_29; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_31 = state_reg_set_left_older_4 ? _state_reg_T_30 : state_reg_right_subtree_state_4; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_3 = {state_reg_set_left_older_4, _state_reg_T_27}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_32 = {state_reg_hi_3, _state_reg_T_31}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_33 = state_reg_set_left_older_3 ? state_reg_left_subtree_state_3 : _state_reg_T_32; // @[package.scala:163:13] wire _state_reg_set_left_older_T_5 = _state_reg_T_34[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_5 = ~_state_reg_set_left_older_T_5; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_5 = state_reg_right_subtree_state_3[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_5 = state_reg_right_subtree_state_3[0]; // @[Replacement.scala:198:38] wire _state_reg_T_35 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_39 = _state_reg_T_34[0]; // @[package.scala:163:13] wire _state_reg_T_36 = _state_reg_T_35; // @[package.scala:163:13] wire _state_reg_T_37 = ~_state_reg_T_36; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_38 = state_reg_set_left_older_5 ? state_reg_left_subtree_state_5 : _state_reg_T_37; // @[package.scala:163:13] wire _state_reg_T_40 = _state_reg_T_39; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_41 = ~_state_reg_T_40; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_42 = state_reg_set_left_older_5 ? _state_reg_T_41 : state_reg_right_subtree_state_5; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_4 = {state_reg_set_left_older_5, _state_reg_T_38}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_43 = {state_reg_hi_4, _state_reg_T_42}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_44 = state_reg_set_left_older_3 ? _state_reg_T_43 : state_reg_right_subtree_state_3; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_5 = {state_reg_set_left_older_3, _state_reg_T_33}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_45 = {state_reg_hi_5, _state_reg_T_44}; // @[Replacement.scala:202:12, :206:16] wire _leaf_T_2 = ~(|count); // @[PTW.scala:259:18, :324:40, :382:47, :751:53] wire [19:0] pte_cache_data = (hits[0] ? data_0 : 20'h0) | (hits[1] ? data_1 : 20'h0) | (hits[2] ? data_2 : 20'h0) | (hits[3] ? data_3 : 20'h0) | (hits[4] ? data_4 : 20'h0) | (hits[5] ? data_5 : 20'h0) | (hits[6] ? data_6 : 20'h0) | (hits[7] ? data_7 : 20'h0); // @[Mux.scala:30:73, :32:36] reg [6:0] state_reg_1; // @[Replacement.scala:168:70] reg [7:0] valid_1; // @[PTW.scala:352:24] reg [19:0] data_1_0; // @[PTW.scala:355:19] reg [19:0] data_1_1; // @[PTW.scala:355:19] reg [19:0] data_1_2; // @[PTW.scala:355:19] reg [19:0] data_1_3; // @[PTW.scala:355:19] reg [19:0] data_1_4; // @[PTW.scala:355:19] reg [19:0] data_1_5; // @[PTW.scala:355:19] reg [19:0] data_1_6; // @[PTW.scala:355:19] reg [19:0] data_1_7; // @[PTW.scala:355:19] wire _can_hit_T_3 = ~(|count); // @[PTW.scala:259:18, :324:40, :357:21] wire _can_hit_T_4 = ~(aux_count[1]); // @[PTW.scala:278:22, :357:60] wire _can_hit_T_5 = _can_hit_T_3 & _can_hit_T_4; // @[PTW.scala:357:{21,47,60}] wire _can_hit_T_6 = _can_hit_T_5 & r_req_vstage1; // @[PTW.scala:270:18, :357:{47,77}] wire _can_hit_T_7 = _can_hit_T_6 & stage2; // @[PTW.scala:282:19, :357:{77,94}] wire _can_hit_T_8 = ~stage2_final; // @[PTW.scala:283:25, :357:107] wire can_hit_1 = _can_hit_T_7 & _can_hit_T_8; // @[PTW.scala:357:{94,104,107}] wire _can_refill_T = ~stage2; // @[PTW.scala:282:19, :306:38, :360:33] wire _can_refill_T_1 = do_both_stages & _can_refill_T; // @[PTW.scala:288:38, :360:{30,33}] wire _can_refill_T_2 = ~stage2_final; // @[PTW.scala:283:25, :357:107, :360:44] wire can_refill = _can_refill_T_1 & _can_refill_T_2; // @[PTW.scala:360:{30,41,44}] wire _r_T_27 = &valid_1; // @[PTW.scala:352:24, :370:25] wire r_left_subtree_older_3 = state_reg_1[6]; // @[Replacement.scala:168:70, :243:38] wire [2:0] r_left_subtree_state_3 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_6 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] state_reg_left_subtree_state_9 = state_reg_1[5:3]; // @[package.scala:163:13] wire [2:0] r_right_subtree_state_3 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :245:38] wire [2:0] state_reg_right_subtree_state_6 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire [2:0] state_reg_right_subtree_state_9 = state_reg_1[2:0]; // @[Replacement.scala:168:70, :198:38, :245:38] wire r_left_subtree_older_4 = r_left_subtree_state_3[2]; // @[package.scala:163:13] wire r_left_subtree_state_4 = r_left_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_28 = r_left_subtree_state_4; // @[package.scala:163:13] wire r_right_subtree_state_4 = r_left_subtree_state_3[0]; // @[package.scala:163:13] wire _r_T_29 = r_right_subtree_state_4; // @[Replacement.scala:245:38, :262:12] wire _r_T_30 = r_left_subtree_older_4 ? _r_T_28 : _r_T_29; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_31 = {r_left_subtree_older_4, _r_T_30}; // @[Replacement.scala:243:38, :249:12, :250:16] wire r_left_subtree_older_5 = r_right_subtree_state_3[2]; // @[Replacement.scala:243:38, :245:38] wire r_left_subtree_state_5 = r_right_subtree_state_3[1]; // @[package.scala:163:13] wire _r_T_32 = r_left_subtree_state_5; // @[package.scala:163:13] wire r_right_subtree_state_5 = r_right_subtree_state_3[0]; // @[Replacement.scala:245:38] wire _r_T_33 = r_right_subtree_state_5; // @[Replacement.scala:245:38, :262:12] wire _r_T_34 = r_left_subtree_older_5 ? _r_T_32 : _r_T_33; // @[Replacement.scala:243:38, :250:16, :262:12] wire [1:0] _r_T_35 = {r_left_subtree_older_5, _r_T_34}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [1:0] _r_T_36 = r_left_subtree_older_3 ? _r_T_31 : _r_T_35; // @[Replacement.scala:243:38, :249:12, :250:16] wire [2:0] _r_T_37 = {r_left_subtree_older_3, _r_T_36}; // @[Replacement.scala:243:38, :249:12, :250:16] wire [7:0] _r_T_38 = ~valid_1; // @[PTW.scala:352:24, :370:57] wire _r_T_39 = _r_T_38[0]; // @[OneHot.scala:48:45] wire _r_T_40 = _r_T_38[1]; // @[OneHot.scala:48:45] wire _r_T_41 = _r_T_38[2]; // @[OneHot.scala:48:45] wire _r_T_42 = _r_T_38[3]; // @[OneHot.scala:48:45] wire _r_T_43 = _r_T_38[4]; // @[OneHot.scala:48:45] wire _r_T_44 = _r_T_38[5]; // @[OneHot.scala:48:45] wire _r_T_45 = _r_T_38[6]; // @[OneHot.scala:48:45] wire _r_T_46 = _r_T_38[7]; // @[OneHot.scala:48:45] wire [2:0] _r_T_47 = {2'h3, ~_r_T_45}; // @[OneHot.scala:48:45] wire [2:0] _r_T_48 = _r_T_44 ? 3'h5 : _r_T_47; // @[OneHot.scala:48:45] wire [2:0] _r_T_49 = _r_T_43 ? 3'h4 : _r_T_48; // @[OneHot.scala:48:45] wire [2:0] _r_T_50 = _r_T_42 ? 3'h3 : _r_T_49; // @[OneHot.scala:48:45] wire [2:0] _r_T_51 = _r_T_41 ? 3'h2 : _r_T_50; // @[OneHot.scala:48:45] wire [2:0] _r_T_52 = _r_T_40 ? 3'h1 : _r_T_51; // @[OneHot.scala:48:45] wire [2:0] _r_T_53 = _r_T_39 ? 3'h0 : _r_T_52; // @[OneHot.scala:48:45] wire [2:0] r_1 = _r_T_27 ? _r_T_37 : _r_T_53; // @[Mux.scala:50:70] wire [2:0] state_reg_touch_way_sized_2 = r_1; // @[package.scala:163:13] wire [7:0] _valid_T_2 = 8'h1 << r_1; // @[OneHot.scala:58:35] wire [7:0] _valid_T_3 = valid_1 | _valid_T_2; // @[OneHot.scala:58:35] wire _state_reg_set_left_older_T_6 = state_reg_touch_way_sized_2[2]; // @[package.scala:163:13] wire state_reg_set_left_older_6 = ~_state_reg_set_left_older_T_6; // @[Replacement.scala:196:{33,43}] wire [1:0] _state_reg_T_46 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire [1:0] _state_reg_T_57 = state_reg_touch_way_sized_2[1:0]; // @[package.scala:163:13] wire _state_reg_set_left_older_T_7 = _state_reg_T_46[1]; // @[package.scala:163:13] wire state_reg_set_left_older_7 = ~_state_reg_set_left_older_T_7; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_7 = state_reg_left_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_7 = state_reg_left_subtree_state_6[0]; // @[package.scala:163:13] wire _state_reg_T_47 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_51 = _state_reg_T_46[0]; // @[package.scala:163:13] wire _state_reg_T_48 = _state_reg_T_47; // @[package.scala:163:13] wire _state_reg_T_49 = ~_state_reg_T_48; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_50 = state_reg_set_left_older_7 ? state_reg_left_subtree_state_7 : _state_reg_T_49; // @[package.scala:163:13] wire _state_reg_T_52 = _state_reg_T_51; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_53 = ~_state_reg_T_52; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_54 = state_reg_set_left_older_7 ? _state_reg_T_53 : state_reg_right_subtree_state_7; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_6 = {state_reg_set_left_older_7, _state_reg_T_50}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_55 = {state_reg_hi_6, _state_reg_T_54}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_56 = state_reg_set_left_older_6 ? state_reg_left_subtree_state_6 : _state_reg_T_55; // @[package.scala:163:13] wire _state_reg_set_left_older_T_8 = _state_reg_T_57[1]; // @[Replacement.scala:196:43, :207:62] wire state_reg_set_left_older_8 = ~_state_reg_set_left_older_T_8; // @[Replacement.scala:196:{33,43}] wire state_reg_left_subtree_state_8 = state_reg_right_subtree_state_6[1]; // @[package.scala:163:13] wire state_reg_right_subtree_state_8 = state_reg_right_subtree_state_6[0]; // @[Replacement.scala:198:38] wire _state_reg_T_58 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_62 = _state_reg_T_57[0]; // @[package.scala:163:13] wire _state_reg_T_59 = _state_reg_T_58; // @[package.scala:163:13] wire _state_reg_T_60 = ~_state_reg_T_59; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_61 = state_reg_set_left_older_8 ? state_reg_left_subtree_state_8 : _state_reg_T_60; // @[package.scala:163:13] wire _state_reg_T_63 = _state_reg_T_62; // @[Replacement.scala:207:62, :218:17] wire _state_reg_T_64 = ~_state_reg_T_63; // @[Replacement.scala:218:{7,17}] wire _state_reg_T_65 = state_reg_set_left_older_8 ? _state_reg_T_64 : state_reg_right_subtree_state_8; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7] wire [1:0] state_reg_hi_7 = {state_reg_set_left_older_8, _state_reg_T_61}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [2:0] _state_reg_T_66 = {state_reg_hi_7, _state_reg_T_65}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_67 = state_reg_set_left_older_6 ? _state_reg_T_66 : state_reg_right_subtree_state_6; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16] wire [3:0] state_reg_hi_8 = {state_reg_set_left_older_6, _state_reg_T_56}; // @[Replacement.scala:196:33, :202:12, :203:16] wire [6:0] _state_reg_T_68 = {state_reg_hi_8, _state_reg_T_67}; // @[Replacement.scala:202:12, :206:16] wire [2:0] _state_reg_T_79 = state_reg_left_subtree_state_9; // @[package.scala:163:13] wire state_reg_left_subtree_state_10 = state_reg_left_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_73 = state_reg_left_subtree_state_10; // @[package.scala:163:13] wire state_reg_right_subtree_state_10 = state_reg_left_subtree_state_9[0]; // @[package.scala:163:13] wire [1:0] state_reg_hi_9 = {1'h1, _state_reg_T_73}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_78 = {state_reg_hi_9, 1'h1}; // @[Replacement.scala:202:12] wire state_reg_left_subtree_state_11 = state_reg_right_subtree_state_9[1]; // @[package.scala:163:13] wire _state_reg_T_84 = state_reg_left_subtree_state_11; // @[package.scala:163:13] wire state_reg_right_subtree_state_11 = state_reg_right_subtree_state_9[0]; // @[Replacement.scala:198:38] wire [1:0] state_reg_hi_10 = {1'h1, _state_reg_T_84}; // @[Replacement.scala:202:12, :203:16] wire [2:0] _state_reg_T_89 = {state_reg_hi_10, 1'h1}; // @[Replacement.scala:202:12] wire [2:0] _state_reg_T_90 = _state_reg_T_89; // @[Replacement.scala:202:12, :206:16] wire [3:0] state_reg_hi_11 = {1'h1, _state_reg_T_79}; // @[Replacement.scala:202:12, :203:16] wire [6:0] _state_reg_T_91 = {state_reg_hi_11, _state_reg_T_90}; // @[Replacement.scala:202:12, :206:16] reg pte_hit; // @[PTW.scala:392:24] wire _io_dpath_perf_pte_hit_T_1 = pte_hit & _io_dpath_perf_pte_hit_T; // @[PTW.scala:392:24, :394:{36,46}] assign _io_dpath_perf_pte_hit_T_3 = _io_dpath_perf_pte_hit_T_1; // @[PTW.scala:394:{36,57}] assign io_dpath_perf_pte_hit_0 = _io_dpath_perf_pte_hit_T_3; // @[PTW.scala:219:7, :394:57] reg l2_refill; // @[PTW.scala:398:26] assign l2_refill_wire = l2_refill; // @[PTW.scala:234:28, :398:26] wire _invalidated_T = |state; // @[PTW.scala:233:22, :240:30, :511:65] wire _invalidated_T_1 = invalidated & _invalidated_T; // @[PTW.scala:251:24, :511:{56,65}] wire _invalidated_T_2 = io_dpath_sfence_valid_0 | _invalidated_T_1; // @[PTW.scala:219:7, :511:{40,56}] wire _io_mem_req_valid_T_1 = state == 3'h3; // @[PTW.scala:233:22, :515:48] assign _io_mem_req_valid_T_2 = _io_mem_req_valid_T | _io_mem_req_valid_T_1; // @[PTW.scala:515:{29,39,48}] assign io_mem_req_valid_0 = _io_mem_req_valid_T_2; // @[PTW.scala:219:7, :515:39] assign io_mem_req_bits_addr_0 = {8'h0, pte_addr}; // @[PTW.scala:219:7, :330:23, :520:24] wire _io_mem_req_bits_dv_T = ~stage2; // @[PTW.scala:282:19, :306:38, :523:43] assign _io_mem_req_bits_dv_T_1 = do_both_stages & _io_mem_req_bits_dv_T; // @[PTW.scala:288:38, :523:{40,43}] assign io_mem_req_bits_dv_0 = _io_mem_req_bits_dv_T_1; // @[PTW.scala:219:7, :523:40] wire _io_mem_s1_kill_T = state != 3'h2; // @[PTW.scala:233:22, :531:38] wire _io_mem_s1_kill_T_1 = _io_mem_s1_kill_T; // @[PTW.scala:531:{28,38}] assign _io_mem_s1_kill_T_2 = _io_mem_s1_kill_T_1 | resp_gf; // @[PTW.scala:263:20, :531:{28,51}] assign io_mem_s1_kill_0 = _io_mem_s1_kill_T_2; // @[PTW.scala:219:7, :531:51] wire [55:0] _GEN = {r_pte_ppn, 12'h0}; // @[PTW.scala:275:18, :544:96] wire [55:0] _pmaPgLevelHomogeneous_T; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T = _GEN; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_7 = _GEN; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] assign _pmaPgLevelHomogeneous_T_37 = _GEN; // @[PTW.scala:544:96] wire [55:0] _pmpHomogeneous_T; // @[PTW.scala:548:80] assign _pmpHomogeneous_T = _GEN; // @[PTW.scala:544:96, :548:80] wire [55:0] _pmaPgLevelHomogeneous_T_21 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_28 = _pmaPgLevelHomogeneous_T_7; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_8 = {_pmaPgLevelHomogeneous_T_7[55:28], _pmaPgLevelHomogeneous_T_7[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_9 = {1'h0, _pmaPgLevelHomogeneous_T_8}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_10 = _pmaPgLevelHomogeneous_T_9 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_11 = _pmaPgLevelHomogeneous_T_10; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_12 = _pmaPgLevelHomogeneous_T_11 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_18 = _pmaPgLevelHomogeneous_T_12; // @[TLBPermissions.scala:101:65] wire [55:0] _pmaPgLevelHomogeneous_T_13 = {_pmaPgLevelHomogeneous_T_7[55:32], _pmaPgLevelHomogeneous_T_7[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_14 = {1'h0, _pmaPgLevelHomogeneous_T_13}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_15 = _pmaPgLevelHomogeneous_T_14 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_16 = _pmaPgLevelHomogeneous_T_15; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_17 = _pmaPgLevelHomogeneous_T_16 == 57'h0; // @[Parameters.scala:137:{46,59}] wire pmaPgLevelHomogeneous_1 = _pmaPgLevelHomogeneous_T_18 | _pmaPgLevelHomogeneous_T_17; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_22 = {1'h0, _pmaPgLevelHomogeneous_T_21}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_23 = _pmaPgLevelHomogeneous_T_22 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_24 = _pmaPgLevelHomogeneous_T_23; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_25 = _pmaPgLevelHomogeneous_T_24 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_26 = _pmaPgLevelHomogeneous_T_25; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_27 = ~_pmaPgLevelHomogeneous_T_26; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_29 = {1'h0, _pmaPgLevelHomogeneous_T_28}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_30 = _pmaPgLevelHomogeneous_T_29 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_31 = _pmaPgLevelHomogeneous_T_30; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_32 = _pmaPgLevelHomogeneous_T_31 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_33 = _pmaPgLevelHomogeneous_T_32; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_34 = ~_pmaPgLevelHomogeneous_T_33; // @[TLBPermissions.scala:87:{22,66}] wire [55:0] _pmaPgLevelHomogeneous_T_38 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_105 = _pmaPgLevelHomogeneous_T_37; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_39 = {1'h0, _pmaPgLevelHomogeneous_T_38}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_40 = _pmaPgLevelHomogeneous_T_39 & 57'h1FFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_41 = _pmaPgLevelHomogeneous_T_40; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_42 = _pmaPgLevelHomogeneous_T_41 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_88 = _pmaPgLevelHomogeneous_T_42; // @[TLBPermissions.scala:101:65] wire [55:0] _GEN_0 = {_pmaPgLevelHomogeneous_T_37[55:14], _pmaPgLevelHomogeneous_T_37[13:0] ^ 14'h3000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_43; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_43 = _GEN_0; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_110; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_110 = _GEN_0; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_44 = {1'h0, _pmaPgLevelHomogeneous_T_43}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_45 = _pmaPgLevelHomogeneous_T_44 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_46 = _pmaPgLevelHomogeneous_T_45; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_47 = _pmaPgLevelHomogeneous_T_46 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_1 = {_pmaPgLevelHomogeneous_T_37[55:17], _pmaPgLevelHomogeneous_T_37[16:0] ^ 17'h10000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_48; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_48 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_98; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_98 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_115; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_115 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_147; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_147 = _GEN_1; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_154; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_154 = _GEN_1; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_49 = {1'h0, _pmaPgLevelHomogeneous_T_48}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_50 = _pmaPgLevelHomogeneous_T_49 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_51 = _pmaPgLevelHomogeneous_T_50; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_52 = _pmaPgLevelHomogeneous_T_51 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_53 = {_pmaPgLevelHomogeneous_T_37[55:21], _pmaPgLevelHomogeneous_T_37[20:0] ^ 21'h100000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_54 = {1'h0, _pmaPgLevelHomogeneous_T_53}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_55 = _pmaPgLevelHomogeneous_T_54 & 57'h1FFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_56 = _pmaPgLevelHomogeneous_T_55; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_57 = _pmaPgLevelHomogeneous_T_56 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_58 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_59 = {1'h0, _pmaPgLevelHomogeneous_T_58}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_60 = _pmaPgLevelHomogeneous_T_59 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_61 = _pmaPgLevelHomogeneous_T_60; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_62 = _pmaPgLevelHomogeneous_T_61 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_63 = {_pmaPgLevelHomogeneous_T_37[55:26], _pmaPgLevelHomogeneous_T_37[25:0] ^ 26'h2010000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_64 = {1'h0, _pmaPgLevelHomogeneous_T_63}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_65 = _pmaPgLevelHomogeneous_T_64 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_66 = _pmaPgLevelHomogeneous_T_65; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_67 = _pmaPgLevelHomogeneous_T_66 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_2 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'h8000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_68; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_68 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_120; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_120 = _GEN_2; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_135; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_135 = _GEN_2; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_69 = {1'h0, _pmaPgLevelHomogeneous_T_68}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_70 = _pmaPgLevelHomogeneous_T_69 & 57'h1FFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_71 = _pmaPgLevelHomogeneous_T_70; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_72 = _pmaPgLevelHomogeneous_T_71 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_73 = {_pmaPgLevelHomogeneous_T_37[55:28], _pmaPgLevelHomogeneous_T_37[27:0] ^ 28'hC000000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_74 = {1'h0, _pmaPgLevelHomogeneous_T_73}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_75 = _pmaPgLevelHomogeneous_T_74 & 57'h1FFFFFFFC000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_76 = _pmaPgLevelHomogeneous_T_75; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_77 = _pmaPgLevelHomogeneous_T_76 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _pmaPgLevelHomogeneous_T_78 = {_pmaPgLevelHomogeneous_T_37[55:29], _pmaPgLevelHomogeneous_T_37[28:0] ^ 29'h10020000}; // @[PTW.scala:544:96] wire [56:0] _pmaPgLevelHomogeneous_T_79 = {1'h0, _pmaPgLevelHomogeneous_T_78}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_80 = _pmaPgLevelHomogeneous_T_79 & 57'h1FFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_81 = _pmaPgLevelHomogeneous_T_80; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_82 = _pmaPgLevelHomogeneous_T_81 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [55:0] _GEN_3 = {_pmaPgLevelHomogeneous_T_37[55:32], _pmaPgLevelHomogeneous_T_37[31:0] ^ 32'h80000000}; // @[PTW.scala:544:96] wire [55:0] _pmaPgLevelHomogeneous_T_83; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_83 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_125; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_125 = _GEN_3; // @[Parameters.scala:137:31] wire [55:0] _pmaPgLevelHomogeneous_T_140; // @[Parameters.scala:137:31] assign _pmaPgLevelHomogeneous_T_140 = _GEN_3; // @[Parameters.scala:137:31] wire [56:0] _pmaPgLevelHomogeneous_T_84 = {1'h0, _pmaPgLevelHomogeneous_T_83}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_85 = _pmaPgLevelHomogeneous_T_84 & 57'h1FFFFFFF0000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_86 = _pmaPgLevelHomogeneous_T_85; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_87 = _pmaPgLevelHomogeneous_T_86 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_89 = _pmaPgLevelHomogeneous_T_88 | _pmaPgLevelHomogeneous_T_47; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_90 = _pmaPgLevelHomogeneous_T_89 | _pmaPgLevelHomogeneous_T_52; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_91 = _pmaPgLevelHomogeneous_T_90 | _pmaPgLevelHomogeneous_T_57; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_92 = _pmaPgLevelHomogeneous_T_91 | _pmaPgLevelHomogeneous_T_62; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_93 = _pmaPgLevelHomogeneous_T_92 | _pmaPgLevelHomogeneous_T_67; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_94 = _pmaPgLevelHomogeneous_T_93 | _pmaPgLevelHomogeneous_T_72; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_95 = _pmaPgLevelHomogeneous_T_94 | _pmaPgLevelHomogeneous_T_77; // @[TLBPermissions.scala:101:65] wire _pmaPgLevelHomogeneous_T_96 = _pmaPgLevelHomogeneous_T_95 | _pmaPgLevelHomogeneous_T_82; // @[TLBPermissions.scala:101:65] wire pmaPgLevelHomogeneous_2 = _pmaPgLevelHomogeneous_T_96 | _pmaPgLevelHomogeneous_T_87; // @[TLBPermissions.scala:101:65] wire [56:0] _pmaPgLevelHomogeneous_T_99 = {1'h0, _pmaPgLevelHomogeneous_T_98}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_100 = _pmaPgLevelHomogeneous_T_99 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_101 = _pmaPgLevelHomogeneous_T_100; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_102 = _pmaPgLevelHomogeneous_T_101 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_103 = _pmaPgLevelHomogeneous_T_102; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_104 = ~_pmaPgLevelHomogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_106 = {1'h0, _pmaPgLevelHomogeneous_T_105}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_107 = _pmaPgLevelHomogeneous_T_106 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_108 = _pmaPgLevelHomogeneous_T_107; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_109 = _pmaPgLevelHomogeneous_T_108 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_130 = _pmaPgLevelHomogeneous_T_109; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_111 = {1'h0, _pmaPgLevelHomogeneous_T_110}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_112 = _pmaPgLevelHomogeneous_T_111 & 57'h9E113000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_113 = _pmaPgLevelHomogeneous_T_112; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_114 = _pmaPgLevelHomogeneous_T_113 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_116 = {1'h0, _pmaPgLevelHomogeneous_T_115}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_117 = _pmaPgLevelHomogeneous_T_116 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_118 = _pmaPgLevelHomogeneous_T_117; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_119 = _pmaPgLevelHomogeneous_T_118 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_121 = {1'h0, _pmaPgLevelHomogeneous_T_120}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_122 = _pmaPgLevelHomogeneous_T_121 & 57'h9E110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_123 = _pmaPgLevelHomogeneous_T_122; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_124 = _pmaPgLevelHomogeneous_T_123 == 57'h0; // @[Parameters.scala:137:{46,59}] wire [56:0] _pmaPgLevelHomogeneous_T_126 = {1'h0, _pmaPgLevelHomogeneous_T_125}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_127 = _pmaPgLevelHomogeneous_T_126 & 57'h90000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_128 = _pmaPgLevelHomogeneous_T_127; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_129 = _pmaPgLevelHomogeneous_T_128 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_131 = _pmaPgLevelHomogeneous_T_130 | _pmaPgLevelHomogeneous_T_114; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_132 = _pmaPgLevelHomogeneous_T_131 | _pmaPgLevelHomogeneous_T_119; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_133 = _pmaPgLevelHomogeneous_T_132 | _pmaPgLevelHomogeneous_T_124; // @[TLBPermissions.scala:85:66] wire _pmaPgLevelHomogeneous_T_134 = _pmaPgLevelHomogeneous_T_133 | _pmaPgLevelHomogeneous_T_129; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_136 = {1'h0, _pmaPgLevelHomogeneous_T_135}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_137 = _pmaPgLevelHomogeneous_T_136 & 57'h8E000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_138 = _pmaPgLevelHomogeneous_T_137; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_139 = _pmaPgLevelHomogeneous_T_138 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_145 = _pmaPgLevelHomogeneous_T_139; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_141 = {1'h0, _pmaPgLevelHomogeneous_T_140}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_142 = _pmaPgLevelHomogeneous_T_141 & 57'h80000000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_143 = _pmaPgLevelHomogeneous_T_142; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_144 = _pmaPgLevelHomogeneous_T_143 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_146 = _pmaPgLevelHomogeneous_T_145 | _pmaPgLevelHomogeneous_T_144; // @[TLBPermissions.scala:85:66] wire [56:0] _pmaPgLevelHomogeneous_T_148 = {1'h0, _pmaPgLevelHomogeneous_T_147}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_149 = _pmaPgLevelHomogeneous_T_148 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_150 = _pmaPgLevelHomogeneous_T_149; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_151 = _pmaPgLevelHomogeneous_T_150 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_152 = _pmaPgLevelHomogeneous_T_151; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_153 = ~_pmaPgLevelHomogeneous_T_152; // @[TLBPermissions.scala:87:{22,66}] wire [56:0] _pmaPgLevelHomogeneous_T_155 = {1'h0, _pmaPgLevelHomogeneous_T_154}; // @[Parameters.scala:137:{31,41}] wire [56:0] _pmaPgLevelHomogeneous_T_156 = _pmaPgLevelHomogeneous_T_155 & 57'h8A110000; // @[Parameters.scala:137:{41,46}] wire [56:0] _pmaPgLevelHomogeneous_T_157 = _pmaPgLevelHomogeneous_T_156; // @[Parameters.scala:137:46] wire _pmaPgLevelHomogeneous_T_158 = _pmaPgLevelHomogeneous_T_157 == 57'h0; // @[Parameters.scala:137:{46,59}] wire _pmaPgLevelHomogeneous_T_159 = _pmaPgLevelHomogeneous_T_158; // @[TLBPermissions.scala:87:66] wire _pmaPgLevelHomogeneous_T_160 = ~_pmaPgLevelHomogeneous_T_159; // @[TLBPermissions.scala:87:{22,66}] wire _pmaHomogeneous_T_1 = _pmaHomogeneous_T & pmaPgLevelHomogeneous_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_3 = _pmaHomogeneous_T_2 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_1; // @[package.scala:39:{76,86}] wire _pmaHomogeneous_T_4 = &count; // @[package.scala:39:86] wire pmaHomogeneous = _pmaHomogeneous_T_4 ? pmaPgLevelHomogeneous_2 : _pmaHomogeneous_T_3; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_1 = io_dpath_pmp_0_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T = io_dpath_pmp_0_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_1 = io_dpath_pmp_0_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_2 = io_dpath_pmp_0_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_4 = _pmpHomogeneous_maskHomogeneous_T_3 ? _pmpHomogeneous_maskHomogeneous_T_1 : _pmpHomogeneous_maskHomogeneous_T; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_6 = _pmpHomogeneous_maskHomogeneous_T_5 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_4; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_7 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous = _pmpHomogeneous_maskHomogeneous_T_7 ? _pmpHomogeneous_maskHomogeneous_T_2 : _pmpHomogeneous_maskHomogeneous_T_6; // @[package.scala:39:{76,86}] wire [31:0] _GEN_4 = {io_dpath_pmp_0_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_2; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_2 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_9; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_9 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_16; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_16 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_1 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_5 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_7 = _GEN_4; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_3 = ~_pmpHomogeneous_T_2; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_4 = {_pmpHomogeneous_T_3[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_5 = ~_pmpHomogeneous_T_4; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_6 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_5}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_7 = _pmpHomogeneous_T_6[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_8 = |_pmpHomogeneous_T_7; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_10 = ~_pmpHomogeneous_T_9; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_11 = {_pmpHomogeneous_T_10[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_12 = ~_pmpHomogeneous_T_11; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_13 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_12}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_14 = _pmpHomogeneous_T_13[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_15 = |_pmpHomogeneous_T_14; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_17 = ~_pmpHomogeneous_T_16; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_18 = {_pmpHomogeneous_T_17[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_19 = ~_pmpHomogeneous_T_18; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_20 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_19}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_21 = _pmpHomogeneous_T_20[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_22 = |_pmpHomogeneous_T_21; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_24 = _pmpHomogeneous_T_23 ? _pmpHomogeneous_T_15 : _pmpHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_26 = _pmpHomogeneous_T_25 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_27 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_28 = _pmpHomogeneous_T_27 ? _pmpHomogeneous_T_22 : _pmpHomogeneous_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_29 = pmpHomogeneous_maskHomogeneous | _pmpHomogeneous_T_28; // @[package.scala:39:76] wire _pmpHomogeneous_T_30 = io_dpath_pmp_0_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_31 = ~_pmpHomogeneous_T_30; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_1 = ~_pmpHomogeneous_beginsAfterUpper_T; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_2 = {_pmpHomogeneous_beginsAfterUpper_T_1[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_3 = ~_pmpHomogeneous_beginsAfterUpper_T_2; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_4 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_3}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper = ~_pmpHomogeneous_beginsAfterUpper_T_4; // @[PMP.scala:107:{28,32}] wire _pmpHomogeneous_T_32 = pmpHomogeneous_beginsAfterUpper; // @[PMP.scala:107:28, :113:21] wire [31:0] _pmpHomogeneous_pgMask_T_1 = _pmpHomogeneous_pgMask_T ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_3 = _pmpHomogeneous_pgMask_T_2 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_1; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_4 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask = _pmpHomogeneous_pgMask_T_4 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_3; // @[package.scala:39:{76,86}] wire [55:0] _GEN_5 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T = _GEN_5; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T = _GEN_5; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_2 = ~_pmpHomogeneous_endsBeforeUpper_T_1; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_3 = {_pmpHomogeneous_endsBeforeUpper_T_2[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_4 = ~_pmpHomogeneous_endsBeforeUpper_T_3; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_5 = _pmpHomogeneous_endsBeforeUpper_T_4 & pmpHomogeneous_pgMask; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper = _pmpHomogeneous_endsBeforeUpper_T < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_5}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_33 = pmpHomogeneous_endsBeforeUpper; // @[PMP.scala:111:40, :113:62] wire _pmpHomogeneous_T_34 = _pmpHomogeneous_T_32 | _pmpHomogeneous_T_33; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_35 = _pmpHomogeneous_T_31 | _pmpHomogeneous_T_34; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_36 = _pmpHomogeneous_T_1 ? _pmpHomogeneous_T_29 : _pmpHomogeneous_T_35; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_37 = _pmpHomogeneous_T_36; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_38 = io_dpath_pmp_1_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_8 = io_dpath_pmp_1_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_9 = io_dpath_pmp_1_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_10 = io_dpath_pmp_1_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_12 = _pmpHomogeneous_maskHomogeneous_T_11 ? _pmpHomogeneous_maskHomogeneous_T_9 : _pmpHomogeneous_maskHomogeneous_T_8; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_14 = _pmpHomogeneous_maskHomogeneous_T_13 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_12; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_15 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_1 = _pmpHomogeneous_maskHomogeneous_T_15 ? _pmpHomogeneous_maskHomogeneous_T_10 : _pmpHomogeneous_maskHomogeneous_T_14; // @[package.scala:39:{76,86}] wire [31:0] _GEN_6 = {io_dpath_pmp_1_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_39; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_39 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_46; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_46 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_53; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_53 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_5 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_7 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_10 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_13 = _GEN_6; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_40 = ~_pmpHomogeneous_T_39; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_41 = {_pmpHomogeneous_T_40[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_42 = ~_pmpHomogeneous_T_41; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_43 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_42}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_44 = _pmpHomogeneous_T_43[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_45 = |_pmpHomogeneous_T_44; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_47 = ~_pmpHomogeneous_T_46; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_48 = {_pmpHomogeneous_T_47[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_49 = ~_pmpHomogeneous_T_48; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_50 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_49}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_51 = _pmpHomogeneous_T_50[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_52 = |_pmpHomogeneous_T_51; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_54 = ~_pmpHomogeneous_T_53; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_55 = {_pmpHomogeneous_T_54[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_56 = ~_pmpHomogeneous_T_55; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_57 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_56}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_58 = _pmpHomogeneous_T_57[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_59 = |_pmpHomogeneous_T_58; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_61 = _pmpHomogeneous_T_60 ? _pmpHomogeneous_T_52 : _pmpHomogeneous_T_45; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_63 = _pmpHomogeneous_T_62 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_61; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_64 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_65 = _pmpHomogeneous_T_64 ? _pmpHomogeneous_T_59 : _pmpHomogeneous_T_63; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_66 = pmpHomogeneous_maskHomogeneous_1 | _pmpHomogeneous_T_65; // @[package.scala:39:76] wire _pmpHomogeneous_T_67 = io_dpath_pmp_1_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_68 = ~_pmpHomogeneous_T_67; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_6 = ~_pmpHomogeneous_beginsAfterLower_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_7 = {_pmpHomogeneous_beginsAfterLower_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_8 = ~_pmpHomogeneous_beginsAfterLower_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_1 = ~_pmpHomogeneous_beginsAfterLower_T_9; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_6 = ~_pmpHomogeneous_beginsAfterUpper_T_5; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_7 = {_pmpHomogeneous_beginsAfterUpper_T_6[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_8 = ~_pmpHomogeneous_beginsAfterUpper_T_7; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_9 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_8}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_1 = ~_pmpHomogeneous_beginsAfterUpper_T_9; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_6 = _pmpHomogeneous_pgMask_T_5 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_8 = _pmpHomogeneous_pgMask_T_7 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_6; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_9 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_1 = _pmpHomogeneous_pgMask_T_9 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_8; // @[package.scala:39:{76,86}] wire [55:0] _GEN_7 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_1}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_6; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_6 = _GEN_7; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_6; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_6 = _GEN_7; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_8 = ~_pmpHomogeneous_endsBeforeLower_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_9 = {_pmpHomogeneous_endsBeforeLower_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_10 = ~_pmpHomogeneous_endsBeforeLower_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_11 = _pmpHomogeneous_endsBeforeLower_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_1 = _pmpHomogeneous_endsBeforeLower_T_6 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_11}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_8 = ~_pmpHomogeneous_endsBeforeUpper_T_7; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_9 = {_pmpHomogeneous_endsBeforeUpper_T_8[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_10 = ~_pmpHomogeneous_endsBeforeUpper_T_9; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_11 = _pmpHomogeneous_endsBeforeUpper_T_10 & pmpHomogeneous_pgMask_1; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_1 = _pmpHomogeneous_endsBeforeUpper_T_6 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_11}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_69 = pmpHomogeneous_endsBeforeLower_1 | pmpHomogeneous_beginsAfterUpper_1; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_70 = pmpHomogeneous_beginsAfterLower_1 & pmpHomogeneous_endsBeforeUpper_1; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_71 = _pmpHomogeneous_T_69 | _pmpHomogeneous_T_70; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_72 = _pmpHomogeneous_T_68 | _pmpHomogeneous_T_71; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_73 = _pmpHomogeneous_T_38 ? _pmpHomogeneous_T_66 : _pmpHomogeneous_T_72; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_74 = _pmpHomogeneous_T_37 & _pmpHomogeneous_T_73; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_75 = io_dpath_pmp_2_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_16 = io_dpath_pmp_2_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_17 = io_dpath_pmp_2_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_18 = io_dpath_pmp_2_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_20 = _pmpHomogeneous_maskHomogeneous_T_19 ? _pmpHomogeneous_maskHomogeneous_T_17 : _pmpHomogeneous_maskHomogeneous_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_22 = _pmpHomogeneous_maskHomogeneous_T_21 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_20; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_23 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_2 = _pmpHomogeneous_maskHomogeneous_T_23 ? _pmpHomogeneous_maskHomogeneous_T_18 : _pmpHomogeneous_maskHomogeneous_T_22; // @[package.scala:39:{76,86}] wire [31:0] _GEN_8 = {io_dpath_pmp_2_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_76; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_76 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_83; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_83 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_90; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_90 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_10 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_13 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_15 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_19 = _GEN_8; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_77 = ~_pmpHomogeneous_T_76; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_78 = {_pmpHomogeneous_T_77[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_79 = ~_pmpHomogeneous_T_78; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_80 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_79}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_81 = _pmpHomogeneous_T_80[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_82 = |_pmpHomogeneous_T_81; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_84 = ~_pmpHomogeneous_T_83; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_85 = {_pmpHomogeneous_T_84[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_86 = ~_pmpHomogeneous_T_85; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_87 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_86}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_88 = _pmpHomogeneous_T_87[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_89 = |_pmpHomogeneous_T_88; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_91 = ~_pmpHomogeneous_T_90; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_92 = {_pmpHomogeneous_T_91[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_93 = ~_pmpHomogeneous_T_92; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_94 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_93}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_95 = _pmpHomogeneous_T_94[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_96 = |_pmpHomogeneous_T_95; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_98 = _pmpHomogeneous_T_97 ? _pmpHomogeneous_T_89 : _pmpHomogeneous_T_82; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_100 = _pmpHomogeneous_T_99 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_98; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_101 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_102 = _pmpHomogeneous_T_101 ? _pmpHomogeneous_T_96 : _pmpHomogeneous_T_100; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_103 = pmpHomogeneous_maskHomogeneous_2 | _pmpHomogeneous_T_102; // @[package.scala:39:76] wire _pmpHomogeneous_T_104 = io_dpath_pmp_2_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_105 = ~_pmpHomogeneous_T_104; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_11 = ~_pmpHomogeneous_beginsAfterLower_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_12 = {_pmpHomogeneous_beginsAfterLower_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_13 = ~_pmpHomogeneous_beginsAfterLower_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_2 = ~_pmpHomogeneous_beginsAfterLower_T_14; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_11 = ~_pmpHomogeneous_beginsAfterUpper_T_10; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_12 = {_pmpHomogeneous_beginsAfterUpper_T_11[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_13 = ~_pmpHomogeneous_beginsAfterUpper_T_12; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_14 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_13}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_2 = ~_pmpHomogeneous_beginsAfterUpper_T_14; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_11 = _pmpHomogeneous_pgMask_T_10 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_13 = _pmpHomogeneous_pgMask_T_12 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_11; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_14 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_2 = _pmpHomogeneous_pgMask_T_14 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_13; // @[package.scala:39:{76,86}] wire [55:0] _GEN_9 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_2}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_12; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_12 = _GEN_9; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_12; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_12 = _GEN_9; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_14 = ~_pmpHomogeneous_endsBeforeLower_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_15 = {_pmpHomogeneous_endsBeforeLower_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_16 = ~_pmpHomogeneous_endsBeforeLower_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_17 = _pmpHomogeneous_endsBeforeLower_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_2 = _pmpHomogeneous_endsBeforeLower_T_12 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_17}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_14 = ~_pmpHomogeneous_endsBeforeUpper_T_13; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_15 = {_pmpHomogeneous_endsBeforeUpper_T_14[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_16 = ~_pmpHomogeneous_endsBeforeUpper_T_15; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_17 = _pmpHomogeneous_endsBeforeUpper_T_16 & pmpHomogeneous_pgMask_2; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_2 = _pmpHomogeneous_endsBeforeUpper_T_12 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_17}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_106 = pmpHomogeneous_endsBeforeLower_2 | pmpHomogeneous_beginsAfterUpper_2; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_107 = pmpHomogeneous_beginsAfterLower_2 & pmpHomogeneous_endsBeforeUpper_2; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_108 = _pmpHomogeneous_T_106 | _pmpHomogeneous_T_107; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_109 = _pmpHomogeneous_T_105 | _pmpHomogeneous_T_108; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_110 = _pmpHomogeneous_T_75 ? _pmpHomogeneous_T_103 : _pmpHomogeneous_T_109; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_111 = _pmpHomogeneous_T_74 & _pmpHomogeneous_T_110; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_112 = io_dpath_pmp_3_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_24 = io_dpath_pmp_3_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_25 = io_dpath_pmp_3_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_26 = io_dpath_pmp_3_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_28 = _pmpHomogeneous_maskHomogeneous_T_27 ? _pmpHomogeneous_maskHomogeneous_T_25 : _pmpHomogeneous_maskHomogeneous_T_24; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_30 = _pmpHomogeneous_maskHomogeneous_T_29 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_28; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_31 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_3 = _pmpHomogeneous_maskHomogeneous_T_31 ? _pmpHomogeneous_maskHomogeneous_T_26 : _pmpHomogeneous_maskHomogeneous_T_30; // @[package.scala:39:{76,86}] wire [31:0] _GEN_10 = {io_dpath_pmp_3_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_113; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_113 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_120; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_120 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_127; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_127 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_15 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_19 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_20 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_25 = _GEN_10; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_114 = ~_pmpHomogeneous_T_113; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_115 = {_pmpHomogeneous_T_114[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_116 = ~_pmpHomogeneous_T_115; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_117 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_116}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_118 = _pmpHomogeneous_T_117[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_119 = |_pmpHomogeneous_T_118; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_121 = ~_pmpHomogeneous_T_120; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_122 = {_pmpHomogeneous_T_121[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_123 = ~_pmpHomogeneous_T_122; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_124 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_123}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_125 = _pmpHomogeneous_T_124[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_126 = |_pmpHomogeneous_T_125; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_128 = ~_pmpHomogeneous_T_127; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_129 = {_pmpHomogeneous_T_128[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_130 = ~_pmpHomogeneous_T_129; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_131 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_130}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_132 = _pmpHomogeneous_T_131[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_133 = |_pmpHomogeneous_T_132; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_135 = _pmpHomogeneous_T_134 ? _pmpHomogeneous_T_126 : _pmpHomogeneous_T_119; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_137 = _pmpHomogeneous_T_136 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_135; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_138 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_139 = _pmpHomogeneous_T_138 ? _pmpHomogeneous_T_133 : _pmpHomogeneous_T_137; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_140 = pmpHomogeneous_maskHomogeneous_3 | _pmpHomogeneous_T_139; // @[package.scala:39:76] wire _pmpHomogeneous_T_141 = io_dpath_pmp_3_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_142 = ~_pmpHomogeneous_T_141; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_16 = ~_pmpHomogeneous_beginsAfterLower_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_17 = {_pmpHomogeneous_beginsAfterLower_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_18 = ~_pmpHomogeneous_beginsAfterLower_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_3 = ~_pmpHomogeneous_beginsAfterLower_T_19; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_16 = ~_pmpHomogeneous_beginsAfterUpper_T_15; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_17 = {_pmpHomogeneous_beginsAfterUpper_T_16[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_18 = ~_pmpHomogeneous_beginsAfterUpper_T_17; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_19 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_18}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_3 = ~_pmpHomogeneous_beginsAfterUpper_T_19; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_16 = _pmpHomogeneous_pgMask_T_15 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_18 = _pmpHomogeneous_pgMask_T_17 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_16; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_19 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_3 = _pmpHomogeneous_pgMask_T_19 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_18; // @[package.scala:39:{76,86}] wire [55:0] _GEN_11 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_3}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_18; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_18 = _GEN_11; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_18; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_18 = _GEN_11; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_20 = ~_pmpHomogeneous_endsBeforeLower_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_21 = {_pmpHomogeneous_endsBeforeLower_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_22 = ~_pmpHomogeneous_endsBeforeLower_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_23 = _pmpHomogeneous_endsBeforeLower_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_3 = _pmpHomogeneous_endsBeforeLower_T_18 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_23}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_20 = ~_pmpHomogeneous_endsBeforeUpper_T_19; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_21 = {_pmpHomogeneous_endsBeforeUpper_T_20[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_22 = ~_pmpHomogeneous_endsBeforeUpper_T_21; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_23 = _pmpHomogeneous_endsBeforeUpper_T_22 & pmpHomogeneous_pgMask_3; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_3 = _pmpHomogeneous_endsBeforeUpper_T_18 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_23}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_143 = pmpHomogeneous_endsBeforeLower_3 | pmpHomogeneous_beginsAfterUpper_3; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_144 = pmpHomogeneous_beginsAfterLower_3 & pmpHomogeneous_endsBeforeUpper_3; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_145 = _pmpHomogeneous_T_143 | _pmpHomogeneous_T_144; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_146 = _pmpHomogeneous_T_142 | _pmpHomogeneous_T_145; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_147 = _pmpHomogeneous_T_112 ? _pmpHomogeneous_T_140 : _pmpHomogeneous_T_146; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_148 = _pmpHomogeneous_T_111 & _pmpHomogeneous_T_147; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_149 = io_dpath_pmp_4_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_32 = io_dpath_pmp_4_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_33 = io_dpath_pmp_4_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_34 = io_dpath_pmp_4_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_36 = _pmpHomogeneous_maskHomogeneous_T_35 ? _pmpHomogeneous_maskHomogeneous_T_33 : _pmpHomogeneous_maskHomogeneous_T_32; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_38 = _pmpHomogeneous_maskHomogeneous_T_37 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_39 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_4 = _pmpHomogeneous_maskHomogeneous_T_39 ? _pmpHomogeneous_maskHomogeneous_T_34 : _pmpHomogeneous_maskHomogeneous_T_38; // @[package.scala:39:{76,86}] wire [31:0] _GEN_12 = {io_dpath_pmp_4_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_150; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_150 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_157; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_157 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_164; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_164 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_20 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_25 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_31 = _GEN_12; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_151 = ~_pmpHomogeneous_T_150; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_152 = {_pmpHomogeneous_T_151[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_153 = ~_pmpHomogeneous_T_152; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_154 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_153}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_155 = _pmpHomogeneous_T_154[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_156 = |_pmpHomogeneous_T_155; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_158 = ~_pmpHomogeneous_T_157; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_159 = {_pmpHomogeneous_T_158[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_160 = ~_pmpHomogeneous_T_159; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_161 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_160}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_162 = _pmpHomogeneous_T_161[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_163 = |_pmpHomogeneous_T_162; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_165 = ~_pmpHomogeneous_T_164; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_166 = {_pmpHomogeneous_T_165[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_167 = ~_pmpHomogeneous_T_166; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_168 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_167}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_169 = _pmpHomogeneous_T_168[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_170 = |_pmpHomogeneous_T_169; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_172 = _pmpHomogeneous_T_171 ? _pmpHomogeneous_T_163 : _pmpHomogeneous_T_156; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_174 = _pmpHomogeneous_T_173 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_172; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_175 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_176 = _pmpHomogeneous_T_175 ? _pmpHomogeneous_T_170 : _pmpHomogeneous_T_174; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_177 = pmpHomogeneous_maskHomogeneous_4 | _pmpHomogeneous_T_176; // @[package.scala:39:76] wire _pmpHomogeneous_T_178 = io_dpath_pmp_4_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_179 = ~_pmpHomogeneous_T_178; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_21 = ~_pmpHomogeneous_beginsAfterLower_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_22 = {_pmpHomogeneous_beginsAfterLower_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_23 = ~_pmpHomogeneous_beginsAfterLower_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_4 = ~_pmpHomogeneous_beginsAfterLower_T_24; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_21 = ~_pmpHomogeneous_beginsAfterUpper_T_20; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_22 = {_pmpHomogeneous_beginsAfterUpper_T_21[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_23 = ~_pmpHomogeneous_beginsAfterUpper_T_22; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_24 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_23}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_4 = ~_pmpHomogeneous_beginsAfterUpper_T_24; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_21 = _pmpHomogeneous_pgMask_T_20 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_23 = _pmpHomogeneous_pgMask_T_22 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_21; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_24 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_4 = _pmpHomogeneous_pgMask_T_24 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_23; // @[package.scala:39:{76,86}] wire [55:0] _GEN_13 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_4}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_24; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_24 = _GEN_13; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_24; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_24 = _GEN_13; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_26 = ~_pmpHomogeneous_endsBeforeLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_27 = {_pmpHomogeneous_endsBeforeLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_28 = ~_pmpHomogeneous_endsBeforeLower_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_29 = _pmpHomogeneous_endsBeforeLower_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_4 = _pmpHomogeneous_endsBeforeLower_T_24 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_29}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_26 = ~_pmpHomogeneous_endsBeforeUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_27 = {_pmpHomogeneous_endsBeforeUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_28 = ~_pmpHomogeneous_endsBeforeUpper_T_27; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_29 = _pmpHomogeneous_endsBeforeUpper_T_28 & pmpHomogeneous_pgMask_4; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_4 = _pmpHomogeneous_endsBeforeUpper_T_24 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_29}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_180 = pmpHomogeneous_endsBeforeLower_4 | pmpHomogeneous_beginsAfterUpper_4; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_181 = pmpHomogeneous_beginsAfterLower_4 & pmpHomogeneous_endsBeforeUpper_4; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_182 = _pmpHomogeneous_T_180 | _pmpHomogeneous_T_181; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_183 = _pmpHomogeneous_T_179 | _pmpHomogeneous_T_182; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_184 = _pmpHomogeneous_T_149 ? _pmpHomogeneous_T_177 : _pmpHomogeneous_T_183; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_185 = _pmpHomogeneous_T_148 & _pmpHomogeneous_T_184; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_186 = io_dpath_pmp_5_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_40 = io_dpath_pmp_5_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_41 = io_dpath_pmp_5_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_42 = io_dpath_pmp_5_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_44 = _pmpHomogeneous_maskHomogeneous_T_43 ? _pmpHomogeneous_maskHomogeneous_T_41 : _pmpHomogeneous_maskHomogeneous_T_40; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_46 = _pmpHomogeneous_maskHomogeneous_T_45 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_44; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_47 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_5 = _pmpHomogeneous_maskHomogeneous_T_47 ? _pmpHomogeneous_maskHomogeneous_T_42 : _pmpHomogeneous_maskHomogeneous_T_46; // @[package.scala:39:{76,86}] wire [31:0] _GEN_14 = {io_dpath_pmp_5_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_187; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_187 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_194; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_194 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_201; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_201 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_25 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_31 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_30 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_37 = _GEN_14; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_188 = ~_pmpHomogeneous_T_187; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_189 = {_pmpHomogeneous_T_188[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_190 = ~_pmpHomogeneous_T_189; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_191 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_190}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_192 = _pmpHomogeneous_T_191[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_193 = |_pmpHomogeneous_T_192; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_195 = ~_pmpHomogeneous_T_194; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_196 = {_pmpHomogeneous_T_195[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_197 = ~_pmpHomogeneous_T_196; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_198 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_197}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_199 = _pmpHomogeneous_T_198[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_200 = |_pmpHomogeneous_T_199; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_202 = ~_pmpHomogeneous_T_201; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_203 = {_pmpHomogeneous_T_202[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_204 = ~_pmpHomogeneous_T_203; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_205 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_204}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_206 = _pmpHomogeneous_T_205[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_207 = |_pmpHomogeneous_T_206; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_209 = _pmpHomogeneous_T_208 ? _pmpHomogeneous_T_200 : _pmpHomogeneous_T_193; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_211 = _pmpHomogeneous_T_210 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_209; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_212 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_213 = _pmpHomogeneous_T_212 ? _pmpHomogeneous_T_207 : _pmpHomogeneous_T_211; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_214 = pmpHomogeneous_maskHomogeneous_5 | _pmpHomogeneous_T_213; // @[package.scala:39:76] wire _pmpHomogeneous_T_215 = io_dpath_pmp_5_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_216 = ~_pmpHomogeneous_T_215; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_26 = ~_pmpHomogeneous_beginsAfterLower_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_27 = {_pmpHomogeneous_beginsAfterLower_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_28 = ~_pmpHomogeneous_beginsAfterLower_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_5 = ~_pmpHomogeneous_beginsAfterLower_T_29; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_26 = ~_pmpHomogeneous_beginsAfterUpper_T_25; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_27 = {_pmpHomogeneous_beginsAfterUpper_T_26[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_28 = ~_pmpHomogeneous_beginsAfterUpper_T_27; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_29 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_28}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_5 = ~_pmpHomogeneous_beginsAfterUpper_T_29; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_26 = _pmpHomogeneous_pgMask_T_25 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_28 = _pmpHomogeneous_pgMask_T_27 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_26; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_29 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_5 = _pmpHomogeneous_pgMask_T_29 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_28; // @[package.scala:39:{76,86}] wire [55:0] _GEN_15 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_5}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_30; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_30 = _GEN_15; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_30; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_30 = _GEN_15; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_32 = ~_pmpHomogeneous_endsBeforeLower_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_33 = {_pmpHomogeneous_endsBeforeLower_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_34 = ~_pmpHomogeneous_endsBeforeLower_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_35 = _pmpHomogeneous_endsBeforeLower_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_5 = _pmpHomogeneous_endsBeforeLower_T_30 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_35}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_32 = ~_pmpHomogeneous_endsBeforeUpper_T_31; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_33 = {_pmpHomogeneous_endsBeforeUpper_T_32[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_34 = ~_pmpHomogeneous_endsBeforeUpper_T_33; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_35 = _pmpHomogeneous_endsBeforeUpper_T_34 & pmpHomogeneous_pgMask_5; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_5 = _pmpHomogeneous_endsBeforeUpper_T_30 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_35}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_217 = pmpHomogeneous_endsBeforeLower_5 | pmpHomogeneous_beginsAfterUpper_5; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_218 = pmpHomogeneous_beginsAfterLower_5 & pmpHomogeneous_endsBeforeUpper_5; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_219 = _pmpHomogeneous_T_217 | _pmpHomogeneous_T_218; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_220 = _pmpHomogeneous_T_216 | _pmpHomogeneous_T_219; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_221 = _pmpHomogeneous_T_186 ? _pmpHomogeneous_T_214 : _pmpHomogeneous_T_220; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_222 = _pmpHomogeneous_T_185 & _pmpHomogeneous_T_221; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_223 = io_dpath_pmp_6_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_48 = io_dpath_pmp_6_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_49 = io_dpath_pmp_6_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_50 = io_dpath_pmp_6_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_52 = _pmpHomogeneous_maskHomogeneous_T_51 ? _pmpHomogeneous_maskHomogeneous_T_49 : _pmpHomogeneous_maskHomogeneous_T_48; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_54 = _pmpHomogeneous_maskHomogeneous_T_53 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_52; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_55 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_6 = _pmpHomogeneous_maskHomogeneous_T_55 ? _pmpHomogeneous_maskHomogeneous_T_50 : _pmpHomogeneous_maskHomogeneous_T_54; // @[package.scala:39:{76,86}] wire [31:0] _GEN_16 = {io_dpath_pmp_6_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_224; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_224 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_231; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_231 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_238; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_238 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_30 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_37 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterLower_T_35 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeLower_T_43 = _GEN_16; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_225 = ~_pmpHomogeneous_T_224; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_226 = {_pmpHomogeneous_T_225[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_227 = ~_pmpHomogeneous_T_226; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_228 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_227}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_229 = _pmpHomogeneous_T_228[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_230 = |_pmpHomogeneous_T_229; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_232 = ~_pmpHomogeneous_T_231; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_233 = {_pmpHomogeneous_T_232[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_234 = ~_pmpHomogeneous_T_233; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_235 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_234}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_236 = _pmpHomogeneous_T_235[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_237 = |_pmpHomogeneous_T_236; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_239 = ~_pmpHomogeneous_T_238; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_240 = {_pmpHomogeneous_T_239[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_241 = ~_pmpHomogeneous_T_240; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_242 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_241}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_243 = _pmpHomogeneous_T_242[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_244 = |_pmpHomogeneous_T_243; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_246 = _pmpHomogeneous_T_245 ? _pmpHomogeneous_T_237 : _pmpHomogeneous_T_230; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_248 = _pmpHomogeneous_T_247 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_246; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_249 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_250 = _pmpHomogeneous_T_249 ? _pmpHomogeneous_T_244 : _pmpHomogeneous_T_248; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_251 = pmpHomogeneous_maskHomogeneous_6 | _pmpHomogeneous_T_250; // @[package.scala:39:76] wire _pmpHomogeneous_T_252 = io_dpath_pmp_6_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_253 = ~_pmpHomogeneous_T_252; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_31 = ~_pmpHomogeneous_beginsAfterLower_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_32 = {_pmpHomogeneous_beginsAfterLower_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_33 = ~_pmpHomogeneous_beginsAfterLower_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_6 = ~_pmpHomogeneous_beginsAfterLower_T_34; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_31 = ~_pmpHomogeneous_beginsAfterUpper_T_30; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_32 = {_pmpHomogeneous_beginsAfterUpper_T_31[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_33 = ~_pmpHomogeneous_beginsAfterUpper_T_32; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_34 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_33}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_6 = ~_pmpHomogeneous_beginsAfterUpper_T_34; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_31 = _pmpHomogeneous_pgMask_T_30 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_33 = _pmpHomogeneous_pgMask_T_32 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_31; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_34 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_6 = _pmpHomogeneous_pgMask_T_34 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_33; // @[package.scala:39:{76,86}] wire [55:0] _GEN_17 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_6}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_36; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_36 = _GEN_17; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_36; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_36 = _GEN_17; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_38 = ~_pmpHomogeneous_endsBeforeLower_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_39 = {_pmpHomogeneous_endsBeforeLower_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_40 = ~_pmpHomogeneous_endsBeforeLower_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_41 = _pmpHomogeneous_endsBeforeLower_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_6 = _pmpHomogeneous_endsBeforeLower_T_36 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_41}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_38 = ~_pmpHomogeneous_endsBeforeUpper_T_37; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_39 = {_pmpHomogeneous_endsBeforeUpper_T_38[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_40 = ~_pmpHomogeneous_endsBeforeUpper_T_39; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_41 = _pmpHomogeneous_endsBeforeUpper_T_40 & pmpHomogeneous_pgMask_6; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_6 = _pmpHomogeneous_endsBeforeUpper_T_36 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_41}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_254 = pmpHomogeneous_endsBeforeLower_6 | pmpHomogeneous_beginsAfterUpper_6; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_255 = pmpHomogeneous_beginsAfterLower_6 & pmpHomogeneous_endsBeforeUpper_6; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_256 = _pmpHomogeneous_T_254 | _pmpHomogeneous_T_255; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_257 = _pmpHomogeneous_T_253 | _pmpHomogeneous_T_256; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_258 = _pmpHomogeneous_T_223 ? _pmpHomogeneous_T_251 : _pmpHomogeneous_T_257; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire _pmpHomogeneous_T_259 = _pmpHomogeneous_T_222 & _pmpHomogeneous_T_258; // @[PMP.scala:118:8, :138:10] wire _pmpHomogeneous_T_260 = io_dpath_pmp_7_cfg_a_0[1]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_56 = io_dpath_pmp_7_mask_0[29]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_57 = io_dpath_pmp_7_mask_0[20]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_58 = io_dpath_pmp_7_mask_0[11]; // @[PTW.scala:219:7] wire _pmpHomogeneous_maskHomogeneous_T_60 = _pmpHomogeneous_maskHomogeneous_T_59 ? _pmpHomogeneous_maskHomogeneous_T_57 : _pmpHomogeneous_maskHomogeneous_T_56; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_62 = _pmpHomogeneous_maskHomogeneous_T_61 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_60; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_maskHomogeneous_T_63 = &count; // @[package.scala:39:86] wire pmpHomogeneous_maskHomogeneous_7 = _pmpHomogeneous_maskHomogeneous_T_63 ? _pmpHomogeneous_maskHomogeneous_T_58 : _pmpHomogeneous_maskHomogeneous_T_62; // @[package.scala:39:{76,86}] wire [31:0] _GEN_18 = {io_dpath_pmp_7_addr_0, 2'h0}; // @[PTW.scala:219:7] wire [31:0] _pmpHomogeneous_T_261; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_261 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_268; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_268 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_275; // @[PMP.scala:60:36] assign _pmpHomogeneous_T_275 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:36] assign _pmpHomogeneous_beginsAfterUpper_T_35 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:36] assign _pmpHomogeneous_endsBeforeUpper_T_43 = _GEN_18; // @[PMP.scala:60:36] wire [31:0] _pmpHomogeneous_T_262 = ~_pmpHomogeneous_T_261; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_263 = {_pmpHomogeneous_T_262[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_264 = ~_pmpHomogeneous_T_263; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_265 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_264}; // @[PTW.scala:548:80] wire [25:0] _pmpHomogeneous_T_266 = _pmpHomogeneous_T_265[55:30]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_267 = |_pmpHomogeneous_T_266; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_269 = ~_pmpHomogeneous_T_268; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_270 = {_pmpHomogeneous_T_269[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_271 = ~_pmpHomogeneous_T_270; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_272 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_271}; // @[PTW.scala:548:80] wire [34:0] _pmpHomogeneous_T_273 = _pmpHomogeneous_T_272[55:21]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_274 = |_pmpHomogeneous_T_273; // @[PMP.scala:98:{66,78}] wire [31:0] _pmpHomogeneous_T_276 = ~_pmpHomogeneous_T_275; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_T_277 = {_pmpHomogeneous_T_276[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_T_278 = ~_pmpHomogeneous_T_277; // @[PMP.scala:60:{27,48}] wire [55:0] _pmpHomogeneous_T_279 = {_pmpHomogeneous_T[55:32], _pmpHomogeneous_T[31:0] ^ _pmpHomogeneous_T_278}; // @[PTW.scala:548:80] wire [43:0] _pmpHomogeneous_T_280 = _pmpHomogeneous_T_279[55:12]; // @[PMP.scala:98:{53,66}] wire _pmpHomogeneous_T_281 = |_pmpHomogeneous_T_280; // @[PMP.scala:98:{66,78}] wire _pmpHomogeneous_T_283 = _pmpHomogeneous_T_282 ? _pmpHomogeneous_T_274 : _pmpHomogeneous_T_267; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_285 = _pmpHomogeneous_T_284 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_283; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_286 = &count; // @[package.scala:39:86] wire _pmpHomogeneous_T_287 = _pmpHomogeneous_T_286 ? _pmpHomogeneous_T_281 : _pmpHomogeneous_T_285; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_T_288 = pmpHomogeneous_maskHomogeneous_7 | _pmpHomogeneous_T_287; // @[package.scala:39:76] wire _pmpHomogeneous_T_289 = io_dpath_pmp_7_cfg_a_0[0]; // @[PTW.scala:219:7] wire _pmpHomogeneous_T_290 = ~_pmpHomogeneous_T_289; // @[PMP.scala:46:26, :118:45] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_36 = ~_pmpHomogeneous_beginsAfterLower_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_37 = {_pmpHomogeneous_beginsAfterLower_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterLower_T_38 = ~_pmpHomogeneous_beginsAfterLower_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterLower_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterLower_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterLower_7 = ~_pmpHomogeneous_beginsAfterLower_T_39; // @[PMP.scala:106:{28,32}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_36 = ~_pmpHomogeneous_beginsAfterUpper_T_35; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_37 = {_pmpHomogeneous_beginsAfterUpper_T_36[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_beginsAfterUpper_T_38 = ~_pmpHomogeneous_beginsAfterUpper_T_37; // @[PMP.scala:60:{27,48}] wire _pmpHomogeneous_beginsAfterUpper_T_39 = _pmpHomogeneous_T < {24'h0, _pmpHomogeneous_beginsAfterUpper_T_38}; // @[PTW.scala:548:80] wire pmpHomogeneous_beginsAfterUpper_7 = ~_pmpHomogeneous_beginsAfterUpper_T_39; // @[PMP.scala:107:{28,32}] wire [31:0] _pmpHomogeneous_pgMask_T_36 = _pmpHomogeneous_pgMask_T_35 ? 32'hFFE00000 : 32'hC0000000; // @[package.scala:39:{76,86}] wire [31:0] _pmpHomogeneous_pgMask_T_38 = _pmpHomogeneous_pgMask_T_37 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_36; // @[package.scala:39:{76,86}] wire _pmpHomogeneous_pgMask_T_39 = &count; // @[package.scala:39:86] wire [31:0] pmpHomogeneous_pgMask_7 = _pmpHomogeneous_pgMask_T_39 ? 32'hFFFFF000 : _pmpHomogeneous_pgMask_T_38; // @[package.scala:39:{76,86}] wire [55:0] _GEN_19 = {24'h0, _pmpHomogeneous_T[31:0] & pmpHomogeneous_pgMask_7}; // @[package.scala:39:76] wire [55:0] _pmpHomogeneous_endsBeforeLower_T_42; // @[PMP.scala:110:30] assign _pmpHomogeneous_endsBeforeLower_T_42 = _GEN_19; // @[PMP.scala:110:30] wire [55:0] _pmpHomogeneous_endsBeforeUpper_T_42; // @[PMP.scala:111:30] assign _pmpHomogeneous_endsBeforeUpper_T_42 = _GEN_19; // @[PMP.scala:110:30, :111:30] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_44 = ~_pmpHomogeneous_endsBeforeLower_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_45 = {_pmpHomogeneous_endsBeforeLower_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_46 = ~_pmpHomogeneous_endsBeforeLower_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeLower_T_47 = _pmpHomogeneous_endsBeforeLower_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeLower_7 = _pmpHomogeneous_endsBeforeLower_T_42 < {24'h0, _pmpHomogeneous_endsBeforeLower_T_47}; // @[PMP.scala:110:{30,40,58}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_44 = ~_pmpHomogeneous_endsBeforeUpper_T_43; // @[PMP.scala:60:{29,36}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_45 = {_pmpHomogeneous_endsBeforeUpper_T_44[31:2], 2'h3}; // @[PMP.scala:60:{29,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_46 = ~_pmpHomogeneous_endsBeforeUpper_T_45; // @[PMP.scala:60:{27,48}] wire [31:0] _pmpHomogeneous_endsBeforeUpper_T_47 = _pmpHomogeneous_endsBeforeUpper_T_46 & pmpHomogeneous_pgMask_7; // @[package.scala:39:76] wire pmpHomogeneous_endsBeforeUpper_7 = _pmpHomogeneous_endsBeforeUpper_T_42 < {24'h0, _pmpHomogeneous_endsBeforeUpper_T_47}; // @[PMP.scala:111:{30,40,53}] wire _pmpHomogeneous_T_291 = pmpHomogeneous_endsBeforeLower_7 | pmpHomogeneous_beginsAfterUpper_7; // @[PMP.scala:107:28, :110:40, :113:21] wire _pmpHomogeneous_T_292 = pmpHomogeneous_beginsAfterLower_7 & pmpHomogeneous_endsBeforeUpper_7; // @[PMP.scala:106:28, :111:40, :113:62] wire _pmpHomogeneous_T_293 = _pmpHomogeneous_T_291 | _pmpHomogeneous_T_292; // @[PMP.scala:113:{21,41,62}] wire _pmpHomogeneous_T_294 = _pmpHomogeneous_T_290 | _pmpHomogeneous_T_293; // @[PMP.scala:113:41, :118:{45,58}] wire _pmpHomogeneous_T_295 = _pmpHomogeneous_T_260 ? _pmpHomogeneous_T_288 : _pmpHomogeneous_T_294; // @[PMP.scala:45:20, :98:21, :118:{8,58}] wire pmpHomogeneous = _pmpHomogeneous_T_259 & _pmpHomogeneous_T_295; // @[PMP.scala:118:8, :138:10] wire homogeneous = pmaHomogeneous & pmpHomogeneous; // @[package.scala:39:76] assign _io_requestor_0_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_1_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_2_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_3_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_4_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_5_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_6_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_7_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_8_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_9_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_10_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_11_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_12_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_13_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_14_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_15_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_16_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_17_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_18_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign _io_requestor_19_resp_bits_homogeneous_T = homogeneous; // @[PTW.scala:549:36, :562:58] assign io_requestor_0_resp_bits_homogeneous_0 = _io_requestor_0_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_0_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_0_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_0_resp_bits_gpa_bits_T_2 = _io_requestor_0_resp_bits_gpa_bits_T | _io_requestor_0_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _T_171 = aux_count == 2'h2; // @[PTW.scala:278:22, :566:60] wire _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_0_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_1_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_2_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_3_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_3_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_4_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_4_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_5_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_5_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_6_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_6_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_7_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_7_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_8_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_8_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_9_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_9_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_10_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_10_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_11_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_11_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_12_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_12_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_13_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_13_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_14_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_14_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_15_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_15_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_16_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_16_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_17_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_17_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_18_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_18_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _io_requestor_19_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:60] assign _io_requestor_19_resp_bits_gpa_bits_T_3 = _T_171; // @[PTW.scala:566:60] wire _gpa_pgoff_T; // @[PTW.scala:615:36] assign _gpa_pgoff_T = _T_171; // @[PTW.scala:566:60, :615:36] wire _l2_refill_T_7; // @[PTW.scala:715:40] assign _l2_refill_T_7 = _T_171; // @[PTW.scala:566:60, :715:40] wire _io_requestor_0_resp_bits_gpa_bits_T_4 = _io_requestor_0_resp_bits_gpa_bits_T_2 | _io_requestor_0_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [25:0] _io_requestor_0_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_1_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_2_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_3_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_4_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_5_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_6_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_7_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_8_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_9_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_10_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_11_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_12_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_13_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_14_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_15_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_16_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_17_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_18_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [25:0] _io_requestor_19_resp_bits_gpa_bits_T_5 = aux_pte_ppn[43:18]; // @[PTW.scala:280:20, :343:49] wire [17:0] _io_requestor_0_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_1_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_2_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_3_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_4_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_5_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_6_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_7_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_8_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_9_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_10_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_11_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_12_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_13_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_14_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_15_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_16_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_17_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_18_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _io_requestor_19_resp_bits_gpa_bits_T_6 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _r_pte_T_18 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79] wire [17:0] _aux_pte_s1_ppns_T_1 = r_req_addr[17:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_7 = {_io_requestor_0_resp_bits_gpa_bits_T_5, _io_requestor_0_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _io_requestor_0_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_1_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_2_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_3_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_4_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_5_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_6_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_7_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_8_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_9_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_10_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_11_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_12_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_13_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_14_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_15_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_16_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_17_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_18_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [34:0] _io_requestor_19_resp_bits_gpa_bits_T_8 = aux_pte_ppn[43:9]; // @[PTW.scala:280:20, :343:49] wire [8:0] _io_requestor_0_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_1_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_2_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_3_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_4_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_5_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_6_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_7_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_8_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_9_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_10_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_11_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_12_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_13_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_14_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_15_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_16_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_17_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_18_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _io_requestor_19_resp_bits_gpa_bits_T_9 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _r_pte_T_21 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79] wire [8:0] _aux_pte_s1_ppns_T_3 = r_req_addr[8:0]; // @[PTW.scala:270:18, :343:79, :744:122] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_10 = {_io_requestor_0_resp_bits_gpa_bits_T_8, _io_requestor_0_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_0_resp_bits_gpa_bits_truncIdx = _io_requestor_0_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_0_resp_bits_gpa_bits_T_11 = io_requestor_0_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_12 = _io_requestor_0_resp_bits_gpa_bits_T_11 ? _io_requestor_0_resp_bits_gpa_bits_T_10 : _io_requestor_0_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_0_resp_bits_gpa_bits_T_13 = _io_requestor_0_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_0_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_0_resp_bits_gpa_bits_T_14 = {_io_requestor_0_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_0_resp_bits_gpa_bits_0 = _io_requestor_0_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_0_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_0_resp_bits_gpa_is_pte_0 = _io_requestor_0_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_1_resp_bits_homogeneous_0 = _io_requestor_1_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_1_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_1_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_1_resp_bits_gpa_bits_T_2 = _io_requestor_1_resp_bits_gpa_bits_T | _io_requestor_1_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_1_resp_bits_gpa_bits_T_4 = _io_requestor_1_resp_bits_gpa_bits_T_2 | _io_requestor_1_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_7 = {_io_requestor_1_resp_bits_gpa_bits_T_5, _io_requestor_1_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_10 = {_io_requestor_1_resp_bits_gpa_bits_T_8, _io_requestor_1_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_1_resp_bits_gpa_bits_truncIdx = _io_requestor_1_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_1_resp_bits_gpa_bits_T_11 = io_requestor_1_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_12 = _io_requestor_1_resp_bits_gpa_bits_T_11 ? _io_requestor_1_resp_bits_gpa_bits_T_10 : _io_requestor_1_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_1_resp_bits_gpa_bits_T_13 = _io_requestor_1_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_1_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_1_resp_bits_gpa_bits_T_14 = {_io_requestor_1_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_1_resp_bits_gpa_bits_0 = _io_requestor_1_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_1_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_1_resp_bits_gpa_is_pte_0 = _io_requestor_1_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_2_resp_bits_homogeneous_0 = _io_requestor_2_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_2_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_2_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_2_resp_bits_gpa_bits_T_2 = _io_requestor_2_resp_bits_gpa_bits_T | _io_requestor_2_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_2_resp_bits_gpa_bits_T_4 = _io_requestor_2_resp_bits_gpa_bits_T_2 | _io_requestor_2_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_7 = {_io_requestor_2_resp_bits_gpa_bits_T_5, _io_requestor_2_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_10 = {_io_requestor_2_resp_bits_gpa_bits_T_8, _io_requestor_2_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_2_resp_bits_gpa_bits_truncIdx = _io_requestor_2_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_2_resp_bits_gpa_bits_T_11 = io_requestor_2_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_12 = _io_requestor_2_resp_bits_gpa_bits_T_11 ? _io_requestor_2_resp_bits_gpa_bits_T_10 : _io_requestor_2_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_2_resp_bits_gpa_bits_T_13 = _io_requestor_2_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_2_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_2_resp_bits_gpa_bits_T_14 = {_io_requestor_2_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_2_resp_bits_gpa_bits_0 = _io_requestor_2_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_2_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_2_resp_bits_gpa_is_pte_0 = _io_requestor_2_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_3_resp_bits_homogeneous_0 = _io_requestor_3_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_3_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_3_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_3_resp_bits_gpa_bits_T_2 = _io_requestor_3_resp_bits_gpa_bits_T | _io_requestor_3_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_3_resp_bits_gpa_bits_T_4 = _io_requestor_3_resp_bits_gpa_bits_T_2 | _io_requestor_3_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_7 = {_io_requestor_3_resp_bits_gpa_bits_T_5, _io_requestor_3_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_10 = {_io_requestor_3_resp_bits_gpa_bits_T_8, _io_requestor_3_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_3_resp_bits_gpa_bits_truncIdx = _io_requestor_3_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_3_resp_bits_gpa_bits_T_11 = io_requestor_3_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_12 = _io_requestor_3_resp_bits_gpa_bits_T_11 ? _io_requestor_3_resp_bits_gpa_bits_T_10 : _io_requestor_3_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_3_resp_bits_gpa_bits_T_13 = _io_requestor_3_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_3_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_3_resp_bits_gpa_bits_T_14 = {_io_requestor_3_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_3_resp_bits_gpa_bits_0 = _io_requestor_3_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_3_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_3_resp_bits_gpa_is_pte_0 = _io_requestor_3_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_4_resp_bits_homogeneous_0 = _io_requestor_4_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_4_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_4_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_4_resp_bits_gpa_bits_T_2 = _io_requestor_4_resp_bits_gpa_bits_T | _io_requestor_4_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_4_resp_bits_gpa_bits_T_4 = _io_requestor_4_resp_bits_gpa_bits_T_2 | _io_requestor_4_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_4_resp_bits_gpa_bits_T_7 = {_io_requestor_4_resp_bits_gpa_bits_T_5, _io_requestor_4_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_4_resp_bits_gpa_bits_T_10 = {_io_requestor_4_resp_bits_gpa_bits_T_8, _io_requestor_4_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_4_resp_bits_gpa_bits_truncIdx = _io_requestor_4_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_4_resp_bits_gpa_bits_T_11 = io_requestor_4_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_4_resp_bits_gpa_bits_T_12 = _io_requestor_4_resp_bits_gpa_bits_T_11 ? _io_requestor_4_resp_bits_gpa_bits_T_10 : _io_requestor_4_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_4_resp_bits_gpa_bits_T_13 = _io_requestor_4_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_4_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_4_resp_bits_gpa_bits_T_14 = {_io_requestor_4_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_4_resp_bits_gpa_bits_0 = _io_requestor_4_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_4_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_4_resp_bits_gpa_is_pte_0 = _io_requestor_4_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_5_resp_bits_homogeneous_0 = _io_requestor_5_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_5_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_5_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_5_resp_bits_gpa_bits_T_2 = _io_requestor_5_resp_bits_gpa_bits_T | _io_requestor_5_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_5_resp_bits_gpa_bits_T_4 = _io_requestor_5_resp_bits_gpa_bits_T_2 | _io_requestor_5_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_5_resp_bits_gpa_bits_T_7 = {_io_requestor_5_resp_bits_gpa_bits_T_5, _io_requestor_5_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_5_resp_bits_gpa_bits_T_10 = {_io_requestor_5_resp_bits_gpa_bits_T_8, _io_requestor_5_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_5_resp_bits_gpa_bits_truncIdx = _io_requestor_5_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_5_resp_bits_gpa_bits_T_11 = io_requestor_5_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_5_resp_bits_gpa_bits_T_12 = _io_requestor_5_resp_bits_gpa_bits_T_11 ? _io_requestor_5_resp_bits_gpa_bits_T_10 : _io_requestor_5_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_5_resp_bits_gpa_bits_T_13 = _io_requestor_5_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_5_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_5_resp_bits_gpa_bits_T_14 = {_io_requestor_5_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_5_resp_bits_gpa_bits_0 = _io_requestor_5_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_5_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_5_resp_bits_gpa_is_pte_0 = _io_requestor_5_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_6_resp_bits_homogeneous_0 = _io_requestor_6_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_6_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_6_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_6_resp_bits_gpa_bits_T_2 = _io_requestor_6_resp_bits_gpa_bits_T | _io_requestor_6_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_6_resp_bits_gpa_bits_T_4 = _io_requestor_6_resp_bits_gpa_bits_T_2 | _io_requestor_6_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_6_resp_bits_gpa_bits_T_7 = {_io_requestor_6_resp_bits_gpa_bits_T_5, _io_requestor_6_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_6_resp_bits_gpa_bits_T_10 = {_io_requestor_6_resp_bits_gpa_bits_T_8, _io_requestor_6_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_6_resp_bits_gpa_bits_truncIdx = _io_requestor_6_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_6_resp_bits_gpa_bits_T_11 = io_requestor_6_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_6_resp_bits_gpa_bits_T_12 = _io_requestor_6_resp_bits_gpa_bits_T_11 ? _io_requestor_6_resp_bits_gpa_bits_T_10 : _io_requestor_6_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_6_resp_bits_gpa_bits_T_13 = _io_requestor_6_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_6_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_6_resp_bits_gpa_bits_T_14 = {_io_requestor_6_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_6_resp_bits_gpa_bits_0 = _io_requestor_6_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_6_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_6_resp_bits_gpa_is_pte_0 = _io_requestor_6_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_7_resp_bits_homogeneous_0 = _io_requestor_7_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_7_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_7_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_7_resp_bits_gpa_bits_T_2 = _io_requestor_7_resp_bits_gpa_bits_T | _io_requestor_7_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_7_resp_bits_gpa_bits_T_4 = _io_requestor_7_resp_bits_gpa_bits_T_2 | _io_requestor_7_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_7_resp_bits_gpa_bits_T_7 = {_io_requestor_7_resp_bits_gpa_bits_T_5, _io_requestor_7_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_7_resp_bits_gpa_bits_T_10 = {_io_requestor_7_resp_bits_gpa_bits_T_8, _io_requestor_7_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_7_resp_bits_gpa_bits_truncIdx = _io_requestor_7_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_7_resp_bits_gpa_bits_T_11 = io_requestor_7_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_7_resp_bits_gpa_bits_T_12 = _io_requestor_7_resp_bits_gpa_bits_T_11 ? _io_requestor_7_resp_bits_gpa_bits_T_10 : _io_requestor_7_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_7_resp_bits_gpa_bits_T_13 = _io_requestor_7_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_7_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_7_resp_bits_gpa_bits_T_14 = {_io_requestor_7_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_7_resp_bits_gpa_bits_0 = _io_requestor_7_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_7_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_7_resp_bits_gpa_is_pte_0 = _io_requestor_7_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_8_resp_bits_homogeneous_0 = _io_requestor_8_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_8_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_8_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_8_resp_bits_gpa_bits_T_2 = _io_requestor_8_resp_bits_gpa_bits_T | _io_requestor_8_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_8_resp_bits_gpa_bits_T_4 = _io_requestor_8_resp_bits_gpa_bits_T_2 | _io_requestor_8_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_8_resp_bits_gpa_bits_T_7 = {_io_requestor_8_resp_bits_gpa_bits_T_5, _io_requestor_8_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_8_resp_bits_gpa_bits_T_10 = {_io_requestor_8_resp_bits_gpa_bits_T_8, _io_requestor_8_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_8_resp_bits_gpa_bits_truncIdx = _io_requestor_8_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_8_resp_bits_gpa_bits_T_11 = io_requestor_8_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_8_resp_bits_gpa_bits_T_12 = _io_requestor_8_resp_bits_gpa_bits_T_11 ? _io_requestor_8_resp_bits_gpa_bits_T_10 : _io_requestor_8_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_8_resp_bits_gpa_bits_T_13 = _io_requestor_8_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_8_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_8_resp_bits_gpa_bits_T_14 = {_io_requestor_8_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_8_resp_bits_gpa_bits_0 = _io_requestor_8_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_8_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_8_resp_bits_gpa_is_pte_0 = _io_requestor_8_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_9_resp_bits_homogeneous_0 = _io_requestor_9_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_9_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_9_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_9_resp_bits_gpa_bits_T_2 = _io_requestor_9_resp_bits_gpa_bits_T | _io_requestor_9_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_9_resp_bits_gpa_bits_T_4 = _io_requestor_9_resp_bits_gpa_bits_T_2 | _io_requestor_9_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_9_resp_bits_gpa_bits_T_7 = {_io_requestor_9_resp_bits_gpa_bits_T_5, _io_requestor_9_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_9_resp_bits_gpa_bits_T_10 = {_io_requestor_9_resp_bits_gpa_bits_T_8, _io_requestor_9_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_9_resp_bits_gpa_bits_truncIdx = _io_requestor_9_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_9_resp_bits_gpa_bits_T_11 = io_requestor_9_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_9_resp_bits_gpa_bits_T_12 = _io_requestor_9_resp_bits_gpa_bits_T_11 ? _io_requestor_9_resp_bits_gpa_bits_T_10 : _io_requestor_9_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_9_resp_bits_gpa_bits_T_13 = _io_requestor_9_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_9_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_9_resp_bits_gpa_bits_T_14 = {_io_requestor_9_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_9_resp_bits_gpa_bits_0 = _io_requestor_9_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_9_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_9_resp_bits_gpa_is_pte_0 = _io_requestor_9_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_10_resp_bits_homogeneous_0 = _io_requestor_10_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_10_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_10_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_10_resp_bits_gpa_bits_T_2 = _io_requestor_10_resp_bits_gpa_bits_T | _io_requestor_10_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_10_resp_bits_gpa_bits_T_4 = _io_requestor_10_resp_bits_gpa_bits_T_2 | _io_requestor_10_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_10_resp_bits_gpa_bits_T_7 = {_io_requestor_10_resp_bits_gpa_bits_T_5, _io_requestor_10_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_10_resp_bits_gpa_bits_T_10 = {_io_requestor_10_resp_bits_gpa_bits_T_8, _io_requestor_10_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_10_resp_bits_gpa_bits_truncIdx = _io_requestor_10_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_10_resp_bits_gpa_bits_T_11 = io_requestor_10_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_10_resp_bits_gpa_bits_T_12 = _io_requestor_10_resp_bits_gpa_bits_T_11 ? _io_requestor_10_resp_bits_gpa_bits_T_10 : _io_requestor_10_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_10_resp_bits_gpa_bits_T_13 = _io_requestor_10_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_10_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_10_resp_bits_gpa_bits_T_14 = {_io_requestor_10_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_10_resp_bits_gpa_bits_0 = _io_requestor_10_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_10_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_10_resp_bits_gpa_is_pte_0 = _io_requestor_10_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_11_resp_bits_homogeneous_0 = _io_requestor_11_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_11_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_11_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_11_resp_bits_gpa_bits_T_2 = _io_requestor_11_resp_bits_gpa_bits_T | _io_requestor_11_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_11_resp_bits_gpa_bits_T_4 = _io_requestor_11_resp_bits_gpa_bits_T_2 | _io_requestor_11_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_11_resp_bits_gpa_bits_T_7 = {_io_requestor_11_resp_bits_gpa_bits_T_5, _io_requestor_11_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_11_resp_bits_gpa_bits_T_10 = {_io_requestor_11_resp_bits_gpa_bits_T_8, _io_requestor_11_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_11_resp_bits_gpa_bits_truncIdx = _io_requestor_11_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_11_resp_bits_gpa_bits_T_11 = io_requestor_11_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_11_resp_bits_gpa_bits_T_12 = _io_requestor_11_resp_bits_gpa_bits_T_11 ? _io_requestor_11_resp_bits_gpa_bits_T_10 : _io_requestor_11_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_11_resp_bits_gpa_bits_T_13 = _io_requestor_11_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_11_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_11_resp_bits_gpa_bits_T_14 = {_io_requestor_11_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_11_resp_bits_gpa_bits_0 = _io_requestor_11_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_11_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_11_resp_bits_gpa_is_pte_0 = _io_requestor_11_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_12_resp_bits_homogeneous_0 = _io_requestor_12_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_12_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_12_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_12_resp_bits_gpa_bits_T_2 = _io_requestor_12_resp_bits_gpa_bits_T | _io_requestor_12_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_12_resp_bits_gpa_bits_T_4 = _io_requestor_12_resp_bits_gpa_bits_T_2 | _io_requestor_12_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_12_resp_bits_gpa_bits_T_7 = {_io_requestor_12_resp_bits_gpa_bits_T_5, _io_requestor_12_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_12_resp_bits_gpa_bits_T_10 = {_io_requestor_12_resp_bits_gpa_bits_T_8, _io_requestor_12_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_12_resp_bits_gpa_bits_truncIdx = _io_requestor_12_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_12_resp_bits_gpa_bits_T_11 = io_requestor_12_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_12_resp_bits_gpa_bits_T_12 = _io_requestor_12_resp_bits_gpa_bits_T_11 ? _io_requestor_12_resp_bits_gpa_bits_T_10 : _io_requestor_12_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_12_resp_bits_gpa_bits_T_13 = _io_requestor_12_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_12_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_12_resp_bits_gpa_bits_T_14 = {_io_requestor_12_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_12_resp_bits_gpa_bits_0 = _io_requestor_12_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_12_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_12_resp_bits_gpa_is_pte_0 = _io_requestor_12_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_13_resp_bits_homogeneous_0 = _io_requestor_13_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_13_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_13_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_13_resp_bits_gpa_bits_T_2 = _io_requestor_13_resp_bits_gpa_bits_T | _io_requestor_13_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_13_resp_bits_gpa_bits_T_4 = _io_requestor_13_resp_bits_gpa_bits_T_2 | _io_requestor_13_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_13_resp_bits_gpa_bits_T_7 = {_io_requestor_13_resp_bits_gpa_bits_T_5, _io_requestor_13_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_13_resp_bits_gpa_bits_T_10 = {_io_requestor_13_resp_bits_gpa_bits_T_8, _io_requestor_13_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_13_resp_bits_gpa_bits_truncIdx = _io_requestor_13_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_13_resp_bits_gpa_bits_T_11 = io_requestor_13_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_13_resp_bits_gpa_bits_T_12 = _io_requestor_13_resp_bits_gpa_bits_T_11 ? _io_requestor_13_resp_bits_gpa_bits_T_10 : _io_requestor_13_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_13_resp_bits_gpa_bits_T_13 = _io_requestor_13_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_13_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_13_resp_bits_gpa_bits_T_14 = {_io_requestor_13_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_13_resp_bits_gpa_bits_0 = _io_requestor_13_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_13_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_13_resp_bits_gpa_is_pte_0 = _io_requestor_13_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_14_resp_bits_homogeneous_0 = _io_requestor_14_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_14_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_14_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_14_resp_bits_gpa_bits_T_2 = _io_requestor_14_resp_bits_gpa_bits_T | _io_requestor_14_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_14_resp_bits_gpa_bits_T_4 = _io_requestor_14_resp_bits_gpa_bits_T_2 | _io_requestor_14_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_14_resp_bits_gpa_bits_T_7 = {_io_requestor_14_resp_bits_gpa_bits_T_5, _io_requestor_14_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_14_resp_bits_gpa_bits_T_10 = {_io_requestor_14_resp_bits_gpa_bits_T_8, _io_requestor_14_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_14_resp_bits_gpa_bits_truncIdx = _io_requestor_14_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_14_resp_bits_gpa_bits_T_11 = io_requestor_14_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_14_resp_bits_gpa_bits_T_12 = _io_requestor_14_resp_bits_gpa_bits_T_11 ? _io_requestor_14_resp_bits_gpa_bits_T_10 : _io_requestor_14_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_14_resp_bits_gpa_bits_T_13 = _io_requestor_14_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_14_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_14_resp_bits_gpa_bits_T_14 = {_io_requestor_14_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_14_resp_bits_gpa_bits_0 = _io_requestor_14_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_14_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_14_resp_bits_gpa_is_pte_0 = _io_requestor_14_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_15_resp_bits_homogeneous_0 = _io_requestor_15_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_15_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_15_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_15_resp_bits_gpa_bits_T_2 = _io_requestor_15_resp_bits_gpa_bits_T | _io_requestor_15_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_15_resp_bits_gpa_bits_T_4 = _io_requestor_15_resp_bits_gpa_bits_T_2 | _io_requestor_15_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_15_resp_bits_gpa_bits_T_7 = {_io_requestor_15_resp_bits_gpa_bits_T_5, _io_requestor_15_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_15_resp_bits_gpa_bits_T_10 = {_io_requestor_15_resp_bits_gpa_bits_T_8, _io_requestor_15_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_15_resp_bits_gpa_bits_truncIdx = _io_requestor_15_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_15_resp_bits_gpa_bits_T_11 = io_requestor_15_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_15_resp_bits_gpa_bits_T_12 = _io_requestor_15_resp_bits_gpa_bits_T_11 ? _io_requestor_15_resp_bits_gpa_bits_T_10 : _io_requestor_15_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_15_resp_bits_gpa_bits_T_13 = _io_requestor_15_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_15_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_15_resp_bits_gpa_bits_T_14 = {_io_requestor_15_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_15_resp_bits_gpa_bits_0 = _io_requestor_15_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_15_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_15_resp_bits_gpa_is_pte_0 = _io_requestor_15_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_16_resp_bits_homogeneous_0 = _io_requestor_16_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_16_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_16_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_16_resp_bits_gpa_bits_T_2 = _io_requestor_16_resp_bits_gpa_bits_T | _io_requestor_16_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_16_resp_bits_gpa_bits_T_4 = _io_requestor_16_resp_bits_gpa_bits_T_2 | _io_requestor_16_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_16_resp_bits_gpa_bits_T_7 = {_io_requestor_16_resp_bits_gpa_bits_T_5, _io_requestor_16_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_16_resp_bits_gpa_bits_T_10 = {_io_requestor_16_resp_bits_gpa_bits_T_8, _io_requestor_16_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_16_resp_bits_gpa_bits_truncIdx = _io_requestor_16_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_16_resp_bits_gpa_bits_T_11 = io_requestor_16_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_16_resp_bits_gpa_bits_T_12 = _io_requestor_16_resp_bits_gpa_bits_T_11 ? _io_requestor_16_resp_bits_gpa_bits_T_10 : _io_requestor_16_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_16_resp_bits_gpa_bits_T_13 = _io_requestor_16_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_16_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_16_resp_bits_gpa_bits_T_14 = {_io_requestor_16_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_16_resp_bits_gpa_bits_0 = _io_requestor_16_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_16_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_16_resp_bits_gpa_is_pte_0 = _io_requestor_16_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_17_resp_bits_homogeneous_0 = _io_requestor_17_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_17_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_17_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_17_resp_bits_gpa_bits_T_2 = _io_requestor_17_resp_bits_gpa_bits_T | _io_requestor_17_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_17_resp_bits_gpa_bits_T_4 = _io_requestor_17_resp_bits_gpa_bits_T_2 | _io_requestor_17_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_17_resp_bits_gpa_bits_T_7 = {_io_requestor_17_resp_bits_gpa_bits_T_5, _io_requestor_17_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_17_resp_bits_gpa_bits_T_10 = {_io_requestor_17_resp_bits_gpa_bits_T_8, _io_requestor_17_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_17_resp_bits_gpa_bits_truncIdx = _io_requestor_17_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_17_resp_bits_gpa_bits_T_11 = io_requestor_17_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_17_resp_bits_gpa_bits_T_12 = _io_requestor_17_resp_bits_gpa_bits_T_11 ? _io_requestor_17_resp_bits_gpa_bits_T_10 : _io_requestor_17_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_17_resp_bits_gpa_bits_T_13 = _io_requestor_17_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_17_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_17_resp_bits_gpa_bits_T_14 = {_io_requestor_17_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_17_resp_bits_gpa_bits_0 = _io_requestor_17_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_17_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_17_resp_bits_gpa_is_pte_0 = _io_requestor_17_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_18_resp_bits_homogeneous_0 = _io_requestor_18_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_18_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_18_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_18_resp_bits_gpa_bits_T_2 = _io_requestor_18_resp_bits_gpa_bits_T | _io_requestor_18_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_18_resp_bits_gpa_bits_T_4 = _io_requestor_18_resp_bits_gpa_bits_T_2 | _io_requestor_18_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_18_resp_bits_gpa_bits_T_7 = {_io_requestor_18_resp_bits_gpa_bits_T_5, _io_requestor_18_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_18_resp_bits_gpa_bits_T_10 = {_io_requestor_18_resp_bits_gpa_bits_T_8, _io_requestor_18_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_18_resp_bits_gpa_bits_truncIdx = _io_requestor_18_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_18_resp_bits_gpa_bits_T_11 = io_requestor_18_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_18_resp_bits_gpa_bits_T_12 = _io_requestor_18_resp_bits_gpa_bits_T_11 ? _io_requestor_18_resp_bits_gpa_bits_T_10 : _io_requestor_18_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_18_resp_bits_gpa_bits_T_13 = _io_requestor_18_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_18_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_18_resp_bits_gpa_bits_T_14 = {_io_requestor_18_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_18_resp_bits_gpa_bits_0 = _io_requestor_18_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_18_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_18_resp_bits_gpa_is_pte_0 = _io_requestor_18_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] assign io_requestor_19_resp_bits_homogeneous_0 = _io_requestor_19_resp_bits_homogeneous_T; // @[PTW.scala:219:7, :562:58] wire _io_requestor_19_resp_bits_gpa_bits_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :566:15] wire _io_requestor_19_resp_bits_gpa_bits_T_1 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32] wire _io_requestor_19_resp_bits_gpa_bits_T_2 = _io_requestor_19_resp_bits_gpa_bits_T | _io_requestor_19_resp_bits_gpa_bits_T_1; // @[PTW.scala:566:{15,29,32}] wire _io_requestor_19_resp_bits_gpa_bits_T_4 = _io_requestor_19_resp_bits_gpa_bits_T_2 | _io_requestor_19_resp_bits_gpa_bits_T_3; // @[PTW.scala:566:{29,47,60}] wire [43:0] _io_requestor_19_resp_bits_gpa_bits_T_7 = {_io_requestor_19_resp_bits_gpa_bits_T_5, _io_requestor_19_resp_bits_gpa_bits_T_6}; // @[PTW.scala:343:{44,49,79}] wire [43:0] _io_requestor_19_resp_bits_gpa_bits_T_10 = {_io_requestor_19_resp_bits_gpa_bits_T_8, _io_requestor_19_resp_bits_gpa_bits_T_9}; // @[PTW.scala:343:{44,49,79}] wire io_requestor_19_resp_bits_gpa_bits_truncIdx = _io_requestor_19_resp_bits_gpa_bits_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _io_requestor_19_resp_bits_gpa_bits_T_11 = io_requestor_19_resp_bits_gpa_bits_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _io_requestor_19_resp_bits_gpa_bits_T_12 = _io_requestor_19_resp_bits_gpa_bits_T_11 ? _io_requestor_19_resp_bits_gpa_bits_T_10 : _io_requestor_19_resp_bits_gpa_bits_T_7; // @[package.scala:39:{76,86}] wire [43:0] _io_requestor_19_resp_bits_gpa_bits_T_13 = _io_requestor_19_resp_bits_gpa_bits_T_4 ? aux_pte_ppn : _io_requestor_19_resp_bits_gpa_bits_T_12; // @[package.scala:39:76] wire [55:0] _io_requestor_19_resp_bits_gpa_bits_T_14 = {_io_requestor_19_resp_bits_gpa_bits_T_13, gpa_pgoff}; // @[PTW.scala:281:22, :566:{10,14}] assign io_requestor_19_resp_bits_gpa_bits_0 = _io_requestor_19_resp_bits_gpa_bits_T_14[38:0]; // @[PTW.scala:219:7, :565:40, :566:10] assign _io_requestor_19_resp_bits_gpa_is_pte_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :567:45] assign io_requestor_19_resp_bits_gpa_is_pte_0 = _io_requestor_19_resp_bits_gpa_is_pte_T; // @[PTW.scala:219:7, :567:45] wire [2:0] next_state; // @[PTW.scala:579:31] wire do_switch; // @[PTW.scala:581:30] wire _T_129 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire _GEN_20 = ~(|state) & _T_129; // @[Decoupled.scala:51:35] wire [43:0] aux_ppn = {17'h0, _arb_io_out_bits_bits_addr}; // @[PTW.scala:236:19, :589:38] wire [2:0] _next_state_T = {2'h0, _arb_io_out_bits_valid}; // @[PTW.scala:236:19, :593:26] wire [14:0] resp_gf_idxs_0 = aux_ppn[43:29]; // @[PTW.scala:589:38, :787:58] wire [14:0] _resp_gf_WIRE_0 = resp_gf_idxs_0; // @[package.scala:43:40] wire _resp_gf_T_1 = |_resp_gf_WIRE_0; // @[package.scala:43:40] wire [29:0] _gpa_pgoff_T_1 = {r_req_addr, 3'h0}; // @[PTW.scala:270:18, :615:67] wire [29:0] _gpa_pgoff_T_2 = _gpa_pgoff_T ? _gpa_pgoff_T_1 : 30'h0; // @[PTW.scala:615:{25,36,67}] wire [2:0] _aux_count_T_1 = {1'h0, aux_count} + 3'h1; // @[PTW.scala:278:22, :619:32] wire [1:0] _aux_count_T_2 = _aux_count_T_1[1:0]; // @[PTW.scala:619:32] wire [2:0] _GEN_21 = {1'h0, count} + 3'h1; // @[PTW.scala:259:18, :624:24] wire [2:0] _count_T_4; // @[PTW.scala:624:24] assign _count_T_4 = _GEN_21; // @[PTW.scala:624:24] wire [2:0] _count_T_6; // @[PTW.scala:696:22] assign _count_T_6 = _GEN_21; // @[PTW.scala:624:24, :696:22] wire [2:0] _aux_count_T_3; // @[PTW.scala:741:38] assign _aux_count_T_3 = _GEN_21; // @[PTW.scala:624:24, :741:38] wire [1:0] _count_T_5 = _count_T_4[1:0]; // @[PTW.scala:624:24] wire [2:0] _next_state_T_1 = io_mem_req_ready_0 ? 3'h2 : 3'h1; // @[PTW.scala:219:7, :627:26] wire _T_140 = state == 3'h2; // @[PTW.scala:233:22, :583:18] wire _T_141 = state == 3'h4; // @[PTW.scala:233:22, :583:18] wire _io_dpath_perf_pte_miss_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :640:39] wire _GEN_22 = _T_152 | _T_140; // @[PTW.scala:377:24, :393:26, :583:18] assign io_dpath_perf_pte_miss_0 = ~(~(|state) | _GEN_22) & _T_141 & _io_dpath_perf_pte_miss_T; // @[PTW.scala:219:7, :233:22, :240:30, :393:26, :583:18, :640:{30,39}] wire [1:0] _merged_pte_superpage_mask_T = stage2_final ? max_count : 2'h2; // @[PTW.scala:283:25, :289:25, :662:45] wire _merged_pte_superpage_mask_T_1 = _merged_pte_superpage_mask_T == 2'h1; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_2 = _merged_pte_superpage_mask_T_1 ? 44'hFFFFFFFFE00 : 44'hFFFFFFC0000; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_3 = _merged_pte_superpage_mask_T == 2'h2; // @[package.scala:39:86] wire [43:0] _merged_pte_superpage_mask_T_4 = _merged_pte_superpage_mask_T_3 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_2; // @[package.scala:39:{76,86}] wire _merged_pte_superpage_mask_T_5 = &_merged_pte_superpage_mask_T; // @[package.scala:39:86] wire [43:0] merged_pte_superpage_mask = _merged_pte_superpage_mask_T_5 ? 44'hFFFFFFFFFFF : _merged_pte_superpage_mask_T_4; // @[package.scala:39:{76,86}] wire [25:0] _merged_pte_stage1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64] wire [25:0] _aux_pte_s1_ppns_T = pte_ppn[43:18]; // @[PTW.scala:305:26, :663:64, :744:62] wire [17:0] _merged_pte_stage1_ppns_T_1 = aux_pte_ppn[17:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_0 = {_merged_pte_stage1_ppns_T, _merged_pte_stage1_ppns_T_1}; // @[PTW.scala:663:{56,64,125}] wire [34:0] _merged_pte_stage1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64] wire [34:0] _aux_pte_s1_ppns_T_2 = pte_ppn[43:9]; // @[PTW.scala:305:26, :663:64, :744:62] wire [8:0] _merged_pte_stage1_ppns_T_3 = aux_pte_ppn[8:0]; // @[PTW.scala:280:20, :663:125] wire [43:0] merged_pte_stage1_ppns_1 = {_merged_pte_stage1_ppns_T_2, _merged_pte_stage1_ppns_T_3}; // @[PTW.scala:663:{56,64,125}] wire [43:0] _merged_pte_stage1_ppn_T_1 = _merged_pte_stage1_ppn_T ? merged_pte_stage1_ppns_1 : merged_pte_stage1_ppns_0; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_stage1_ppn_T_3 = _merged_pte_stage1_ppn_T_2 ? pte_ppn : _merged_pte_stage1_ppn_T_1; // @[package.scala:39:{76,86}] wire _merged_pte_stage1_ppn_T_4 = &count; // @[package.scala:39:86] wire [43:0] merged_pte_stage1_ppn = _merged_pte_stage1_ppn_T_4 ? pte_ppn : _merged_pte_stage1_ppn_T_3; // @[package.scala:39:{76,86}] wire [43:0] _merged_pte_T = merged_pte_stage1_ppn & merged_pte_superpage_mask; // @[package.scala:39:76] wire [43:0] merged_pte_ppn = _merged_pte_T; // @[PTW.scala:665:24, :771:26] wire _r_pte_T_2 = ~resp_gf; // @[PTW.scala:263:20, :670:32] wire [43:0] _r_pte_pte_ppn_T_1; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_ppn; // @[PTW.scala:780:26] wire [41:0] _r_pte_pte_ppn_T = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] wire [41:0] _r_pte_pte_ppn_T_2 = r_hgatp_ppn[43:2]; // @[PTW.scala:276:20, :781:30] assign _r_pte_pte_ppn_T_1 = {_r_pte_pte_ppn_T, 2'h0}; // @[PTW.scala:781:{19,30}] assign r_pte_pte_ppn = _r_pte_pte_ppn_T_1; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_7 = _r_pte_T_6 & pte_cache_hit; // @[PTW.scala:367:24, :674:{15,25}] wire [43:0] r_pte_pte_1_ppn; // @[PTW.scala:771:26] assign r_pte_pte_1_ppn = {24'h0, pte_cache_data}; // @[Mux.scala:30:73] wire [16:0] r_pte_idxs_0_1 = pte_ppn[43:27]; // @[PTW.scala:305:26, :778:58] wire [1:0] r_pte_lsbs_1; // @[PTW.scala:779:27] assign r_pte_lsbs_1 = r_pte_idxs_0_1[1:0]; // @[PTW.scala:778:58, :779:27] wire [43:0] _r_pte_pte_ppn_T_3; // @[PTW.scala:781:19] wire [43:0] r_pte_pte_2_ppn; // @[PTW.scala:780:26] assign _r_pte_pte_ppn_T_3 = {_r_pte_pte_ppn_T_2, r_pte_lsbs_1}; // @[PTW.scala:779:27, :781:{19,30}] assign r_pte_pte_2_ppn = _r_pte_pte_ppn_T_3; // @[PTW.scala:780:26, :781:19] wire _r_pte_T_8 = ~traverse; // @[PTW.scala:317:64, :678:29] wire _r_pte_T_9 = _r_pte_T_8 & r_req_vstage1; // @[PTW.scala:270:18, :678:{29,39}] wire _r_pte_T_10 = _r_pte_T_9 & stage2; // @[PTW.scala:282:19, :678:{39,56}] wire [9:0] _r_pte_T_11_reserved_for_future = _r_pte_T_10 ? merged_pte_reserved_for_future : pte_reserved_for_future; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [43:0] _r_pte_T_11_ppn = _r_pte_T_10 ? merged_pte_ppn : pte_ppn; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire [1:0] _r_pte_T_11_reserved_for_software = _r_pte_T_10 ? merged_pte_reserved_for_software : pte_reserved_for_software; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_d = _r_pte_T_10 ? merged_pte_d : pte_d; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_a = _r_pte_T_10 ? merged_pte_a : pte_a; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_g = _r_pte_T_10 ? merged_pte_g : pte_g; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_u = _r_pte_T_10 ? merged_pte_u : pte_u; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_x = _r_pte_T_10 ? merged_pte_x : pte_x; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_w = _r_pte_T_10 ? merged_pte_w : pte_w; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_r = _r_pte_T_10 ? merged_pte_r : pte_r; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_11_v = _r_pte_T_10 ? merged_pte_v : pte_v; // @[PTW.scala:305:26, :678:{28,56}, :771:26] wire _r_pte_T_12 = &state; // @[PTW.scala:233:22, :680:15] wire _r_pte_T_13 = ~homogeneous; // @[PTW.scala:549:36, :680:43] wire _r_pte_T_14 = _r_pte_T_12 & _r_pte_T_13; // @[PTW.scala:680:{15,40,43}] wire _r_pte_T_15 = count != 2'h2; // @[PTW.scala:259:18, :680:65] wire _r_pte_T_16 = _r_pte_T_14 & _r_pte_T_15; // @[PTW.scala:680:{40,56,65}] wire [25:0] _r_pte_T_17 = r_pte_ppn[43:18]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_19 = {_r_pte_T_17, _r_pte_T_18}; // @[PTW.scala:343:{44,49,79}] wire [34:0] _r_pte_T_20 = r_pte_ppn[43:9]; // @[PTW.scala:275:18, :343:49] wire [43:0] _r_pte_T_22 = {_r_pte_T_20, _r_pte_T_21}; // @[PTW.scala:343:{44,49,79}] wire r_pte_truncIdx = _r_pte_truncIdx_T[0]; // @[package.scala:38:{21,47}] wire _r_pte_T_23 = r_pte_truncIdx; // @[package.scala:38:47, :39:86] wire [43:0] _r_pte_T_24 = _r_pte_T_23 ? _r_pte_T_22 : _r_pte_T_19; // @[package.scala:39:{76,86}] wire [43:0] r_pte_pte_3_ppn = _r_pte_T_24; // @[package.scala:39:76] wire _r_pte_T_25 = _arb_io_out_ready_T_2 & _arb_io_out_valid; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_26_reserved_for_future = r_pte_pte_5_reserved_for_future; // @[PTW.scala:682:29, :771:26] wire [43:0] _r_pte_T_26_ppn = r_pte_pte_5_ppn; // @[PTW.scala:682:29, :771:26] wire [1:0] _r_pte_T_26_reserved_for_software = r_pte_pte_5_reserved_for_software; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_d = r_pte_pte_5_d; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_a = r_pte_pte_5_a; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_g = r_pte_pte_5_g; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_u = r_pte_pte_5_u; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_x = r_pte_pte_5_x; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_w = r_pte_pte_5_w; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_r = r_pte_pte_5_r; // @[PTW.scala:682:29, :771:26] wire _r_pte_T_26_v = r_pte_pte_5_v; // @[PTW.scala:682:29, :771:26] wire [9:0] _r_pte_T_27_reserved_for_future = _r_pte_T_25 ? _r_pte_T_26_reserved_for_future : r_pte_reserved_for_future; // @[Decoupled.scala:51:35] wire [43:0] _r_pte_T_27_ppn = _r_pte_T_25 ? _r_pte_T_26_ppn : r_pte_ppn; // @[Decoupled.scala:51:35] wire [1:0] _r_pte_T_27_reserved_for_software = _r_pte_T_25 ? _r_pte_T_26_reserved_for_software : r_pte_reserved_for_software; // @[Decoupled.scala:51:35] wire _r_pte_T_27_d = _r_pte_T_25 ? _r_pte_T_26_d : r_pte_d; // @[Decoupled.scala:51:35] wire _r_pte_T_27_a = _r_pte_T_25 ? _r_pte_T_26_a : r_pte_a; // @[Decoupled.scala:51:35] wire _r_pte_T_27_g = _r_pte_T_25 ? _r_pte_T_26_g : r_pte_g; // @[Decoupled.scala:51:35] wire _r_pte_T_27_u = _r_pte_T_25 ? _r_pte_T_26_u : r_pte_u; // @[Decoupled.scala:51:35] wire _r_pte_T_27_x = _r_pte_T_25 ? _r_pte_T_26_x : r_pte_x; // @[Decoupled.scala:51:35] wire _r_pte_T_27_w = _r_pte_T_25 ? _r_pte_T_26_w : r_pte_w; // @[Decoupled.scala:51:35] wire _r_pte_T_27_r = _r_pte_T_25 ? _r_pte_T_26_r : r_pte_r; // @[Decoupled.scala:51:35] wire _r_pte_T_27_v = _r_pte_T_25 ? _r_pte_T_26_v : r_pte_v; // @[Decoupled.scala:51:35] wire [9:0] _r_pte_T_28_reserved_for_future = _r_pte_T_16 ? r_pte_pte_3_reserved_for_future : _r_pte_T_27_reserved_for_future; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [43:0] _r_pte_T_28_ppn = _r_pte_T_16 ? r_pte_pte_3_ppn : _r_pte_T_27_ppn; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [1:0] _r_pte_T_28_reserved_for_software = _r_pte_T_16 ? r_pte_pte_3_reserved_for_software : _r_pte_T_27_reserved_for_software; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_d = _r_pte_T_16 ? r_pte_pte_3_d : _r_pte_T_27_d; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_a = _r_pte_T_16 ? r_pte_pte_3_a : _r_pte_T_27_a; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_g = _r_pte_T_16 ? r_pte_pte_3_g : _r_pte_T_27_g; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_u = _r_pte_T_16 ? r_pte_pte_3_u : _r_pte_T_27_u; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_x = _r_pte_T_16 ? r_pte_pte_3_x : _r_pte_T_27_x; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_w = _r_pte_T_16 ? r_pte_pte_3_w : _r_pte_T_27_w; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_r = _r_pte_T_16 ? r_pte_pte_3_r : _r_pte_T_27_r; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire _r_pte_T_28_v = _r_pte_T_16 ? r_pte_pte_3_v : _r_pte_T_27_v; // @[PTW.scala:680:{8,56}, :682:8, :771:26] wire [9:0] _r_pte_T_29_reserved_for_future = mem_resp_valid ? _r_pte_T_11_reserved_for_future : _r_pte_T_28_reserved_for_future; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [43:0] _r_pte_T_29_ppn = mem_resp_valid ? _r_pte_T_11_ppn : _r_pte_T_28_ppn; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [1:0] _r_pte_T_29_reserved_for_software = mem_resp_valid ? _r_pte_T_11_reserved_for_software : _r_pte_T_28_reserved_for_software; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_d = mem_resp_valid ? _r_pte_T_11_d : _r_pte_T_28_d; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_a = mem_resp_valid ? _r_pte_T_11_a : _r_pte_T_28_a; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_g = mem_resp_valid ? _r_pte_T_11_g : _r_pte_T_28_g; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_u = mem_resp_valid ? _r_pte_T_11_u : _r_pte_T_28_u; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_x = mem_resp_valid ? _r_pte_T_11_x : _r_pte_T_28_x; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_w = mem_resp_valid ? _r_pte_T_11_w : _r_pte_T_28_w; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_r = mem_resp_valid ? _r_pte_T_11_r : _r_pte_T_28_r; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire _r_pte_T_29_v = mem_resp_valid ? _r_pte_T_11_v : _r_pte_T_28_v; // @[PTW.scala:292:31, :678:{8,28}, :680:8] wire [9:0] _r_pte_T_30_reserved_for_future = do_switch ? r_pte_pte_2_reserved_for_future : _r_pte_T_29_reserved_for_future; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [43:0] _r_pte_T_30_ppn = do_switch ? r_pte_pte_2_ppn : _r_pte_T_29_ppn; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [1:0] _r_pte_T_30_reserved_for_software = do_switch ? r_pte_pte_2_reserved_for_software : _r_pte_T_29_reserved_for_software; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_d = do_switch ? r_pte_pte_2_d : _r_pte_T_29_d; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_a = do_switch ? r_pte_pte_2_a : _r_pte_T_29_a; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_g = do_switch ? r_pte_pte_2_g : _r_pte_T_29_g; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_u = do_switch ? r_pte_pte_2_u : _r_pte_T_29_u; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_x = do_switch ? r_pte_pte_2_x : _r_pte_T_29_x; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_w = do_switch ? r_pte_pte_2_w : _r_pte_T_29_w; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_r = do_switch ? r_pte_pte_2_r : _r_pte_T_29_r; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire _r_pte_T_30_v = do_switch ? r_pte_pte_2_v : _r_pte_T_29_v; // @[PTW.scala:581:30, :676:8, :678:8, :780:26] wire [9:0] _r_pte_T_31_reserved_for_future = _r_pte_T_7 ? 10'h0 : _r_pte_T_30_reserved_for_future; // @[PTW.scala:674:{8,25}, :676:8] wire [43:0] _r_pte_T_31_ppn = _r_pte_T_7 ? r_pte_pte_1_ppn : _r_pte_T_30_ppn; // @[PTW.scala:674:{8,25}, :676:8, :771:26] wire [1:0] _r_pte_T_31_reserved_for_software = _r_pte_T_7 ? 2'h0 : _r_pte_T_30_reserved_for_software; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_d = ~_r_pte_T_7 & _r_pte_T_30_d; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_a = ~_r_pte_T_7 & _r_pte_T_30_a; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_g = ~_r_pte_T_7 & _r_pte_T_30_g; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_u = ~_r_pte_T_7 & _r_pte_T_30_u; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_x = ~_r_pte_T_7 & _r_pte_T_30_x; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_w = ~_r_pte_T_7 & _r_pte_T_30_w; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_r = ~_r_pte_T_7 & _r_pte_T_30_r; // @[PTW.scala:674:{8,25}, :676:8] wire _r_pte_T_31_v = ~_r_pte_T_7 & _r_pte_T_30_v; // @[PTW.scala:674:{8,25}, :676:8] wire [9:0] _r_pte_T_32_reserved_for_future = _r_pte_T_31_reserved_for_future; // @[PTW.scala:672:8, :674:8] wire [43:0] _r_pte_T_32_ppn = _r_pte_T_31_ppn; // @[PTW.scala:672:8, :674:8] wire [1:0] _r_pte_T_32_reserved_for_software = _r_pte_T_31_reserved_for_software; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_d = _r_pte_T_31_d; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_a = _r_pte_T_31_a; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_g = _r_pte_T_31_g; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_u = _r_pte_T_31_u; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_x = _r_pte_T_31_x; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_w = _r_pte_T_31_w; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_r = _r_pte_T_31_r; // @[PTW.scala:672:8, :674:8] wire _r_pte_T_32_v = _r_pte_T_31_v; // @[PTW.scala:672:8, :674:8] wire [9:0] _r_pte_T_33_reserved_for_future = _r_pte_T_32_reserved_for_future; // @[PTW.scala:670:8, :672:8] wire [43:0] _r_pte_T_33_ppn = _r_pte_T_32_ppn; // @[PTW.scala:670:8, :672:8] wire [1:0] _r_pte_T_33_reserved_for_software = _r_pte_T_32_reserved_for_software; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_d = _r_pte_T_32_d; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_a = _r_pte_T_32_a; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_g = _r_pte_T_32_g; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_u = _r_pte_T_32_u; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_x = _r_pte_T_32_x; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_w = _r_pte_T_32_w; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_r = _r_pte_T_32_r; // @[PTW.scala:670:8, :672:8] wire _r_pte_T_33_v = _r_pte_T_32_v; // @[PTW.scala:670:8, :672:8] wire [1:0] _count_T_7 = _count_T_6[1:0]; // @[PTW.scala:696:22] wire _gf_T = ~stage2_final; // @[PTW.scala:283:25, :357:107, :698:27] wire _gf_T_1 = stage2 & _gf_T; // @[PTW.scala:282:19, :698:{24,27}] wire _gf_T_2 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_3 = pte_x & _gf_T_2; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_4 = pte_r | _gf_T_3; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_5 = pte_v & _gf_T_4; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_6 = _gf_T_5 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_7 = _gf_T_6 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _gf_T_8 = _gf_T_7 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _gf_T_9 = ~_gf_T_8; // @[PTW.scala:143:33, :698:44] wire _gf_T_10 = _gf_T_1 & _gf_T_9; // @[PTW.scala:698:{24,41,44}] wire _gf_T_11 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _gf_T_12 = pte_x & _gf_T_11; // @[PTW.scala:141:{44,47}, :305:26] wire _gf_T_13 = pte_r | _gf_T_12; // @[PTW.scala:141:{38,44}, :305:26] wire _gf_T_14 = pte_v & _gf_T_13; // @[PTW.scala:141:{32,38}, :305:26] wire _gf_T_15 = _gf_T_14 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _gf_T_16 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26, :698:97] wire _gf_T_17 = _gf_T_15 & _gf_T_16; // @[PTW.scala:141:52, :698:{70,97}] wire _gf_T_18 = _gf_T_17 & invalid_gpa; // @[PTW.scala:314:32, :698:{70,105}] wire gf = _gf_T_10 | _gf_T_18; // @[PTW.scala:698:{41,55,105}] wire ae = pte_v & invalid_paddr; // @[PTW.scala:305:26, :313:9, :699:22] wire _pf_T = |pte_reserved_for_future; // @[PTW.scala:139:92, :305:26, :700:49] wire pf = pte_v & _pf_T; // @[PTW.scala:305:26, :700:{22,49}] wire _success_T = ~ae; // @[PTW.scala:699:22, :701:30] wire _success_T_1 = pte_v & _success_T; // @[PTW.scala:305:26, :701:{27,30}] wire _success_T_2 = ~pf; // @[PTW.scala:700:22, :701:37] wire _success_T_3 = _success_T_1 & _success_T_2; // @[PTW.scala:701:{27,34,37}] wire _success_T_4 = ~gf; // @[PTW.scala:698:55, :701:44] wire success = _success_T_3 & _success_T_4; // @[PTW.scala:701:{34,41,44}] wire _T_168 = do_both_stages & ~stage2_final & success; // @[PTW.scala:283:25, :288:38, :357:107, :701:41, :703:{28,45}] assign do_switch = mem_resp_valid & (traverse ? do_both_stages & ~stage2 : _T_168 & ~stage2); // @[PTW.scala:282:19, :288:38, :292:31, :306:38, :317:64, :581:30, :691:25, :694:21, :695:{28,40}, :703:{28,45,57}, :704:23, :709:21] wire _l2_refill_T_1 = success & _l2_refill_T; // @[PTW.scala:701:41, :713:{30,39}] wire _l2_refill_T_2 = ~r_req_need_gpa; // @[PTW.scala:270:18, :713:61] wire _l2_refill_T_3 = _l2_refill_T_1 & _l2_refill_T_2; // @[PTW.scala:713:{30,58,61}] wire _l2_refill_T_4 = ~r_req_vstage1; // @[PTW.scala:270:18, :566:32, :714:12] wire _l2_refill_T_5 = ~r_req_stage2; // @[PTW.scala:270:18, :358:65, :714:30] wire _l2_refill_T_6 = _l2_refill_T_4 & _l2_refill_T_5; // @[PTW.scala:714:{12,27,30}] wire _l2_refill_T_8 = do_both_stages & _l2_refill_T_7; // @[PTW.scala:288:38, :715:{27,40}] wire _l2_refill_T_9 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_10 = pte_x & _l2_refill_T_9; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_11 = pte_r | _l2_refill_T_10; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_12 = pte_v & _l2_refill_T_11; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_13 = _l2_refill_T_12 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_14 = _l2_refill_T_13 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _l2_refill_T_15 = _l2_refill_T_14 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _l2_refill_T_16 = _l2_refill_T_15 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _l2_refill_T_17 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _l2_refill_T_18 = pte_x & _l2_refill_T_17; // @[PTW.scala:141:{44,47}, :305:26] wire _l2_refill_T_19 = pte_r | _l2_refill_T_18; // @[PTW.scala:141:{38,44}, :305:26] wire _l2_refill_T_20 = pte_v & _l2_refill_T_19; // @[PTW.scala:141:{32,38}, :305:26] wire _l2_refill_T_21 = _l2_refill_T_20 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _l2_refill_T_22 = _l2_refill_T_21 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _l2_refill_T_23 = _l2_refill_T_22 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _l2_refill_T_24 = _l2_refill_T_16 & _l2_refill_T_23; // @[PTW.scala:145:33, :147:33, :155:41] wire _l2_refill_T_25 = _l2_refill_T_8 & _l2_refill_T_24; // @[PTW.scala:155:41, :715:{27,59}] wire _l2_refill_T_26 = _l2_refill_T_6 | _l2_refill_T_25; // @[PTW.scala:714:{27,44}, :715:59] wire _l2_refill_T_27 = _l2_refill_T_3 & _l2_refill_T_26; // @[PTW.scala:713:{58,77}, :714:44] wire _GEN_23 = traverse | _T_168; // @[PTW.scala:317:64, :398:26, :694:21, :703:{28,45,57}, :713:19] wire _resp_ae_ptw_T = ~(count[1]); // @[PTW.scala:259:18, :310:21, :317:73, :725:36] wire _resp_ae_ptw_T_1 = ae & _resp_ae_ptw_T; // @[PTW.scala:699:22, :725:{27,36}] wire _resp_ae_ptw_T_2 = ~pte_r; // @[PTW.scala:139:36, :305:26] wire _resp_ae_ptw_T_3 = pte_v & _resp_ae_ptw_T_2; // @[PTW.scala:139:{33,36}, :305:26] wire _resp_ae_ptw_T_4 = ~pte_w; // @[PTW.scala:139:42, :305:26] wire _resp_ae_ptw_T_5 = _resp_ae_ptw_T_3 & _resp_ae_ptw_T_4; // @[PTW.scala:139:{33,39,42}] wire _resp_ae_ptw_T_6 = ~pte_x; // @[PTW.scala:139:48, :305:26] wire _resp_ae_ptw_T_7 = _resp_ae_ptw_T_5 & _resp_ae_ptw_T_6; // @[PTW.scala:139:{39,45,48}] wire _resp_ae_ptw_T_8 = ~pte_d; // @[PTW.scala:139:54, :305:26] wire _resp_ae_ptw_T_9 = _resp_ae_ptw_T_7 & _resp_ae_ptw_T_8; // @[PTW.scala:139:{45,51,54}] wire _resp_ae_ptw_T_10 = ~pte_a; // @[PTW.scala:139:60, :305:26] wire _resp_ae_ptw_T_11 = _resp_ae_ptw_T_9 & _resp_ae_ptw_T_10; // @[PTW.scala:139:{51,57,60}] wire _resp_ae_ptw_T_12 = ~pte_u; // @[PTW.scala:139:66, :305:26] wire _resp_ae_ptw_T_13 = _resp_ae_ptw_T_11 & _resp_ae_ptw_T_12; // @[PTW.scala:139:{57,63,66}] wire _resp_ae_ptw_T_14 = ~(|pte_reserved_for_future); // @[PTW.scala:139:92, :305:26] wire _resp_ae_ptw_T_15 = _resp_ae_ptw_T_13 & _resp_ae_ptw_T_14; // @[PTW.scala:139:{63,69,92}] wire _resp_ae_ptw_T_16 = _resp_ae_ptw_T_1 & _resp_ae_ptw_T_15; // @[PTW.scala:139:69, :725:{27,53}] wire _resp_ae_final_T = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_ae_final_T_1 = pte_x & _resp_ae_final_T; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_ae_final_T_2 = pte_r | _resp_ae_final_T_1; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_ae_final_T_3 = pte_v & _resp_ae_final_T_2; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_ae_final_T_4 = _resp_ae_final_T_3 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_ae_final_T_5 = ae & _resp_ae_final_T_4; // @[PTW.scala:141:52, :699:22, :726:29] wire _resp_pf_T = ~stage2; // @[PTW.scala:282:19, :306:38, :727:26] wire _resp_pf_T_1 = pf & _resp_pf_T; // @[PTW.scala:700:22, :727:{23,26}] wire _resp_gf_T_3 = pf & stage2; // @[PTW.scala:282:19, :700:22, :728:30] wire _resp_gf_T_4 = gf | _resp_gf_T_3; // @[PTW.scala:698:55, :728:{23,30}] wire _resp_hr_T = ~stage2; // @[PTW.scala:282:19, :306:38, :729:20] wire _resp_hr_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :729:32] wire _resp_hr_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :729:39] wire _resp_hr_T_3 = _resp_hr_T_1 & _resp_hr_T_2; // @[PTW.scala:729:{32,36,39}] wire _resp_hr_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hr_T_5 = pte_x & _resp_hr_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hr_T_6 = pte_r | _resp_hr_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hr_T_7 = pte_v & _resp_hr_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hr_T_8 = _resp_hr_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hr_T_9 = _resp_hr_T_8 & pte_r; // @[PTW.scala:141:52, :149:35, :305:26] wire _resp_hr_T_10 = _resp_hr_T_9 & pte_u; // @[PTW.scala:143:33, :149:35, :305:26] wire _resp_hr_T_11 = _resp_hr_T_3 & _resp_hr_T_10; // @[PTW.scala:143:33, :729:{36,43}] wire _resp_hr_T_12 = _resp_hr_T | _resp_hr_T_11; // @[PTW.scala:729:{20,28,43}] wire _resp_hw_T = ~stage2; // @[PTW.scala:282:19, :306:38, :730:20] wire _resp_hw_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :730:32] wire _resp_hw_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :730:39] wire _resp_hw_T_3 = _resp_hw_T_1 & _resp_hw_T_2; // @[PTW.scala:730:{32,36,39}] wire _resp_hw_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hw_T_5 = pte_x & _resp_hw_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hw_T_6 = pte_r | _resp_hw_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hw_T_7 = pte_v & _resp_hw_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hw_T_8 = _resp_hw_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hw_T_9 = _resp_hw_T_8 & pte_w; // @[PTW.scala:141:52, :151:35, :305:26] wire _resp_hw_T_10 = _resp_hw_T_9 & pte_d; // @[PTW.scala:151:{35,40}, :305:26] wire _resp_hw_T_11 = _resp_hw_T_10 & pte_u; // @[PTW.scala:145:33, :151:40, :305:26] wire _resp_hw_T_12 = _resp_hw_T_3 & _resp_hw_T_11; // @[PTW.scala:145:33, :730:{36,43}] wire _resp_hw_T_13 = _resp_hw_T | _resp_hw_T_12; // @[PTW.scala:730:{20,28,43}] wire _resp_hx_T = ~stage2; // @[PTW.scala:282:19, :306:38, :731:20] wire _resp_hx_T_1 = ~pf; // @[PTW.scala:700:22, :701:37, :731:32] wire _resp_hx_T_2 = ~gf; // @[PTW.scala:698:55, :701:44, :731:39] wire _resp_hx_T_3 = _resp_hx_T_1 & _resp_hx_T_2; // @[PTW.scala:731:{32,36,39}] wire _resp_hx_T_4 = ~pte_w; // @[PTW.scala:139:42, :141:47, :305:26] wire _resp_hx_T_5 = pte_x & _resp_hx_T_4; // @[PTW.scala:141:{44,47}, :305:26] wire _resp_hx_T_6 = pte_r | _resp_hx_T_5; // @[PTW.scala:141:{38,44}, :305:26] wire _resp_hx_T_7 = pte_v & _resp_hx_T_6; // @[PTW.scala:141:{32,38}, :305:26] wire _resp_hx_T_8 = _resp_hx_T_7 & pte_a; // @[PTW.scala:141:{32,52}, :305:26] wire _resp_hx_T_9 = _resp_hx_T_8 & pte_x; // @[PTW.scala:141:52, :153:35, :305:26] wire _resp_hx_T_10 = _resp_hx_T_9 & pte_u; // @[PTW.scala:147:33, :153:35, :305:26] wire _resp_hx_T_11 = _resp_hx_T_3 & _resp_hx_T_10; // @[PTW.scala:147:33, :731:{36,43}] wire _resp_hx_T_12 = _resp_hx_T | _resp_hx_T_11; // @[PTW.scala:731:{20,28,43}]
Generate the Verilog code corresponding to this FIRRTL code module Directory : input clock : Clock input reset : Reset output io : { flip write : { flip ready : UInt<1>, valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, flip read : { valid : UInt<1>, bits : { set : UInt<11>, tag : UInt<9>}}, result : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>, hit : UInt<1>, way : UInt<4>}}, ready : UInt<1>} smem cc_dir : UInt<13>[16] [2048] inst write_q of Queue1_DirectoryWrite connect write_q.clock, clock connect write_q.reset, reset connect write_q.io.enq.valid, io.write.valid connect write_q.io.enq.bits.data.tag, io.write.bits.data.tag connect write_q.io.enq.bits.data.clients, io.write.bits.data.clients connect write_q.io.enq.bits.data.state, io.write.bits.data.state connect write_q.io.enq.bits.data.dirty, io.write.bits.data.dirty connect write_q.io.enq.bits.way, io.write.bits.way connect write_q.io.enq.bits.set, io.write.bits.set connect io.write.ready, write_q.io.enq.ready regreset wipeCount : UInt<12>, clock, reset, UInt<12>(0h0) regreset wipeOff : UInt<1>, clock, reset, UInt<1>(0h1) connect wipeOff, UInt<1>(0h0) node wipeDone = bits(wipeCount, 11, 11) node wipeSet = bits(wipeCount, 10, 0) connect io.ready, wipeDone node _T = eq(wipeDone, UInt<1>(0h0)) node _T_1 = eq(wipeOff, UInt<1>(0h0)) node _T_2 = and(_T, _T_1) when _T_2 : node _wipeCount_T = add(wipeCount, UInt<1>(0h1)) node _wipeCount_T_1 = tail(_wipeCount_T, 1) connect wipeCount, _wipeCount_T_1 node _T_3 = eq(io.read.valid, UInt<1>(0h0)) node _T_4 = or(wipeDone, _T_3) node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(_T_4, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:86 assert (wipeDone || !io.read.valid)\n") : printf assert(clock, _T_4, UInt<1>(0h1), "") : assert node _wen_T = eq(wipeDone, UInt<1>(0h0)) node _wen_T_1 = eq(wipeOff, UInt<1>(0h0)) node _wen_T_2 = and(_wen_T, _wen_T_1) node wen = or(_wen_T_2, write_q.io.deq.valid) node _T_8 = eq(io.read.valid, UInt<1>(0h0)) node _T_9 = or(_T_8, wipeDone) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:91 assert (!io.read.valid || wipeDone)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 node _q_io_deq_ready_T = eq(io.read.valid, UInt<1>(0h0)) connect write_q.io.deq.ready, _q_io_deq_ready_T node _T_13 = eq(io.read.valid, UInt<1>(0h0)) node _T_14 = and(_T_13, wen) when _T_14 : node _T_15 = mux(wipeDone, write_q.io.deq.bits.set, wipeSet) node lo = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_16 = cat(hi, lo) node _T_17 = mux(wipeDone, _T_16, UInt<1>(0h0)) node lo_1 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_1 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_18 = cat(hi_1, lo_1) node _T_19 = mux(wipeDone, _T_18, UInt<1>(0h0)) node lo_2 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_2 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_20 = cat(hi_2, lo_2) node _T_21 = mux(wipeDone, _T_20, UInt<1>(0h0)) node lo_3 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_3 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_22 = cat(hi_3, lo_3) node _T_23 = mux(wipeDone, _T_22, UInt<1>(0h0)) node lo_4 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_4 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_24 = cat(hi_4, lo_4) node _T_25 = mux(wipeDone, _T_24, UInt<1>(0h0)) node lo_5 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_5 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_26 = cat(hi_5, lo_5) node _T_27 = mux(wipeDone, _T_26, UInt<1>(0h0)) node lo_6 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_6 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_28 = cat(hi_6, lo_6) node _T_29 = mux(wipeDone, _T_28, UInt<1>(0h0)) node lo_7 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_7 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_30 = cat(hi_7, lo_7) node _T_31 = mux(wipeDone, _T_30, UInt<1>(0h0)) node lo_8 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_8 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_32 = cat(hi_8, lo_8) node _T_33 = mux(wipeDone, _T_32, UInt<1>(0h0)) node lo_9 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_9 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_34 = cat(hi_9, lo_9) node _T_35 = mux(wipeDone, _T_34, UInt<1>(0h0)) node lo_10 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_10 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_36 = cat(hi_10, lo_10) node _T_37 = mux(wipeDone, _T_36, UInt<1>(0h0)) node lo_11 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_11 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_38 = cat(hi_11, lo_11) node _T_39 = mux(wipeDone, _T_38, UInt<1>(0h0)) node lo_12 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_12 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_40 = cat(hi_12, lo_12) node _T_41 = mux(wipeDone, _T_40, UInt<1>(0h0)) node lo_13 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_13 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_42 = cat(hi_13, lo_13) node _T_43 = mux(wipeDone, _T_42, UInt<1>(0h0)) node lo_14 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_14 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_44 = cat(hi_14, lo_14) node _T_45 = mux(wipeDone, _T_44, UInt<1>(0h0)) node lo_15 = cat(write_q.io.deq.bits.data.clients, write_q.io.deq.bits.data.tag) node hi_15 = cat(write_q.io.deq.bits.data.dirty, write_q.io.deq.bits.data.state) node _T_46 = cat(hi_15, lo_15) node _T_47 = mux(wipeDone, _T_46, UInt<1>(0h0)) wire _WIRE : UInt<13>[16] connect _WIRE[0], _T_17 connect _WIRE[1], _T_19 connect _WIRE[2], _T_21 connect _WIRE[3], _T_23 connect _WIRE[4], _T_25 connect _WIRE[5], _T_27 connect _WIRE[6], _T_29 connect _WIRE[7], _T_31 connect _WIRE[8], _T_33 connect _WIRE[9], _T_35 connect _WIRE[10], _T_37 connect _WIRE[11], _T_39 connect _WIRE[12], _T_41 connect _WIRE[13], _T_43 connect _WIRE[14], _T_45 connect _WIRE[15], _T_47 node shiftAmount = bits(write_q.io.deq.bits.way, 3, 0) node _T_48 = dshl(UInt<1>(0h1), shiftAmount) node _T_49 = bits(_T_48, 15, 0) node _T_50 = bits(_T_49, 0, 0) node _T_51 = bits(_T_49, 1, 1) node _T_52 = bits(_T_49, 2, 2) node _T_53 = bits(_T_49, 3, 3) node _T_54 = bits(_T_49, 4, 4) node _T_55 = bits(_T_49, 5, 5) node _T_56 = bits(_T_49, 6, 6) node _T_57 = bits(_T_49, 7, 7) node _T_58 = bits(_T_49, 8, 8) node _T_59 = bits(_T_49, 9, 9) node _T_60 = bits(_T_49, 10, 10) node _T_61 = bits(_T_49, 11, 11) node _T_62 = bits(_T_49, 12, 12) node _T_63 = bits(_T_49, 13, 13) node _T_64 = bits(_T_49, 14, 14) node _T_65 = bits(_T_49, 15, 15) node _T_66 = eq(wipeDone, UInt<1>(0h0)) node _T_67 = or(_T_50, _T_66) node _T_68 = eq(wipeDone, UInt<1>(0h0)) node _T_69 = or(_T_51, _T_68) node _T_70 = eq(wipeDone, UInt<1>(0h0)) node _T_71 = or(_T_52, _T_70) node _T_72 = eq(wipeDone, UInt<1>(0h0)) node _T_73 = or(_T_53, _T_72) node _T_74 = eq(wipeDone, UInt<1>(0h0)) node _T_75 = or(_T_54, _T_74) node _T_76 = eq(wipeDone, UInt<1>(0h0)) node _T_77 = or(_T_55, _T_76) node _T_78 = eq(wipeDone, UInt<1>(0h0)) node _T_79 = or(_T_56, _T_78) node _T_80 = eq(wipeDone, UInt<1>(0h0)) node _T_81 = or(_T_57, _T_80) node _T_82 = eq(wipeDone, UInt<1>(0h0)) node _T_83 = or(_T_58, _T_82) node _T_84 = eq(wipeDone, UInt<1>(0h0)) node _T_85 = or(_T_59, _T_84) node _T_86 = eq(wipeDone, UInt<1>(0h0)) node _T_87 = or(_T_60, _T_86) node _T_88 = eq(wipeDone, UInt<1>(0h0)) node _T_89 = or(_T_61, _T_88) node _T_90 = eq(wipeDone, UInt<1>(0h0)) node _T_91 = or(_T_62, _T_90) node _T_92 = eq(wipeDone, UInt<1>(0h0)) node _T_93 = or(_T_63, _T_92) node _T_94 = eq(wipeDone, UInt<1>(0h0)) node _T_95 = or(_T_64, _T_94) node _T_96 = eq(wipeDone, UInt<1>(0h0)) node _T_97 = or(_T_65, _T_96) write mport MPORT = cc_dir[_T_15], clock when _T_67 : connect MPORT[0], _WIRE[0] when _T_69 : connect MPORT[1], _WIRE[1] when _T_71 : connect MPORT[2], _WIRE[2] when _T_73 : connect MPORT[3], _WIRE[3] when _T_75 : connect MPORT[4], _WIRE[4] when _T_77 : connect MPORT[5], _WIRE[5] when _T_79 : connect MPORT[6], _WIRE[6] when _T_81 : connect MPORT[7], _WIRE[7] when _T_83 : connect MPORT[8], _WIRE[8] when _T_85 : connect MPORT[9], _WIRE[9] when _T_87 : connect MPORT[10], _WIRE[10] when _T_89 : connect MPORT[11], _WIRE[11] when _T_91 : connect MPORT[12], _WIRE[12] when _T_93 : connect MPORT[13], _WIRE[13] when _T_95 : connect MPORT[14], _WIRE[14] when _T_97 : connect MPORT[15], _WIRE[15] regreset ren1 : UInt<1>, clock, reset, UInt<1>(0h0) connect ren1, ren1 connect ren1, io.read.valid node _bypass_T = and(ren1, write_q.io.deq.valid) wire _regout_WIRE : UInt<11> invalidate _regout_WIRE when io.read.valid : connect _regout_WIRE, io.read.bits.set read mport regout = cc_dir[_regout_WIRE], clock reg tag : UInt<9>, clock when io.read.valid : connect tag, io.read.bits.tag reg set : UInt<11>, clock when io.read.valid : connect set, io.read.bits.set inst victimLFSR_prng of MaxPeriodFibonacciLFSR connect victimLFSR_prng.clock, clock connect victimLFSR_prng.reset, reset connect victimLFSR_prng.io.seed.valid, UInt<1>(0h0) invalidate victimLFSR_prng.io.seed.bits[0] invalidate victimLFSR_prng.io.seed.bits[1] invalidate victimLFSR_prng.io.seed.bits[2] invalidate victimLFSR_prng.io.seed.bits[3] invalidate victimLFSR_prng.io.seed.bits[4] invalidate victimLFSR_prng.io.seed.bits[5] invalidate victimLFSR_prng.io.seed.bits[6] invalidate victimLFSR_prng.io.seed.bits[7] invalidate victimLFSR_prng.io.seed.bits[8] invalidate victimLFSR_prng.io.seed.bits[9] invalidate victimLFSR_prng.io.seed.bits[10] invalidate victimLFSR_prng.io.seed.bits[11] invalidate victimLFSR_prng.io.seed.bits[12] invalidate victimLFSR_prng.io.seed.bits[13] invalidate victimLFSR_prng.io.seed.bits[14] invalidate victimLFSR_prng.io.seed.bits[15] connect victimLFSR_prng.io.increment, io.read.valid node victimLFSR_lo_lo_lo = cat(victimLFSR_prng.io.out[1], victimLFSR_prng.io.out[0]) node victimLFSR_lo_lo_hi = cat(victimLFSR_prng.io.out[3], victimLFSR_prng.io.out[2]) node victimLFSR_lo_lo = cat(victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo) node victimLFSR_lo_hi_lo = cat(victimLFSR_prng.io.out[5], victimLFSR_prng.io.out[4]) node victimLFSR_lo_hi_hi = cat(victimLFSR_prng.io.out[7], victimLFSR_prng.io.out[6]) node victimLFSR_lo_hi = cat(victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo) node victimLFSR_lo = cat(victimLFSR_lo_hi, victimLFSR_lo_lo) node victimLFSR_hi_lo_lo = cat(victimLFSR_prng.io.out[9], victimLFSR_prng.io.out[8]) node victimLFSR_hi_lo_hi = cat(victimLFSR_prng.io.out[11], victimLFSR_prng.io.out[10]) node victimLFSR_hi_lo = cat(victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo) node victimLFSR_hi_hi_lo = cat(victimLFSR_prng.io.out[13], victimLFSR_prng.io.out[12]) node victimLFSR_hi_hi_hi = cat(victimLFSR_prng.io.out[15], victimLFSR_prng.io.out[14]) node victimLFSR_hi_hi = cat(victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo) node victimLFSR_hi = cat(victimLFSR_hi_hi, victimLFSR_hi_lo) node _victimLFSR_T = cat(victimLFSR_hi, victimLFSR_lo) node victimLFSR = bits(_victimLFSR_T, 9, 0) node _victimLTE_T = leq(UInt<1>(0h0), victimLFSR) node _victimLTE_T_1 = leq(UInt<7>(0h40), victimLFSR) node _victimLTE_T_2 = leq(UInt<8>(0h80), victimLFSR) node _victimLTE_T_3 = leq(UInt<8>(0hc0), victimLFSR) node _victimLTE_T_4 = leq(UInt<9>(0h100), victimLFSR) node _victimLTE_T_5 = leq(UInt<9>(0h140), victimLFSR) node _victimLTE_T_6 = leq(UInt<9>(0h180), victimLFSR) node _victimLTE_T_7 = leq(UInt<9>(0h1c0), victimLFSR) node _victimLTE_T_8 = leq(UInt<10>(0h200), victimLFSR) node _victimLTE_T_9 = leq(UInt<10>(0h240), victimLFSR) node _victimLTE_T_10 = leq(UInt<10>(0h280), victimLFSR) node _victimLTE_T_11 = leq(UInt<10>(0h2c0), victimLFSR) node _victimLTE_T_12 = leq(UInt<10>(0h300), victimLFSR) node _victimLTE_T_13 = leq(UInt<10>(0h340), victimLFSR) node _victimLTE_T_14 = leq(UInt<10>(0h380), victimLFSR) node _victimLTE_T_15 = leq(UInt<10>(0h3c0), victimLFSR) node victimLTE_lo_lo_lo = cat(_victimLTE_T_1, _victimLTE_T) node victimLTE_lo_lo_hi = cat(_victimLTE_T_3, _victimLTE_T_2) node victimLTE_lo_lo = cat(victimLTE_lo_lo_hi, victimLTE_lo_lo_lo) node victimLTE_lo_hi_lo = cat(_victimLTE_T_5, _victimLTE_T_4) node victimLTE_lo_hi_hi = cat(_victimLTE_T_7, _victimLTE_T_6) node victimLTE_lo_hi = cat(victimLTE_lo_hi_hi, victimLTE_lo_hi_lo) node victimLTE_lo = cat(victimLTE_lo_hi, victimLTE_lo_lo) node victimLTE_hi_lo_lo = cat(_victimLTE_T_9, _victimLTE_T_8) node victimLTE_hi_lo_hi = cat(_victimLTE_T_11, _victimLTE_T_10) node victimLTE_hi_lo = cat(victimLTE_hi_lo_hi, victimLTE_hi_lo_lo) node victimLTE_hi_hi_lo = cat(_victimLTE_T_13, _victimLTE_T_12) node victimLTE_hi_hi_hi = cat(_victimLTE_T_15, _victimLTE_T_14) node victimLTE_hi_hi = cat(victimLTE_hi_hi_hi, victimLTE_hi_hi_lo) node victimLTE_hi = cat(victimLTE_hi_hi, victimLTE_hi_lo) node victimLTE = cat(victimLTE_hi, victimLTE_lo) node _victimSimp_T = bits(victimLTE, 15, 1) node victimSimp_hi = cat(UInt<1>(0h0), _victimSimp_T) node victimSimp = cat(victimSimp_hi, UInt<1>(0h1)) node _victimWayOH_T = bits(victimSimp, 15, 0) node _victimWayOH_T_1 = shr(victimSimp, 1) node _victimWayOH_T_2 = not(_victimWayOH_T_1) node victimWayOH = and(_victimWayOH_T, _victimWayOH_T_2) node victimWay_hi = bits(victimWayOH, 15, 8) node victimWay_lo = bits(victimWayOH, 7, 0) node _victimWay_T = orr(victimWay_hi) node _victimWay_T_1 = or(victimWay_hi, victimWay_lo) node victimWay_hi_1 = bits(_victimWay_T_1, 7, 4) node victimWay_lo_1 = bits(_victimWay_T_1, 3, 0) node _victimWay_T_2 = orr(victimWay_hi_1) node _victimWay_T_3 = or(victimWay_hi_1, victimWay_lo_1) node victimWay_hi_2 = bits(_victimWay_T_3, 3, 2) node victimWay_lo_2 = bits(_victimWay_T_3, 1, 0) node _victimWay_T_4 = orr(victimWay_hi_2) node _victimWay_T_5 = or(victimWay_hi_2, victimWay_lo_2) node _victimWay_T_6 = bits(_victimWay_T_5, 1, 1) node _victimWay_T_7 = cat(_victimWay_T_4, _victimWay_T_6) node _victimWay_T_8 = cat(_victimWay_T_2, _victimWay_T_7) node victimWay = cat(_victimWay_T, _victimWay_T_8) node _T_98 = eq(ren1, UInt<1>(0h0)) node _T_99 = bits(victimLTE, 0, 0) node _T_100 = eq(_T_99, UInt<1>(0h1)) node _T_101 = or(_T_98, _T_100) node _T_102 = asUInt(reset) node _T_103 = eq(_T_102, UInt<1>(0h0)) when _T_103 : node _T_104 = eq(_T_101, UInt<1>(0h0)) when _T_104 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:121 assert (!ren2 || victimLTE(0) === 1.U)\n") : printf_2 assert(clock, _T_101, UInt<1>(0h1), "") : assert_2 node _T_105 = eq(ren1, UInt<1>(0h0)) node _T_106 = shr(victimSimp, 1) node _T_107 = not(victimSimp) node _T_108 = and(_T_106, _T_107) node _T_109 = eq(_T_108, UInt<1>(0h0)) node _T_110 = or(_T_105, _T_109) node _T_111 = asUInt(reset) node _T_112 = eq(_T_111, UInt<1>(0h0)) when _T_112 : node _T_113 = eq(_T_110, UInt<1>(0h0)) when _T_113 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:122 assert (!ren2 || ((victimSimp >> 1) & ~victimSimp) === 0.U) // monotone\n") : printf_3 assert(clock, _T_110, UInt<1>(0h1), "") : assert_3 node _T_114 = eq(ren1, UInt<1>(0h0)) node _T_115 = bits(victimWayOH, 0, 0) node _T_116 = bits(victimWayOH, 1, 1) node _T_117 = bits(victimWayOH, 2, 2) node _T_118 = bits(victimWayOH, 3, 3) node _T_119 = bits(victimWayOH, 4, 4) node _T_120 = bits(victimWayOH, 5, 5) node _T_121 = bits(victimWayOH, 6, 6) node _T_122 = bits(victimWayOH, 7, 7) node _T_123 = bits(victimWayOH, 8, 8) node _T_124 = bits(victimWayOH, 9, 9) node _T_125 = bits(victimWayOH, 10, 10) node _T_126 = bits(victimWayOH, 11, 11) node _T_127 = bits(victimWayOH, 12, 12) node _T_128 = bits(victimWayOH, 13, 13) node _T_129 = bits(victimWayOH, 14, 14) node _T_130 = bits(victimWayOH, 15, 15) node _T_131 = add(_T_115, _T_116) node _T_132 = bits(_T_131, 1, 0) node _T_133 = add(_T_117, _T_118) node _T_134 = bits(_T_133, 1, 0) node _T_135 = add(_T_132, _T_134) node _T_136 = bits(_T_135, 2, 0) node _T_137 = add(_T_119, _T_120) node _T_138 = bits(_T_137, 1, 0) node _T_139 = add(_T_121, _T_122) node _T_140 = bits(_T_139, 1, 0) node _T_141 = add(_T_138, _T_140) node _T_142 = bits(_T_141, 2, 0) node _T_143 = add(_T_136, _T_142) node _T_144 = bits(_T_143, 3, 0) node _T_145 = add(_T_123, _T_124) node _T_146 = bits(_T_145, 1, 0) node _T_147 = add(_T_125, _T_126) node _T_148 = bits(_T_147, 1, 0) node _T_149 = add(_T_146, _T_148) node _T_150 = bits(_T_149, 2, 0) node _T_151 = add(_T_127, _T_128) node _T_152 = bits(_T_151, 1, 0) node _T_153 = add(_T_129, _T_130) node _T_154 = bits(_T_153, 1, 0) node _T_155 = add(_T_152, _T_154) node _T_156 = bits(_T_155, 2, 0) node _T_157 = add(_T_150, _T_156) node _T_158 = bits(_T_157, 3, 0) node _T_159 = add(_T_144, _T_158) node _T_160 = bits(_T_159, 4, 0) node _T_161 = eq(_T_160, UInt<1>(0h1)) node _T_162 = or(_T_114, _T_161) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Directory.scala:123 assert (!ren2 || PopCount(victimWayOH) === 1.U)\n") : printf_4 assert(clock, _T_162, UInt<1>(0h1), "") : assert_4 node _setQuash_T = eq(write_q.io.deq.bits.set, set) node setQuash = and(write_q.io.deq.valid, _setQuash_T) node tagMatch = eq(write_q.io.deq.bits.data.tag, tag) node wayMatch = eq(write_q.io.deq.bits.way, victimWay) wire ways_0 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE : UInt<13> connect _ways_WIRE, regout[0] node _ways_T = bits(_ways_WIRE, 8, 0) connect ways_0.tag, _ways_T node _ways_T_1 = bits(_ways_WIRE, 9, 9) connect ways_0.clients, _ways_T_1 node _ways_T_2 = bits(_ways_WIRE, 11, 10) connect ways_0.state, _ways_T_2 node _ways_T_3 = bits(_ways_WIRE, 12, 12) connect ways_0.dirty, _ways_T_3 wire ways_1 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_1 : UInt<13> connect _ways_WIRE_1, regout[1] node _ways_T_4 = bits(_ways_WIRE_1, 8, 0) connect ways_1.tag, _ways_T_4 node _ways_T_5 = bits(_ways_WIRE_1, 9, 9) connect ways_1.clients, _ways_T_5 node _ways_T_6 = bits(_ways_WIRE_1, 11, 10) connect ways_1.state, _ways_T_6 node _ways_T_7 = bits(_ways_WIRE_1, 12, 12) connect ways_1.dirty, _ways_T_7 wire ways_2 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_2 : UInt<13> connect _ways_WIRE_2, regout[2] node _ways_T_8 = bits(_ways_WIRE_2, 8, 0) connect ways_2.tag, _ways_T_8 node _ways_T_9 = bits(_ways_WIRE_2, 9, 9) connect ways_2.clients, _ways_T_9 node _ways_T_10 = bits(_ways_WIRE_2, 11, 10) connect ways_2.state, _ways_T_10 node _ways_T_11 = bits(_ways_WIRE_2, 12, 12) connect ways_2.dirty, _ways_T_11 wire ways_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_3 : UInt<13> connect _ways_WIRE_3, regout[3] node _ways_T_12 = bits(_ways_WIRE_3, 8, 0) connect ways_3.tag, _ways_T_12 node _ways_T_13 = bits(_ways_WIRE_3, 9, 9) connect ways_3.clients, _ways_T_13 node _ways_T_14 = bits(_ways_WIRE_3, 11, 10) connect ways_3.state, _ways_T_14 node _ways_T_15 = bits(_ways_WIRE_3, 12, 12) connect ways_3.dirty, _ways_T_15 wire ways_4 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_4 : UInt<13> connect _ways_WIRE_4, regout[4] node _ways_T_16 = bits(_ways_WIRE_4, 8, 0) connect ways_4.tag, _ways_T_16 node _ways_T_17 = bits(_ways_WIRE_4, 9, 9) connect ways_4.clients, _ways_T_17 node _ways_T_18 = bits(_ways_WIRE_4, 11, 10) connect ways_4.state, _ways_T_18 node _ways_T_19 = bits(_ways_WIRE_4, 12, 12) connect ways_4.dirty, _ways_T_19 wire ways_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_5 : UInt<13> connect _ways_WIRE_5, regout[5] node _ways_T_20 = bits(_ways_WIRE_5, 8, 0) connect ways_5.tag, _ways_T_20 node _ways_T_21 = bits(_ways_WIRE_5, 9, 9) connect ways_5.clients, _ways_T_21 node _ways_T_22 = bits(_ways_WIRE_5, 11, 10) connect ways_5.state, _ways_T_22 node _ways_T_23 = bits(_ways_WIRE_5, 12, 12) connect ways_5.dirty, _ways_T_23 wire ways_6 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_6 : UInt<13> connect _ways_WIRE_6, regout[6] node _ways_T_24 = bits(_ways_WIRE_6, 8, 0) connect ways_6.tag, _ways_T_24 node _ways_T_25 = bits(_ways_WIRE_6, 9, 9) connect ways_6.clients, _ways_T_25 node _ways_T_26 = bits(_ways_WIRE_6, 11, 10) connect ways_6.state, _ways_T_26 node _ways_T_27 = bits(_ways_WIRE_6, 12, 12) connect ways_6.dirty, _ways_T_27 wire ways_7 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_7 : UInt<13> connect _ways_WIRE_7, regout[7] node _ways_T_28 = bits(_ways_WIRE_7, 8, 0) connect ways_7.tag, _ways_T_28 node _ways_T_29 = bits(_ways_WIRE_7, 9, 9) connect ways_7.clients, _ways_T_29 node _ways_T_30 = bits(_ways_WIRE_7, 11, 10) connect ways_7.state, _ways_T_30 node _ways_T_31 = bits(_ways_WIRE_7, 12, 12) connect ways_7.dirty, _ways_T_31 wire ways_8 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_8 : UInt<13> connect _ways_WIRE_8, regout[8] node _ways_T_32 = bits(_ways_WIRE_8, 8, 0) connect ways_8.tag, _ways_T_32 node _ways_T_33 = bits(_ways_WIRE_8, 9, 9) connect ways_8.clients, _ways_T_33 node _ways_T_34 = bits(_ways_WIRE_8, 11, 10) connect ways_8.state, _ways_T_34 node _ways_T_35 = bits(_ways_WIRE_8, 12, 12) connect ways_8.dirty, _ways_T_35 wire ways_9 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_9 : UInt<13> connect _ways_WIRE_9, regout[9] node _ways_T_36 = bits(_ways_WIRE_9, 8, 0) connect ways_9.tag, _ways_T_36 node _ways_T_37 = bits(_ways_WIRE_9, 9, 9) connect ways_9.clients, _ways_T_37 node _ways_T_38 = bits(_ways_WIRE_9, 11, 10) connect ways_9.state, _ways_T_38 node _ways_T_39 = bits(_ways_WIRE_9, 12, 12) connect ways_9.dirty, _ways_T_39 wire ways_10 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_10 : UInt<13> connect _ways_WIRE_10, regout[10] node _ways_T_40 = bits(_ways_WIRE_10, 8, 0) connect ways_10.tag, _ways_T_40 node _ways_T_41 = bits(_ways_WIRE_10, 9, 9) connect ways_10.clients, _ways_T_41 node _ways_T_42 = bits(_ways_WIRE_10, 11, 10) connect ways_10.state, _ways_T_42 node _ways_T_43 = bits(_ways_WIRE_10, 12, 12) connect ways_10.dirty, _ways_T_43 wire ways_11 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_11 : UInt<13> connect _ways_WIRE_11, regout[11] node _ways_T_44 = bits(_ways_WIRE_11, 8, 0) connect ways_11.tag, _ways_T_44 node _ways_T_45 = bits(_ways_WIRE_11, 9, 9) connect ways_11.clients, _ways_T_45 node _ways_T_46 = bits(_ways_WIRE_11, 11, 10) connect ways_11.state, _ways_T_46 node _ways_T_47 = bits(_ways_WIRE_11, 12, 12) connect ways_11.dirty, _ways_T_47 wire ways_12 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_12 : UInt<13> connect _ways_WIRE_12, regout[12] node _ways_T_48 = bits(_ways_WIRE_12, 8, 0) connect ways_12.tag, _ways_T_48 node _ways_T_49 = bits(_ways_WIRE_12, 9, 9) connect ways_12.clients, _ways_T_49 node _ways_T_50 = bits(_ways_WIRE_12, 11, 10) connect ways_12.state, _ways_T_50 node _ways_T_51 = bits(_ways_WIRE_12, 12, 12) connect ways_12.dirty, _ways_T_51 wire ways_13 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_13 : UInt<13> connect _ways_WIRE_13, regout[13] node _ways_T_52 = bits(_ways_WIRE_13, 8, 0) connect ways_13.tag, _ways_T_52 node _ways_T_53 = bits(_ways_WIRE_13, 9, 9) connect ways_13.clients, _ways_T_53 node _ways_T_54 = bits(_ways_WIRE_13, 11, 10) connect ways_13.state, _ways_T_54 node _ways_T_55 = bits(_ways_WIRE_13, 12, 12) connect ways_13.dirty, _ways_T_55 wire ways_14 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_14 : UInt<13> connect _ways_WIRE_14, regout[14] node _ways_T_56 = bits(_ways_WIRE_14, 8, 0) connect ways_14.tag, _ways_T_56 node _ways_T_57 = bits(_ways_WIRE_14, 9, 9) connect ways_14.clients, _ways_T_57 node _ways_T_58 = bits(_ways_WIRE_14, 11, 10) connect ways_14.state, _ways_T_58 node _ways_T_59 = bits(_ways_WIRE_14, 12, 12) connect ways_14.dirty, _ways_T_59 wire ways_15 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} wire _ways_WIRE_15 : UInt<13> connect _ways_WIRE_15, regout[15] node _ways_T_60 = bits(_ways_WIRE_15, 8, 0) connect ways_15.tag, _ways_T_60 node _ways_T_61 = bits(_ways_WIRE_15, 9, 9) connect ways_15.clients, _ways_T_61 node _ways_T_62 = bits(_ways_WIRE_15, 11, 10) connect ways_15.state, _ways_T_62 node _ways_T_63 = bits(_ways_WIRE_15, 12, 12) connect ways_15.dirty, _ways_T_63 node _hits_T = eq(ways_0.tag, tag) node _hits_T_1 = neq(ways_0.state, UInt<2>(0h0)) node _hits_T_2 = and(_hits_T, _hits_T_1) node _hits_T_3 = eq(setQuash, UInt<1>(0h0)) node _hits_T_4 = neq(UInt<1>(0h0), write_q.io.deq.bits.way) node _hits_T_5 = or(_hits_T_3, _hits_T_4) node _hits_T_6 = and(_hits_T_2, _hits_T_5) node _hits_T_7 = eq(ways_1.tag, tag) node _hits_T_8 = neq(ways_1.state, UInt<2>(0h0)) node _hits_T_9 = and(_hits_T_7, _hits_T_8) node _hits_T_10 = eq(setQuash, UInt<1>(0h0)) node _hits_T_11 = neq(UInt<1>(0h1), write_q.io.deq.bits.way) node _hits_T_12 = or(_hits_T_10, _hits_T_11) node _hits_T_13 = and(_hits_T_9, _hits_T_12) node _hits_T_14 = eq(ways_2.tag, tag) node _hits_T_15 = neq(ways_2.state, UInt<2>(0h0)) node _hits_T_16 = and(_hits_T_14, _hits_T_15) node _hits_T_17 = eq(setQuash, UInt<1>(0h0)) node _hits_T_18 = neq(UInt<2>(0h2), write_q.io.deq.bits.way) node _hits_T_19 = or(_hits_T_17, _hits_T_18) node _hits_T_20 = and(_hits_T_16, _hits_T_19) node _hits_T_21 = eq(ways_3.tag, tag) node _hits_T_22 = neq(ways_3.state, UInt<2>(0h0)) node _hits_T_23 = and(_hits_T_21, _hits_T_22) node _hits_T_24 = eq(setQuash, UInt<1>(0h0)) node _hits_T_25 = neq(UInt<2>(0h3), write_q.io.deq.bits.way) node _hits_T_26 = or(_hits_T_24, _hits_T_25) node _hits_T_27 = and(_hits_T_23, _hits_T_26) node _hits_T_28 = eq(ways_4.tag, tag) node _hits_T_29 = neq(ways_4.state, UInt<2>(0h0)) node _hits_T_30 = and(_hits_T_28, _hits_T_29) node _hits_T_31 = eq(setQuash, UInt<1>(0h0)) node _hits_T_32 = neq(UInt<3>(0h4), write_q.io.deq.bits.way) node _hits_T_33 = or(_hits_T_31, _hits_T_32) node _hits_T_34 = and(_hits_T_30, _hits_T_33) node _hits_T_35 = eq(ways_5.tag, tag) node _hits_T_36 = neq(ways_5.state, UInt<2>(0h0)) node _hits_T_37 = and(_hits_T_35, _hits_T_36) node _hits_T_38 = eq(setQuash, UInt<1>(0h0)) node _hits_T_39 = neq(UInt<3>(0h5), write_q.io.deq.bits.way) node _hits_T_40 = or(_hits_T_38, _hits_T_39) node _hits_T_41 = and(_hits_T_37, _hits_T_40) node _hits_T_42 = eq(ways_6.tag, tag) node _hits_T_43 = neq(ways_6.state, UInt<2>(0h0)) node _hits_T_44 = and(_hits_T_42, _hits_T_43) node _hits_T_45 = eq(setQuash, UInt<1>(0h0)) node _hits_T_46 = neq(UInt<3>(0h6), write_q.io.deq.bits.way) node _hits_T_47 = or(_hits_T_45, _hits_T_46) node _hits_T_48 = and(_hits_T_44, _hits_T_47) node _hits_T_49 = eq(ways_7.tag, tag) node _hits_T_50 = neq(ways_7.state, UInt<2>(0h0)) node _hits_T_51 = and(_hits_T_49, _hits_T_50) node _hits_T_52 = eq(setQuash, UInt<1>(0h0)) node _hits_T_53 = neq(UInt<3>(0h7), write_q.io.deq.bits.way) node _hits_T_54 = or(_hits_T_52, _hits_T_53) node _hits_T_55 = and(_hits_T_51, _hits_T_54) node _hits_T_56 = eq(ways_8.tag, tag) node _hits_T_57 = neq(ways_8.state, UInt<2>(0h0)) node _hits_T_58 = and(_hits_T_56, _hits_T_57) node _hits_T_59 = eq(setQuash, UInt<1>(0h0)) node _hits_T_60 = neq(UInt<4>(0h8), write_q.io.deq.bits.way) node _hits_T_61 = or(_hits_T_59, _hits_T_60) node _hits_T_62 = and(_hits_T_58, _hits_T_61) node _hits_T_63 = eq(ways_9.tag, tag) node _hits_T_64 = neq(ways_9.state, UInt<2>(0h0)) node _hits_T_65 = and(_hits_T_63, _hits_T_64) node _hits_T_66 = eq(setQuash, UInt<1>(0h0)) node _hits_T_67 = neq(UInt<4>(0h9), write_q.io.deq.bits.way) node _hits_T_68 = or(_hits_T_66, _hits_T_67) node _hits_T_69 = and(_hits_T_65, _hits_T_68) node _hits_T_70 = eq(ways_10.tag, tag) node _hits_T_71 = neq(ways_10.state, UInt<2>(0h0)) node _hits_T_72 = and(_hits_T_70, _hits_T_71) node _hits_T_73 = eq(setQuash, UInt<1>(0h0)) node _hits_T_74 = neq(UInt<4>(0ha), write_q.io.deq.bits.way) node _hits_T_75 = or(_hits_T_73, _hits_T_74) node _hits_T_76 = and(_hits_T_72, _hits_T_75) node _hits_T_77 = eq(ways_11.tag, tag) node _hits_T_78 = neq(ways_11.state, UInt<2>(0h0)) node _hits_T_79 = and(_hits_T_77, _hits_T_78) node _hits_T_80 = eq(setQuash, UInt<1>(0h0)) node _hits_T_81 = neq(UInt<4>(0hb), write_q.io.deq.bits.way) node _hits_T_82 = or(_hits_T_80, _hits_T_81) node _hits_T_83 = and(_hits_T_79, _hits_T_82) node _hits_T_84 = eq(ways_12.tag, tag) node _hits_T_85 = neq(ways_12.state, UInt<2>(0h0)) node _hits_T_86 = and(_hits_T_84, _hits_T_85) node _hits_T_87 = eq(setQuash, UInt<1>(0h0)) node _hits_T_88 = neq(UInt<4>(0hc), write_q.io.deq.bits.way) node _hits_T_89 = or(_hits_T_87, _hits_T_88) node _hits_T_90 = and(_hits_T_86, _hits_T_89) node _hits_T_91 = eq(ways_13.tag, tag) node _hits_T_92 = neq(ways_13.state, UInt<2>(0h0)) node _hits_T_93 = and(_hits_T_91, _hits_T_92) node _hits_T_94 = eq(setQuash, UInt<1>(0h0)) node _hits_T_95 = neq(UInt<4>(0hd), write_q.io.deq.bits.way) node _hits_T_96 = or(_hits_T_94, _hits_T_95) node _hits_T_97 = and(_hits_T_93, _hits_T_96) node _hits_T_98 = eq(ways_14.tag, tag) node _hits_T_99 = neq(ways_14.state, UInt<2>(0h0)) node _hits_T_100 = and(_hits_T_98, _hits_T_99) node _hits_T_101 = eq(setQuash, UInt<1>(0h0)) node _hits_T_102 = neq(UInt<4>(0he), write_q.io.deq.bits.way) node _hits_T_103 = or(_hits_T_101, _hits_T_102) node _hits_T_104 = and(_hits_T_100, _hits_T_103) node _hits_T_105 = eq(ways_15.tag, tag) node _hits_T_106 = neq(ways_15.state, UInt<2>(0h0)) node _hits_T_107 = and(_hits_T_105, _hits_T_106) node _hits_T_108 = eq(setQuash, UInt<1>(0h0)) node _hits_T_109 = neq(UInt<4>(0hf), write_q.io.deq.bits.way) node _hits_T_110 = or(_hits_T_108, _hits_T_109) node _hits_T_111 = and(_hits_T_107, _hits_T_110) node hits_lo_lo_lo = cat(_hits_T_13, _hits_T_6) node hits_lo_lo_hi = cat(_hits_T_27, _hits_T_20) node hits_lo_lo = cat(hits_lo_lo_hi, hits_lo_lo_lo) node hits_lo_hi_lo = cat(_hits_T_41, _hits_T_34) node hits_lo_hi_hi = cat(_hits_T_55, _hits_T_48) node hits_lo_hi = cat(hits_lo_hi_hi, hits_lo_hi_lo) node hits_lo = cat(hits_lo_hi, hits_lo_lo) node hits_hi_lo_lo = cat(_hits_T_69, _hits_T_62) node hits_hi_lo_hi = cat(_hits_T_83, _hits_T_76) node hits_hi_lo = cat(hits_hi_lo_hi, hits_hi_lo_lo) node hits_hi_hi_lo = cat(_hits_T_97, _hits_T_90) node hits_hi_hi_hi = cat(_hits_T_111, _hits_T_104) node hits_hi_hi = cat(hits_hi_hi_hi, hits_hi_hi_lo) node hits_hi = cat(hits_hi_hi, hits_hi_lo) node hits = cat(hits_hi, hits_lo) node hit = orr(hits) connect io.result.valid, ren1 node _view__T = bits(hits, 0, 0) node _view__T_1 = bits(hits, 1, 1) node _view__T_2 = bits(hits, 2, 2) node _view__T_3 = bits(hits, 3, 3) node _view__T_4 = bits(hits, 4, 4) node _view__T_5 = bits(hits, 5, 5) node _view__T_6 = bits(hits, 6, 6) node _view__T_7 = bits(hits, 7, 7) node _view__T_8 = bits(hits, 8, 8) node _view__T_9 = bits(hits, 9, 9) node _view__T_10 = bits(hits, 10, 10) node _view__T_11 = bits(hits, 11, 11) node _view__T_12 = bits(hits, 12, 12) node _view__T_13 = bits(hits, 13, 13) node _view__T_14 = bits(hits, 14, 14) node _view__T_15 = bits(hits, 15, 15) wire _view__WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_16 = mux(_view__T, ways_0.tag, UInt<1>(0h0)) node _view__T_17 = mux(_view__T_1, ways_1.tag, UInt<1>(0h0)) node _view__T_18 = mux(_view__T_2, ways_2.tag, UInt<1>(0h0)) node _view__T_19 = mux(_view__T_3, ways_3.tag, UInt<1>(0h0)) node _view__T_20 = mux(_view__T_4, ways_4.tag, UInt<1>(0h0)) node _view__T_21 = mux(_view__T_5, ways_5.tag, UInt<1>(0h0)) node _view__T_22 = mux(_view__T_6, ways_6.tag, UInt<1>(0h0)) node _view__T_23 = mux(_view__T_7, ways_7.tag, UInt<1>(0h0)) node _view__T_24 = mux(_view__T_8, ways_8.tag, UInt<1>(0h0)) node _view__T_25 = mux(_view__T_9, ways_9.tag, UInt<1>(0h0)) node _view__T_26 = mux(_view__T_10, ways_10.tag, UInt<1>(0h0)) node _view__T_27 = mux(_view__T_11, ways_11.tag, UInt<1>(0h0)) node _view__T_28 = mux(_view__T_12, ways_12.tag, UInt<1>(0h0)) node _view__T_29 = mux(_view__T_13, ways_13.tag, UInt<1>(0h0)) node _view__T_30 = mux(_view__T_14, ways_14.tag, UInt<1>(0h0)) node _view__T_31 = mux(_view__T_15, ways_15.tag, UInt<1>(0h0)) node _view__T_32 = or(_view__T_16, _view__T_17) node _view__T_33 = or(_view__T_32, _view__T_18) node _view__T_34 = or(_view__T_33, _view__T_19) node _view__T_35 = or(_view__T_34, _view__T_20) node _view__T_36 = or(_view__T_35, _view__T_21) node _view__T_37 = or(_view__T_36, _view__T_22) node _view__T_38 = or(_view__T_37, _view__T_23) node _view__T_39 = or(_view__T_38, _view__T_24) node _view__T_40 = or(_view__T_39, _view__T_25) node _view__T_41 = or(_view__T_40, _view__T_26) node _view__T_42 = or(_view__T_41, _view__T_27) node _view__T_43 = or(_view__T_42, _view__T_28) node _view__T_44 = or(_view__T_43, _view__T_29) node _view__T_45 = or(_view__T_44, _view__T_30) node _view__T_46 = or(_view__T_45, _view__T_31) wire _view__WIRE_1 : UInt<9> connect _view__WIRE_1, _view__T_46 connect _view__WIRE.tag, _view__WIRE_1 node _view__T_47 = mux(_view__T, ways_0.clients, UInt<1>(0h0)) node _view__T_48 = mux(_view__T_1, ways_1.clients, UInt<1>(0h0)) node _view__T_49 = mux(_view__T_2, ways_2.clients, UInt<1>(0h0)) node _view__T_50 = mux(_view__T_3, ways_3.clients, UInt<1>(0h0)) node _view__T_51 = mux(_view__T_4, ways_4.clients, UInt<1>(0h0)) node _view__T_52 = mux(_view__T_5, ways_5.clients, UInt<1>(0h0)) node _view__T_53 = mux(_view__T_6, ways_6.clients, UInt<1>(0h0)) node _view__T_54 = mux(_view__T_7, ways_7.clients, UInt<1>(0h0)) node _view__T_55 = mux(_view__T_8, ways_8.clients, UInt<1>(0h0)) node _view__T_56 = mux(_view__T_9, ways_9.clients, UInt<1>(0h0)) node _view__T_57 = mux(_view__T_10, ways_10.clients, UInt<1>(0h0)) node _view__T_58 = mux(_view__T_11, ways_11.clients, UInt<1>(0h0)) node _view__T_59 = mux(_view__T_12, ways_12.clients, UInt<1>(0h0)) node _view__T_60 = mux(_view__T_13, ways_13.clients, UInt<1>(0h0)) node _view__T_61 = mux(_view__T_14, ways_14.clients, UInt<1>(0h0)) node _view__T_62 = mux(_view__T_15, ways_15.clients, UInt<1>(0h0)) node _view__T_63 = or(_view__T_47, _view__T_48) node _view__T_64 = or(_view__T_63, _view__T_49) node _view__T_65 = or(_view__T_64, _view__T_50) node _view__T_66 = or(_view__T_65, _view__T_51) node _view__T_67 = or(_view__T_66, _view__T_52) node _view__T_68 = or(_view__T_67, _view__T_53) node _view__T_69 = or(_view__T_68, _view__T_54) node _view__T_70 = or(_view__T_69, _view__T_55) node _view__T_71 = or(_view__T_70, _view__T_56) node _view__T_72 = or(_view__T_71, _view__T_57) node _view__T_73 = or(_view__T_72, _view__T_58) node _view__T_74 = or(_view__T_73, _view__T_59) node _view__T_75 = or(_view__T_74, _view__T_60) node _view__T_76 = or(_view__T_75, _view__T_61) node _view__T_77 = or(_view__T_76, _view__T_62) wire _view__WIRE_2 : UInt<1> connect _view__WIRE_2, _view__T_77 connect _view__WIRE.clients, _view__WIRE_2 node _view__T_78 = mux(_view__T, ways_0.state, UInt<1>(0h0)) node _view__T_79 = mux(_view__T_1, ways_1.state, UInt<1>(0h0)) node _view__T_80 = mux(_view__T_2, ways_2.state, UInt<1>(0h0)) node _view__T_81 = mux(_view__T_3, ways_3.state, UInt<1>(0h0)) node _view__T_82 = mux(_view__T_4, ways_4.state, UInt<1>(0h0)) node _view__T_83 = mux(_view__T_5, ways_5.state, UInt<1>(0h0)) node _view__T_84 = mux(_view__T_6, ways_6.state, UInt<1>(0h0)) node _view__T_85 = mux(_view__T_7, ways_7.state, UInt<1>(0h0)) node _view__T_86 = mux(_view__T_8, ways_8.state, UInt<1>(0h0)) node _view__T_87 = mux(_view__T_9, ways_9.state, UInt<1>(0h0)) node _view__T_88 = mux(_view__T_10, ways_10.state, UInt<1>(0h0)) node _view__T_89 = mux(_view__T_11, ways_11.state, UInt<1>(0h0)) node _view__T_90 = mux(_view__T_12, ways_12.state, UInt<1>(0h0)) node _view__T_91 = mux(_view__T_13, ways_13.state, UInt<1>(0h0)) node _view__T_92 = mux(_view__T_14, ways_14.state, UInt<1>(0h0)) node _view__T_93 = mux(_view__T_15, ways_15.state, UInt<1>(0h0)) node _view__T_94 = or(_view__T_78, _view__T_79) node _view__T_95 = or(_view__T_94, _view__T_80) node _view__T_96 = or(_view__T_95, _view__T_81) node _view__T_97 = or(_view__T_96, _view__T_82) node _view__T_98 = or(_view__T_97, _view__T_83) node _view__T_99 = or(_view__T_98, _view__T_84) node _view__T_100 = or(_view__T_99, _view__T_85) node _view__T_101 = or(_view__T_100, _view__T_86) node _view__T_102 = or(_view__T_101, _view__T_87) node _view__T_103 = or(_view__T_102, _view__T_88) node _view__T_104 = or(_view__T_103, _view__T_89) node _view__T_105 = or(_view__T_104, _view__T_90) node _view__T_106 = or(_view__T_105, _view__T_91) node _view__T_107 = or(_view__T_106, _view__T_92) node _view__T_108 = or(_view__T_107, _view__T_93) wire _view__WIRE_3 : UInt<2> connect _view__WIRE_3, _view__T_108 connect _view__WIRE.state, _view__WIRE_3 node _view__T_109 = mux(_view__T, ways_0.dirty, UInt<1>(0h0)) node _view__T_110 = mux(_view__T_1, ways_1.dirty, UInt<1>(0h0)) node _view__T_111 = mux(_view__T_2, ways_2.dirty, UInt<1>(0h0)) node _view__T_112 = mux(_view__T_3, ways_3.dirty, UInt<1>(0h0)) node _view__T_113 = mux(_view__T_4, ways_4.dirty, UInt<1>(0h0)) node _view__T_114 = mux(_view__T_5, ways_5.dirty, UInt<1>(0h0)) node _view__T_115 = mux(_view__T_6, ways_6.dirty, UInt<1>(0h0)) node _view__T_116 = mux(_view__T_7, ways_7.dirty, UInt<1>(0h0)) node _view__T_117 = mux(_view__T_8, ways_8.dirty, UInt<1>(0h0)) node _view__T_118 = mux(_view__T_9, ways_9.dirty, UInt<1>(0h0)) node _view__T_119 = mux(_view__T_10, ways_10.dirty, UInt<1>(0h0)) node _view__T_120 = mux(_view__T_11, ways_11.dirty, UInt<1>(0h0)) node _view__T_121 = mux(_view__T_12, ways_12.dirty, UInt<1>(0h0)) node _view__T_122 = mux(_view__T_13, ways_13.dirty, UInt<1>(0h0)) node _view__T_123 = mux(_view__T_14, ways_14.dirty, UInt<1>(0h0)) node _view__T_124 = mux(_view__T_15, ways_15.dirty, UInt<1>(0h0)) node _view__T_125 = or(_view__T_109, _view__T_110) node _view__T_126 = or(_view__T_125, _view__T_111) node _view__T_127 = or(_view__T_126, _view__T_112) node _view__T_128 = or(_view__T_127, _view__T_113) node _view__T_129 = or(_view__T_128, _view__T_114) node _view__T_130 = or(_view__T_129, _view__T_115) node _view__T_131 = or(_view__T_130, _view__T_116) node _view__T_132 = or(_view__T_131, _view__T_117) node _view__T_133 = or(_view__T_132, _view__T_118) node _view__T_134 = or(_view__T_133, _view__T_119) node _view__T_135 = or(_view__T_134, _view__T_120) node _view__T_136 = or(_view__T_135, _view__T_121) node _view__T_137 = or(_view__T_136, _view__T_122) node _view__T_138 = or(_view__T_137, _view__T_123) node _view__T_139 = or(_view__T_138, _view__T_124) wire _view__WIRE_4 : UInt<1> connect _view__WIRE_4, _view__T_139 connect _view__WIRE.dirty, _view__WIRE_4 node _view__T_140 = or(tagMatch, wayMatch) node _view__T_141 = and(setQuash, _view__T_140) node _view__T_142 = bits(victimWayOH, 0, 0) node _view__T_143 = bits(victimWayOH, 1, 1) node _view__T_144 = bits(victimWayOH, 2, 2) node _view__T_145 = bits(victimWayOH, 3, 3) node _view__T_146 = bits(victimWayOH, 4, 4) node _view__T_147 = bits(victimWayOH, 5, 5) node _view__T_148 = bits(victimWayOH, 6, 6) node _view__T_149 = bits(victimWayOH, 7, 7) node _view__T_150 = bits(victimWayOH, 8, 8) node _view__T_151 = bits(victimWayOH, 9, 9) node _view__T_152 = bits(victimWayOH, 10, 10) node _view__T_153 = bits(victimWayOH, 11, 11) node _view__T_154 = bits(victimWayOH, 12, 12) node _view__T_155 = bits(victimWayOH, 13, 13) node _view__T_156 = bits(victimWayOH, 14, 14) node _view__T_157 = bits(victimWayOH, 15, 15) wire _view__WIRE_5 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _view__T_158 = mux(_view__T_142, ways_0.tag, UInt<1>(0h0)) node _view__T_159 = mux(_view__T_143, ways_1.tag, UInt<1>(0h0)) node _view__T_160 = mux(_view__T_144, ways_2.tag, UInt<1>(0h0)) node _view__T_161 = mux(_view__T_145, ways_3.tag, UInt<1>(0h0)) node _view__T_162 = mux(_view__T_146, ways_4.tag, UInt<1>(0h0)) node _view__T_163 = mux(_view__T_147, ways_5.tag, UInt<1>(0h0)) node _view__T_164 = mux(_view__T_148, ways_6.tag, UInt<1>(0h0)) node _view__T_165 = mux(_view__T_149, ways_7.tag, UInt<1>(0h0)) node _view__T_166 = mux(_view__T_150, ways_8.tag, UInt<1>(0h0)) node _view__T_167 = mux(_view__T_151, ways_9.tag, UInt<1>(0h0)) node _view__T_168 = mux(_view__T_152, ways_10.tag, UInt<1>(0h0)) node _view__T_169 = mux(_view__T_153, ways_11.tag, UInt<1>(0h0)) node _view__T_170 = mux(_view__T_154, ways_12.tag, UInt<1>(0h0)) node _view__T_171 = mux(_view__T_155, ways_13.tag, UInt<1>(0h0)) node _view__T_172 = mux(_view__T_156, ways_14.tag, UInt<1>(0h0)) node _view__T_173 = mux(_view__T_157, ways_15.tag, UInt<1>(0h0)) node _view__T_174 = or(_view__T_158, _view__T_159) node _view__T_175 = or(_view__T_174, _view__T_160) node _view__T_176 = or(_view__T_175, _view__T_161) node _view__T_177 = or(_view__T_176, _view__T_162) node _view__T_178 = or(_view__T_177, _view__T_163) node _view__T_179 = or(_view__T_178, _view__T_164) node _view__T_180 = or(_view__T_179, _view__T_165) node _view__T_181 = or(_view__T_180, _view__T_166) node _view__T_182 = or(_view__T_181, _view__T_167) node _view__T_183 = or(_view__T_182, _view__T_168) node _view__T_184 = or(_view__T_183, _view__T_169) node _view__T_185 = or(_view__T_184, _view__T_170) node _view__T_186 = or(_view__T_185, _view__T_171) node _view__T_187 = or(_view__T_186, _view__T_172) node _view__T_188 = or(_view__T_187, _view__T_173) wire _view__WIRE_6 : UInt<9> connect _view__WIRE_6, _view__T_188 connect _view__WIRE_5.tag, _view__WIRE_6 node _view__T_189 = mux(_view__T_142, ways_0.clients, UInt<1>(0h0)) node _view__T_190 = mux(_view__T_143, ways_1.clients, UInt<1>(0h0)) node _view__T_191 = mux(_view__T_144, ways_2.clients, UInt<1>(0h0)) node _view__T_192 = mux(_view__T_145, ways_3.clients, UInt<1>(0h0)) node _view__T_193 = mux(_view__T_146, ways_4.clients, UInt<1>(0h0)) node _view__T_194 = mux(_view__T_147, ways_5.clients, UInt<1>(0h0)) node _view__T_195 = mux(_view__T_148, ways_6.clients, UInt<1>(0h0)) node _view__T_196 = mux(_view__T_149, ways_7.clients, UInt<1>(0h0)) node _view__T_197 = mux(_view__T_150, ways_8.clients, UInt<1>(0h0)) node _view__T_198 = mux(_view__T_151, ways_9.clients, UInt<1>(0h0)) node _view__T_199 = mux(_view__T_152, ways_10.clients, UInt<1>(0h0)) node _view__T_200 = mux(_view__T_153, ways_11.clients, UInt<1>(0h0)) node _view__T_201 = mux(_view__T_154, ways_12.clients, UInt<1>(0h0)) node _view__T_202 = mux(_view__T_155, ways_13.clients, UInt<1>(0h0)) node _view__T_203 = mux(_view__T_156, ways_14.clients, UInt<1>(0h0)) node _view__T_204 = mux(_view__T_157, ways_15.clients, UInt<1>(0h0)) node _view__T_205 = or(_view__T_189, _view__T_190) node _view__T_206 = or(_view__T_205, _view__T_191) node _view__T_207 = or(_view__T_206, _view__T_192) node _view__T_208 = or(_view__T_207, _view__T_193) node _view__T_209 = or(_view__T_208, _view__T_194) node _view__T_210 = or(_view__T_209, _view__T_195) node _view__T_211 = or(_view__T_210, _view__T_196) node _view__T_212 = or(_view__T_211, _view__T_197) node _view__T_213 = or(_view__T_212, _view__T_198) node _view__T_214 = or(_view__T_213, _view__T_199) node _view__T_215 = or(_view__T_214, _view__T_200) node _view__T_216 = or(_view__T_215, _view__T_201) node _view__T_217 = or(_view__T_216, _view__T_202) node _view__T_218 = or(_view__T_217, _view__T_203) node _view__T_219 = or(_view__T_218, _view__T_204) wire _view__WIRE_7 : UInt<1> connect _view__WIRE_7, _view__T_219 connect _view__WIRE_5.clients, _view__WIRE_7 node _view__T_220 = mux(_view__T_142, ways_0.state, UInt<1>(0h0)) node _view__T_221 = mux(_view__T_143, ways_1.state, UInt<1>(0h0)) node _view__T_222 = mux(_view__T_144, ways_2.state, UInt<1>(0h0)) node _view__T_223 = mux(_view__T_145, ways_3.state, UInt<1>(0h0)) node _view__T_224 = mux(_view__T_146, ways_4.state, UInt<1>(0h0)) node _view__T_225 = mux(_view__T_147, ways_5.state, UInt<1>(0h0)) node _view__T_226 = mux(_view__T_148, ways_6.state, UInt<1>(0h0)) node _view__T_227 = mux(_view__T_149, ways_7.state, UInt<1>(0h0)) node _view__T_228 = mux(_view__T_150, ways_8.state, UInt<1>(0h0)) node _view__T_229 = mux(_view__T_151, ways_9.state, UInt<1>(0h0)) node _view__T_230 = mux(_view__T_152, ways_10.state, UInt<1>(0h0)) node _view__T_231 = mux(_view__T_153, ways_11.state, UInt<1>(0h0)) node _view__T_232 = mux(_view__T_154, ways_12.state, UInt<1>(0h0)) node _view__T_233 = mux(_view__T_155, ways_13.state, UInt<1>(0h0)) node _view__T_234 = mux(_view__T_156, ways_14.state, UInt<1>(0h0)) node _view__T_235 = mux(_view__T_157, ways_15.state, UInt<1>(0h0)) node _view__T_236 = or(_view__T_220, _view__T_221) node _view__T_237 = or(_view__T_236, _view__T_222) node _view__T_238 = or(_view__T_237, _view__T_223) node _view__T_239 = or(_view__T_238, _view__T_224) node _view__T_240 = or(_view__T_239, _view__T_225) node _view__T_241 = or(_view__T_240, _view__T_226) node _view__T_242 = or(_view__T_241, _view__T_227) node _view__T_243 = or(_view__T_242, _view__T_228) node _view__T_244 = or(_view__T_243, _view__T_229) node _view__T_245 = or(_view__T_244, _view__T_230) node _view__T_246 = or(_view__T_245, _view__T_231) node _view__T_247 = or(_view__T_246, _view__T_232) node _view__T_248 = or(_view__T_247, _view__T_233) node _view__T_249 = or(_view__T_248, _view__T_234) node _view__T_250 = or(_view__T_249, _view__T_235) wire _view__WIRE_8 : UInt<2> connect _view__WIRE_8, _view__T_250 connect _view__WIRE_5.state, _view__WIRE_8 node _view__T_251 = mux(_view__T_142, ways_0.dirty, UInt<1>(0h0)) node _view__T_252 = mux(_view__T_143, ways_1.dirty, UInt<1>(0h0)) node _view__T_253 = mux(_view__T_144, ways_2.dirty, UInt<1>(0h0)) node _view__T_254 = mux(_view__T_145, ways_3.dirty, UInt<1>(0h0)) node _view__T_255 = mux(_view__T_146, ways_4.dirty, UInt<1>(0h0)) node _view__T_256 = mux(_view__T_147, ways_5.dirty, UInt<1>(0h0)) node _view__T_257 = mux(_view__T_148, ways_6.dirty, UInt<1>(0h0)) node _view__T_258 = mux(_view__T_149, ways_7.dirty, UInt<1>(0h0)) node _view__T_259 = mux(_view__T_150, ways_8.dirty, UInt<1>(0h0)) node _view__T_260 = mux(_view__T_151, ways_9.dirty, UInt<1>(0h0)) node _view__T_261 = mux(_view__T_152, ways_10.dirty, UInt<1>(0h0)) node _view__T_262 = mux(_view__T_153, ways_11.dirty, UInt<1>(0h0)) node _view__T_263 = mux(_view__T_154, ways_12.dirty, UInt<1>(0h0)) node _view__T_264 = mux(_view__T_155, ways_13.dirty, UInt<1>(0h0)) node _view__T_265 = mux(_view__T_156, ways_14.dirty, UInt<1>(0h0)) node _view__T_266 = mux(_view__T_157, ways_15.dirty, UInt<1>(0h0)) node _view__T_267 = or(_view__T_251, _view__T_252) node _view__T_268 = or(_view__T_267, _view__T_253) node _view__T_269 = or(_view__T_268, _view__T_254) node _view__T_270 = or(_view__T_269, _view__T_255) node _view__T_271 = or(_view__T_270, _view__T_256) node _view__T_272 = or(_view__T_271, _view__T_257) node _view__T_273 = or(_view__T_272, _view__T_258) node _view__T_274 = or(_view__T_273, _view__T_259) node _view__T_275 = or(_view__T_274, _view__T_260) node _view__T_276 = or(_view__T_275, _view__T_261) node _view__T_277 = or(_view__T_276, _view__T_262) node _view__T_278 = or(_view__T_277, _view__T_263) node _view__T_279 = or(_view__T_278, _view__T_264) node _view__T_280 = or(_view__T_279, _view__T_265) node _view__T_281 = or(_view__T_280, _view__T_266) wire _view__WIRE_9 : UInt<1> connect _view__WIRE_9, _view__T_281 connect _view__WIRE_5.dirty, _view__WIRE_9 node _view__T_282 = mux(_view__T_141, write_q.io.deq.bits.data, _view__WIRE_5) node _view__T_283 = mux(hit, _view__WIRE, _view__T_282) connect io.result.bits.tag, _view__T_283.tag connect io.result.bits.clients, _view__T_283.clients connect io.result.bits.state, _view__T_283.state connect io.result.bits.dirty, _view__T_283.dirty node _io_result_bits_hit_T = and(setQuash, tagMatch) node _io_result_bits_hit_T_1 = neq(write_q.io.deq.bits.data.state, UInt<2>(0h0)) node _io_result_bits_hit_T_2 = and(_io_result_bits_hit_T, _io_result_bits_hit_T_1) node _io_result_bits_hit_T_3 = or(hit, _io_result_bits_hit_T_2) connect io.result.bits.hit, _io_result_bits_hit_T_3 node io_result_bits_way_hi = bits(hits, 15, 8) node io_result_bits_way_lo = bits(hits, 7, 0) node _io_result_bits_way_T = orr(io_result_bits_way_hi) node _io_result_bits_way_T_1 = or(io_result_bits_way_hi, io_result_bits_way_lo) node io_result_bits_way_hi_1 = bits(_io_result_bits_way_T_1, 7, 4) node io_result_bits_way_lo_1 = bits(_io_result_bits_way_T_1, 3, 0) node _io_result_bits_way_T_2 = orr(io_result_bits_way_hi_1) node _io_result_bits_way_T_3 = or(io_result_bits_way_hi_1, io_result_bits_way_lo_1) node io_result_bits_way_hi_2 = bits(_io_result_bits_way_T_3, 3, 2) node io_result_bits_way_lo_2 = bits(_io_result_bits_way_T_3, 1, 0) node _io_result_bits_way_T_4 = orr(io_result_bits_way_hi_2) node _io_result_bits_way_T_5 = or(io_result_bits_way_hi_2, io_result_bits_way_lo_2) node _io_result_bits_way_T_6 = bits(_io_result_bits_way_T_5, 1, 1) node _io_result_bits_way_T_7 = cat(_io_result_bits_way_T_4, _io_result_bits_way_T_6) node _io_result_bits_way_T_8 = cat(_io_result_bits_way_T_2, _io_result_bits_way_T_7) node _io_result_bits_way_T_9 = cat(_io_result_bits_way_T, _io_result_bits_way_T_8) node _io_result_bits_way_T_10 = and(setQuash, tagMatch) node _io_result_bits_way_T_11 = mux(_io_result_bits_way_T_10, write_q.io.deq.bits.way, victimWay) node _io_result_bits_way_T_12 = mux(hit, _io_result_bits_way_T_9, _io_result_bits_way_T_11) connect io.result.bits.way, _io_result_bits_way_T_12 node _T_166 = and(ren1, setQuash) node _T_167 = and(_T_166, tagMatch) node _T_168 = and(ren1, setQuash) node _T_169 = eq(tagMatch, UInt<1>(0h0)) node _T_170 = and(_T_168, _T_169) node _T_171 = and(_T_170, wayMatch)
module Directory( // @[Directory.scala:56:7] input clock, // @[Directory.scala:56:7] input reset, // @[Directory.scala:56:7] output io_write_ready, // @[Directory.scala:58:14] input io_write_valid, // @[Directory.scala:58:14] input [10:0] io_write_bits_set, // @[Directory.scala:58:14] input [3:0] io_write_bits_way, // @[Directory.scala:58:14] input io_write_bits_data_dirty, // @[Directory.scala:58:14] input [1:0] io_write_bits_data_state, // @[Directory.scala:58:14] input io_write_bits_data_clients, // @[Directory.scala:58:14] input [8:0] io_write_bits_data_tag, // @[Directory.scala:58:14] input io_read_valid, // @[Directory.scala:58:14] input [10:0] io_read_bits_set, // @[Directory.scala:58:14] input [8:0] io_read_bits_tag, // @[Directory.scala:58:14] output io_result_bits_dirty, // @[Directory.scala:58:14] output [1:0] io_result_bits_state, // @[Directory.scala:58:14] output io_result_bits_clients, // @[Directory.scala:58:14] output [8:0] io_result_bits_tag, // @[Directory.scala:58:14] output io_result_bits_hit, // @[Directory.scala:58:14] output [3:0] io_result_bits_way, // @[Directory.scala:58:14] output io_ready // @[Directory.scala:58:14] ); wire cc_dir_MPORT_mask_15; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_14; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_13; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_12; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_11; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_10; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_9; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_8; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_7; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_6; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_5; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_4; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_3; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_2; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_1; // @[Directory.scala:100:65] wire cc_dir_MPORT_mask_0; // @[Directory.scala:100:65] wire [12:0] _T_47; // @[Directory.scala:99:44] wire [12:0] _T_45; // @[Directory.scala:99:44] wire [12:0] _T_43; // @[Directory.scala:99:44] wire [12:0] _T_41; // @[Directory.scala:99:44] wire [12:0] _T_39; // @[Directory.scala:99:44] wire [12:0] _T_37; // @[Directory.scala:99:44] wire [12:0] _T_35; // @[Directory.scala:99:44] wire [12:0] _T_33; // @[Directory.scala:99:44] wire [12:0] _T_31; // @[Directory.scala:99:44] wire [12:0] _T_29; // @[Directory.scala:99:44] wire [12:0] _T_27; // @[Directory.scala:99:44] wire [12:0] _T_25; // @[Directory.scala:99:44] wire [12:0] _T_23; // @[Directory.scala:99:44] wire [12:0] _T_21; // @[Directory.scala:99:44] wire [12:0] _T_19; // @[Directory.scala:99:44] wire [12:0] _T_17; // @[Directory.scala:99:44] wire [10:0] cc_dir_MPORT_addr; // @[Directory.scala:98:10] wire cc_dir_MPORT_en; // @[Directory.scala:96:14] wire _victimLFSR_prng_io_out_0; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_1; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_2; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_3; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_4; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_5; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_6; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_7; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_8; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_9; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_10; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_11; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_12; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_13; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_14; // @[PRNG.scala:91:22] wire _victimLFSR_prng_io_out_15; // @[PRNG.scala:91:22] wire _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [10:0] _write_q_io_deq_bits_set; // @[Decoupled.scala:362:21] wire [3:0] _write_q_io_deq_bits_way; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_dirty; // @[Decoupled.scala:362:21] wire [1:0] _write_q_io_deq_bits_data_state; // @[Decoupled.scala:362:21] wire _write_q_io_deq_bits_data_clients; // @[Decoupled.scala:362:21] wire [8:0] _write_q_io_deq_bits_data_tag; // @[Decoupled.scala:362:21] wire [207:0] _cc_dir_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire io_write_valid_0 = io_write_valid; // @[Directory.scala:56:7] wire [10:0] io_write_bits_set_0 = io_write_bits_set; // @[Directory.scala:56:7] wire [3:0] io_write_bits_way_0 = io_write_bits_way; // @[Directory.scala:56:7] wire io_write_bits_data_dirty_0 = io_write_bits_data_dirty; // @[Directory.scala:56:7] wire [1:0] io_write_bits_data_state_0 = io_write_bits_data_state; // @[Directory.scala:56:7] wire io_write_bits_data_clients_0 = io_write_bits_data_clients; // @[Directory.scala:56:7] wire [8:0] io_write_bits_data_tag_0 = io_write_bits_data_tag; // @[Directory.scala:56:7] wire io_read_valid_0 = io_read_valid; // @[Directory.scala:56:7] wire [10:0] io_read_bits_set_0 = io_read_bits_set; // @[Directory.scala:56:7] wire [8:0] io_read_bits_tag_0 = io_read_bits_tag; // @[Directory.scala:56:7] wire _victimLTE_T = 1'h1; // @[Directory.scala:117:43] wire [10:0] _regout_WIRE = io_read_bits_set_0; // @[Directory.scala:56:7, :110:41] wire _view__T_283_dirty; // @[Directory.scala:136:67] wire [1:0] _view__T_283_state; // @[Directory.scala:136:67] wire _view__T_283_clients; // @[Directory.scala:136:67] wire [8:0] _view__T_283_tag; // @[Directory.scala:136:67] wire _io_result_bits_hit_T_3; // @[Directory.scala:137:29] wire [3:0] _io_result_bits_way_T_12; // @[Directory.scala:138:28] wire wipeDone; // @[Directory.scala:81:27] wire io_write_ready_0; // @[Directory.scala:56:7] wire io_result_bits_dirty_0; // @[Directory.scala:56:7] wire [1:0] io_result_bits_state_0; // @[Directory.scala:56:7] wire io_result_bits_clients_0; // @[Directory.scala:56:7] wire [8:0] io_result_bits_tag_0; // @[Directory.scala:56:7] wire io_result_bits_hit_0; // @[Directory.scala:56:7] wire [3:0] io_result_bits_way_0; // @[Directory.scala:56:7] wire io_result_valid; // @[Directory.scala:56:7] wire io_ready_0; // @[Directory.scala:56:7] wire [12:0] _ways_WIRE = _cc_dir_RW0_rdata[12:0]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_1 = _cc_dir_RW0_rdata[25:13]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_2 = _cc_dir_RW0_rdata[38:26]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_3 = _cc_dir_RW0_rdata[51:39]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_4 = _cc_dir_RW0_rdata[64:52]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_5 = _cc_dir_RW0_rdata[77:65]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_6 = _cc_dir_RW0_rdata[90:78]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_7 = _cc_dir_RW0_rdata[103:91]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_8 = _cc_dir_RW0_rdata[116:104]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_9 = _cc_dir_RW0_rdata[129:117]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_10 = _cc_dir_RW0_rdata[142:130]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_11 = _cc_dir_RW0_rdata[155:143]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_12 = _cc_dir_RW0_rdata[168:156]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_13 = _cc_dir_RW0_rdata[181:169]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_14 = _cc_dir_RW0_rdata[194:182]; // @[DescribedSRAM.scala:17:26] wire [12:0] _ways_WIRE_15 = _cc_dir_RW0_rdata[207:195]; // @[DescribedSRAM.scala:17:26] reg [11:0] wipeCount; // @[Directory.scala:79:26] reg wipeOff; // @[Directory.scala:80:24] assign wipeDone = wipeCount[11]; // @[Directory.scala:79:26, :81:27] assign io_ready_0 = wipeDone; // @[Directory.scala:56:7, :81:27] wire [10:0] wipeSet = wipeCount[10:0]; // @[Directory.scala:79:26, :82:26] wire _wen_T_1 = ~wipeOff; // @[Directory.scala:80:24, :85:22, :90:27] wire [12:0] _wipeCount_T = {1'h0, wipeCount} + 13'h1; // @[Directory.scala:79:26, :85:57] wire [11:0] _wipeCount_T_1 = _wipeCount_T[11:0]; // @[Directory.scala:85:57] wire _wen_T = ~wipeDone; // @[Directory.scala:81:27, :85:9, :90:14] wire _wen_T_2 = _wen_T & _wen_T_1; // @[Directory.scala:90:{14,24,27}] wire wen = _wen_T_2 | _write_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _q_io_deq_ready_T = ~io_read_valid_0; // @[Directory.scala:56:7, :86:23, :95:18] assign cc_dir_MPORT_en = ~io_read_valid_0 & wen; // @[Directory.scala:56:7, :86:23, :90:37, :96:14] assign cc_dir_MPORT_addr = wipeDone ? _write_q_io_deq_bits_set : wipeSet; // @[Decoupled.scala:362:21] wire [9:0] _GEN = {_write_q_io_deq_bits_data_clients, _write_q_io_deq_bits_data_tag}; // @[Decoupled.scala:362:21] wire [9:0] lo; // @[Directory.scala:99:71] assign lo = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_1; // @[Directory.scala:99:71] assign lo_1 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_2; // @[Directory.scala:99:71] assign lo_2 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_3; // @[Directory.scala:99:71] assign lo_3 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_4; // @[Directory.scala:99:71] assign lo_4 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_5; // @[Directory.scala:99:71] assign lo_5 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_6; // @[Directory.scala:99:71] assign lo_6 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_7; // @[Directory.scala:99:71] assign lo_7 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_8; // @[Directory.scala:99:71] assign lo_8 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_9; // @[Directory.scala:99:71] assign lo_9 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_10; // @[Directory.scala:99:71] assign lo_10 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_11; // @[Directory.scala:99:71] assign lo_11 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_12; // @[Directory.scala:99:71] assign lo_12 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_13; // @[Directory.scala:99:71] assign lo_13 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_14; // @[Directory.scala:99:71] assign lo_14 = _GEN; // @[Directory.scala:99:71] wire [9:0] lo_15; // @[Directory.scala:99:71] assign lo_15 = _GEN; // @[Directory.scala:99:71] wire [2:0] _GEN_0 = {_write_q_io_deq_bits_data_dirty, _write_q_io_deq_bits_data_state}; // @[Decoupled.scala:362:21] wire [2:0] hi; // @[Directory.scala:99:71] assign hi = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_1; // @[Directory.scala:99:71] assign hi_1 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_2; // @[Directory.scala:99:71] assign hi_2 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_3; // @[Directory.scala:99:71] assign hi_3 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_4; // @[Directory.scala:99:71] assign hi_4 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_5; // @[Directory.scala:99:71] assign hi_5 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_6; // @[Directory.scala:99:71] assign hi_6 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_7; // @[Directory.scala:99:71] assign hi_7 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_8; // @[Directory.scala:99:71] assign hi_8 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_9; // @[Directory.scala:99:71] assign hi_9 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_10; // @[Directory.scala:99:71] assign hi_10 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_11; // @[Directory.scala:99:71] assign hi_11 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_12; // @[Directory.scala:99:71] assign hi_12 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_13; // @[Directory.scala:99:71] assign hi_13 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_14; // @[Directory.scala:99:71] assign hi_14 = _GEN_0; // @[Directory.scala:99:71] wire [2:0] hi_15; // @[Directory.scala:99:71] assign hi_15 = _GEN_0; // @[Directory.scala:99:71] assign _T_17 = wipeDone ? {hi, lo} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_19 = wipeDone ? {hi_1, lo_1} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_21 = wipeDone ? {hi_2, lo_2} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_23 = wipeDone ? {hi_3, lo_3} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_25 = wipeDone ? {hi_4, lo_4} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_27 = wipeDone ? {hi_5, lo_5} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_29 = wipeDone ? {hi_6, lo_6} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_31 = wipeDone ? {hi_7, lo_7} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_33 = wipeDone ? {hi_8, lo_8} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_35 = wipeDone ? {hi_9, lo_9} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_37 = wipeDone ? {hi_10, lo_10} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_39 = wipeDone ? {hi_11, lo_11} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_41 = wipeDone ? {hi_12, lo_12} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_43 = wipeDone ? {hi_13, lo_13} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_45 = wipeDone ? {hi_14, lo_14} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] assign _T_47 = wipeDone ? {hi_15, lo_15} : 13'h0; // @[Directory.scala:81:27, :99:{44,71}] wire [3:0] shiftAmount; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_0 = shiftAmount == 4'h0 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_1 = shiftAmount == 4'h1 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_2 = shiftAmount == 4'h2 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_3 = shiftAmount == 4'h3 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_4 = shiftAmount == 4'h4 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_5 = shiftAmount == 4'h5 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_6 = shiftAmount == 4'h6 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_7 = shiftAmount == 4'h7 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_8 = shiftAmount == 4'h8 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_9 = shiftAmount == 4'h9 | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_10 = shiftAmount == 4'hA | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_11 = shiftAmount == 4'hB | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_12 = shiftAmount == 4'hC | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_13 = shiftAmount == 4'hD | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_14 = shiftAmount == 4'hE | ~wipeDone; // @[OneHot.scala:64:49] assign cc_dir_MPORT_mask_15 = (&shiftAmount) | ~wipeDone; // @[OneHot.scala:64:49] reg ren1; // @[Directory.scala:103:21] assign io_result_valid = ren1; // @[Directory.scala:56:7, :103:21] wire _bypass_T = ren1 & _write_q_io_deq_valid; // @[Decoupled.scala:362:21] reg [8:0] tag; // @[Directory.scala:111:36] reg [10:0] set; // @[Directory.scala:112:36] wire [1:0] victimLFSR_lo_lo_lo = {_victimLFSR_prng_io_out_1, _victimLFSR_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_lo_hi = {_victimLFSR_prng_io_out_3, _victimLFSR_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_lo = {victimLFSR_lo_lo_hi, victimLFSR_lo_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_lo_hi_lo = {_victimLFSR_prng_io_out_5, _victimLFSR_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_lo_hi_hi = {_victimLFSR_prng_io_out_7, _victimLFSR_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_lo_hi = {victimLFSR_lo_hi_hi, victimLFSR_lo_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_lo = {victimLFSR_lo_hi, victimLFSR_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_lo_lo = {_victimLFSR_prng_io_out_9, _victimLFSR_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_lo_hi = {_victimLFSR_prng_io_out_11, _victimLFSR_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_lo = {victimLFSR_hi_lo_hi, victimLFSR_hi_lo_lo}; // @[PRNG.scala:95:17] wire [1:0] victimLFSR_hi_hi_lo = {_victimLFSR_prng_io_out_13, _victimLFSR_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17] wire [1:0] victimLFSR_hi_hi_hi = {_victimLFSR_prng_io_out_15, _victimLFSR_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17] wire [3:0] victimLFSR_hi_hi = {victimLFSR_hi_hi_hi, victimLFSR_hi_hi_lo}; // @[PRNG.scala:95:17] wire [7:0] victimLFSR_hi = {victimLFSR_hi_hi, victimLFSR_hi_lo}; // @[PRNG.scala:95:17] wire [15:0] _victimLFSR_T = {victimLFSR_hi, victimLFSR_lo}; // @[PRNG.scala:95:17] wire [9:0] victimLFSR = _victimLFSR_T[9:0]; // @[PRNG.scala:95:17] wire _victimLTE_T_1 = |(victimLFSR[9:6]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_2 = |(victimLFSR[9:7]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_3 = victimLFSR > 10'hBF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_4 = |(victimLFSR[9:8]); // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_5 = victimLFSR > 10'h13F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_6 = victimLFSR > 10'h17F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_7 = victimLFSR > 10'h1BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_8 = victimLFSR[9]; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_9 = victimLFSR > 10'h23F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_10 = victimLFSR > 10'h27F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_11 = victimLFSR > 10'h2BF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_12 = victimLFSR > 10'h2FF; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_13 = victimLFSR > 10'h33F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_14 = victimLFSR > 10'h37F; // @[Directory.scala:115:63, :117:43] wire _victimLTE_T_15 = victimLFSR > 10'h3BF; // @[Directory.scala:115:63, :117:43] wire [1:0] victimLTE_lo_lo_lo = {_victimLTE_T_1, 1'h1}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_lo_hi = {_victimLTE_T_3, _victimLTE_T_2}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_lo = {victimLTE_lo_lo_hi, victimLTE_lo_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_lo_hi_lo = {_victimLTE_T_5, _victimLTE_T_4}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_lo_hi_hi = {_victimLTE_T_7, _victimLTE_T_6}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_lo_hi = {victimLTE_lo_hi_hi, victimLTE_lo_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_lo = {victimLTE_lo_hi, victimLTE_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_lo_lo = {_victimLTE_T_9, _victimLTE_T_8}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_lo_hi = {_victimLTE_T_11, _victimLTE_T_10}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_lo = {victimLTE_hi_lo_hi, victimLTE_hi_lo_lo}; // @[Directory.scala:117:23] wire [1:0] victimLTE_hi_hi_lo = {_victimLTE_T_13, _victimLTE_T_12}; // @[Directory.scala:117:{23,43}] wire [1:0] victimLTE_hi_hi_hi = {_victimLTE_T_15, _victimLTE_T_14}; // @[Directory.scala:117:{23,43}] wire [3:0] victimLTE_hi_hi = {victimLTE_hi_hi_hi, victimLTE_hi_hi_lo}; // @[Directory.scala:117:23] wire [7:0] victimLTE_hi = {victimLTE_hi_hi, victimLTE_hi_lo}; // @[Directory.scala:117:23] wire [15:0] victimLTE = {victimLTE_hi, victimLTE_lo}; // @[Directory.scala:117:23] wire [14:0] _victimSimp_T = victimLTE[15:1]; // @[Directory.scala:117:23, :118:43] wire [15:0] victimSimp_hi = {1'h0, _victimSimp_T}; // @[Directory.scala:118:{23,43}] wire [16:0] victimSimp = {victimSimp_hi, 1'h1}; // @[Directory.scala:118:23] wire [15:0] _victimWayOH_T = victimSimp[15:0]; // @[Directory.scala:118:23, :119:31] wire [15:0] _victimWayOH_T_1 = victimSimp[16:1]; // @[Directory.scala:118:23, :119:70] wire [15:0] _victimWayOH_T_2 = ~_victimWayOH_T_1; // @[Directory.scala:119:{57,70}] wire [15:0] victimWayOH = _victimWayOH_T & _victimWayOH_T_2; // @[Directory.scala:119:{31,55,57}] wire [7:0] victimWay_hi = victimWayOH[15:8]; // @[OneHot.scala:30:18] wire [7:0] victimWay_lo = victimWayOH[7:0]; // @[OneHot.scala:31:18] wire _victimWay_T = |victimWay_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _victimWay_T_1 = victimWay_hi | victimWay_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] victimWay_hi_1 = _victimWay_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] victimWay_lo_1 = _victimWay_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_2 = |victimWay_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _victimWay_T_3 = victimWay_hi_1 | victimWay_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] victimWay_hi_2 = _victimWay_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] victimWay_lo_2 = _victimWay_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _victimWay_T_4 = |victimWay_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _victimWay_T_5 = victimWay_hi_2 | victimWay_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _victimWay_T_6 = _victimWay_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _victimWay_T_7 = {_victimWay_T_4, _victimWay_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _victimWay_T_8 = {_victimWay_T_2, _victimWay_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] victimWay = {_victimWay_T, _victimWay_T_8}; // @[OneHot.scala:32:{10,14}] wire _view__T_142 = victimWayOH[0]; // @[Mux.scala:32:36] wire _view__T_143 = victimWayOH[1]; // @[Mux.scala:32:36] wire _view__T_144 = victimWayOH[2]; // @[Mux.scala:32:36] wire _view__T_145 = victimWayOH[3]; // @[Mux.scala:32:36] wire _view__T_146 = victimWayOH[4]; // @[Mux.scala:32:36] wire _view__T_147 = victimWayOH[5]; // @[Mux.scala:32:36] wire _view__T_148 = victimWayOH[6]; // @[Mux.scala:32:36] wire _view__T_149 = victimWayOH[7]; // @[Mux.scala:32:36] wire _view__T_150 = victimWayOH[8]; // @[Mux.scala:32:36] wire _view__T_151 = victimWayOH[9]; // @[Mux.scala:32:36] wire _view__T_152 = victimWayOH[10]; // @[Mux.scala:32:36] wire _view__T_153 = victimWayOH[11]; // @[Mux.scala:32:36] wire _view__T_154 = victimWayOH[12]; // @[Mux.scala:32:36] wire _view__T_155 = victimWayOH[13]; // @[Mux.scala:32:36] wire _view__T_156 = victimWayOH[14]; // @[Mux.scala:32:36] wire _view__T_157 = victimWayOH[15]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_83 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<8>(0h80)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_4.bits.sink, UInt<7>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_166 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_167 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/rocket/Frontend.scala:394:21)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_83( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_4_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_5_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_6_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_7_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_4 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_5 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_6 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_7 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_9 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_10 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_11 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_12 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_13 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_14 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_15 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_beats1_opdata_T = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_beats1_opdata_T_1 = 1'h1; // @[Edges.scala:92:37] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire mask_sub_sub_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_sub_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_sub_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_opdata = 1'h0; // @[Edges.scala:92:28] wire a_first_beats1_opdata_1 = 1'h0; // @[Edges.scala:92:28] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] a_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] a_first_beats1_1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] a_first_count_1 = 8'h0; // @[Edges.scala:234:25] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] mask_lo = 8'hFF; // @[Misc.scala:222:10] wire [7:0] mask_hi = 8'hFF; // @[Misc.scala:222:10] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [3:0] io_in_a_bits_size = 4'h6; // @[Monitor.scala:36:7] wire [3:0] _mask_sizeOH_T = 4'h6; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_opcode = 3'h4; // @[Monitor.scala:36:7] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [15:0] io_in_a_bits_mask = 16'hFFFF; // @[Monitor.scala:36:7] wire [15:0] mask = 16'hFFFF; // @[Misc.scala:222:10] wire [127:0] io_in_a_bits_data = 128'h0; // @[Monitor.scala:36:7] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _a_opcodes_set_interm_T = 4'h8; // @[Monitor.scala:657:53] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] mask_lo_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_lo_hi = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_lo = 4'hF; // @[Misc.scala:222:10] wire [3:0] mask_hi_hi = 4'hF; // @[Misc.scala:222:10] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [3:0] _mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12] wire [3:0] _mask_sizeOH_T_2 = 4'h4; // @[OneHot.scala:65:27] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [4:0] _a_sizes_set_interm_T_1 = 5'hD; // @[Monitor.scala:658:59] wire [4:0] _a_sizes_set_interm_T = 5'hC; // @[Monitor.scala:658:51] wire [3:0] _a_opcodes_set_interm_T_1 = 4'h9; // @[Monitor.scala:657:61] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [7:0] a_first_beats1_decode = 8'h3; // @[Edges.scala:220:59] wire [7:0] a_first_beats1_decode_1 = 8'h3; // @[Edges.scala:220:59] wire [11:0] is_aligned_mask = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_2 = 12'h3F; // @[package.scala:243:46] wire [11:0] _a_first_beats1_decode_T_5 = 12'h3F; // @[package.scala:243:46] wire [11:0] _is_aligned_mask_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_1 = 12'hFC0; // @[package.scala:243:76] wire [11:0] _a_first_beats1_decode_T_4 = 12'hFC0; // @[package.scala:243:76] wire [26:0] _is_aligned_mask_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T = 27'h3FFC0; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3 = 27'h3FFC0; // @[package.scala:243:71] wire [1:0] mask_lo_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_hi = 2'h3; // @[Misc.scala:222:10] wire [3:0] mask_sizeOH = 4'h5; // @[Misc.scala:202:81] wire [1:0] mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49] wire _d_first_T = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_1 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T_2 = io_in_d_valid_0; // @[Decoupled.scala:51:35] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_2_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_3_2; // @[Misc.scala:214:27, :215:38] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_eq_4; // @[Misc.scala:214:27, :215:38] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_eq_5; // @[Misc.scala:214:27, :215:38] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_eq_6; // @[Misc.scala:214:27, :215:38] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_eq_7; // @[Misc.scala:214:27, :215:38] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_eq_8; // @[Misc.scala:214:27, :215:38] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_eq_9; // @[Misc.scala:214:27, :215:38] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_eq_10; // @[Misc.scala:214:27, :215:38] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_eq_11; // @[Misc.scala:214:27, :215:38] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_eq_12; // @[Misc.scala:214:27, :215:38] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_eq_13; // @[Misc.scala:214:27, :215:38] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_eq_14; // @[Misc.scala:214:27, :215:38] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_eq_15; // @[Misc.scala:214:27, :215:38] wire _T_1222 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1222; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1222; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T = a_first ? 8'h0 : a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [31:0] address; // @[Monitor.scala:391:22] wire [26:0] _GEN = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] _a_first_counter_T_1 = a_first_1 ? 8'h0 : a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1145 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1145; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1145; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1222 & a_first_1; // @[Decoupled.scala:51:35] assign a_opcodes_set_interm = a_set ? 4'h9 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:28] assign a_sizes_set_interm = a_set ? 5'hD : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[package.scala:243:71] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[package.scala:243:71] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_1194 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1194 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = io_in_d_valid_0 & d_first_1 & ~d_release_ack; // @[Monitor.scala:36:7, :664:34, :673:46, :674:74, :678:{25,70}] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1266 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1266 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = io_in_d_valid_0 & d_first_2 & d_release_ack_1; // @[Monitor.scala:36:7, :774:34, :783:46, :788:{25,70}] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_198 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_198( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_13 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node _sAdjustedExp_T = add(io.in.sExp, asSInt(UInt<9>(0hc0))) node _sAdjustedExp_T_1 = bits(_sAdjustedExp_T, 8, 0) node sAdjustedExp = cvt(_sAdjustedExp_T_1) node _adjustedSig_T = bits(io.in.sig, 32, 7) node _adjustedSig_T_1 = bits(io.in.sig, 6, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<24>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 connect common_overflow, UInt<1>(0h0) connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_13( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [7:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [32:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [7:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [32:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [24:0] _roundMask_T = 25'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [26:0] roundMask = 27'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [27:0] _shiftedRoundMask_T = 28'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [26:0] shiftedRoundMask = 27'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [26:0] _roundPosMask_T = 27'h7FFFFFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [26:0] roundPosMask = 27'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [26:0] _roundedSig_T_10 = 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [25:0] _roundedSig_T_6 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_14 = 26'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_12 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14, :265:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_11 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:265:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [8:0] _expOut_T_18 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:277:16] wire [8:0] _expOut_T_20 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [22:0] _fractOut_T_2 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:281:16, :284:13] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire [3:0] _io_exceptionFlags_T_2 = 4'h0; // @[RoundAnyRawFNToRecFN.scala:288:53] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire [2:0] _io_exceptionFlags_T_1 = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :58:16, :288:41] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire common_overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:124:37] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire overflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:238:32] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire _notNaN_isInfOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:45] wire notNaN_isInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:248:32] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire [9:0] _sAdjustedExp_T = {{2{io_in_sExp_0[7]}}, io_in_sExp_0} + 10'hC0; // @[RoundAnyRawFNToRecFN.scala:48:5, :104:25] wire [8:0] _sAdjustedExp_T_1 = _sAdjustedExp_T[8:0]; // @[RoundAnyRawFNToRecFN.scala:104:25, :106:14] wire [9:0] sAdjustedExp = {1'h0, _sAdjustedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:{14,31}] wire [25:0] _adjustedSig_T = io_in_sig_0[32:7]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [6:0] _adjustedSig_T_1 = io_in_sig_0[6:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [26:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [26:0] _roundPosBit_T = adjustedSig & 27'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & 27'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | 27'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_7 = {25'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_11 = adjustedSig & 27'h7FFFFFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:106:31, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = _inexact_T; // @[RoundAnyRawFNToRecFN.scala:240:{28,43}] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_13 = _expOut_T_10; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_19 = _expOut_T_17; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15] wire [8:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? 23'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16, :284:13] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] assign _io_exceptionFlags_T_3 = {4'h0, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_102 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_102( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_19 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 2) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[9] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7]) node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_64 = shr(io.in.a.bits.source, 2) node _T_65 = eq(_T_64, UInt<4>(0h8)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<2>(0h2)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = and(_T_11, _T_24) node _T_102 = and(_T_101, _T_37) node _T_103 = and(_T_102, _T_50) node _T_104 = and(_T_103, _T_63) node _T_105 = and(_T_104, _T_76) node _T_106 = and(_T_105, _T_84) node _T_107 = and(_T_106, _T_92) node _T_108 = and(_T_107, _T_100) node _T_109 = asUInt(reset) node _T_110 = eq(_T_109, UInt<1>(0h0)) when _T_110 : node _T_111 = eq(_T_108, UInt<1>(0h0)) when _T_111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_108, UInt<1>(0h1), "") : assert_1 node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_112 : node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_115 = and(_T_113, _T_114) node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_117 = shr(io.in.a.bits.source, 2) node _T_118 = eq(_T_117, UInt<1>(0h0)) node _T_119 = leq(UInt<1>(0h0), uncommonBits_5) node _T_120 = and(_T_118, _T_119) node _T_121 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_122 = and(_T_120, _T_121) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_123 = shr(io.in.a.bits.source, 2) node _T_124 = eq(_T_123, UInt<1>(0h1)) node _T_125 = leq(UInt<1>(0h0), uncommonBits_6) node _T_126 = and(_T_124, _T_125) node _T_127 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_128 = and(_T_126, _T_127) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_129 = shr(io.in.a.bits.source, 2) node _T_130 = eq(_T_129, UInt<2>(0h2)) node _T_131 = leq(UInt<1>(0h0), uncommonBits_7) node _T_132 = and(_T_130, _T_131) node _T_133 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_134 = and(_T_132, _T_133) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_135 = shr(io.in.a.bits.source, 2) node _T_136 = eq(_T_135, UInt<2>(0h3)) node _T_137 = leq(UInt<1>(0h0), uncommonBits_8) node _T_138 = and(_T_136, _T_137) node _T_139 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_140 = and(_T_138, _T_139) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_141 = shr(io.in.a.bits.source, 2) node _T_142 = eq(_T_141, UInt<4>(0h8)) node _T_143 = leq(UInt<1>(0h0), uncommonBits_9) node _T_144 = and(_T_142, _T_143) node _T_145 = leq(uncommonBits_9, UInt<2>(0h2)) node _T_146 = and(_T_144, _T_145) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_116, _T_122) node _T_151 = or(_T_150, _T_128) node _T_152 = or(_T_151, _T_134) node _T_153 = or(_T_152, _T_140) node _T_154 = or(_T_153, _T_146) node _T_155 = or(_T_154, _T_147) node _T_156 = or(_T_155, _T_148) node _T_157 = or(_T_156, _T_149) node _T_158 = and(_T_115, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_161 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = and(_T_160, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = and(_T_159, _T_167) node _T_169 = asUInt(reset) node _T_170 = eq(_T_169, UInt<1>(0h0)) when _T_170 : node _T_171 = eq(_T_168, UInt<1>(0h0)) when _T_171 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_168, UInt<1>(0h1), "") : assert_2 node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_173 = shr(io.in.a.bits.source, 2) node _T_174 = eq(_T_173, UInt<1>(0h0)) node _T_175 = leq(UInt<1>(0h0), uncommonBits_10) node _T_176 = and(_T_174, _T_175) node _T_177 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_178 = and(_T_176, _T_177) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_179 = shr(io.in.a.bits.source, 2) node _T_180 = eq(_T_179, UInt<1>(0h1)) node _T_181 = leq(UInt<1>(0h0), uncommonBits_11) node _T_182 = and(_T_180, _T_181) node _T_183 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_184 = and(_T_182, _T_183) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_185 = shr(io.in.a.bits.source, 2) node _T_186 = eq(_T_185, UInt<2>(0h2)) node _T_187 = leq(UInt<1>(0h0), uncommonBits_12) node _T_188 = and(_T_186, _T_187) node _T_189 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_190 = and(_T_188, _T_189) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_191 = shr(io.in.a.bits.source, 2) node _T_192 = eq(_T_191, UInt<2>(0h3)) node _T_193 = leq(UInt<1>(0h0), uncommonBits_13) node _T_194 = and(_T_192, _T_193) node _T_195 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_196 = and(_T_194, _T_195) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_197 = shr(io.in.a.bits.source, 2) node _T_198 = eq(_T_197, UInt<4>(0h8)) node _T_199 = leq(UInt<1>(0h0), uncommonBits_14) node _T_200 = and(_T_198, _T_199) node _T_201 = leq(uncommonBits_14, UInt<2>(0h2)) node _T_202 = and(_T_200, _T_201) node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[9] connect _WIRE[0], _T_172 connect _WIRE[1], _T_178 connect _WIRE[2], _T_184 connect _WIRE[3], _T_190 connect _WIRE[4], _T_196 connect _WIRE[5], _T_202 connect _WIRE[6], _T_203 connect _WIRE[7], _T_204 connect _WIRE[8], _T_205 node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0)) node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_216 = or(_T_207, _T_208) node _T_217 = or(_T_216, _T_209) node _T_218 = or(_T_217, _T_210) node _T_219 = or(_T_218, _T_211) node _T_220 = or(_T_219, _T_212) node _T_221 = or(_T_220, _T_213) node _T_222 = or(_T_221, _T_214) node _T_223 = or(_T_222, _T_215) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_223 node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_226 = and(_T_224, _T_225) node _T_227 = or(UInt<1>(0h0), _T_226) node _T_228 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = and(_T_227, _T_232) node _T_234 = or(UInt<1>(0h0), _T_233) node _T_235 = and(_WIRE_1, _T_234) node _T_236 = asUInt(reset) node _T_237 = eq(_T_236, UInt<1>(0h0)) when _T_237 : node _T_238 = eq(_T_235, UInt<1>(0h0)) when _T_238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_235, UInt<1>(0h1), "") : assert_3 node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(source_ok, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_242, UInt<1>(0h1), "") : assert_5 node _T_246 = asUInt(reset) node _T_247 = eq(_T_246, UInt<1>(0h0)) when _T_247 : node _T_248 = eq(is_aligned, UInt<1>(0h0)) when _T_248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_249, UInt<1>(0h1), "") : assert_7 node _T_253 = not(io.in.a.bits.mask) node _T_254 = eq(_T_253, UInt<1>(0h0)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_254, UInt<1>(0h1), "") : assert_8 node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_258, UInt<1>(0h1), "") : assert_9 node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_262 : node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_265 = and(_T_263, _T_264) node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_267 = shr(io.in.a.bits.source, 2) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = leq(UInt<1>(0h0), uncommonBits_15) node _T_270 = and(_T_268, _T_269) node _T_271 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_272 = and(_T_270, _T_271) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_273 = shr(io.in.a.bits.source, 2) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_279 = shr(io.in.a.bits.source, 2) node _T_280 = eq(_T_279, UInt<2>(0h2)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_284 = and(_T_282, _T_283) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_285 = shr(io.in.a.bits.source, 2) node _T_286 = eq(_T_285, UInt<2>(0h3)) node _T_287 = leq(UInt<1>(0h0), uncommonBits_18) node _T_288 = and(_T_286, _T_287) node _T_289 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_291 = shr(io.in.a.bits.source, 2) node _T_292 = eq(_T_291, UInt<4>(0h8)) node _T_293 = leq(UInt<1>(0h0), uncommonBits_19) node _T_294 = and(_T_292, _T_293) node _T_295 = leq(uncommonBits_19, UInt<2>(0h2)) node _T_296 = and(_T_294, _T_295) node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_300 = or(_T_266, _T_272) node _T_301 = or(_T_300, _T_278) node _T_302 = or(_T_301, _T_284) node _T_303 = or(_T_302, _T_290) node _T_304 = or(_T_303, _T_296) node _T_305 = or(_T_304, _T_297) node _T_306 = or(_T_305, _T_298) node _T_307 = or(_T_306, _T_299) node _T_308 = and(_T_265, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_311 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = and(_T_310, _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = and(_T_309, _T_317) node _T_319 = asUInt(reset) node _T_320 = eq(_T_319, UInt<1>(0h0)) when _T_320 : node _T_321 = eq(_T_318, UInt<1>(0h0)) when _T_321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_318, UInt<1>(0h1), "") : assert_10 node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_323 = shr(io.in.a.bits.source, 2) node _T_324 = eq(_T_323, UInt<1>(0h0)) node _T_325 = leq(UInt<1>(0h0), uncommonBits_20) node _T_326 = and(_T_324, _T_325) node _T_327 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_328 = and(_T_326, _T_327) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_329 = shr(io.in.a.bits.source, 2) node _T_330 = eq(_T_329, UInt<1>(0h1)) node _T_331 = leq(UInt<1>(0h0), uncommonBits_21) node _T_332 = and(_T_330, _T_331) node _T_333 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_335 = shr(io.in.a.bits.source, 2) node _T_336 = eq(_T_335, UInt<2>(0h2)) node _T_337 = leq(UInt<1>(0h0), uncommonBits_22) node _T_338 = and(_T_336, _T_337) node _T_339 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_340 = and(_T_338, _T_339) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_341 = shr(io.in.a.bits.source, 2) node _T_342 = eq(_T_341, UInt<2>(0h3)) node _T_343 = leq(UInt<1>(0h0), uncommonBits_23) node _T_344 = and(_T_342, _T_343) node _T_345 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_346 = and(_T_344, _T_345) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_347 = shr(io.in.a.bits.source, 2) node _T_348 = eq(_T_347, UInt<4>(0h8)) node _T_349 = leq(UInt<1>(0h0), uncommonBits_24) node _T_350 = and(_T_348, _T_349) node _T_351 = leq(uncommonBits_24, UInt<2>(0h2)) node _T_352 = and(_T_350, _T_351) node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[9] connect _WIRE_2[0], _T_322 connect _WIRE_2[1], _T_328 connect _WIRE_2[2], _T_334 connect _WIRE_2[3], _T_340 connect _WIRE_2[4], _T_346 connect _WIRE_2[5], _T_352 connect _WIRE_2[6], _T_353 connect _WIRE_2[7], _T_354 connect _WIRE_2[8], _T_355 node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0)) node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_366 = or(_T_357, _T_358) node _T_367 = or(_T_366, _T_359) node _T_368 = or(_T_367, _T_360) node _T_369 = or(_T_368, _T_361) node _T_370 = or(_T_369, _T_362) node _T_371 = or(_T_370, _T_363) node _T_372 = or(_T_371, _T_364) node _T_373 = or(_T_372, _T_365) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_373 node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _T_377 = or(UInt<1>(0h0), _T_376) node _T_378 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_379 = cvt(_T_378) node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000))) node _T_381 = asSInt(_T_380) node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0))) node _T_383 = and(_T_377, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = and(_WIRE_3, _T_384) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_385, UInt<1>(0h1), "") : assert_11 node _T_389 = asUInt(reset) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(source_ok, UInt<1>(0h0)) when _T_391 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_393 = asUInt(reset) node _T_394 = eq(_T_393, UInt<1>(0h0)) when _T_394 : node _T_395 = eq(_T_392, UInt<1>(0h0)) when _T_395 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_392, UInt<1>(0h1), "") : assert_13 node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(is_aligned, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_399, UInt<1>(0h1), "") : assert_15 node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_404 = asUInt(reset) node _T_405 = eq(_T_404, UInt<1>(0h0)) when _T_405 : node _T_406 = eq(_T_403, UInt<1>(0h0)) when _T_406 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_403, UInt<1>(0h1), "") : assert_16 node _T_407 = not(io.in.a.bits.mask) node _T_408 = eq(_T_407, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_408, UInt<1>(0h1), "") : assert_17 node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_412, UInt<1>(0h1), "") : assert_18 node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_416 : node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_419 = and(_T_417, _T_418) node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_25) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<1>(0h1)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_26) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h2)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_27) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_439 = shr(io.in.a.bits.source, 2) node _T_440 = eq(_T_439, UInt<2>(0h3)) node _T_441 = leq(UInt<1>(0h0), uncommonBits_28) node _T_442 = and(_T_440, _T_441) node _T_443 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_444 = and(_T_442, _T_443) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_445 = shr(io.in.a.bits.source, 2) node _T_446 = eq(_T_445, UInt<4>(0h8)) node _T_447 = leq(UInt<1>(0h0), uncommonBits_29) node _T_448 = and(_T_446, _T_447) node _T_449 = leq(uncommonBits_29, UInt<2>(0h2)) node _T_450 = and(_T_448, _T_449) node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_454 = or(_T_420, _T_426) node _T_455 = or(_T_454, _T_432) node _T_456 = or(_T_455, _T_438) node _T_457 = or(_T_456, _T_444) node _T_458 = or(_T_457, _T_450) node _T_459 = or(_T_458, _T_451) node _T_460 = or(_T_459, _T_452) node _T_461 = or(_T_460, _T_453) node _T_462 = and(_T_419, _T_461) node _T_463 = or(UInt<1>(0h0), _T_462) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_463, UInt<1>(0h1), "") : assert_19 node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_468 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_469 = and(_T_467, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_472 = cvt(_T_471) node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000))) node _T_474 = asSInt(_T_473) node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0))) node _T_476 = and(_T_470, _T_475) node _T_477 = or(UInt<1>(0h0), _T_476) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_477, UInt<1>(0h1), "") : assert_20 node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(source_ok, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_484 = asUInt(reset) node _T_485 = eq(_T_484, UInt<1>(0h0)) when _T_485 : node _T_486 = eq(is_aligned, UInt<1>(0h0)) when _T_486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_488 = asUInt(reset) node _T_489 = eq(_T_488, UInt<1>(0h0)) when _T_489 : node _T_490 = eq(_T_487, UInt<1>(0h0)) when _T_490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_487, UInt<1>(0h1), "") : assert_23 node _T_491 = eq(io.in.a.bits.mask, mask) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_491, UInt<1>(0h1), "") : assert_24 node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_495, UInt<1>(0h1), "") : assert_25 node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_499 : node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_502 = and(_T_500, _T_501) node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_504 = shr(io.in.a.bits.source, 2) node _T_505 = eq(_T_504, UInt<1>(0h0)) node _T_506 = leq(UInt<1>(0h0), uncommonBits_30) node _T_507 = and(_T_505, _T_506) node _T_508 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_509 = and(_T_507, _T_508) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_510 = shr(io.in.a.bits.source, 2) node _T_511 = eq(_T_510, UInt<1>(0h1)) node _T_512 = leq(UInt<1>(0h0), uncommonBits_31) node _T_513 = and(_T_511, _T_512) node _T_514 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_515 = and(_T_513, _T_514) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_516 = shr(io.in.a.bits.source, 2) node _T_517 = eq(_T_516, UInt<2>(0h2)) node _T_518 = leq(UInt<1>(0h0), uncommonBits_32) node _T_519 = and(_T_517, _T_518) node _T_520 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_522 = shr(io.in.a.bits.source, 2) node _T_523 = eq(_T_522, UInt<2>(0h3)) node _T_524 = leq(UInt<1>(0h0), uncommonBits_33) node _T_525 = and(_T_523, _T_524) node _T_526 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_527 = and(_T_525, _T_526) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_528 = shr(io.in.a.bits.source, 2) node _T_529 = eq(_T_528, UInt<4>(0h8)) node _T_530 = leq(UInt<1>(0h0), uncommonBits_34) node _T_531 = and(_T_529, _T_530) node _T_532 = leq(uncommonBits_34, UInt<2>(0h2)) node _T_533 = and(_T_531, _T_532) node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_537 = or(_T_503, _T_509) node _T_538 = or(_T_537, _T_515) node _T_539 = or(_T_538, _T_521) node _T_540 = or(_T_539, _T_527) node _T_541 = or(_T_540, _T_533) node _T_542 = or(_T_541, _T_534) node _T_543 = or(_T_542, _T_535) node _T_544 = or(_T_543, _T_536) node _T_545 = and(_T_502, _T_544) node _T_546 = or(UInt<1>(0h0), _T_545) node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_548 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_549 = and(_T_547, _T_548) node _T_550 = or(UInt<1>(0h0), _T_549) node _T_551 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_552 = cvt(_T_551) node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000))) node _T_554 = asSInt(_T_553) node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0))) node _T_556 = and(_T_550, _T_555) node _T_557 = or(UInt<1>(0h0), _T_556) node _T_558 = and(_T_546, _T_557) node _T_559 = asUInt(reset) node _T_560 = eq(_T_559, UInt<1>(0h0)) when _T_560 : node _T_561 = eq(_T_558, UInt<1>(0h0)) when _T_561 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_558, UInt<1>(0h1), "") : assert_26 node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(source_ok, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_565 = asUInt(reset) node _T_566 = eq(_T_565, UInt<1>(0h0)) when _T_566 : node _T_567 = eq(is_aligned, UInt<1>(0h0)) when _T_567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_568, UInt<1>(0h1), "") : assert_29 node _T_572 = eq(io.in.a.bits.mask, mask) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_572, UInt<1>(0h1), "") : assert_30 node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_576 : node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_579 = and(_T_577, _T_578) node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<1>(0h0)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_35) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<1>(0h1)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_36) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_593 = shr(io.in.a.bits.source, 2) node _T_594 = eq(_T_593, UInt<2>(0h2)) node _T_595 = leq(UInt<1>(0h0), uncommonBits_37) node _T_596 = and(_T_594, _T_595) node _T_597 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_598 = and(_T_596, _T_597) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_599 = shr(io.in.a.bits.source, 2) node _T_600 = eq(_T_599, UInt<2>(0h3)) node _T_601 = leq(UInt<1>(0h0), uncommonBits_38) node _T_602 = and(_T_600, _T_601) node _T_603 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_604 = and(_T_602, _T_603) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_605 = shr(io.in.a.bits.source, 2) node _T_606 = eq(_T_605, UInt<4>(0h8)) node _T_607 = leq(UInt<1>(0h0), uncommonBits_39) node _T_608 = and(_T_606, _T_607) node _T_609 = leq(uncommonBits_39, UInt<2>(0h2)) node _T_610 = and(_T_608, _T_609) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_580, _T_586) node _T_615 = or(_T_614, _T_592) node _T_616 = or(_T_615, _T_598) node _T_617 = or(_T_616, _T_604) node _T_618 = or(_T_617, _T_610) node _T_619 = or(_T_618, _T_611) node _T_620 = or(_T_619, _T_612) node _T_621 = or(_T_620, _T_613) node _T_622 = and(_T_579, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = and(_T_627, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_T_635, UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_635, UInt<1>(0h1), "") : assert_31 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(source_ok, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_642 = asUInt(reset) node _T_643 = eq(_T_642, UInt<1>(0h0)) when _T_643 : node _T_644 = eq(is_aligned, UInt<1>(0h0)) when _T_644 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_645, UInt<1>(0h1), "") : assert_34 node _T_649 = not(mask) node _T_650 = and(io.in.a.bits.mask, _T_649) node _T_651 = eq(_T_650, UInt<1>(0h0)) node _T_652 = asUInt(reset) node _T_653 = eq(_T_652, UInt<1>(0h0)) when _T_653 : node _T_654 = eq(_T_651, UInt<1>(0h0)) when _T_654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_651, UInt<1>(0h1), "") : assert_35 node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_655 : node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_658 = and(_T_656, _T_657) node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_660 = shr(io.in.a.bits.source, 2) node _T_661 = eq(_T_660, UInt<1>(0h0)) node _T_662 = leq(UInt<1>(0h0), uncommonBits_40) node _T_663 = and(_T_661, _T_662) node _T_664 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_665 = and(_T_663, _T_664) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_666 = shr(io.in.a.bits.source, 2) node _T_667 = eq(_T_666, UInt<1>(0h1)) node _T_668 = leq(UInt<1>(0h0), uncommonBits_41) node _T_669 = and(_T_667, _T_668) node _T_670 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_671 = and(_T_669, _T_670) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_672 = shr(io.in.a.bits.source, 2) node _T_673 = eq(_T_672, UInt<2>(0h2)) node _T_674 = leq(UInt<1>(0h0), uncommonBits_42) node _T_675 = and(_T_673, _T_674) node _T_676 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_677 = and(_T_675, _T_676) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_678 = shr(io.in.a.bits.source, 2) node _T_679 = eq(_T_678, UInt<2>(0h3)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_43) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_684 = shr(io.in.a.bits.source, 2) node _T_685 = eq(_T_684, UInt<4>(0h8)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_44) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_44, UInt<2>(0h2)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_693 = or(_T_659, _T_665) node _T_694 = or(_T_693, _T_671) node _T_695 = or(_T_694, _T_677) node _T_696 = or(_T_695, _T_683) node _T_697 = or(_T_696, _T_689) node _T_698 = or(_T_697, _T_690) node _T_699 = or(_T_698, _T_691) node _T_700 = or(_T_699, _T_692) node _T_701 = and(_T_658, _T_700) node _T_702 = or(UInt<1>(0h0), _T_701) node _T_703 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_704 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_705 = and(_T_703, _T_704) node _T_706 = or(UInt<1>(0h0), _T_705) node _T_707 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<13>(0h1000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = and(_T_706, _T_711) node _T_713 = or(UInt<1>(0h0), _T_712) node _T_714 = and(_T_702, _T_713) node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(_T_714, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_714, UInt<1>(0h1), "") : assert_36 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(source_ok, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(is_aligned, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_724 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_725 = asUInt(reset) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(_T_724, UInt<1>(0h0)) when _T_727 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_724, UInt<1>(0h1), "") : assert_39 node _T_728 = eq(io.in.a.bits.mask, mask) node _T_729 = asUInt(reset) node _T_730 = eq(_T_729, UInt<1>(0h0)) when _T_730 : node _T_731 = eq(_T_728, UInt<1>(0h0)) when _T_731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_728, UInt<1>(0h1), "") : assert_40 node _T_732 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_732 : node _T_733 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_734 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_735 = and(_T_733, _T_734) node _T_736 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_737 = shr(io.in.a.bits.source, 2) node _T_738 = eq(_T_737, UInt<1>(0h0)) node _T_739 = leq(UInt<1>(0h0), uncommonBits_45) node _T_740 = and(_T_738, _T_739) node _T_741 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_742 = and(_T_740, _T_741) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_743 = shr(io.in.a.bits.source, 2) node _T_744 = eq(_T_743, UInt<1>(0h1)) node _T_745 = leq(UInt<1>(0h0), uncommonBits_46) node _T_746 = and(_T_744, _T_745) node _T_747 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_748 = and(_T_746, _T_747) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_749 = shr(io.in.a.bits.source, 2) node _T_750 = eq(_T_749, UInt<2>(0h2)) node _T_751 = leq(UInt<1>(0h0), uncommonBits_47) node _T_752 = and(_T_750, _T_751) node _T_753 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_754 = and(_T_752, _T_753) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_755 = shr(io.in.a.bits.source, 2) node _T_756 = eq(_T_755, UInt<2>(0h3)) node _T_757 = leq(UInt<1>(0h0), uncommonBits_48) node _T_758 = and(_T_756, _T_757) node _T_759 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_760 = and(_T_758, _T_759) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_761 = shr(io.in.a.bits.source, 2) node _T_762 = eq(_T_761, UInt<4>(0h8)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_49) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_49, UInt<2>(0h2)) node _T_766 = and(_T_764, _T_765) node _T_767 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_768 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_769 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_770 = or(_T_736, _T_742) node _T_771 = or(_T_770, _T_748) node _T_772 = or(_T_771, _T_754) node _T_773 = or(_T_772, _T_760) node _T_774 = or(_T_773, _T_766) node _T_775 = or(_T_774, _T_767) node _T_776 = or(_T_775, _T_768) node _T_777 = or(_T_776, _T_769) node _T_778 = and(_T_735, _T_777) node _T_779 = or(UInt<1>(0h0), _T_778) node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_782 = and(_T_780, _T_781) node _T_783 = or(UInt<1>(0h0), _T_782) node _T_784 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_785 = cvt(_T_784) node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000))) node _T_787 = asSInt(_T_786) node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0))) node _T_789 = and(_T_783, _T_788) node _T_790 = or(UInt<1>(0h0), _T_789) node _T_791 = and(_T_779, _T_790) node _T_792 = asUInt(reset) node _T_793 = eq(_T_792, UInt<1>(0h0)) when _T_793 : node _T_794 = eq(_T_791, UInt<1>(0h0)) when _T_794 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_791, UInt<1>(0h1), "") : assert_41 node _T_795 = asUInt(reset) node _T_796 = eq(_T_795, UInt<1>(0h0)) when _T_796 : node _T_797 = eq(source_ok, UInt<1>(0h0)) when _T_797 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(is_aligned, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_801 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_802 = asUInt(reset) node _T_803 = eq(_T_802, UInt<1>(0h0)) when _T_803 : node _T_804 = eq(_T_801, UInt<1>(0h0)) when _T_804 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_801, UInt<1>(0h1), "") : assert_44 node _T_805 = eq(io.in.a.bits.mask, mask) node _T_806 = asUInt(reset) node _T_807 = eq(_T_806, UInt<1>(0h0)) when _T_807 : node _T_808 = eq(_T_805, UInt<1>(0h0)) when _T_808 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_805, UInt<1>(0h1), "") : assert_45 node _T_809 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_809 : node _T_810 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_811 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_812 = and(_T_810, _T_811) node _T_813 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_814 = shr(io.in.a.bits.source, 2) node _T_815 = eq(_T_814, UInt<1>(0h0)) node _T_816 = leq(UInt<1>(0h0), uncommonBits_50) node _T_817 = and(_T_815, _T_816) node _T_818 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_819 = and(_T_817, _T_818) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_820 = shr(io.in.a.bits.source, 2) node _T_821 = eq(_T_820, UInt<1>(0h1)) node _T_822 = leq(UInt<1>(0h0), uncommonBits_51) node _T_823 = and(_T_821, _T_822) node _T_824 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_825 = and(_T_823, _T_824) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_826 = shr(io.in.a.bits.source, 2) node _T_827 = eq(_T_826, UInt<2>(0h2)) node _T_828 = leq(UInt<1>(0h0), uncommonBits_52) node _T_829 = and(_T_827, _T_828) node _T_830 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_831 = and(_T_829, _T_830) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_832 = shr(io.in.a.bits.source, 2) node _T_833 = eq(_T_832, UInt<2>(0h3)) node _T_834 = leq(UInt<1>(0h0), uncommonBits_53) node _T_835 = and(_T_833, _T_834) node _T_836 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_837 = and(_T_835, _T_836) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_838 = shr(io.in.a.bits.source, 2) node _T_839 = eq(_T_838, UInt<4>(0h8)) node _T_840 = leq(UInt<1>(0h0), uncommonBits_54) node _T_841 = and(_T_839, _T_840) node _T_842 = leq(uncommonBits_54, UInt<2>(0h2)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h23)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_846 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_847 = or(_T_813, _T_819) node _T_848 = or(_T_847, _T_825) node _T_849 = or(_T_848, _T_831) node _T_850 = or(_T_849, _T_837) node _T_851 = or(_T_850, _T_843) node _T_852 = or(_T_851, _T_844) node _T_853 = or(_T_852, _T_845) node _T_854 = or(_T_853, _T_846) node _T_855 = and(_T_812, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_858 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_859 = and(_T_857, _T_858) node _T_860 = or(UInt<1>(0h0), _T_859) node _T_861 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<13>(0h1000))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = and(_T_860, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = and(_T_856, _T_867) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_868, UInt<1>(0h1), "") : assert_46 node _T_872 = asUInt(reset) node _T_873 = eq(_T_872, UInt<1>(0h0)) when _T_873 : node _T_874 = eq(source_ok, UInt<1>(0h0)) when _T_874 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_875 = asUInt(reset) node _T_876 = eq(_T_875, UInt<1>(0h0)) when _T_876 : node _T_877 = eq(is_aligned, UInt<1>(0h0)) when _T_877 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_878 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_879 = asUInt(reset) node _T_880 = eq(_T_879, UInt<1>(0h0)) when _T_880 : node _T_881 = eq(_T_878, UInt<1>(0h0)) when _T_881 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_878, UInt<1>(0h1), "") : assert_49 node _T_882 = eq(io.in.a.bits.mask, mask) node _T_883 = asUInt(reset) node _T_884 = eq(_T_883, UInt<1>(0h0)) when _T_884 : node _T_885 = eq(_T_882, UInt<1>(0h0)) when _T_885 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_882, UInt<1>(0h1), "") : assert_50 node _T_886 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(_T_886, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_886, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_890 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_890, UInt<1>(0h1), "") : assert_52 node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_42 = shr(io.in.d.bits.source, 2) node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0)) node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44) node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_48 = shr(io.in.d.bits.source, 2) node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1)) node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50) node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_54 = shr(io.in.d.bits.source, 2) node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2)) node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56) node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_60 = shr(io.in.d.bits.source, 2) node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3)) node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62) node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_66 = shr(io.in.d.bits.source, 2) node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8)) node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68) node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2)) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23)) node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[9] connect _source_ok_WIRE_1[0], _source_ok_T_41 connect _source_ok_WIRE_1[1], _source_ok_T_47 connect _source_ok_WIRE_1[2], _source_ok_T_53 connect _source_ok_WIRE_1[3], _source_ok_T_59 connect _source_ok_WIRE_1[4], _source_ok_T_65 connect _source_ok_WIRE_1[5], _source_ok_T_71 connect _source_ok_WIRE_1[6], _source_ok_T_72 connect _source_ok_WIRE_1[7], _source_ok_T_73 connect _source_ok_WIRE_1[8], _source_ok_T_74 node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3]) node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7]) node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_894 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_894 : node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(source_ok_1, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_898 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_898, UInt<1>(0h1), "") : assert_54 node _T_902 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_902, UInt<1>(0h1), "") : assert_55 node _T_906 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(_T_906, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_906, UInt<1>(0h1), "") : assert_56 node _T_910 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_911 = asUInt(reset) node _T_912 = eq(_T_911, UInt<1>(0h0)) when _T_912 : node _T_913 = eq(_T_910, UInt<1>(0h0)) when _T_913 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_910, UInt<1>(0h1), "") : assert_57 node _T_914 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_914 : node _T_915 = asUInt(reset) node _T_916 = eq(_T_915, UInt<1>(0h0)) when _T_916 : node _T_917 = eq(source_ok_1, UInt<1>(0h0)) when _T_917 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(sink_ok, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_921 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(_T_921, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_921, UInt<1>(0h1), "") : assert_60 node _T_925 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_925, UInt<1>(0h1), "") : assert_61 node _T_929 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_929, UInt<1>(0h1), "") : assert_62 node _T_933 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_933, UInt<1>(0h1), "") : assert_63 node _T_937 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_938 = or(UInt<1>(0h1), _T_937) node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(_T_938, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_938, UInt<1>(0h1), "") : assert_64 node _T_942 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_942 : node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(source_ok_1, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(sink_ok, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_949 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_949, UInt<1>(0h1), "") : assert_67 node _T_953 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_953, UInt<1>(0h1), "") : assert_68 node _T_957 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_957, UInt<1>(0h1), "") : assert_69 node _T_961 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_962 = or(_T_961, io.in.d.bits.corrupt) node _T_963 = asUInt(reset) node _T_964 = eq(_T_963, UInt<1>(0h0)) when _T_964 : node _T_965 = eq(_T_962, UInt<1>(0h0)) when _T_965 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_962, UInt<1>(0h1), "") : assert_70 node _T_966 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_967 = or(UInt<1>(0h1), _T_966) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_967, UInt<1>(0h1), "") : assert_71 node _T_971 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(source_ok_1, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_975 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_975, UInt<1>(0h1), "") : assert_73 node _T_979 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(_T_979, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_979, UInt<1>(0h1), "") : assert_74 node _T_983 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_984 = or(UInt<1>(0h1), _T_983) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_984, UInt<1>(0h1), "") : assert_75 node _T_988 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_988 : node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(source_ok_1, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_992 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(_T_992, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_992, UInt<1>(0h1), "") : assert_77 node _T_996 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_997 = or(_T_996, io.in.d.bits.corrupt) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_997, UInt<1>(0h1), "") : assert_78 node _T_1001 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1002 = or(UInt<1>(0h1), _T_1001) node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(_T_1002, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1002, UInt<1>(0h1), "") : assert_79 node _T_1006 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1006 : node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(source_ok_1, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1010 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_81 node _T_1014 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_82 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(UInt<1>(0h1), _T_1018) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<14>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<7>, address : UInt<14>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1023 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<14>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1027 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1031 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1035 = eq(a_first, UInt<1>(0h0)) node _T_1036 = and(io.in.a.valid, _T_1035) when _T_1036 : node _T_1037 = eq(io.in.a.bits.opcode, opcode) node _T_1038 = asUInt(reset) node _T_1039 = eq(_T_1038, UInt<1>(0h0)) when _T_1039 : node _T_1040 = eq(_T_1037, UInt<1>(0h0)) when _T_1040 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1037, UInt<1>(0h1), "") : assert_87 node _T_1041 = eq(io.in.a.bits.param, param) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_88 node _T_1045 = eq(io.in.a.bits.size, size) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_89 node _T_1049 = eq(io.in.a.bits.source, source) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_90 node _T_1053 = eq(io.in.a.bits.address, address) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_91 node _T_1057 = and(io.in.a.ready, io.in.a.valid) node _T_1058 = and(_T_1057, a_first) when _T_1058 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1059 = eq(d_first, UInt<1>(0h0)) node _T_1060 = and(io.in.d.valid, _T_1059) when _T_1060 : node _T_1061 = eq(io.in.d.bits.opcode, opcode_1) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_92 node _T_1065 = eq(io.in.d.bits.param, param_1) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_93 node _T_1069 = eq(io.in.d.bits.size, size_1) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_94 node _T_1073 = eq(io.in.d.bits.source, source_1) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_95 node _T_1077 = eq(io.in.d.bits.sink, sink) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_96 node _T_1081 = eq(io.in.d.bits.denied, denied) node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_T_1081, UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1081, UInt<1>(0h1), "") : assert_97 node _T_1085 = and(io.in.d.ready, io.in.d.valid) node _T_1086 = and(_T_1085, d_first) when _T_1086 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<520>, clock, reset, UInt<520>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<520> connect a_sizes_set, UInt<520>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1087 = and(io.in.a.valid, a_first_1) node _T_1088 = and(_T_1087, UInt<1>(0h1)) when _T_1088 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1089 = and(io.in.a.ready, io.in.a.valid) node _T_1090 = and(_T_1089, a_first_1) node _T_1091 = and(_T_1090, UInt<1>(0h1)) when _T_1091 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1092 = dshr(inflight, io.in.a.bits.source) node _T_1093 = bits(_T_1092, 0, 0) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<520> connect d_sizes_clr, UInt<520>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1098 = and(io.in.d.valid, d_first_1) node _T_1099 = and(_T_1098, UInt<1>(0h1)) node _T_1100 = eq(d_release_ack, UInt<1>(0h0)) node _T_1101 = and(_T_1099, _T_1100) when _T_1101 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1102 = and(io.in.d.ready, io.in.d.valid) node _T_1103 = and(_T_1102, d_first_1) node _T_1104 = and(_T_1103, UInt<1>(0h1)) node _T_1105 = eq(d_release_ack, UInt<1>(0h0)) node _T_1106 = and(_T_1104, _T_1105) when _T_1106 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1107 = and(io.in.d.valid, d_first_1) node _T_1108 = and(_T_1107, UInt<1>(0h1)) node _T_1109 = eq(d_release_ack, UInt<1>(0h0)) node _T_1110 = and(_T_1108, _T_1109) when _T_1110 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1111 = dshr(inflight, io.in.d.bits.source) node _T_1112 = bits(_T_1111, 0, 0) node _T_1113 = or(_T_1112, same_cycle_resp) node _T_1114 = asUInt(reset) node _T_1115 = eq(_T_1114, UInt<1>(0h0)) when _T_1115 : node _T_1116 = eq(_T_1113, UInt<1>(0h0)) when _T_1116 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1113, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1117 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1118 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1119 = or(_T_1117, _T_1118) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_100 node _T_1123 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1124 = asUInt(reset) node _T_1125 = eq(_T_1124, UInt<1>(0h0)) when _T_1125 : node _T_1126 = eq(_T_1123, UInt<1>(0h0)) when _T_1126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1123, UInt<1>(0h1), "") : assert_101 else : node _T_1127 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1128 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1129 = or(_T_1127, _T_1128) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_102 node _T_1133 = eq(io.in.d.bits.size, a_size_lookup) node _T_1134 = asUInt(reset) node _T_1135 = eq(_T_1134, UInt<1>(0h0)) when _T_1135 : node _T_1136 = eq(_T_1133, UInt<1>(0h0)) when _T_1136 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1133, UInt<1>(0h1), "") : assert_103 node _T_1137 = and(io.in.d.valid, d_first_1) node _T_1138 = and(_T_1137, a_first_1) node _T_1139 = and(_T_1138, io.in.a.valid) node _T_1140 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1141 = and(_T_1139, _T_1140) node _T_1142 = eq(d_release_ack, UInt<1>(0h0)) node _T_1143 = and(_T_1141, _T_1142) when _T_1143 : node _T_1144 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1145 = or(_T_1144, io.in.a.ready) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_104 node _T_1149 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1150 = orr(a_set_wo_ready) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = or(_T_1149, _T_1151) node _T_1153 = asUInt(reset) node _T_1154 = eq(_T_1153, UInt<1>(0h0)) when _T_1154 : node _T_1155 = eq(_T_1152, UInt<1>(0h0)) when _T_1155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1152, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_38 node _T_1156 = orr(inflight) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) node _T_1158 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1159 = or(_T_1157, _T_1158) node _T_1160 = lt(watchdog, plusarg_reader.out) node _T_1161 = or(_T_1159, _T_1160) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1165 = and(io.in.a.ready, io.in.a.valid) node _T_1166 = and(io.in.d.ready, io.in.d.valid) node _T_1167 = or(_T_1165, _T_1166) when _T_1167 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<520>, clock, reset, UInt<520>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<14>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<14>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<520> connect c_sizes_set, UInt<520>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<14>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1168 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<14>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1169 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1170 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1171 = and(_T_1169, _T_1170) node _T_1172 = and(_T_1168, _T_1171) when _T_1172 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<14>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<14>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1173 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1174 = and(_T_1173, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<14>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1175 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1176 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1177 = and(_T_1175, _T_1176) node _T_1178 = and(_T_1174, _T_1177) when _T_1178 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<14>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<14>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<14>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1179 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1180 = bits(_T_1179, 0, 0) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<14>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<520> connect d_sizes_clr_1, UInt<520>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1185 = and(io.in.d.valid, d_first_2) node _T_1186 = and(_T_1185, UInt<1>(0h1)) node _T_1187 = and(_T_1186, d_release_ack_1) when _T_1187 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1188 = and(io.in.d.ready, io.in.d.valid) node _T_1189 = and(_T_1188, d_first_2) node _T_1190 = and(_T_1189, UInt<1>(0h1)) node _T_1191 = and(_T_1190, d_release_ack_1) when _T_1191 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1192 = and(io.in.d.valid, d_first_2) node _T_1193 = and(_T_1192, UInt<1>(0h1)) node _T_1194 = and(_T_1193, d_release_ack_1) when _T_1194 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<14>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1195 = dshr(inflight_1, io.in.d.bits.source) node _T_1196 = bits(_T_1195, 0, 0) node _T_1197 = or(_T_1196, same_cycle_resp_1) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<14>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1201 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(_T_1201, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1201, UInt<1>(0h1), "") : assert_109 else : node _T_1205 = eq(io.in.d.bits.size, c_size_lookup) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_110 node _T_1209 = and(io.in.d.valid, d_first_2) node _T_1210 = and(_T_1209, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<14>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1211 = and(_T_1210, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<14>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1212 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1213 = and(_T_1211, _T_1212) node _T_1214 = and(_T_1213, d_release_ack_1) node _T_1215 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1216 = and(_T_1214, _T_1215) when _T_1216 : node _T_1217 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<14>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1218 = or(_T_1217, _WIRE_27.ready) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_111 node _T_1222 = orr(c_set_wo_ready) when _T_1222 : node _T_1223 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_39 node _T_1227 = orr(inflight_1) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1230 = or(_T_1228, _T_1229) node _T_1231 = lt(watchdog_1, plusarg_reader_1.out) node _T_1232 = or(_T_1230, _T_1231) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CanHaveBuiltInDevices.scala:45:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<14>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<14>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1236 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1237 = and(io.in.d.ready, io.in.d.valid) node _T_1238 = or(_T_1236, _T_1237) when _T_1238 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_19( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [13:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [13:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire io_in_d_bits_denied = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_first_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_first_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_wo_ready_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_wo_ready_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_interm_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_interm_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_opcodes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_opcodes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_sizes_set_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_sizes_set_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _c_probe_ack_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _c_probe_ack_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_1_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_2_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_3_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [13:0] _same_cycle_resp_WIRE_4_bits_address = 14'h0; // @[Bundles.scala:265:74] wire [13:0] _same_cycle_resp_WIRE_5_bits_address = 14'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1027:0] _c_sizes_set_T_1 = 1028'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [519:0] c_sizes_set = 520'h0; // @[Monitor.scala:741:34] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [13:0] _is_aligned_T = {2'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 14'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20] wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31] wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31] wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _T_1165 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1165; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1165; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [13:0] address; // @[Monitor.scala:391:22] wire _T_1238 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1238; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1238; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1238; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [519:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [519:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [9:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [519:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [519:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [519:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[519:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_3 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1091 = _T_1165 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1091 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1091 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1091 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1091 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [9:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [1027:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1091 ? _a_sizes_set_T_1[519:0] : 520'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [519:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1137 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1137 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1106 = _T_1238 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1106 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1106 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1106 ? _d_sizes_clr_T_5[519:0] : 520'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [519:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [519:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [519:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [519:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [519:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [519:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [519:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [519:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[519:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [519:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1209 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1209 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1191 = _T_1238 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1191 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1191 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1191 ? _d_sizes_clr_T_11[519:0] : 520'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [519:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [519:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module CLINT : input clock : Clock input reset : Reset output auto : { int_out : UInt<1>[2], flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { flip rtcTick : UInt<1>} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_45 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire intnodeOut : UInt<1>[2] invalidate intnodeOut[0] invalidate intnodeOut[1] connect nodeIn, auto.in connect auto.int_out, intnodeOut regreset time : UInt<64>, clock, reset, UInt<64>(0h0) when io.rtcTick : node _time_T = add(time, UInt<1>(0h1)) node _time_T_1 = tail(_time_T, 1) connect time, _time_T_1 reg timecmp_0 : UInt<64>, clock regreset ipi_0 : UInt<1>, clock, reset, UInt<1>(0h0) node _intnodeOut_0_T = bits(ipi_0, 0, 0) connect intnodeOut[0], _intnodeOut_0_T node _intnodeOut_1_T = geq(time, timecmp_0) connect intnodeOut[1], _intnodeOut_1_T node pad = or(timecmp_0, UInt<64>(0h0)) node _oldBytes_T = bits(pad, 7, 0) node _oldBytes_T_1 = bits(pad, 15, 8) node _oldBytes_T_2 = bits(pad, 23, 16) node _oldBytes_T_3 = bits(pad, 31, 24) node _oldBytes_T_4 = bits(pad, 39, 32) node _oldBytes_T_5 = bits(pad, 47, 40) node _oldBytes_T_6 = bits(pad, 55, 48) node _oldBytes_T_7 = bits(pad, 63, 56) wire oldBytes : UInt<8>[8] connect oldBytes[0], _oldBytes_T connect oldBytes[1], _oldBytes_T_1 connect oldBytes[2], _oldBytes_T_2 connect oldBytes[3], _oldBytes_T_3 connect oldBytes[4], _oldBytes_T_4 connect oldBytes[5], _oldBytes_T_5 connect oldBytes[6], _oldBytes_T_6 connect oldBytes[7], _oldBytes_T_7 wire newBytes : UInt<8>[8] connect newBytes, oldBytes wire _valids_WIRE : UInt<1>[8] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) wire valids : UInt<1>[8] connect valids, _valids_WIRE node _T = or(valids[0], valids[1]) node _T_1 = or(_T, valids[2]) node _T_2 = or(_T_1, valids[3]) node _T_3 = or(_T_2, valids[4]) node _T_4 = or(_T_3, valids[5]) node _T_5 = or(_T_4, valids[6]) node _T_6 = or(_T_5, valids[7]) when _T_6 : node timecmp_0_lo_lo = cat(newBytes[1], newBytes[0]) node timecmp_0_lo_hi = cat(newBytes[3], newBytes[2]) node timecmp_0_lo = cat(timecmp_0_lo_hi, timecmp_0_lo_lo) node timecmp_0_hi_lo = cat(newBytes[5], newBytes[4]) node timecmp_0_hi_hi = cat(newBytes[7], newBytes[6]) node timecmp_0_hi = cat(timecmp_0_hi_hi, timecmp_0_hi_lo) node _timecmp_0_T = cat(timecmp_0_hi, timecmp_0_lo) connect timecmp_0, _timecmp_0_T node pad_1 = or(time, UInt<64>(0h0)) node _oldBytes_T_8 = bits(pad_1, 7, 0) node _oldBytes_T_9 = bits(pad_1, 15, 8) node _oldBytes_T_10 = bits(pad_1, 23, 16) node _oldBytes_T_11 = bits(pad_1, 31, 24) node _oldBytes_T_12 = bits(pad_1, 39, 32) node _oldBytes_T_13 = bits(pad_1, 47, 40) node _oldBytes_T_14 = bits(pad_1, 55, 48) node _oldBytes_T_15 = bits(pad_1, 63, 56) wire oldBytes_1 : UInt<8>[8] connect oldBytes_1[0], _oldBytes_T_8 connect oldBytes_1[1], _oldBytes_T_9 connect oldBytes_1[2], _oldBytes_T_10 connect oldBytes_1[3], _oldBytes_T_11 connect oldBytes_1[4], _oldBytes_T_12 connect oldBytes_1[5], _oldBytes_T_13 connect oldBytes_1[6], _oldBytes_T_14 connect oldBytes_1[7], _oldBytes_T_15 wire newBytes_1 : UInt<8>[8] connect newBytes_1, oldBytes_1 wire _valids_WIRE_1 : UInt<1>[8] connect _valids_WIRE_1[0], UInt<1>(0h0) connect _valids_WIRE_1[1], UInt<1>(0h0) connect _valids_WIRE_1[2], UInt<1>(0h0) connect _valids_WIRE_1[3], UInt<1>(0h0) connect _valids_WIRE_1[4], UInt<1>(0h0) connect _valids_WIRE_1[5], UInt<1>(0h0) connect _valids_WIRE_1[6], UInt<1>(0h0) connect _valids_WIRE_1[7], UInt<1>(0h0) wire valids_1 : UInt<1>[8] connect valids_1, _valids_WIRE_1 node _T_7 = or(valids_1[0], valids_1[1]) node _T_8 = or(_T_7, valids_1[2]) node _T_9 = or(_T_8, valids_1[3]) node _T_10 = or(_T_9, valids_1[4]) node _T_11 = or(_T_10, valids_1[5]) node _T_12 = or(_T_11, valids_1[6]) node _T_13 = or(_T_12, valids_1[7]) when _T_13 : node time_lo_lo = cat(newBytes_1[1], newBytes_1[0]) node time_lo_hi = cat(newBytes_1[3], newBytes_1[2]) node time_lo = cat(time_lo_hi, time_lo_lo) node time_hi_lo = cat(newBytes_1[5], newBytes_1[4]) node time_hi_hi = cat(newBytes_1[7], newBytes_1[6]) node time_hi = cat(time_hi_hi, time_hi_lo) node _time_T_2 = cat(time_hi, time_lo) connect time, _time_T_2 wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(nodeIn.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(nodeIn.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, nodeIn.a.bits.data connect in.bits.mask, nodeIn.a.bits.mask connect in.bits.extra.tlrr_extra.source, nodeIn.a.bits.source connect in.bits.extra.tlrr_extra.size, nodeIn.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<13>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<13>(0h1800)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<13>(0h0)) node _out_T_1 = eq(out_bindex, UInt<13>(0h0)) node _out_T_2 = eq(out_findex, UInt<13>(0h7ff)) node _out_T_3 = eq(out_bindex, UInt<13>(0h7ff)) node _out_T_4 = eq(out_findex, UInt<13>(0h0)) node _out_T_5 = eq(out_bindex, UInt<13>(0h0)) wire out_rivalid : UInt<1>[18] wire out_wivalid : UInt<1>[18] wire out_roready : UInt<1>[18] wire out_woready : UInt<1>[18] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_6 = bits(out_front.bits.data, 0, 0) when out_f_woready : connect ipi_0, _out_T_6 node _out_T_7 = and(out_f_rivalid, UInt<1>(0h1)) node _out_T_8 = and(UInt<1>(0h1), out_f_roready) node _out_T_9 = and(out_f_wivalid, UInt<1>(0h1)) node _out_T_10 = and(UInt<1>(0h1), out_f_woready) node _out_T_11 = eq(out_rimask, UInt<1>(0h0)) node _out_T_12 = eq(out_wimask, UInt<1>(0h0)) node _out_T_13 = eq(out_romask, UInt<1>(0h0)) node _out_T_14 = eq(out_womask, UInt<1>(0h0)) node _out_T_15 = or(ipi_0, UInt<1>(0h0)) node _out_T_16 = bits(_out_T_15, 0, 0) node _out_rimask_T_1 = bits(out_frontMask, 31, 1) node out_rimask_1 = orr(_out_rimask_T_1) node _out_wimask_T_1 = bits(out_frontMask, 31, 1) node out_wimask_1 = andr(_out_wimask_T_1) node _out_romask_T_1 = bits(out_backMask, 31, 1) node out_romask_1 = orr(_out_romask_T_1) node _out_womask_T_1 = bits(out_backMask, 31, 1) node out_womask_1 = andr(_out_womask_T_1) node out_f_rivalid_1 = and(out_rivalid[1], out_rimask_1) node out_f_roready_1 = and(out_roready[1], out_romask_1) node out_f_wivalid_1 = and(out_wivalid[1], out_wimask_1) node out_f_woready_1 = and(out_woready[1], out_womask_1) node _out_T_17 = bits(out_front.bits.data, 31, 1) node _out_T_18 = and(out_f_rivalid_1, UInt<1>(0h1)) node _out_T_19 = and(UInt<1>(0h1), out_f_roready_1) node _out_T_20 = eq(out_rimask_1, UInt<1>(0h0)) node _out_T_21 = eq(out_wimask_1, UInt<1>(0h0)) node _out_T_22 = eq(out_romask_1, UInt<1>(0h0)) node _out_T_23 = eq(out_womask_1, UInt<1>(0h0)) node _out_prepend_T = or(_out_T_16, UInt<1>(0h0)) node out_prepend = cat(UInt<1>(0h0), _out_prepend_T) node _out_T_24 = or(out_prepend, UInt<32>(0h0)) node _out_T_25 = bits(_out_T_24, 31, 0) node _out_rimask_T_2 = bits(out_frontMask, 7, 0) node out_rimask_2 = orr(_out_rimask_T_2) node _out_wimask_T_2 = bits(out_frontMask, 7, 0) node out_wimask_2 = andr(_out_wimask_T_2) node _out_romask_T_2 = bits(out_backMask, 7, 0) node out_romask_2 = orr(_out_romask_T_2) node _out_womask_T_2 = bits(out_backMask, 7, 0) node out_womask_2 = andr(_out_womask_T_2) node out_f_rivalid_2 = and(out_rivalid[2], out_rimask_2) node out_f_roready_2 = and(out_roready[2], out_romask_2) node out_f_wivalid_2 = and(out_wivalid[2], out_wimask_2) node out_f_woready_2 = and(out_woready[2], out_womask_2) node _out_T_26 = bits(out_front.bits.data, 7, 0) connect valids_1[0], out_f_woready_2 when out_f_woready_2 : connect newBytes_1[0], _out_T_26 node _out_T_27 = and(out_f_rivalid_2, UInt<1>(0h1)) node _out_T_28 = and(UInt<1>(0h1), out_f_roready_2) node _out_T_29 = and(out_f_wivalid_2, UInt<1>(0h1)) node _out_T_30 = and(UInt<1>(0h1), out_f_woready_2) node _out_T_31 = eq(out_rimask_2, UInt<1>(0h0)) node _out_T_32 = eq(out_wimask_2, UInt<1>(0h0)) node _out_T_33 = eq(out_romask_2, UInt<1>(0h0)) node _out_T_34 = eq(out_womask_2, UInt<1>(0h0)) node _out_T_35 = or(oldBytes_1[0], UInt<8>(0h0)) node _out_T_36 = bits(_out_T_35, 7, 0) node _out_rimask_T_3 = bits(out_frontMask, 15, 8) node out_rimask_3 = orr(_out_rimask_T_3) node _out_wimask_T_3 = bits(out_frontMask, 15, 8) node out_wimask_3 = andr(_out_wimask_T_3) node _out_romask_T_3 = bits(out_backMask, 15, 8) node out_romask_3 = orr(_out_romask_T_3) node _out_womask_T_3 = bits(out_backMask, 15, 8) node out_womask_3 = andr(_out_womask_T_3) node out_f_rivalid_3 = and(out_rivalid[3], out_rimask_3) node out_f_roready_3 = and(out_roready[3], out_romask_3) node out_f_wivalid_3 = and(out_wivalid[3], out_wimask_3) node out_f_woready_3 = and(out_woready[3], out_womask_3) node _out_T_37 = bits(out_front.bits.data, 15, 8) connect valids_1[1], out_f_woready_3 when out_f_woready_3 : connect newBytes_1[1], _out_T_37 node _out_T_38 = and(out_f_rivalid_3, UInt<1>(0h1)) node _out_T_39 = and(UInt<1>(0h1), out_f_roready_3) node _out_T_40 = and(out_f_wivalid_3, UInt<1>(0h1)) node _out_T_41 = and(UInt<1>(0h1), out_f_woready_3) node _out_T_42 = eq(out_rimask_3, UInt<1>(0h0)) node _out_T_43 = eq(out_wimask_3, UInt<1>(0h0)) node _out_T_44 = eq(out_romask_3, UInt<1>(0h0)) node _out_T_45 = eq(out_womask_3, UInt<1>(0h0)) node _out_prepend_T_1 = or(_out_T_36, UInt<8>(0h0)) node out_prepend_1 = cat(oldBytes_1[1], _out_prepend_T_1) node _out_T_46 = or(out_prepend_1, UInt<16>(0h0)) node _out_T_47 = bits(_out_T_46, 15, 0) node _out_rimask_T_4 = bits(out_frontMask, 23, 16) node out_rimask_4 = orr(_out_rimask_T_4) node _out_wimask_T_4 = bits(out_frontMask, 23, 16) node out_wimask_4 = andr(_out_wimask_T_4) node _out_romask_T_4 = bits(out_backMask, 23, 16) node out_romask_4 = orr(_out_romask_T_4) node _out_womask_T_4 = bits(out_backMask, 23, 16) node out_womask_4 = andr(_out_womask_T_4) node out_f_rivalid_4 = and(out_rivalid[4], out_rimask_4) node out_f_roready_4 = and(out_roready[4], out_romask_4) node out_f_wivalid_4 = and(out_wivalid[4], out_wimask_4) node out_f_woready_4 = and(out_woready[4], out_womask_4) node _out_T_48 = bits(out_front.bits.data, 23, 16) connect valids_1[2], out_f_woready_4 when out_f_woready_4 : connect newBytes_1[2], _out_T_48 node _out_T_49 = and(out_f_rivalid_4, UInt<1>(0h1)) node _out_T_50 = and(UInt<1>(0h1), out_f_roready_4) node _out_T_51 = and(out_f_wivalid_4, UInt<1>(0h1)) node _out_T_52 = and(UInt<1>(0h1), out_f_woready_4) node _out_T_53 = eq(out_rimask_4, UInt<1>(0h0)) node _out_T_54 = eq(out_wimask_4, UInt<1>(0h0)) node _out_T_55 = eq(out_romask_4, UInt<1>(0h0)) node _out_T_56 = eq(out_womask_4, UInt<1>(0h0)) node _out_prepend_T_2 = or(_out_T_47, UInt<16>(0h0)) node out_prepend_2 = cat(oldBytes_1[2], _out_prepend_T_2) node _out_T_57 = or(out_prepend_2, UInt<24>(0h0)) node _out_T_58 = bits(_out_T_57, 23, 0) node _out_rimask_T_5 = bits(out_frontMask, 31, 24) node out_rimask_5 = orr(_out_rimask_T_5) node _out_wimask_T_5 = bits(out_frontMask, 31, 24) node out_wimask_5 = andr(_out_wimask_T_5) node _out_romask_T_5 = bits(out_backMask, 31, 24) node out_romask_5 = orr(_out_romask_T_5) node _out_womask_T_5 = bits(out_backMask, 31, 24) node out_womask_5 = andr(_out_womask_T_5) node out_f_rivalid_5 = and(out_rivalid[5], out_rimask_5) node out_f_roready_5 = and(out_roready[5], out_romask_5) node out_f_wivalid_5 = and(out_wivalid[5], out_wimask_5) node out_f_woready_5 = and(out_woready[5], out_womask_5) node _out_T_59 = bits(out_front.bits.data, 31, 24) connect valids_1[3], out_f_woready_5 when out_f_woready_5 : connect newBytes_1[3], _out_T_59 node _out_T_60 = and(out_f_rivalid_5, UInt<1>(0h1)) node _out_T_61 = and(UInt<1>(0h1), out_f_roready_5) node _out_T_62 = and(out_f_wivalid_5, UInt<1>(0h1)) node _out_T_63 = and(UInt<1>(0h1), out_f_woready_5) node _out_T_64 = eq(out_rimask_5, UInt<1>(0h0)) node _out_T_65 = eq(out_wimask_5, UInt<1>(0h0)) node _out_T_66 = eq(out_romask_5, UInt<1>(0h0)) node _out_T_67 = eq(out_womask_5, UInt<1>(0h0)) node _out_prepend_T_3 = or(_out_T_58, UInt<24>(0h0)) node out_prepend_3 = cat(oldBytes_1[3], _out_prepend_T_3) node _out_T_68 = or(out_prepend_3, UInt<32>(0h0)) node _out_T_69 = bits(_out_T_68, 31, 0) node _out_rimask_T_6 = bits(out_frontMask, 39, 32) node out_rimask_6 = orr(_out_rimask_T_6) node _out_wimask_T_6 = bits(out_frontMask, 39, 32) node out_wimask_6 = andr(_out_wimask_T_6) node _out_romask_T_6 = bits(out_backMask, 39, 32) node out_romask_6 = orr(_out_romask_T_6) node _out_womask_T_6 = bits(out_backMask, 39, 32) node out_womask_6 = andr(_out_womask_T_6) node out_f_rivalid_6 = and(out_rivalid[6], out_rimask_6) node out_f_roready_6 = and(out_roready[6], out_romask_6) node out_f_wivalid_6 = and(out_wivalid[6], out_wimask_6) node out_f_woready_6 = and(out_woready[6], out_womask_6) node _out_T_70 = bits(out_front.bits.data, 39, 32) connect valids_1[4], out_f_woready_6 when out_f_woready_6 : connect newBytes_1[4], _out_T_70 node _out_T_71 = and(out_f_rivalid_6, UInt<1>(0h1)) node _out_T_72 = and(UInt<1>(0h1), out_f_roready_6) node _out_T_73 = and(out_f_wivalid_6, UInt<1>(0h1)) node _out_T_74 = and(UInt<1>(0h1), out_f_woready_6) node _out_T_75 = eq(out_rimask_6, UInt<1>(0h0)) node _out_T_76 = eq(out_wimask_6, UInt<1>(0h0)) node _out_T_77 = eq(out_romask_6, UInt<1>(0h0)) node _out_T_78 = eq(out_womask_6, UInt<1>(0h0)) node _out_prepend_T_4 = or(_out_T_69, UInt<32>(0h0)) node out_prepend_4 = cat(oldBytes_1[4], _out_prepend_T_4) node _out_T_79 = or(out_prepend_4, UInt<40>(0h0)) node _out_T_80 = bits(_out_T_79, 39, 0) node _out_rimask_T_7 = bits(out_frontMask, 47, 40) node out_rimask_7 = orr(_out_rimask_T_7) node _out_wimask_T_7 = bits(out_frontMask, 47, 40) node out_wimask_7 = andr(_out_wimask_T_7) node _out_romask_T_7 = bits(out_backMask, 47, 40) node out_romask_7 = orr(_out_romask_T_7) node _out_womask_T_7 = bits(out_backMask, 47, 40) node out_womask_7 = andr(_out_womask_T_7) node out_f_rivalid_7 = and(out_rivalid[7], out_rimask_7) node out_f_roready_7 = and(out_roready[7], out_romask_7) node out_f_wivalid_7 = and(out_wivalid[7], out_wimask_7) node out_f_woready_7 = and(out_woready[7], out_womask_7) node _out_T_81 = bits(out_front.bits.data, 47, 40) connect valids_1[5], out_f_woready_7 when out_f_woready_7 : connect newBytes_1[5], _out_T_81 node _out_T_82 = and(out_f_rivalid_7, UInt<1>(0h1)) node _out_T_83 = and(UInt<1>(0h1), out_f_roready_7) node _out_T_84 = and(out_f_wivalid_7, UInt<1>(0h1)) node _out_T_85 = and(UInt<1>(0h1), out_f_woready_7) node _out_T_86 = eq(out_rimask_7, UInt<1>(0h0)) node _out_T_87 = eq(out_wimask_7, UInt<1>(0h0)) node _out_T_88 = eq(out_romask_7, UInt<1>(0h0)) node _out_T_89 = eq(out_womask_7, UInt<1>(0h0)) node _out_prepend_T_5 = or(_out_T_80, UInt<40>(0h0)) node out_prepend_5 = cat(oldBytes_1[5], _out_prepend_T_5) node _out_T_90 = or(out_prepend_5, UInt<48>(0h0)) node _out_T_91 = bits(_out_T_90, 47, 0) node _out_rimask_T_8 = bits(out_frontMask, 55, 48) node out_rimask_8 = orr(_out_rimask_T_8) node _out_wimask_T_8 = bits(out_frontMask, 55, 48) node out_wimask_8 = andr(_out_wimask_T_8) node _out_romask_T_8 = bits(out_backMask, 55, 48) node out_romask_8 = orr(_out_romask_T_8) node _out_womask_T_8 = bits(out_backMask, 55, 48) node out_womask_8 = andr(_out_womask_T_8) node out_f_rivalid_8 = and(out_rivalid[8], out_rimask_8) node out_f_roready_8 = and(out_roready[8], out_romask_8) node out_f_wivalid_8 = and(out_wivalid[8], out_wimask_8) node out_f_woready_8 = and(out_woready[8], out_womask_8) node _out_T_92 = bits(out_front.bits.data, 55, 48) connect valids_1[6], out_f_woready_8 when out_f_woready_8 : connect newBytes_1[6], _out_T_92 node _out_T_93 = and(out_f_rivalid_8, UInt<1>(0h1)) node _out_T_94 = and(UInt<1>(0h1), out_f_roready_8) node _out_T_95 = and(out_f_wivalid_8, UInt<1>(0h1)) node _out_T_96 = and(UInt<1>(0h1), out_f_woready_8) node _out_T_97 = eq(out_rimask_8, UInt<1>(0h0)) node _out_T_98 = eq(out_wimask_8, UInt<1>(0h0)) node _out_T_99 = eq(out_romask_8, UInt<1>(0h0)) node _out_T_100 = eq(out_womask_8, UInt<1>(0h0)) node _out_prepend_T_6 = or(_out_T_91, UInt<48>(0h0)) node out_prepend_6 = cat(oldBytes_1[6], _out_prepend_T_6) node _out_T_101 = or(out_prepend_6, UInt<56>(0h0)) node _out_T_102 = bits(_out_T_101, 55, 0) node _out_rimask_T_9 = bits(out_frontMask, 63, 56) node out_rimask_9 = orr(_out_rimask_T_9) node _out_wimask_T_9 = bits(out_frontMask, 63, 56) node out_wimask_9 = andr(_out_wimask_T_9) node _out_romask_T_9 = bits(out_backMask, 63, 56) node out_romask_9 = orr(_out_romask_T_9) node _out_womask_T_9 = bits(out_backMask, 63, 56) node out_womask_9 = andr(_out_womask_T_9) node out_f_rivalid_9 = and(out_rivalid[9], out_rimask_9) node out_f_roready_9 = and(out_roready[9], out_romask_9) node out_f_wivalid_9 = and(out_wivalid[9], out_wimask_9) node out_f_woready_9 = and(out_woready[9], out_womask_9) node _out_T_103 = bits(out_front.bits.data, 63, 56) connect valids_1[7], out_f_woready_9 when out_f_woready_9 : connect newBytes_1[7], _out_T_103 node _out_T_104 = and(out_f_rivalid_9, UInt<1>(0h1)) node _out_T_105 = and(UInt<1>(0h1), out_f_roready_9) node _out_T_106 = and(out_f_wivalid_9, UInt<1>(0h1)) node _out_T_107 = and(UInt<1>(0h1), out_f_woready_9) node _out_T_108 = eq(out_rimask_9, UInt<1>(0h0)) node _out_T_109 = eq(out_wimask_9, UInt<1>(0h0)) node _out_T_110 = eq(out_romask_9, UInt<1>(0h0)) node _out_T_111 = eq(out_womask_9, UInt<1>(0h0)) node _out_prepend_T_7 = or(_out_T_102, UInt<56>(0h0)) node out_prepend_7 = cat(oldBytes_1[7], _out_prepend_T_7) node _out_T_112 = or(out_prepend_7, UInt<64>(0h0)) node _out_T_113 = bits(_out_T_112, 63, 0) node _out_rimask_T_10 = bits(out_frontMask, 7, 0) node out_rimask_10 = orr(_out_rimask_T_10) node _out_wimask_T_10 = bits(out_frontMask, 7, 0) node out_wimask_10 = andr(_out_wimask_T_10) node _out_romask_T_10 = bits(out_backMask, 7, 0) node out_romask_10 = orr(_out_romask_T_10) node _out_womask_T_10 = bits(out_backMask, 7, 0) node out_womask_10 = andr(_out_womask_T_10) node out_f_rivalid_10 = and(out_rivalid[10], out_rimask_10) node out_f_roready_10 = and(out_roready[10], out_romask_10) node out_f_wivalid_10 = and(out_wivalid[10], out_wimask_10) node out_f_woready_10 = and(out_woready[10], out_womask_10) node _out_T_114 = bits(out_front.bits.data, 7, 0) connect valids[0], out_f_woready_10 when out_f_woready_10 : connect newBytes[0], _out_T_114 node _out_T_115 = and(out_f_rivalid_10, UInt<1>(0h1)) node _out_T_116 = and(UInt<1>(0h1), out_f_roready_10) node _out_T_117 = and(out_f_wivalid_10, UInt<1>(0h1)) node _out_T_118 = and(UInt<1>(0h1), out_f_woready_10) node _out_T_119 = eq(out_rimask_10, UInt<1>(0h0)) node _out_T_120 = eq(out_wimask_10, UInt<1>(0h0)) node _out_T_121 = eq(out_romask_10, UInt<1>(0h0)) node _out_T_122 = eq(out_womask_10, UInt<1>(0h0)) node _out_T_123 = or(oldBytes[0], UInt<8>(0h0)) node _out_T_124 = bits(_out_T_123, 7, 0) node _out_rimask_T_11 = bits(out_frontMask, 15, 8) node out_rimask_11 = orr(_out_rimask_T_11) node _out_wimask_T_11 = bits(out_frontMask, 15, 8) node out_wimask_11 = andr(_out_wimask_T_11) node _out_romask_T_11 = bits(out_backMask, 15, 8) node out_romask_11 = orr(_out_romask_T_11) node _out_womask_T_11 = bits(out_backMask, 15, 8) node out_womask_11 = andr(_out_womask_T_11) node out_f_rivalid_11 = and(out_rivalid[11], out_rimask_11) node out_f_roready_11 = and(out_roready[11], out_romask_11) node out_f_wivalid_11 = and(out_wivalid[11], out_wimask_11) node out_f_woready_11 = and(out_woready[11], out_womask_11) node _out_T_125 = bits(out_front.bits.data, 15, 8) connect valids[1], out_f_woready_11 when out_f_woready_11 : connect newBytes[1], _out_T_125 node _out_T_126 = and(out_f_rivalid_11, UInt<1>(0h1)) node _out_T_127 = and(UInt<1>(0h1), out_f_roready_11) node _out_T_128 = and(out_f_wivalid_11, UInt<1>(0h1)) node _out_T_129 = and(UInt<1>(0h1), out_f_woready_11) node _out_T_130 = eq(out_rimask_11, UInt<1>(0h0)) node _out_T_131 = eq(out_wimask_11, UInt<1>(0h0)) node _out_T_132 = eq(out_romask_11, UInt<1>(0h0)) node _out_T_133 = eq(out_womask_11, UInt<1>(0h0)) node _out_prepend_T_8 = or(_out_T_124, UInt<8>(0h0)) node out_prepend_8 = cat(oldBytes[1], _out_prepend_T_8) node _out_T_134 = or(out_prepend_8, UInt<16>(0h0)) node _out_T_135 = bits(_out_T_134, 15, 0) node _out_rimask_T_12 = bits(out_frontMask, 23, 16) node out_rimask_12 = orr(_out_rimask_T_12) node _out_wimask_T_12 = bits(out_frontMask, 23, 16) node out_wimask_12 = andr(_out_wimask_T_12) node _out_romask_T_12 = bits(out_backMask, 23, 16) node out_romask_12 = orr(_out_romask_T_12) node _out_womask_T_12 = bits(out_backMask, 23, 16) node out_womask_12 = andr(_out_womask_T_12) node out_f_rivalid_12 = and(out_rivalid[12], out_rimask_12) node out_f_roready_12 = and(out_roready[12], out_romask_12) node out_f_wivalid_12 = and(out_wivalid[12], out_wimask_12) node out_f_woready_12 = and(out_woready[12], out_womask_12) node _out_T_136 = bits(out_front.bits.data, 23, 16) connect valids[2], out_f_woready_12 when out_f_woready_12 : connect newBytes[2], _out_T_136 node _out_T_137 = and(out_f_rivalid_12, UInt<1>(0h1)) node _out_T_138 = and(UInt<1>(0h1), out_f_roready_12) node _out_T_139 = and(out_f_wivalid_12, UInt<1>(0h1)) node _out_T_140 = and(UInt<1>(0h1), out_f_woready_12) node _out_T_141 = eq(out_rimask_12, UInt<1>(0h0)) node _out_T_142 = eq(out_wimask_12, UInt<1>(0h0)) node _out_T_143 = eq(out_romask_12, UInt<1>(0h0)) node _out_T_144 = eq(out_womask_12, UInt<1>(0h0)) node _out_prepend_T_9 = or(_out_T_135, UInt<16>(0h0)) node out_prepend_9 = cat(oldBytes[2], _out_prepend_T_9) node _out_T_145 = or(out_prepend_9, UInt<24>(0h0)) node _out_T_146 = bits(_out_T_145, 23, 0) node _out_rimask_T_13 = bits(out_frontMask, 31, 24) node out_rimask_13 = orr(_out_rimask_T_13) node _out_wimask_T_13 = bits(out_frontMask, 31, 24) node out_wimask_13 = andr(_out_wimask_T_13) node _out_romask_T_13 = bits(out_backMask, 31, 24) node out_romask_13 = orr(_out_romask_T_13) node _out_womask_T_13 = bits(out_backMask, 31, 24) node out_womask_13 = andr(_out_womask_T_13) node out_f_rivalid_13 = and(out_rivalid[13], out_rimask_13) node out_f_roready_13 = and(out_roready[13], out_romask_13) node out_f_wivalid_13 = and(out_wivalid[13], out_wimask_13) node out_f_woready_13 = and(out_woready[13], out_womask_13) node _out_T_147 = bits(out_front.bits.data, 31, 24) connect valids[3], out_f_woready_13 when out_f_woready_13 : connect newBytes[3], _out_T_147 node _out_T_148 = and(out_f_rivalid_13, UInt<1>(0h1)) node _out_T_149 = and(UInt<1>(0h1), out_f_roready_13) node _out_T_150 = and(out_f_wivalid_13, UInt<1>(0h1)) node _out_T_151 = and(UInt<1>(0h1), out_f_woready_13) node _out_T_152 = eq(out_rimask_13, UInt<1>(0h0)) node _out_T_153 = eq(out_wimask_13, UInt<1>(0h0)) node _out_T_154 = eq(out_romask_13, UInt<1>(0h0)) node _out_T_155 = eq(out_womask_13, UInt<1>(0h0)) node _out_prepend_T_10 = or(_out_T_146, UInt<24>(0h0)) node out_prepend_10 = cat(oldBytes[3], _out_prepend_T_10) node _out_T_156 = or(out_prepend_10, UInt<32>(0h0)) node _out_T_157 = bits(_out_T_156, 31, 0) node _out_rimask_T_14 = bits(out_frontMask, 39, 32) node out_rimask_14 = orr(_out_rimask_T_14) node _out_wimask_T_14 = bits(out_frontMask, 39, 32) node out_wimask_14 = andr(_out_wimask_T_14) node _out_romask_T_14 = bits(out_backMask, 39, 32) node out_romask_14 = orr(_out_romask_T_14) node _out_womask_T_14 = bits(out_backMask, 39, 32) node out_womask_14 = andr(_out_womask_T_14) node out_f_rivalid_14 = and(out_rivalid[14], out_rimask_14) node out_f_roready_14 = and(out_roready[14], out_romask_14) node out_f_wivalid_14 = and(out_wivalid[14], out_wimask_14) node out_f_woready_14 = and(out_woready[14], out_womask_14) node _out_T_158 = bits(out_front.bits.data, 39, 32) connect valids[4], out_f_woready_14 when out_f_woready_14 : connect newBytes[4], _out_T_158 node _out_T_159 = and(out_f_rivalid_14, UInt<1>(0h1)) node _out_T_160 = and(UInt<1>(0h1), out_f_roready_14) node _out_T_161 = and(out_f_wivalid_14, UInt<1>(0h1)) node _out_T_162 = and(UInt<1>(0h1), out_f_woready_14) node _out_T_163 = eq(out_rimask_14, UInt<1>(0h0)) node _out_T_164 = eq(out_wimask_14, UInt<1>(0h0)) node _out_T_165 = eq(out_romask_14, UInt<1>(0h0)) node _out_T_166 = eq(out_womask_14, UInt<1>(0h0)) node _out_prepend_T_11 = or(_out_T_157, UInt<32>(0h0)) node out_prepend_11 = cat(oldBytes[4], _out_prepend_T_11) node _out_T_167 = or(out_prepend_11, UInt<40>(0h0)) node _out_T_168 = bits(_out_T_167, 39, 0) node _out_rimask_T_15 = bits(out_frontMask, 47, 40) node out_rimask_15 = orr(_out_rimask_T_15) node _out_wimask_T_15 = bits(out_frontMask, 47, 40) node out_wimask_15 = andr(_out_wimask_T_15) node _out_romask_T_15 = bits(out_backMask, 47, 40) node out_romask_15 = orr(_out_romask_T_15) node _out_womask_T_15 = bits(out_backMask, 47, 40) node out_womask_15 = andr(_out_womask_T_15) node out_f_rivalid_15 = and(out_rivalid[15], out_rimask_15) node out_f_roready_15 = and(out_roready[15], out_romask_15) node out_f_wivalid_15 = and(out_wivalid[15], out_wimask_15) node out_f_woready_15 = and(out_woready[15], out_womask_15) node _out_T_169 = bits(out_front.bits.data, 47, 40) connect valids[5], out_f_woready_15 when out_f_woready_15 : connect newBytes[5], _out_T_169 node _out_T_170 = and(out_f_rivalid_15, UInt<1>(0h1)) node _out_T_171 = and(UInt<1>(0h1), out_f_roready_15) node _out_T_172 = and(out_f_wivalid_15, UInt<1>(0h1)) node _out_T_173 = and(UInt<1>(0h1), out_f_woready_15) node _out_T_174 = eq(out_rimask_15, UInt<1>(0h0)) node _out_T_175 = eq(out_wimask_15, UInt<1>(0h0)) node _out_T_176 = eq(out_romask_15, UInt<1>(0h0)) node _out_T_177 = eq(out_womask_15, UInt<1>(0h0)) node _out_prepend_T_12 = or(_out_T_168, UInt<40>(0h0)) node out_prepend_12 = cat(oldBytes[5], _out_prepend_T_12) node _out_T_178 = or(out_prepend_12, UInt<48>(0h0)) node _out_T_179 = bits(_out_T_178, 47, 0) node _out_rimask_T_16 = bits(out_frontMask, 55, 48) node out_rimask_16 = orr(_out_rimask_T_16) node _out_wimask_T_16 = bits(out_frontMask, 55, 48) node out_wimask_16 = andr(_out_wimask_T_16) node _out_romask_T_16 = bits(out_backMask, 55, 48) node out_romask_16 = orr(_out_romask_T_16) node _out_womask_T_16 = bits(out_backMask, 55, 48) node out_womask_16 = andr(_out_womask_T_16) node out_f_rivalid_16 = and(out_rivalid[16], out_rimask_16) node out_f_roready_16 = and(out_roready[16], out_romask_16) node out_f_wivalid_16 = and(out_wivalid[16], out_wimask_16) node out_f_woready_16 = and(out_woready[16], out_womask_16) node _out_T_180 = bits(out_front.bits.data, 55, 48) connect valids[6], out_f_woready_16 when out_f_woready_16 : connect newBytes[6], _out_T_180 node _out_T_181 = and(out_f_rivalid_16, UInt<1>(0h1)) node _out_T_182 = and(UInt<1>(0h1), out_f_roready_16) node _out_T_183 = and(out_f_wivalid_16, UInt<1>(0h1)) node _out_T_184 = and(UInt<1>(0h1), out_f_woready_16) node _out_T_185 = eq(out_rimask_16, UInt<1>(0h0)) node _out_T_186 = eq(out_wimask_16, UInt<1>(0h0)) node _out_T_187 = eq(out_romask_16, UInt<1>(0h0)) node _out_T_188 = eq(out_womask_16, UInt<1>(0h0)) node _out_prepend_T_13 = or(_out_T_179, UInt<48>(0h0)) node out_prepend_13 = cat(oldBytes[6], _out_prepend_T_13) node _out_T_189 = or(out_prepend_13, UInt<56>(0h0)) node _out_T_190 = bits(_out_T_189, 55, 0) node _out_rimask_T_17 = bits(out_frontMask, 63, 56) node out_rimask_17 = orr(_out_rimask_T_17) node _out_wimask_T_17 = bits(out_frontMask, 63, 56) node out_wimask_17 = andr(_out_wimask_T_17) node _out_romask_T_17 = bits(out_backMask, 63, 56) node out_romask_17 = orr(_out_romask_T_17) node _out_womask_T_17 = bits(out_backMask, 63, 56) node out_womask_17 = andr(_out_womask_T_17) node out_f_rivalid_17 = and(out_rivalid[17], out_rimask_17) node out_f_roready_17 = and(out_roready[17], out_romask_17) node out_f_wivalid_17 = and(out_wivalid[17], out_wimask_17) node out_f_woready_17 = and(out_woready[17], out_womask_17) node _out_T_191 = bits(out_front.bits.data, 63, 56) connect valids[7], out_f_woready_17 when out_f_woready_17 : connect newBytes[7], _out_T_191 node _out_T_192 = and(out_f_rivalid_17, UInt<1>(0h1)) node _out_T_193 = and(UInt<1>(0h1), out_f_roready_17) node _out_T_194 = and(out_f_wivalid_17, UInt<1>(0h1)) node _out_T_195 = and(UInt<1>(0h1), out_f_woready_17) node _out_T_196 = eq(out_rimask_17, UInt<1>(0h0)) node _out_T_197 = eq(out_wimask_17, UInt<1>(0h0)) node _out_T_198 = eq(out_romask_17, UInt<1>(0h0)) node _out_T_199 = eq(out_womask_17, UInt<1>(0h0)) node _out_prepend_T_14 = or(_out_T_190, UInt<56>(0h0)) node out_prepend_14 = cat(oldBytes[7], _out_prepend_T_14) node _out_T_200 = or(out_prepend_14, UInt<64>(0h0)) node _out_T_201 = bits(_out_T_200, 63, 0) node _out_iindex_T = bits(out_front.bits.index, 0, 0) node _out_iindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_iindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_iindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_iindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_iindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_iindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_iindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_iindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_iindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_iindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_iindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_iindex_T_12 = bits(out_front.bits.index, 12, 12) node out_iindex = cat(_out_iindex_T_12, _out_iindex_T_11) node _out_oindex_T = bits(out_front.bits.index, 0, 0) node _out_oindex_T_1 = bits(out_front.bits.index, 1, 1) node _out_oindex_T_2 = bits(out_front.bits.index, 2, 2) node _out_oindex_T_3 = bits(out_front.bits.index, 3, 3) node _out_oindex_T_4 = bits(out_front.bits.index, 4, 4) node _out_oindex_T_5 = bits(out_front.bits.index, 5, 5) node _out_oindex_T_6 = bits(out_front.bits.index, 6, 6) node _out_oindex_T_7 = bits(out_front.bits.index, 7, 7) node _out_oindex_T_8 = bits(out_front.bits.index, 8, 8) node _out_oindex_T_9 = bits(out_front.bits.index, 9, 9) node _out_oindex_T_10 = bits(out_front.bits.index, 10, 10) node _out_oindex_T_11 = bits(out_front.bits.index, 11, 11) node _out_oindex_T_12 = bits(out_front.bits.index, 12, 12) node out_oindex = cat(_out_oindex_T_12, _out_oindex_T_11) node _out_frontSel_T = dshl(UInt<1>(0h1), out_iindex) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node out_frontSel_2 = bits(_out_frontSel_T, 2, 2) node out_frontSel_3 = bits(_out_frontSel_T, 3, 3) node _out_backSel_T = dshl(UInt<1>(0h1), out_oindex) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node out_backSel_2 = bits(_out_backSel_T, 2, 2) node out_backSel_3 = bits(_out_backSel_T, 3, 3) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[1], _out_rifireMux_T_3 connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) wire out_rifireMux_out_1 : UInt<1> node _out_rifireMux_T_6 = and(_out_rifireMux_T_1, out_frontSel_1) node _out_rifireMux_T_7 = and(_out_rifireMux_T_6, _out_T_4) connect out_rifireMux_out_1, UInt<1>(0h1) connect out_rivalid[17], _out_rifireMux_T_7 connect out_rivalid[16], _out_rifireMux_T_7 connect out_rivalid[15], _out_rifireMux_T_7 connect out_rivalid[14], _out_rifireMux_T_7 connect out_rivalid[13], _out_rifireMux_T_7 connect out_rivalid[12], _out_rifireMux_T_7 connect out_rivalid[11], _out_rifireMux_T_7 connect out_rivalid[10], _out_rifireMux_T_7 node _out_rifireMux_T_8 = eq(_out_T_4, UInt<1>(0h0)) node _out_rifireMux_T_9 = or(out_rifireMux_out_1, _out_rifireMux_T_8) wire out_rifireMux_out_2 : UInt<1> node _out_rifireMux_T_10 = and(_out_rifireMux_T_1, out_frontSel_2) node _out_rifireMux_T_11 = and(_out_rifireMux_T_10, _out_T_2) connect out_rifireMux_out_2, UInt<1>(0h1) connect out_rivalid[9], _out_rifireMux_T_11 connect out_rivalid[8], _out_rifireMux_T_11 connect out_rivalid[7], _out_rifireMux_T_11 connect out_rivalid[6], _out_rifireMux_T_11 connect out_rivalid[5], _out_rifireMux_T_11 connect out_rivalid[4], _out_rifireMux_T_11 connect out_rivalid[3], _out_rifireMux_T_11 connect out_rivalid[2], _out_rifireMux_T_11 node _out_rifireMux_T_12 = eq(_out_T_2, UInt<1>(0h0)) node _out_rifireMux_T_13 = or(out_rifireMux_out_2, _out_rifireMux_T_12) wire out_rifireMux_out_3 : UInt<1> node _out_rifireMux_T_14 = and(_out_rifireMux_T_1, out_frontSel_3) node _out_rifireMux_T_15 = and(_out_rifireMux_T_14, UInt<1>(0h1)) connect out_rifireMux_out_3, UInt<1>(0h1) node _out_rifireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rifireMux_T_17 = or(out_rifireMux_out_3, _out_rifireMux_T_16) node _out_rifireMux_T_18 = geq(out_iindex, UInt<3>(0h4)) wire _out_rifireMux_WIRE : UInt<1>[4] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 connect _out_rifireMux_WIRE[1], _out_rifireMux_T_9 connect _out_rifireMux_WIRE[2], _out_rifireMux_T_13 connect _out_rifireMux_WIRE[3], _out_rifireMux_T_17 node out_rifireMux = mux(_out_rifireMux_T_18, UInt<1>(0h1), _out_rifireMux_WIRE[out_iindex]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[1], _out_wifireMux_T_4 connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) wire out_wifireMux_out_1 : UInt<1> node _out_wifireMux_T_7 = and(_out_wifireMux_T_2, out_frontSel_1) node _out_wifireMux_T_8 = and(_out_wifireMux_T_7, _out_T_4) connect out_wifireMux_out_1, UInt<1>(0h1) connect out_wivalid[17], _out_wifireMux_T_8 connect out_wivalid[16], _out_wifireMux_T_8 connect out_wivalid[15], _out_wifireMux_T_8 connect out_wivalid[14], _out_wifireMux_T_8 connect out_wivalid[13], _out_wifireMux_T_8 connect out_wivalid[12], _out_wifireMux_T_8 connect out_wivalid[11], _out_wifireMux_T_8 connect out_wivalid[10], _out_wifireMux_T_8 node _out_wifireMux_T_9 = eq(_out_T_4, UInt<1>(0h0)) node _out_wifireMux_T_10 = or(out_wifireMux_out_1, _out_wifireMux_T_9) wire out_wifireMux_out_2 : UInt<1> node _out_wifireMux_T_11 = and(_out_wifireMux_T_2, out_frontSel_2) node _out_wifireMux_T_12 = and(_out_wifireMux_T_11, _out_T_2) connect out_wifireMux_out_2, UInt<1>(0h1) connect out_wivalid[9], _out_wifireMux_T_12 connect out_wivalid[8], _out_wifireMux_T_12 connect out_wivalid[7], _out_wifireMux_T_12 connect out_wivalid[6], _out_wifireMux_T_12 connect out_wivalid[5], _out_wifireMux_T_12 connect out_wivalid[4], _out_wifireMux_T_12 connect out_wivalid[3], _out_wifireMux_T_12 connect out_wivalid[2], _out_wifireMux_T_12 node _out_wifireMux_T_13 = eq(_out_T_2, UInt<1>(0h0)) node _out_wifireMux_T_14 = or(out_wifireMux_out_2, _out_wifireMux_T_13) wire out_wifireMux_out_3 : UInt<1> node _out_wifireMux_T_15 = and(_out_wifireMux_T_2, out_frontSel_3) node _out_wifireMux_T_16 = and(_out_wifireMux_T_15, UInt<1>(0h1)) connect out_wifireMux_out_3, UInt<1>(0h1) node _out_wifireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wifireMux_T_18 = or(out_wifireMux_out_3, _out_wifireMux_T_17) node _out_wifireMux_T_19 = geq(out_iindex, UInt<3>(0h4)) wire _out_wifireMux_WIRE : UInt<1>[4] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 connect _out_wifireMux_WIRE[1], _out_wifireMux_T_10 connect _out_wifireMux_WIRE[2], _out_wifireMux_T_14 connect _out_wifireMux_WIRE[3], _out_wifireMux_T_18 node out_wifireMux = mux(_out_wifireMux_T_19, UInt<1>(0h1), _out_wifireMux_WIRE[out_iindex]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[1], _out_rofireMux_T_3 connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) wire out_rofireMux_out_1 : UInt<1> node _out_rofireMux_T_6 = and(_out_rofireMux_T_1, out_backSel_1) node _out_rofireMux_T_7 = and(_out_rofireMux_T_6, _out_T_5) connect out_rofireMux_out_1, UInt<1>(0h1) connect out_roready[17], _out_rofireMux_T_7 connect out_roready[16], _out_rofireMux_T_7 connect out_roready[15], _out_rofireMux_T_7 connect out_roready[14], _out_rofireMux_T_7 connect out_roready[13], _out_rofireMux_T_7 connect out_roready[12], _out_rofireMux_T_7 connect out_roready[11], _out_rofireMux_T_7 connect out_roready[10], _out_rofireMux_T_7 node _out_rofireMux_T_8 = eq(_out_T_5, UInt<1>(0h0)) node _out_rofireMux_T_9 = or(out_rofireMux_out_1, _out_rofireMux_T_8) wire out_rofireMux_out_2 : UInt<1> node _out_rofireMux_T_10 = and(_out_rofireMux_T_1, out_backSel_2) node _out_rofireMux_T_11 = and(_out_rofireMux_T_10, _out_T_3) connect out_rofireMux_out_2, UInt<1>(0h1) connect out_roready[9], _out_rofireMux_T_11 connect out_roready[8], _out_rofireMux_T_11 connect out_roready[7], _out_rofireMux_T_11 connect out_roready[6], _out_rofireMux_T_11 connect out_roready[5], _out_rofireMux_T_11 connect out_roready[4], _out_rofireMux_T_11 connect out_roready[3], _out_rofireMux_T_11 connect out_roready[2], _out_rofireMux_T_11 node _out_rofireMux_T_12 = eq(_out_T_3, UInt<1>(0h0)) node _out_rofireMux_T_13 = or(out_rofireMux_out_2, _out_rofireMux_T_12) wire out_rofireMux_out_3 : UInt<1> node _out_rofireMux_T_14 = and(_out_rofireMux_T_1, out_backSel_3) node _out_rofireMux_T_15 = and(_out_rofireMux_T_14, UInt<1>(0h1)) connect out_rofireMux_out_3, UInt<1>(0h1) node _out_rofireMux_T_16 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_rofireMux_T_17 = or(out_rofireMux_out_3, _out_rofireMux_T_16) node _out_rofireMux_T_18 = geq(out_oindex, UInt<3>(0h4)) wire _out_rofireMux_WIRE : UInt<1>[4] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 connect _out_rofireMux_WIRE[1], _out_rofireMux_T_9 connect _out_rofireMux_WIRE[2], _out_rofireMux_T_13 connect _out_rofireMux_WIRE[3], _out_rofireMux_T_17 node out_rofireMux = mux(_out_rofireMux_T_18, UInt<1>(0h1), _out_rofireMux_WIRE[out_oindex]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[1], _out_wofireMux_T_4 connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) wire out_wofireMux_out_1 : UInt<1> node _out_wofireMux_T_7 = and(_out_wofireMux_T_2, out_backSel_1) node _out_wofireMux_T_8 = and(_out_wofireMux_T_7, _out_T_5) connect out_wofireMux_out_1, UInt<1>(0h1) connect out_woready[17], _out_wofireMux_T_8 connect out_woready[16], _out_wofireMux_T_8 connect out_woready[15], _out_wofireMux_T_8 connect out_woready[14], _out_wofireMux_T_8 connect out_woready[13], _out_wofireMux_T_8 connect out_woready[12], _out_wofireMux_T_8 connect out_woready[11], _out_wofireMux_T_8 connect out_woready[10], _out_wofireMux_T_8 node _out_wofireMux_T_9 = eq(_out_T_5, UInt<1>(0h0)) node _out_wofireMux_T_10 = or(out_wofireMux_out_1, _out_wofireMux_T_9) wire out_wofireMux_out_2 : UInt<1> node _out_wofireMux_T_11 = and(_out_wofireMux_T_2, out_backSel_2) node _out_wofireMux_T_12 = and(_out_wofireMux_T_11, _out_T_3) connect out_wofireMux_out_2, UInt<1>(0h1) connect out_woready[9], _out_wofireMux_T_12 connect out_woready[8], _out_wofireMux_T_12 connect out_woready[7], _out_wofireMux_T_12 connect out_woready[6], _out_wofireMux_T_12 connect out_woready[5], _out_wofireMux_T_12 connect out_woready[4], _out_wofireMux_T_12 connect out_woready[3], _out_wofireMux_T_12 connect out_woready[2], _out_wofireMux_T_12 node _out_wofireMux_T_13 = eq(_out_T_3, UInt<1>(0h0)) node _out_wofireMux_T_14 = or(out_wofireMux_out_2, _out_wofireMux_T_13) wire out_wofireMux_out_3 : UInt<1> node _out_wofireMux_T_15 = and(_out_wofireMux_T_2, out_backSel_3) node _out_wofireMux_T_16 = and(_out_wofireMux_T_15, UInt<1>(0h1)) connect out_wofireMux_out_3, UInt<1>(0h1) node _out_wofireMux_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _out_wofireMux_T_18 = or(out_wofireMux_out_3, _out_wofireMux_T_17) node _out_wofireMux_T_19 = geq(out_oindex, UInt<3>(0h4)) wire _out_wofireMux_WIRE : UInt<1>[4] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 connect _out_wofireMux_WIRE[1], _out_wofireMux_T_10 connect _out_wofireMux_WIRE[2], _out_wofireMux_T_14 connect _out_wofireMux_WIRE[3], _out_wofireMux_T_18 node out_wofireMux = mux(_out_wofireMux_T_19, UInt<1>(0h1), _out_wofireMux_WIRE[out_oindex]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE : UInt<1>[4] connect _out_out_bits_data_WIRE[0], _out_T_1 connect _out_out_bits_data_WIRE[1], _out_T_5 connect _out_out_bits_data_WIRE[2], _out_T_3 connect _out_out_bits_data_WIRE[3], UInt<1>(0h1) node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[out_oindex]) node _out_out_bits_data_T_2 = geq(out_oindex, UInt<3>(0h4)) wire _out_out_bits_data_WIRE_1 : UInt<64>[4] connect _out_out_bits_data_WIRE_1[0], _out_T_25 connect _out_out_bits_data_WIRE_1[1], _out_T_201 connect _out_out_bits_data_WIRE_1[2], _out_T_113 connect _out_out_bits_data_WIRE_1[3], UInt<1>(0h0) node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[out_oindex]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, nodeIn.a.valid connect nodeIn.a.ready, in.ready connect nodeIn.d.valid, out.valid connect out.ready, nodeIn.d.ready wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h0) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect nodeIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) invalidate nodeIn_d_bits_d.data connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode connect nodeIn.d.bits.data, out.bits.data node _nodeIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect nodeIn.d.bits.opcode, _nodeIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module CLINT( // @[CLINT.scala:65:9] input clock, // @[CLINT.scala:65:9] input reset, // @[CLINT.scala:65:9] output auto_int_out_0, // @[LazyModuleImp.scala:107:25] output auto_int_out_1, // @[LazyModuleImp.scala:107:25] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input io_rtcTick // @[CLINT.scala:69:16] ); wire out_front_valid; // @[RegisterRouter.scala:87:24] wire out_front_ready; // @[RegisterRouter.scala:87:24] wire out_bits_read; // @[RegisterRouter.scala:87:24] wire [10:0] out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [12:0] in_bits_index; // @[RegisterRouter.scala:73:18] wire in_bits_read; // @[RegisterRouter.scala:73:18] wire auto_in_a_valid_0 = auto_in_a_valid; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[CLINT.scala:65:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[CLINT.scala:65:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[CLINT.scala:65:9] wire [10:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[CLINT.scala:65:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[CLINT.scala:65:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[CLINT.scala:65:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[CLINT.scala:65:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[CLINT.scala:65:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[CLINT.scala:65:9] wire io_rtcTick_0 = io_rtcTick; // @[CLINT.scala:65:9] wire [12:0] out_maskMatch = 13'h7FF; // @[RegisterRouter.scala:87:24] wire [2:0] nodeIn_d_bits_d_opcode = 3'h0; // @[Edges.scala:792:17] wire [63:0] _out_out_bits_data_WIRE_1_3 = 64'h0; // @[MuxLiteral.scala:49:48] wire [63:0] nodeIn_d_bits_d_data = 64'h0; // @[Edges.scala:792:17] wire auto_in_d_bits_sink = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_denied = 1'h0; // @[CLINT.scala:65:9] wire auto_in_d_bits_corrupt = 1'h0; // @[CLINT.scala:65:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire _valids_WIRE_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_7 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_0 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_1 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_2 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_3 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_4 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_5 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_6 = 1'h0; // @[RegField.scala:153:53] wire _valids_WIRE_1_7 = 1'h0; // @[RegField.scala:153:53] wire _out_rifireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wifireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_rofireMux_T_16 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_18 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_wofireMux_T_17 = 1'h0; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_19 = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T = 1'h0; // @[MuxLiteral.scala:49:17] wire _out_out_bits_data_T_2 = 1'h0; // @[MuxLiteral.scala:49:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:792:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:792:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:792:17] wire intnodeOut_0; // @[MixedNode.scala:542:17] wire out_rifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wifireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wifireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wifireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wifireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_rofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_5 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_9 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_13 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_rofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_17 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_rofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_rofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_wofireMux_out = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_6 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_1 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_10 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_2 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_14 = 1'h1; // @[RegisterRouter.scala:87:24] wire out_wofireMux_out_3 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_18 = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_WIRE_0 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_1 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_2 = 1'h1; // @[MuxLiteral.scala:49:48] wire _out_wofireMux_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire out_wofireMux = 1'h1; // @[MuxLiteral.scala:49:10] wire out_iready = 1'h1; // @[RegisterRouter.scala:87:24] wire out_oready = 1'h1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_3 = 1'h1; // @[MuxLiteral.scala:49:48] wire intnodeOut_1; // @[MixedNode.scala:542:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[CLINT.scala:65:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[CLINT.scala:65:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[CLINT.scala:65:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[CLINT.scala:65:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[CLINT.scala:65:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[CLINT.scala:65:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[CLINT.scala:65:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[CLINT.scala:65:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [10:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_int_out_0_0; // @[CLINT.scala:65:9] wire auto_int_out_1_0; // @[CLINT.scala:65:9] wire auto_in_a_ready_0; // @[CLINT.scala:65:9] wire [2:0] auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] wire [1:0] auto_in_d_bits_size_0; // @[CLINT.scala:65:9] wire [10:0] auto_in_d_bits_source_0; // @[CLINT.scala:65:9] wire [63:0] auto_in_d_bits_data_0; // @[CLINT.scala:65:9] wire auto_in_d_valid_0; // @[CLINT.scala:65:9] wire in_ready; // @[RegisterRouter.scala:73:18] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[CLINT.scala:65:9] wire in_valid = nodeIn_a_valid; // @[RegisterRouter.scala:73:18] wire [1:0] in_bits_extra_tlrr_extra_size = nodeIn_a_bits_size; // @[RegisterRouter.scala:73:18] wire [10:0] in_bits_extra_tlrr_extra_source = nodeIn_a_bits_source; // @[RegisterRouter.scala:73:18] wire [7:0] in_bits_mask = nodeIn_a_bits_mask; // @[RegisterRouter.scala:73:18] wire [63:0] in_bits_data = nodeIn_a_bits_data; // @[RegisterRouter.scala:73:18] wire out_ready = nodeIn_d_ready; // @[RegisterRouter.scala:87:24] wire out_valid; // @[RegisterRouter.scala:87:24] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[CLINT.scala:65:9] wire [1:0] nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[CLINT.scala:65:9] wire [10:0] nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[CLINT.scala:65:9] wire [63:0] out_bits_data; // @[RegisterRouter.scala:87:24] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[CLINT.scala:65:9] wire _intnodeOut_0_T; // @[CLINT.scala:82:37] assign auto_int_out_0_0 = intnodeOut_0; // @[CLINT.scala:65:9] wire _intnodeOut_1_T; // @[CLINT.scala:83:43] assign auto_int_out_1_0 = intnodeOut_1; // @[CLINT.scala:65:9] reg [63:0] time_0; // @[CLINT.scala:73:23] wire [63:0] pad_1 = time_0; // @[RegField.scala:150:19] wire [64:0] _time_T = {1'h0, time_0} + 65'h1; // @[CLINT.scala:73:23, :74:38] wire [63:0] _time_T_1 = _time_T[63:0]; // @[CLINT.scala:74:38] reg [63:0] timecmp_0; // @[CLINT.scala:77:41] wire [63:0] pad = timecmp_0; // @[RegField.scala:150:19] reg ipi_0; // @[CLINT.scala:78:41] assign _intnodeOut_0_T = ipi_0; // @[CLINT.scala:78:41, :82:37] wire _out_T_15 = ipi_0; // @[RegisterRouter.scala:87:24] assign intnodeOut_0 = _intnodeOut_0_T; // @[CLINT.scala:82:37] assign _intnodeOut_1_T = time_0 >= timecmp_0; // @[CLINT.scala:73:23, :77:41, :83:43] assign intnodeOut_1 = _intnodeOut_1_T; // @[CLINT.scala:83:43] wire [7:0] _oldBytes_T = pad[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_0 = _oldBytes_T; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_1 = pad[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1 = _oldBytes_T_1; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_2 = pad[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_2 = _oldBytes_T_2; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_3 = pad[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_3 = _oldBytes_T_3; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_4 = pad[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_4 = _oldBytes_T_4; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_5 = pad[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_5 = _oldBytes_T_5; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_6 = pad[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_6 = _oldBytes_T_6; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_7 = pad[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_7 = _oldBytes_T_7; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_123 = oldBytes_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1; // @[RegField.scala:152:31] wire [7:0] newBytes_2; // @[RegField.scala:152:31] wire [7:0] newBytes_3; // @[RegField.scala:152:31] wire [7:0] newBytes_4; // @[RegField.scala:152:31] wire [7:0] newBytes_5; // @[RegField.scala:152:31] wire [7:0] newBytes_6; // @[RegField.scala:152:31] wire [7:0] newBytes_7; // @[RegField.scala:152:31] wire out_f_woready_10; // @[RegisterRouter.scala:87:24] wire out_f_woready_11; // @[RegisterRouter.scala:87:24] wire out_f_woready_12; // @[RegisterRouter.scala:87:24] wire out_f_woready_13; // @[RegisterRouter.scala:87:24] wire out_f_woready_14; // @[RegisterRouter.scala:87:24] wire out_f_woready_15; // @[RegisterRouter.scala:87:24] wire out_f_woready_16; // @[RegisterRouter.scala:87:24] wire out_f_woready_17; // @[RegisterRouter.scala:87:24] wire valids_0; // @[RegField.scala:153:29] wire valids_1; // @[RegField.scala:153:29] wire valids_2; // @[RegField.scala:153:29] wire valids_3; // @[RegField.scala:153:29] wire valids_4; // @[RegField.scala:153:29] wire valids_5; // @[RegField.scala:153:29] wire valids_6; // @[RegField.scala:153:29] wire valids_7; // @[RegField.scala:153:29] wire [15:0] timecmp_0_lo_lo = {newBytes_1, newBytes_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_lo_hi = {newBytes_3, newBytes_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_lo = {timecmp_0_lo_hi, timecmp_0_lo_lo}; // @[RegField.scala:154:52] wire [15:0] timecmp_0_hi_lo = {newBytes_5, newBytes_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] timecmp_0_hi_hi = {newBytes_7, newBytes_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] timecmp_0_hi = {timecmp_0_hi_hi, timecmp_0_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _timecmp_0_T = {timecmp_0_hi, timecmp_0_lo}; // @[RegField.scala:154:52] wire [7:0] _oldBytes_T_8 = pad_1[7:0]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_0 = _oldBytes_T_8; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_9 = pad_1[15:8]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_1 = _oldBytes_T_9; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_10 = pad_1[23:16]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_2 = _oldBytes_T_10; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_11 = pad_1[31:24]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_3 = _oldBytes_T_11; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_12 = pad_1[39:32]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_4 = _oldBytes_T_12; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_13 = pad_1[47:40]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_5 = _oldBytes_T_13; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_14 = pad_1[55:48]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_6 = _oldBytes_T_14; // @[RegField.scala:151:{47,57}] wire [7:0] _oldBytes_T_15 = pad_1[63:56]; // @[RegField.scala:150:19, :151:57] wire [7:0] oldBytes_1_7 = _oldBytes_T_15; // @[RegField.scala:151:{47,57}] wire [7:0] _out_T_35 = oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire [7:0] newBytes_1_0; // @[RegField.scala:152:31] wire [7:0] newBytes_1_1; // @[RegField.scala:152:31] wire [7:0] newBytes_1_2; // @[RegField.scala:152:31] wire [7:0] newBytes_1_3; // @[RegField.scala:152:31] wire [7:0] newBytes_1_4; // @[RegField.scala:152:31] wire [7:0] newBytes_1_5; // @[RegField.scala:152:31] wire [7:0] newBytes_1_6; // @[RegField.scala:152:31] wire [7:0] newBytes_1_7; // @[RegField.scala:152:31] wire out_f_woready_2; // @[RegisterRouter.scala:87:24] wire out_f_woready_3; // @[RegisterRouter.scala:87:24] wire out_f_woready_4; // @[RegisterRouter.scala:87:24] wire out_f_woready_5; // @[RegisterRouter.scala:87:24] wire out_f_woready_6; // @[RegisterRouter.scala:87:24] wire out_f_woready_7; // @[RegisterRouter.scala:87:24] wire out_f_woready_8; // @[RegisterRouter.scala:87:24] wire out_f_woready_9; // @[RegisterRouter.scala:87:24] wire valids_1_0; // @[RegField.scala:153:29] wire valids_1_1; // @[RegField.scala:153:29] wire valids_1_2; // @[RegField.scala:153:29] wire valids_1_3; // @[RegField.scala:153:29] wire valids_1_4; // @[RegField.scala:153:29] wire valids_1_5; // @[RegField.scala:153:29] wire valids_1_6; // @[RegField.scala:153:29] wire valids_1_7; // @[RegField.scala:153:29] wire [15:0] time_lo_lo = {newBytes_1_1, newBytes_1_0}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_lo_hi = {newBytes_1_3, newBytes_1_2}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_lo = {time_lo_hi, time_lo_lo}; // @[RegField.scala:154:52] wire [15:0] time_hi_lo = {newBytes_1_5, newBytes_1_4}; // @[RegField.scala:152:31, :154:52] wire [15:0] time_hi_hi = {newBytes_1_7, newBytes_1_6}; // @[RegField.scala:152:31, :154:52] wire [31:0] time_hi = {time_hi_hi, time_hi_lo}; // @[RegField.scala:154:52] wire [63:0] _time_T_2 = {time_hi, time_lo}; // @[RegField.scala:154:52] wire _out_in_ready_T; // @[RegisterRouter.scala:87:24] assign nodeIn_a_ready = in_ready; // @[RegisterRouter.scala:73:18] wire _in_bits_read_T; // @[RegisterRouter.scala:74:36] wire _out_front_valid_T = in_valid; // @[RegisterRouter.scala:73:18, :87:24] wire out_front_bits_read = in_bits_read; // @[RegisterRouter.scala:73:18, :87:24] wire [12:0] out_front_bits_index = in_bits_index; // @[RegisterRouter.scala:73:18, :87:24] wire [63:0] out_front_bits_data = in_bits_data; // @[RegisterRouter.scala:73:18, :87:24] wire [7:0] out_front_bits_mask = in_bits_mask; // @[RegisterRouter.scala:73:18, :87:24] wire [10:0] out_front_bits_extra_tlrr_extra_source = in_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:73:18, :87:24] wire [1:0] out_front_bits_extra_tlrr_extra_size = in_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:73:18, :87:24] assign _in_bits_read_T = nodeIn_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] assign in_bits_read = _in_bits_read_T; // @[RegisterRouter.scala:73:18, :74:36] wire [22:0] _in_bits_index_T = nodeIn_a_bits_address[25:3]; // @[Edges.scala:192:34] assign in_bits_index = _in_bits_index_T[12:0]; // @[RegisterRouter.scala:73:18, :75:19] wire _out_front_ready_T = out_ready; // @[RegisterRouter.scala:87:24] wire _out_out_valid_T; // @[RegisterRouter.scala:87:24] assign nodeIn_d_valid = out_valid; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] wire _nodeIn_d_bits_opcode_T = out_bits_read; // @[RegisterRouter.scala:87:24, :105:25] assign nodeIn_d_bits_data = out_bits_data; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_source = out_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] wire [1:0] out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_d_size = out_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] assign _out_in_ready_T = out_front_ready; // @[RegisterRouter.scala:87:24] assign _out_out_valid_T = out_front_valid; // @[RegisterRouter.scala:87:24] assign out_bits_read = out_front_bits_read; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_source = out_front_bits_extra_tlrr_extra_source; // @[RegisterRouter.scala:87:24] assign out_bits_extra_tlrr_extra_size = out_front_bits_extra_tlrr_extra_size; // @[RegisterRouter.scala:87:24] wire [12:0] _GEN = out_front_bits_index & 13'h7FF; // @[RegisterRouter.scala:87:24] wire [12:0] out_findex; // @[RegisterRouter.scala:87:24] assign out_findex = _GEN; // @[RegisterRouter.scala:87:24] wire [12:0] out_bindex; // @[RegisterRouter.scala:87:24] assign out_bindex = _GEN; // @[RegisterRouter.scala:87:24] wire _GEN_0 = out_findex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T; // @[RegisterRouter.scala:87:24] assign _out_T = _GEN_0; // @[RegisterRouter.scala:87:24] wire _out_T_4; // @[RegisterRouter.scala:87:24] assign _out_T_4 = _GEN_0; // @[RegisterRouter.scala:87:24] wire _GEN_1 = out_bindex == 13'h0; // @[RegisterRouter.scala:87:24] wire _out_T_1; // @[RegisterRouter.scala:87:24] assign _out_T_1 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_T_5; // @[RegisterRouter.scala:87:24] assign _out_T_5 = _GEN_1; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_0 = _out_T_1; // @[MuxLiteral.scala:49:48] wire _out_T_2 = out_findex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_T_3 = out_bindex == 13'h7FF; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_2 = _out_T_3; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_out_bits_data_WIRE_1 = _out_T_5; // @[MuxLiteral.scala:49:48] wire _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_0; // @[RegisterRouter.scala:87:24] wire out_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_rivalid_17; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_0; // @[RegisterRouter.scala:87:24] wire out_wivalid_1; // @[RegisterRouter.scala:87:24] wire out_wivalid_2; // @[RegisterRouter.scala:87:24] wire out_wivalid_3; // @[RegisterRouter.scala:87:24] wire out_wivalid_4; // @[RegisterRouter.scala:87:24] wire out_wivalid_5; // @[RegisterRouter.scala:87:24] wire out_wivalid_6; // @[RegisterRouter.scala:87:24] wire out_wivalid_7; // @[RegisterRouter.scala:87:24] wire out_wivalid_8; // @[RegisterRouter.scala:87:24] wire out_wivalid_9; // @[RegisterRouter.scala:87:24] wire out_wivalid_10; // @[RegisterRouter.scala:87:24] wire out_wivalid_11; // @[RegisterRouter.scala:87:24] wire out_wivalid_12; // @[RegisterRouter.scala:87:24] wire out_wivalid_13; // @[RegisterRouter.scala:87:24] wire out_wivalid_14; // @[RegisterRouter.scala:87:24] wire out_wivalid_15; // @[RegisterRouter.scala:87:24] wire out_wivalid_16; // @[RegisterRouter.scala:87:24] wire out_wivalid_17; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire out_roready_0; // @[RegisterRouter.scala:87:24] wire out_roready_1; // @[RegisterRouter.scala:87:24] wire out_roready_2; // @[RegisterRouter.scala:87:24] wire out_roready_3; // @[RegisterRouter.scala:87:24] wire out_roready_4; // @[RegisterRouter.scala:87:24] wire out_roready_5; // @[RegisterRouter.scala:87:24] wire out_roready_6; // @[RegisterRouter.scala:87:24] wire out_roready_7; // @[RegisterRouter.scala:87:24] wire out_roready_8; // @[RegisterRouter.scala:87:24] wire out_roready_9; // @[RegisterRouter.scala:87:24] wire out_roready_10; // @[RegisterRouter.scala:87:24] wire out_roready_11; // @[RegisterRouter.scala:87:24] wire out_roready_12; // @[RegisterRouter.scala:87:24] wire out_roready_13; // @[RegisterRouter.scala:87:24] wire out_roready_14; // @[RegisterRouter.scala:87:24] wire out_roready_15; // @[RegisterRouter.scala:87:24] wire out_roready_16; // @[RegisterRouter.scala:87:24] wire out_roready_17; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire out_woready_0; // @[RegisterRouter.scala:87:24] wire out_woready_1; // @[RegisterRouter.scala:87:24] wire out_woready_2; // @[RegisterRouter.scala:87:24] wire out_woready_3; // @[RegisterRouter.scala:87:24] wire out_woready_4; // @[RegisterRouter.scala:87:24] wire out_woready_5; // @[RegisterRouter.scala:87:24] wire out_woready_6; // @[RegisterRouter.scala:87:24] wire out_woready_7; // @[RegisterRouter.scala:87:24] wire out_woready_8; // @[RegisterRouter.scala:87:24] wire out_woready_9; // @[RegisterRouter.scala:87:24] wire out_woready_10; // @[RegisterRouter.scala:87:24] wire out_woready_11; // @[RegisterRouter.scala:87:24] wire out_woready_12; // @[RegisterRouter.scala:87:24] wire out_woready_13; // @[RegisterRouter.scala:87:24] wire out_woready_14; // @[RegisterRouter.scala:87:24] wire out_woready_15; // @[RegisterRouter.scala:87:24] wire out_woready_16; // @[RegisterRouter.scala:87:24] wire out_woready_17; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T = out_front_bits_mask[0]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_1 = out_front_bits_mask[1]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_2 = out_front_bits_mask[2]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_3 = out_front_bits_mask[3]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_4 = out_front_bits_mask[4]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_5 = out_front_bits_mask[5]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_6 = out_front_bits_mask[6]; // @[RegisterRouter.scala:87:24] wire _out_frontMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire _out_backMask_T_7 = out_front_bits_mask[7]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_8 = {8{_out_frontMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_9 = {8{_out_frontMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_10 = {8{_out_frontMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_11 = {8{_out_frontMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_12 = {8{_out_frontMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_13 = {8{_out_frontMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_14 = {8{_out_frontMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_frontMask_T_15 = {8{_out_frontMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_lo = {_out_frontMask_T_9, _out_frontMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_lo_hi = {_out_frontMask_T_11, _out_frontMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_lo = {out_frontMask_lo_hi, out_frontMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_lo = {_out_frontMask_T_13, _out_frontMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_frontMask_hi_hi = {_out_frontMask_T_15, _out_frontMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_frontMask_hi = {out_frontMask_hi_hi, out_frontMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_frontMask = {out_frontMask_hi, out_frontMask_lo}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_8 = {8{_out_backMask_T}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_9 = {8{_out_backMask_T_1}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_10 = {8{_out_backMask_T_2}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_11 = {8{_out_backMask_T_3}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_12 = {8{_out_backMask_T_4}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_13 = {8{_out_backMask_T_5}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_14 = {8{_out_backMask_T_6}}; // @[RegisterRouter.scala:87:24] wire [7:0] _out_backMask_T_15 = {8{_out_backMask_T_7}}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_lo = {_out_backMask_T_9, _out_backMask_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_lo_hi = {_out_backMask_T_11, _out_backMask_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_lo = {out_backMask_lo_hi, out_backMask_lo_lo}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_lo = {_out_backMask_T_13, _out_backMask_T_12}; // @[RegisterRouter.scala:87:24] wire [15:0] out_backMask_hi_hi = {_out_backMask_T_15, _out_backMask_T_14}; // @[RegisterRouter.scala:87:24] wire [31:0] out_backMask_hi = {out_backMask_hi_hi, out_backMask_hi_lo}; // @[RegisterRouter.scala:87:24] wire [63:0] out_backMask = {out_backMask_hi, out_backMask_lo}; // @[RegisterRouter.scala:87:24] wire _out_rimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire _out_wimask_T = out_frontMask[0]; // @[RegisterRouter.scala:87:24] wire out_rimask = _out_rimask_T; // @[RegisterRouter.scala:87:24] wire out_wimask = _out_wimask_T; // @[RegisterRouter.scala:87:24] wire _out_romask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire _out_womask_T = out_backMask[0]; // @[RegisterRouter.scala:87:24] wire out_romask = _out_romask_T; // @[RegisterRouter.scala:87:24] wire out_womask = _out_womask_T; // @[RegisterRouter.scala:87:24] wire out_f_rivalid = out_rivalid_0 & out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_7 = out_f_rivalid; // @[RegisterRouter.scala:87:24] wire out_f_roready = out_roready_0 & out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_8 = out_f_roready; // @[RegisterRouter.scala:87:24] wire out_f_wivalid = out_wivalid_0 & out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_9 = out_f_wivalid; // @[RegisterRouter.scala:87:24] wire out_f_woready = out_woready_0 & out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_10 = out_f_woready; // @[RegisterRouter.scala:87:24] wire _out_T_6 = out_front_bits_data[0]; // @[RegisterRouter.scala:87:24] wire _out_T_11 = ~out_rimask; // @[RegisterRouter.scala:87:24] wire _out_T_12 = ~out_wimask; // @[RegisterRouter.scala:87:24] wire _out_T_13 = ~out_romask; // @[RegisterRouter.scala:87:24] wire _out_T_14 = ~out_womask; // @[RegisterRouter.scala:87:24] wire _out_T_16 = _out_T_15; // @[RegisterRouter.scala:87:24] wire _out_prepend_T = _out_T_16; // @[RegisterRouter.scala:87:24] wire [30:0] _out_rimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_wimask_T_1 = out_frontMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_rimask_1 = |_out_rimask_T_1; // @[RegisterRouter.scala:87:24] wire out_wimask_1 = &_out_wimask_T_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_romask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire [30:0] _out_womask_T_1 = out_backMask[31:1]; // @[RegisterRouter.scala:87:24] wire out_romask_1 = |_out_romask_T_1; // @[RegisterRouter.scala:87:24] wire out_womask_1 = &_out_womask_T_1; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_1 = out_rivalid_1 & out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_18 = out_f_rivalid_1; // @[RegisterRouter.scala:87:24] wire out_f_roready_1 = out_roready_1 & out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_19 = out_f_roready_1; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_1 = out_wivalid_1 & out_wimask_1; // @[RegisterRouter.scala:87:24] wire out_f_woready_1 = out_woready_1 & out_womask_1; // @[RegisterRouter.scala:87:24] wire [30:0] _out_T_17 = out_front_bits_data[31:1]; // @[RegisterRouter.scala:87:24] wire _out_T_20 = ~out_rimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_21 = ~out_wimask_1; // @[RegisterRouter.scala:87:24] wire _out_T_22 = ~out_romask_1; // @[RegisterRouter.scala:87:24] wire _out_T_23 = ~out_womask_1; // @[RegisterRouter.scala:87:24] wire [1:0] out_prepend = {1'h0, _out_prepend_T}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_24 = {30'h0, out_prepend}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_25 = _out_T_24; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_2 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_10 = out_frontMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_rimask_2 = |_out_rimask_T_2; // @[RegisterRouter.scala:87:24] wire out_wimask_2 = &_out_wimask_T_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_2 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_10 = out_backMask[7:0]; // @[RegisterRouter.scala:87:24] wire out_romask_2 = |_out_romask_T_2; // @[RegisterRouter.scala:87:24] wire out_womask_2 = &_out_womask_T_2; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_2 = out_rivalid_2 & out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_27 = out_f_rivalid_2; // @[RegisterRouter.scala:87:24] wire out_f_roready_2 = out_roready_2 & out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_28 = out_f_roready_2; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_2 = out_wivalid_2 & out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_29 = out_f_wivalid_2; // @[RegisterRouter.scala:87:24] assign out_f_woready_2 = out_woready_2 & out_womask_2; // @[RegisterRouter.scala:87:24] assign valids_1_0 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire _out_T_30 = out_f_woready_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_26 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_114 = out_front_bits_data[7:0]; // @[RegisterRouter.scala:87:24] assign newBytes_1_0 = out_f_woready_2 ? _out_T_26 : oldBytes_1_0; // @[RegisterRouter.scala:87:24] wire _out_T_31 = ~out_rimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_32 = ~out_wimask_2; // @[RegisterRouter.scala:87:24] wire _out_T_33 = ~out_romask_2; // @[RegisterRouter.scala:87:24] wire _out_T_34 = ~out_womask_2; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_36 = _out_T_35; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_1 = _out_T_36; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_3 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_11 = out_frontMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_rimask_3 = |_out_rimask_T_3; // @[RegisterRouter.scala:87:24] wire out_wimask_3 = &_out_wimask_T_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_3 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_11 = out_backMask[15:8]; // @[RegisterRouter.scala:87:24] wire out_romask_3 = |_out_romask_T_3; // @[RegisterRouter.scala:87:24] wire out_womask_3 = &_out_womask_T_3; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_3 = out_rivalid_3 & out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_38 = out_f_rivalid_3; // @[RegisterRouter.scala:87:24] wire out_f_roready_3 = out_roready_3 & out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_39 = out_f_roready_3; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_3 = out_wivalid_3 & out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_40 = out_f_wivalid_3; // @[RegisterRouter.scala:87:24] assign out_f_woready_3 = out_woready_3 & out_womask_3; // @[RegisterRouter.scala:87:24] assign valids_1_1 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire _out_T_41 = out_f_woready_3; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_37 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_125 = out_front_bits_data[15:8]; // @[RegisterRouter.scala:87:24] assign newBytes_1_1 = out_f_woready_3 ? _out_T_37 : oldBytes_1_1; // @[RegisterRouter.scala:87:24] wire _out_T_42 = ~out_rimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_43 = ~out_wimask_3; // @[RegisterRouter.scala:87:24] wire _out_T_44 = ~out_romask_3; // @[RegisterRouter.scala:87:24] wire _out_T_45 = ~out_womask_3; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_1 = {oldBytes_1_1, _out_prepend_T_1}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_46 = out_prepend_1; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_47 = _out_T_46; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_2 = _out_T_47; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_4 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_12 = out_frontMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_rimask_4 = |_out_rimask_T_4; // @[RegisterRouter.scala:87:24] wire out_wimask_4 = &_out_wimask_T_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_4 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_12 = out_backMask[23:16]; // @[RegisterRouter.scala:87:24] wire out_romask_4 = |_out_romask_T_4; // @[RegisterRouter.scala:87:24] wire out_womask_4 = &_out_womask_T_4; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_4 = out_rivalid_4 & out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_49 = out_f_rivalid_4; // @[RegisterRouter.scala:87:24] wire out_f_roready_4 = out_roready_4 & out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_50 = out_f_roready_4; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_4 = out_wivalid_4 & out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_51 = out_f_wivalid_4; // @[RegisterRouter.scala:87:24] assign out_f_woready_4 = out_woready_4 & out_womask_4; // @[RegisterRouter.scala:87:24] assign valids_1_2 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire _out_T_52 = out_f_woready_4; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_48 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_136 = out_front_bits_data[23:16]; // @[RegisterRouter.scala:87:24] assign newBytes_1_2 = out_f_woready_4 ? _out_T_48 : oldBytes_1_2; // @[RegisterRouter.scala:87:24] wire _out_T_53 = ~out_rimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_54 = ~out_wimask_4; // @[RegisterRouter.scala:87:24] wire _out_T_55 = ~out_romask_4; // @[RegisterRouter.scala:87:24] wire _out_T_56 = ~out_womask_4; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_2 = {oldBytes_1_2, _out_prepend_T_2}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_57 = out_prepend_2; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_58 = _out_T_57; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_3 = _out_T_58; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_5 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_13 = out_frontMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_rimask_5 = |_out_rimask_T_5; // @[RegisterRouter.scala:87:24] wire out_wimask_5 = &_out_wimask_T_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_5 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_13 = out_backMask[31:24]; // @[RegisterRouter.scala:87:24] wire out_romask_5 = |_out_romask_T_5; // @[RegisterRouter.scala:87:24] wire out_womask_5 = &_out_womask_T_5; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_5 = out_rivalid_5 & out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_60 = out_f_rivalid_5; // @[RegisterRouter.scala:87:24] wire out_f_roready_5 = out_roready_5 & out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_61 = out_f_roready_5; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_5 = out_wivalid_5 & out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_62 = out_f_wivalid_5; // @[RegisterRouter.scala:87:24] assign out_f_woready_5 = out_woready_5 & out_womask_5; // @[RegisterRouter.scala:87:24] assign valids_1_3 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire _out_T_63 = out_f_woready_5; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_59 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_147 = out_front_bits_data[31:24]; // @[RegisterRouter.scala:87:24] assign newBytes_1_3 = out_f_woready_5 ? _out_T_59 : oldBytes_1_3; // @[RegisterRouter.scala:87:24] wire _out_T_64 = ~out_rimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_65 = ~out_wimask_5; // @[RegisterRouter.scala:87:24] wire _out_T_66 = ~out_romask_5; // @[RegisterRouter.scala:87:24] wire _out_T_67 = ~out_womask_5; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_3 = {oldBytes_1_3, _out_prepend_T_3}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_68 = out_prepend_3; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_69 = _out_T_68; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_4 = _out_T_69; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_6 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_14 = out_frontMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_rimask_6 = |_out_rimask_T_6; // @[RegisterRouter.scala:87:24] wire out_wimask_6 = &_out_wimask_T_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_6 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_14 = out_backMask[39:32]; // @[RegisterRouter.scala:87:24] wire out_romask_6 = |_out_romask_T_6; // @[RegisterRouter.scala:87:24] wire out_womask_6 = &_out_womask_T_6; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_6 = out_rivalid_6 & out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_71 = out_f_rivalid_6; // @[RegisterRouter.scala:87:24] wire out_f_roready_6 = out_roready_6 & out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_72 = out_f_roready_6; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_6 = out_wivalid_6 & out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_73 = out_f_wivalid_6; // @[RegisterRouter.scala:87:24] assign out_f_woready_6 = out_woready_6 & out_womask_6; // @[RegisterRouter.scala:87:24] assign valids_1_4 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire _out_T_74 = out_f_woready_6; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_70 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_158 = out_front_bits_data[39:32]; // @[RegisterRouter.scala:87:24] assign newBytes_1_4 = out_f_woready_6 ? _out_T_70 : oldBytes_1_4; // @[RegisterRouter.scala:87:24] wire _out_T_75 = ~out_rimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_76 = ~out_wimask_6; // @[RegisterRouter.scala:87:24] wire _out_T_77 = ~out_romask_6; // @[RegisterRouter.scala:87:24] wire _out_T_78 = ~out_womask_6; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_4 = {oldBytes_1_4, _out_prepend_T_4}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_79 = out_prepend_4; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_80 = _out_T_79; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_5 = _out_T_80; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_7 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_15 = out_frontMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_rimask_7 = |_out_rimask_T_7; // @[RegisterRouter.scala:87:24] wire out_wimask_7 = &_out_wimask_T_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_7 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_15 = out_backMask[47:40]; // @[RegisterRouter.scala:87:24] wire out_romask_7 = |_out_romask_T_7; // @[RegisterRouter.scala:87:24] wire out_womask_7 = &_out_womask_T_7; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_7 = out_rivalid_7 & out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_82 = out_f_rivalid_7; // @[RegisterRouter.scala:87:24] wire out_f_roready_7 = out_roready_7 & out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_83 = out_f_roready_7; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_7 = out_wivalid_7 & out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_84 = out_f_wivalid_7; // @[RegisterRouter.scala:87:24] assign out_f_woready_7 = out_woready_7 & out_womask_7; // @[RegisterRouter.scala:87:24] assign valids_1_5 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire _out_T_85 = out_f_woready_7; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_81 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_169 = out_front_bits_data[47:40]; // @[RegisterRouter.scala:87:24] assign newBytes_1_5 = out_f_woready_7 ? _out_T_81 : oldBytes_1_5; // @[RegisterRouter.scala:87:24] wire _out_T_86 = ~out_rimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_87 = ~out_wimask_7; // @[RegisterRouter.scala:87:24] wire _out_T_88 = ~out_romask_7; // @[RegisterRouter.scala:87:24] wire _out_T_89 = ~out_womask_7; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_5 = {oldBytes_1_5, _out_prepend_T_5}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_90 = out_prepend_5; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_91 = _out_T_90; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_6 = _out_T_91; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_8 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_16 = out_frontMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_rimask_8 = |_out_rimask_T_8; // @[RegisterRouter.scala:87:24] wire out_wimask_8 = &_out_wimask_T_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_8 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_16 = out_backMask[55:48]; // @[RegisterRouter.scala:87:24] wire out_romask_8 = |_out_romask_T_8; // @[RegisterRouter.scala:87:24] wire out_womask_8 = &_out_womask_T_8; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_8 = out_rivalid_8 & out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_93 = out_f_rivalid_8; // @[RegisterRouter.scala:87:24] wire out_f_roready_8 = out_roready_8 & out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_94 = out_f_roready_8; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_8 = out_wivalid_8 & out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_95 = out_f_wivalid_8; // @[RegisterRouter.scala:87:24] assign out_f_woready_8 = out_woready_8 & out_womask_8; // @[RegisterRouter.scala:87:24] assign valids_1_6 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire _out_T_96 = out_f_woready_8; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_92 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_180 = out_front_bits_data[55:48]; // @[RegisterRouter.scala:87:24] assign newBytes_1_6 = out_f_woready_8 ? _out_T_92 : oldBytes_1_6; // @[RegisterRouter.scala:87:24] wire _out_T_97 = ~out_rimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_98 = ~out_wimask_8; // @[RegisterRouter.scala:87:24] wire _out_T_99 = ~out_romask_8; // @[RegisterRouter.scala:87:24] wire _out_T_100 = ~out_womask_8; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_6 = {oldBytes_1_6, _out_prepend_T_6}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_101 = out_prepend_6; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_102 = _out_T_101; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_7 = _out_T_102; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_9 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_rimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_wimask_T_17 = out_frontMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_rimask_9 = |_out_rimask_T_9; // @[RegisterRouter.scala:87:24] wire out_wimask_9 = &_out_wimask_T_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_9 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_romask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_womask_T_17 = out_backMask[63:56]; // @[RegisterRouter.scala:87:24] wire out_romask_9 = |_out_romask_T_9; // @[RegisterRouter.scala:87:24] wire out_womask_9 = &_out_womask_T_9; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_9 = out_rivalid_9 & out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_104 = out_f_rivalid_9; // @[RegisterRouter.scala:87:24] wire out_f_roready_9 = out_roready_9 & out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_105 = out_f_roready_9; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_9 = out_wivalid_9 & out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_106 = out_f_wivalid_9; // @[RegisterRouter.scala:87:24] assign out_f_woready_9 = out_woready_9 & out_womask_9; // @[RegisterRouter.scala:87:24] assign valids_1_7 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire _out_T_107 = out_f_woready_9; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_103 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_191 = out_front_bits_data[63:56]; // @[RegisterRouter.scala:87:24] assign newBytes_1_7 = out_f_woready_9 ? _out_T_103 : oldBytes_1_7; // @[RegisterRouter.scala:87:24] wire _out_T_108 = ~out_rimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_109 = ~out_wimask_9; // @[RegisterRouter.scala:87:24] wire _out_T_110 = ~out_romask_9; // @[RegisterRouter.scala:87:24] wire _out_T_111 = ~out_womask_9; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_7 = {oldBytes_1_7, _out_prepend_T_7}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_112 = out_prepend_7; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_113 = _out_T_112; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_2 = _out_T_113; // @[MuxLiteral.scala:49:48] wire out_rimask_10 = |_out_rimask_T_10; // @[RegisterRouter.scala:87:24] wire out_wimask_10 = &_out_wimask_T_10; // @[RegisterRouter.scala:87:24] wire out_romask_10 = |_out_romask_T_10; // @[RegisterRouter.scala:87:24] wire out_womask_10 = &_out_womask_T_10; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_10 = out_rivalid_10 & out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_115 = out_f_rivalid_10; // @[RegisterRouter.scala:87:24] wire out_f_roready_10 = out_roready_10 & out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_116 = out_f_roready_10; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_10 = out_wivalid_10 & out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_117 = out_f_wivalid_10; // @[RegisterRouter.scala:87:24] assign out_f_woready_10 = out_woready_10 & out_womask_10; // @[RegisterRouter.scala:87:24] assign valids_0 = out_f_woready_10; // @[RegisterRouter.scala:87:24] wire _out_T_118 = out_f_woready_10; // @[RegisterRouter.scala:87:24] assign newBytes_0 = out_f_woready_10 ? _out_T_114 : oldBytes_0; // @[RegisterRouter.scala:87:24] wire _out_T_119 = ~out_rimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_120 = ~out_wimask_10; // @[RegisterRouter.scala:87:24] wire _out_T_121 = ~out_romask_10; // @[RegisterRouter.scala:87:24] wire _out_T_122 = ~out_womask_10; // @[RegisterRouter.scala:87:24] wire [7:0] _out_T_124 = _out_T_123; // @[RegisterRouter.scala:87:24] wire [7:0] _out_prepend_T_8 = _out_T_124; // @[RegisterRouter.scala:87:24] wire out_rimask_11 = |_out_rimask_T_11; // @[RegisterRouter.scala:87:24] wire out_wimask_11 = &_out_wimask_T_11; // @[RegisterRouter.scala:87:24] wire out_romask_11 = |_out_romask_T_11; // @[RegisterRouter.scala:87:24] wire out_womask_11 = &_out_womask_T_11; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_11 = out_rivalid_11 & out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_126 = out_f_rivalid_11; // @[RegisterRouter.scala:87:24] wire out_f_roready_11 = out_roready_11 & out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_127 = out_f_roready_11; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_11 = out_wivalid_11 & out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_128 = out_f_wivalid_11; // @[RegisterRouter.scala:87:24] assign out_f_woready_11 = out_woready_11 & out_womask_11; // @[RegisterRouter.scala:87:24] assign valids_1 = out_f_woready_11; // @[RegisterRouter.scala:87:24] wire _out_T_129 = out_f_woready_11; // @[RegisterRouter.scala:87:24] assign newBytes_1 = out_f_woready_11 ? _out_T_125 : oldBytes_1; // @[RegisterRouter.scala:87:24] wire _out_T_130 = ~out_rimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_131 = ~out_wimask_11; // @[RegisterRouter.scala:87:24] wire _out_T_132 = ~out_romask_11; // @[RegisterRouter.scala:87:24] wire _out_T_133 = ~out_womask_11; // @[RegisterRouter.scala:87:24] wire [15:0] out_prepend_8 = {oldBytes_1, _out_prepend_T_8}; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_134 = out_prepend_8; // @[RegisterRouter.scala:87:24] wire [15:0] _out_T_135 = _out_T_134; // @[RegisterRouter.scala:87:24] wire [15:0] _out_prepend_T_9 = _out_T_135; // @[RegisterRouter.scala:87:24] wire out_rimask_12 = |_out_rimask_T_12; // @[RegisterRouter.scala:87:24] wire out_wimask_12 = &_out_wimask_T_12; // @[RegisterRouter.scala:87:24] wire out_romask_12 = |_out_romask_T_12; // @[RegisterRouter.scala:87:24] wire out_womask_12 = &_out_womask_T_12; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_12 = out_rivalid_12 & out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_137 = out_f_rivalid_12; // @[RegisterRouter.scala:87:24] wire out_f_roready_12 = out_roready_12 & out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_138 = out_f_roready_12; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_12 = out_wivalid_12 & out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_139 = out_f_wivalid_12; // @[RegisterRouter.scala:87:24] assign out_f_woready_12 = out_woready_12 & out_womask_12; // @[RegisterRouter.scala:87:24] assign valids_2 = out_f_woready_12; // @[RegisterRouter.scala:87:24] wire _out_T_140 = out_f_woready_12; // @[RegisterRouter.scala:87:24] assign newBytes_2 = out_f_woready_12 ? _out_T_136 : oldBytes_2; // @[RegisterRouter.scala:87:24] wire _out_T_141 = ~out_rimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_142 = ~out_wimask_12; // @[RegisterRouter.scala:87:24] wire _out_T_143 = ~out_romask_12; // @[RegisterRouter.scala:87:24] wire _out_T_144 = ~out_womask_12; // @[RegisterRouter.scala:87:24] wire [23:0] out_prepend_9 = {oldBytes_2, _out_prepend_T_9}; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_145 = out_prepend_9; // @[RegisterRouter.scala:87:24] wire [23:0] _out_T_146 = _out_T_145; // @[RegisterRouter.scala:87:24] wire [23:0] _out_prepend_T_10 = _out_T_146; // @[RegisterRouter.scala:87:24] wire out_rimask_13 = |_out_rimask_T_13; // @[RegisterRouter.scala:87:24] wire out_wimask_13 = &_out_wimask_T_13; // @[RegisterRouter.scala:87:24] wire out_romask_13 = |_out_romask_T_13; // @[RegisterRouter.scala:87:24] wire out_womask_13 = &_out_womask_T_13; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_13 = out_rivalid_13 & out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_148 = out_f_rivalid_13; // @[RegisterRouter.scala:87:24] wire out_f_roready_13 = out_roready_13 & out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_149 = out_f_roready_13; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_13 = out_wivalid_13 & out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_150 = out_f_wivalid_13; // @[RegisterRouter.scala:87:24] assign out_f_woready_13 = out_woready_13 & out_womask_13; // @[RegisterRouter.scala:87:24] assign valids_3 = out_f_woready_13; // @[RegisterRouter.scala:87:24] wire _out_T_151 = out_f_woready_13; // @[RegisterRouter.scala:87:24] assign newBytes_3 = out_f_woready_13 ? _out_T_147 : oldBytes_3; // @[RegisterRouter.scala:87:24] wire _out_T_152 = ~out_rimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_153 = ~out_wimask_13; // @[RegisterRouter.scala:87:24] wire _out_T_154 = ~out_romask_13; // @[RegisterRouter.scala:87:24] wire _out_T_155 = ~out_womask_13; // @[RegisterRouter.scala:87:24] wire [31:0] out_prepend_10 = {oldBytes_3, _out_prepend_T_10}; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_156 = out_prepend_10; // @[RegisterRouter.scala:87:24] wire [31:0] _out_T_157 = _out_T_156; // @[RegisterRouter.scala:87:24] wire [31:0] _out_prepend_T_11 = _out_T_157; // @[RegisterRouter.scala:87:24] wire out_rimask_14 = |_out_rimask_T_14; // @[RegisterRouter.scala:87:24] wire out_wimask_14 = &_out_wimask_T_14; // @[RegisterRouter.scala:87:24] wire out_romask_14 = |_out_romask_T_14; // @[RegisterRouter.scala:87:24] wire out_womask_14 = &_out_womask_T_14; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_14 = out_rivalid_14 & out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_159 = out_f_rivalid_14; // @[RegisterRouter.scala:87:24] wire out_f_roready_14 = out_roready_14 & out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_160 = out_f_roready_14; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_14 = out_wivalid_14 & out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_161 = out_f_wivalid_14; // @[RegisterRouter.scala:87:24] assign out_f_woready_14 = out_woready_14 & out_womask_14; // @[RegisterRouter.scala:87:24] assign valids_4 = out_f_woready_14; // @[RegisterRouter.scala:87:24] wire _out_T_162 = out_f_woready_14; // @[RegisterRouter.scala:87:24] assign newBytes_4 = out_f_woready_14 ? _out_T_158 : oldBytes_4; // @[RegisterRouter.scala:87:24] wire _out_T_163 = ~out_rimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_164 = ~out_wimask_14; // @[RegisterRouter.scala:87:24] wire _out_T_165 = ~out_romask_14; // @[RegisterRouter.scala:87:24] wire _out_T_166 = ~out_womask_14; // @[RegisterRouter.scala:87:24] wire [39:0] out_prepend_11 = {oldBytes_4, _out_prepend_T_11}; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_167 = out_prepend_11; // @[RegisterRouter.scala:87:24] wire [39:0] _out_T_168 = _out_T_167; // @[RegisterRouter.scala:87:24] wire [39:0] _out_prepend_T_12 = _out_T_168; // @[RegisterRouter.scala:87:24] wire out_rimask_15 = |_out_rimask_T_15; // @[RegisterRouter.scala:87:24] wire out_wimask_15 = &_out_wimask_T_15; // @[RegisterRouter.scala:87:24] wire out_romask_15 = |_out_romask_T_15; // @[RegisterRouter.scala:87:24] wire out_womask_15 = &_out_womask_T_15; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_15 = out_rivalid_15 & out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_170 = out_f_rivalid_15; // @[RegisterRouter.scala:87:24] wire out_f_roready_15 = out_roready_15 & out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_171 = out_f_roready_15; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_15 = out_wivalid_15 & out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_172 = out_f_wivalid_15; // @[RegisterRouter.scala:87:24] assign out_f_woready_15 = out_woready_15 & out_womask_15; // @[RegisterRouter.scala:87:24] assign valids_5 = out_f_woready_15; // @[RegisterRouter.scala:87:24] wire _out_T_173 = out_f_woready_15; // @[RegisterRouter.scala:87:24] assign newBytes_5 = out_f_woready_15 ? _out_T_169 : oldBytes_5; // @[RegisterRouter.scala:87:24] wire _out_T_174 = ~out_rimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_175 = ~out_wimask_15; // @[RegisterRouter.scala:87:24] wire _out_T_176 = ~out_romask_15; // @[RegisterRouter.scala:87:24] wire _out_T_177 = ~out_womask_15; // @[RegisterRouter.scala:87:24] wire [47:0] out_prepend_12 = {oldBytes_5, _out_prepend_T_12}; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_178 = out_prepend_12; // @[RegisterRouter.scala:87:24] wire [47:0] _out_T_179 = _out_T_178; // @[RegisterRouter.scala:87:24] wire [47:0] _out_prepend_T_13 = _out_T_179; // @[RegisterRouter.scala:87:24] wire out_rimask_16 = |_out_rimask_T_16; // @[RegisterRouter.scala:87:24] wire out_wimask_16 = &_out_wimask_T_16; // @[RegisterRouter.scala:87:24] wire out_romask_16 = |_out_romask_T_16; // @[RegisterRouter.scala:87:24] wire out_womask_16 = &_out_womask_T_16; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_16 = out_rivalid_16 & out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_181 = out_f_rivalid_16; // @[RegisterRouter.scala:87:24] wire out_f_roready_16 = out_roready_16 & out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_182 = out_f_roready_16; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_16 = out_wivalid_16 & out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_183 = out_f_wivalid_16; // @[RegisterRouter.scala:87:24] assign out_f_woready_16 = out_woready_16 & out_womask_16; // @[RegisterRouter.scala:87:24] assign valids_6 = out_f_woready_16; // @[RegisterRouter.scala:87:24] wire _out_T_184 = out_f_woready_16; // @[RegisterRouter.scala:87:24] assign newBytes_6 = out_f_woready_16 ? _out_T_180 : oldBytes_6; // @[RegisterRouter.scala:87:24] wire _out_T_185 = ~out_rimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_186 = ~out_wimask_16; // @[RegisterRouter.scala:87:24] wire _out_T_187 = ~out_romask_16; // @[RegisterRouter.scala:87:24] wire _out_T_188 = ~out_womask_16; // @[RegisterRouter.scala:87:24] wire [55:0] out_prepend_13 = {oldBytes_6, _out_prepend_T_13}; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_189 = out_prepend_13; // @[RegisterRouter.scala:87:24] wire [55:0] _out_T_190 = _out_T_189; // @[RegisterRouter.scala:87:24] wire [55:0] _out_prepend_T_14 = _out_T_190; // @[RegisterRouter.scala:87:24] wire out_rimask_17 = |_out_rimask_T_17; // @[RegisterRouter.scala:87:24] wire out_wimask_17 = &_out_wimask_T_17; // @[RegisterRouter.scala:87:24] wire out_romask_17 = |_out_romask_T_17; // @[RegisterRouter.scala:87:24] wire out_womask_17 = &_out_womask_T_17; // @[RegisterRouter.scala:87:24] wire out_f_rivalid_17 = out_rivalid_17 & out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_192 = out_f_rivalid_17; // @[RegisterRouter.scala:87:24] wire out_f_roready_17 = out_roready_17 & out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_193 = out_f_roready_17; // @[RegisterRouter.scala:87:24] wire out_f_wivalid_17 = out_wivalid_17 & out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_194 = out_f_wivalid_17; // @[RegisterRouter.scala:87:24] assign out_f_woready_17 = out_woready_17 & out_womask_17; // @[RegisterRouter.scala:87:24] assign valids_7 = out_f_woready_17; // @[RegisterRouter.scala:87:24] wire _out_T_195 = out_f_woready_17; // @[RegisterRouter.scala:87:24] assign newBytes_7 = out_f_woready_17 ? _out_T_191 : oldBytes_7; // @[RegisterRouter.scala:87:24] wire _out_T_196 = ~out_rimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_197 = ~out_wimask_17; // @[RegisterRouter.scala:87:24] wire _out_T_198 = ~out_romask_17; // @[RegisterRouter.scala:87:24] wire _out_T_199 = ~out_womask_17; // @[RegisterRouter.scala:87:24] wire [63:0] out_prepend_14 = {oldBytes_7, _out_prepend_T_14}; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_200 = out_prepend_14; // @[RegisterRouter.scala:87:24] wire [63:0] _out_T_201 = _out_T_200; // @[RegisterRouter.scala:87:24] wire [63:0] _out_out_bits_data_WIRE_1_1 = _out_T_201; // @[MuxLiteral.scala:49:48] wire _out_iindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T = out_front_bits_index[0]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_1 = out_front_bits_index[1]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_2 = out_front_bits_index[2]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_3 = out_front_bits_index[3]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_4 = out_front_bits_index[4]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_5 = out_front_bits_index[5]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_6 = out_front_bits_index[6]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_7 = out_front_bits_index[7]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_8 = out_front_bits_index[8]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_9 = out_front_bits_index[9]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_10 = out_front_bits_index[10]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_11 = out_front_bits_index[11]; // @[RegisterRouter.scala:87:24] wire _out_iindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire _out_oindex_T_12 = out_front_bits_index[12]; // @[RegisterRouter.scala:87:24] wire [1:0] out_iindex = {_out_iindex_T_12, _out_iindex_T_11}; // @[RegisterRouter.scala:87:24] wire [1:0] out_oindex = {_out_oindex_T_12, _out_oindex_T_11}; // @[RegisterRouter.scala:87:24] wire [3:0] _out_frontSel_T = 4'h1 << out_iindex; // @[OneHot.scala:58:35] wire out_frontSel_0 = _out_frontSel_T[0]; // @[OneHot.scala:58:35] wire out_frontSel_1 = _out_frontSel_T[1]; // @[OneHot.scala:58:35] wire out_frontSel_2 = _out_frontSel_T[2]; // @[OneHot.scala:58:35] wire out_frontSel_3 = _out_frontSel_T[3]; // @[OneHot.scala:58:35] wire [3:0] _out_backSel_T = 4'h1 << out_oindex; // @[OneHot.scala:58:35] wire out_backSel_0 = _out_backSel_T[0]; // @[OneHot.scala:58:35] wire out_backSel_1 = _out_backSel_T[1]; // @[OneHot.scala:58:35] wire out_backSel_2 = _out_backSel_T[2]; // @[OneHot.scala:58:35] wire out_backSel_3 = _out_backSel_T[3]; // @[OneHot.scala:58:35] wire _GEN_2 = in_valid & out_front_ready; // @[RegisterRouter.scala:73:18, :87:24] wire _out_rifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T = _GEN_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_1 = _out_rifireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_2 = _out_rifireMux_T_1 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_3 = _out_rifireMux_T_2 & _out_T; // @[RegisterRouter.scala:87:24] assign out_rivalid_0 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_rivalid_1 = _out_rifireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_4 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_6 = _out_rifireMux_T_1 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_7 = _out_rifireMux_T_6 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_rivalid_10 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_11 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_12 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_13 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_14 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_15 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_16 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_rivalid_17 = _out_rifireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_8 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_10 = _out_rifireMux_T_1 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_rifireMux_T_11 = _out_rifireMux_T_10 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_rivalid_2 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_3 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_4 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_5 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_6 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_7 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_8 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_rivalid_9 = _out_rifireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_12 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_14 = _out_rifireMux_T_1 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_rifireMux_T_15 = _out_rifireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_2 = _out_wifireMux_T & _out_wifireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_3 = _out_wifireMux_T_2 & out_frontSel_0; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_4 = _out_wifireMux_T_3 & _out_T; // @[RegisterRouter.scala:87:24] assign out_wivalid_0 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_1 = _out_wifireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_5 = ~_out_T; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_7 = _out_wifireMux_T_2 & out_frontSel_1; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_8 = _out_wifireMux_T_7 & _out_T_4; // @[RegisterRouter.scala:87:24] assign out_wivalid_10 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_11 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_12 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_13 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_14 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_15 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_16 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_wivalid_17 = _out_wifireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_9 = ~_out_T_4; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_11 = _out_wifireMux_T_2 & out_frontSel_2; // @[RegisterRouter.scala:87:24] assign _out_wifireMux_T_12 = _out_wifireMux_T_11 & _out_T_2; // @[RegisterRouter.scala:87:24] assign out_wivalid_2 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_3 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_4 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_5 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_6 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_7 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_8 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_wivalid_9 = _out_wifireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_13 = ~_out_T_2; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_15 = _out_wifireMux_T_2 & out_frontSel_3; // @[RegisterRouter.scala:87:24] wire _out_wifireMux_T_16 = _out_wifireMux_T_15; // @[RegisterRouter.scala:87:24] wire _GEN_3 = out_front_valid & out_ready; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T = _GEN_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_1 = _out_rofireMux_T & out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_2 = _out_rofireMux_T_1 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_3 = _out_rofireMux_T_2 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_roready_0 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_1 = _out_rofireMux_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_4 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_6 = _out_rofireMux_T_1 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_7 = _out_rofireMux_T_6 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_roready_10 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_11 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_12 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_13 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_14 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_15 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_16 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] assign out_roready_17 = _out_rofireMux_T_7; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_8 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_10 = _out_rofireMux_T_1 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_rofireMux_T_11 = _out_rofireMux_T_10 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_roready_2 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_3 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_4 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_5 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_6 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_7 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_8 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] assign out_roready_9 = _out_rofireMux_T_11; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_12 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_14 = _out_rofireMux_T_1 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_rofireMux_T_15 = _out_rofireMux_T_14; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_1 = ~out_front_bits_read; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_2 = _out_wofireMux_T & _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_3 = _out_wofireMux_T_2 & out_backSel_0; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_4 = _out_wofireMux_T_3 & _out_T_1; // @[RegisterRouter.scala:87:24] assign out_woready_0 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] assign out_woready_1 = _out_wofireMux_T_4; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_5 = ~_out_T_1; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_7 = _out_wofireMux_T_2 & out_backSel_1; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_8 = _out_wofireMux_T_7 & _out_T_5; // @[RegisterRouter.scala:87:24] assign out_woready_10 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_11 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_12 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_13 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_14 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_15 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_16 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] assign out_woready_17 = _out_wofireMux_T_8; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_9 = ~_out_T_5; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_11 = _out_wofireMux_T_2 & out_backSel_2; // @[RegisterRouter.scala:87:24] assign _out_wofireMux_T_12 = _out_wofireMux_T_11 & _out_T_3; // @[RegisterRouter.scala:87:24] assign out_woready_2 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_3 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_4 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_5 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_6 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_7 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_8 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] assign out_woready_9 = _out_wofireMux_T_12; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_13 = ~_out_T_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_15 = _out_wofireMux_T_2 & out_backSel_3; // @[RegisterRouter.scala:87:24] wire _out_wofireMux_T_16 = _out_wofireMux_T_15; // @[RegisterRouter.scala:87:24] assign in_ready = _out_in_ready_T; // @[RegisterRouter.scala:73:18, :87:24] assign out_front_valid = _out_front_valid_T; // @[RegisterRouter.scala:87:24] assign out_front_ready = _out_front_ready_T; // @[RegisterRouter.scala:87:24] assign out_valid = _out_out_valid_T; // @[RegisterRouter.scala:87:24] wire [3:0] _GEN_4 = {{1'h1}, {_out_out_bits_data_WIRE_2}, {_out_out_bits_data_WIRE_1}, {_out_out_bits_data_WIRE_0}}; // @[MuxLiteral.scala:49:{10,48}] wire _out_out_bits_data_T_1 = _GEN_4[out_oindex]; // @[MuxLiteral.scala:49:10] wire [63:0] _out_out_bits_data_WIRE_1_0 = {32'h0, _out_T_25}; // @[MuxLiteral.scala:49:48] wire [3:0][63:0] _GEN_5 = {{64'h0}, {_out_out_bits_data_WIRE_1_2}, {_out_out_bits_data_WIRE_1_1}, {_out_out_bits_data_WIRE_1_0}}; // @[MuxLiteral.scala:49:{10,48}] wire [63:0] _out_out_bits_data_T_3 = _GEN_5[out_oindex]; // @[MuxLiteral.scala:49:10] assign _out_out_bits_data_T_4 = _out_out_bits_data_T_1 ? _out_out_bits_data_T_3 : 64'h0; // @[MuxLiteral.scala:49:10] assign out_bits_data = _out_out_bits_data_T_4; // @[RegisterRouter.scala:87:24] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:792:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:792:17] assign nodeIn_d_bits_opcode = {2'h0, _nodeIn_d_bits_opcode_T}; // @[RegisterRouter.scala:105:{19,25}] always @(posedge clock) begin // @[CLINT.scala:65:9] if (reset) begin // @[CLINT.scala:65:9] time_0 <= 64'h0; // @[CLINT.scala:73:23] ipi_0 <= 1'h0; // @[CLINT.scala:78:41] end else begin // @[CLINT.scala:65:9] if (valids_1_0 | valids_1_1 | valids_1_2 | valids_1_3 | valids_1_4 | valids_1_5 | valids_1_6 | valids_1_7) // @[RegField.scala:153:29, :154:27] time_0 <= _time_T_2; // @[RegField.scala:154:52] else if (io_rtcTick_0) // @[CLINT.scala:65:9] time_0 <= _time_T_1; // @[CLINT.scala:73:23, :74:38] if (out_f_woready) // @[RegisterRouter.scala:87:24] ipi_0 <= _out_T_6; // @[RegisterRouter.scala:87:24] end if (valids_0 | valids_1 | valids_2 | valids_3 | valids_4 | valids_5 | valids_6 | valids_7) // @[RegField.scala:153:29, :154:27] timecmp_0 <= _timecmp_0_T; // @[RegField.scala:154:52] always @(posedge) TLMonitor_45 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_int_out_0 = auto_int_out_0_0; // @[CLINT.scala:65:9] assign auto_int_out_1 = auto_int_out_1_0; // @[CLINT.scala:65:9] assign auto_in_a_ready = auto_in_a_ready_0; // @[CLINT.scala:65:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[CLINT.scala:65:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[CLINT.scala:65:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_34 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_34( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_33 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[20] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[9]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[10]) node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[11]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[12]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[13]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[14]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[15]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[16]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[17]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[18]) node source_ok = or(_source_ok_T_57, _source_ok_WIRE[19]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = and(_T_11, _T_24) node _T_185 = and(_T_184, _T_37) node _T_186 = and(_T_185, _T_50) node _T_187 = and(_T_186, _T_63) node _T_188 = and(_T_187, _T_71) node _T_189 = and(_T_188, _T_79) node _T_190 = and(_T_189, _T_87) node _T_191 = and(_T_190, _T_95) node _T_192 = and(_T_191, _T_103) node _T_193 = and(_T_192, _T_111) node _T_194 = and(_T_193, _T_119) node _T_195 = and(_T_194, _T_127) node _T_196 = and(_T_195, _T_135) node _T_197 = and(_T_196, _T_143) node _T_198 = and(_T_197, _T_151) node _T_199 = and(_T_198, _T_159) node _T_200 = and(_T_199, _T_167) node _T_201 = and(_T_200, _T_175) node _T_202 = and(_T_201, _T_183) node _T_203 = asUInt(reset) node _T_204 = eq(_T_203, UInt<1>(0h0)) when _T_204 : node _T_205 = eq(_T_202, UInt<1>(0h0)) when _T_205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_202, UInt<1>(0h1), "") : assert_1 node _T_206 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_206 : node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_209 = and(_T_207, _T_208) node _T_210 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_211 = shr(io.in.a.bits.source, 2) node _T_212 = eq(_T_211, UInt<1>(0h0)) node _T_213 = leq(UInt<1>(0h0), uncommonBits_4) node _T_214 = and(_T_212, _T_213) node _T_215 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_216 = and(_T_214, _T_215) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_217 = shr(io.in.a.bits.source, 2) node _T_218 = eq(_T_217, UInt<1>(0h1)) node _T_219 = leq(UInt<1>(0h0), uncommonBits_5) node _T_220 = and(_T_218, _T_219) node _T_221 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_222 = and(_T_220, _T_221) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_223 = shr(io.in.a.bits.source, 2) node _T_224 = eq(_T_223, UInt<2>(0h2)) node _T_225 = leq(UInt<1>(0h0), uncommonBits_6) node _T_226 = and(_T_224, _T_225) node _T_227 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_228 = and(_T_226, _T_227) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_229 = shr(io.in.a.bits.source, 2) node _T_230 = eq(_T_229, UInt<2>(0h3)) node _T_231 = leq(UInt<1>(0h0), uncommonBits_7) node _T_232 = and(_T_230, _T_231) node _T_233 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_234 = and(_T_232, _T_233) node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_236 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_237 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_249 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_250 = or(_T_210, _T_216) node _T_251 = or(_T_250, _T_222) node _T_252 = or(_T_251, _T_228) node _T_253 = or(_T_252, _T_234) node _T_254 = or(_T_253, _T_235) node _T_255 = or(_T_254, _T_236) node _T_256 = or(_T_255, _T_237) node _T_257 = or(_T_256, _T_238) node _T_258 = or(_T_257, _T_239) node _T_259 = or(_T_258, _T_240) node _T_260 = or(_T_259, _T_241) node _T_261 = or(_T_260, _T_242) node _T_262 = or(_T_261, _T_243) node _T_263 = or(_T_262, _T_244) node _T_264 = or(_T_263, _T_245) node _T_265 = or(_T_264, _T_246) node _T_266 = or(_T_265, _T_247) node _T_267 = or(_T_266, _T_248) node _T_268 = or(_T_267, _T_249) node _T_269 = and(_T_209, _T_268) node _T_270 = or(UInt<1>(0h0), _T_269) node _T_271 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_272 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_273 = cvt(_T_272) node _T_274 = and(_T_273, asSInt(UInt<17>(0h10000))) node _T_275 = asSInt(_T_274) node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0))) node _T_277 = and(_T_271, _T_276) node _T_278 = or(UInt<1>(0h0), _T_277) node _T_279 = and(_T_270, _T_278) node _T_280 = asUInt(reset) node _T_281 = eq(_T_280, UInt<1>(0h0)) when _T_281 : node _T_282 = eq(_T_279, UInt<1>(0h0)) when _T_282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_279, UInt<1>(0h1), "") : assert_2 node _T_283 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_8) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<1>(0h1)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_9) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_296 = shr(io.in.a.bits.source, 2) node _T_297 = eq(_T_296, UInt<2>(0h2)) node _T_298 = leq(UInt<1>(0h0), uncommonBits_10) node _T_299 = and(_T_297, _T_298) node _T_300 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_301 = and(_T_299, _T_300) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_302 = shr(io.in.a.bits.source, 2) node _T_303 = eq(_T_302, UInt<2>(0h3)) node _T_304 = leq(UInt<1>(0h0), uncommonBits_11) node _T_305 = and(_T_303, _T_304) node _T_306 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_315 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_316 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_317 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[20] connect _WIRE[0], _T_283 connect _WIRE[1], _T_289 connect _WIRE[2], _T_295 connect _WIRE[3], _T_301 connect _WIRE[4], _T_307 connect _WIRE[5], _T_308 connect _WIRE[6], _T_309 connect _WIRE[7], _T_310 connect _WIRE[8], _T_311 connect _WIRE[9], _T_312 connect _WIRE[10], _T_313 connect _WIRE[11], _T_314 connect _WIRE[12], _T_315 connect _WIRE[13], _T_316 connect _WIRE[14], _T_317 connect _WIRE[15], _T_318 connect _WIRE[16], _T_319 connect _WIRE[17], _T_320 connect _WIRE[18], _T_321 connect _WIRE[19], _T_322 node _T_323 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_324 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_325 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_326 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_327 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_328 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_329 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_331 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_332 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_333 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_334 = mux(_WIRE[5], _T_323, UInt<1>(0h0)) node _T_335 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_336 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_337 = mux(_WIRE[8], _T_324, UInt<1>(0h0)) node _T_338 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_339 = mux(_WIRE[10], _T_325, UInt<1>(0h0)) node _T_340 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_341 = mux(_WIRE[12], _T_326, UInt<1>(0h0)) node _T_342 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_343 = mux(_WIRE[14], _T_327, UInt<1>(0h0)) node _T_344 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_345 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_346 = mux(_WIRE[17], _T_328, UInt<1>(0h0)) node _T_347 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_348 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_349 = or(_T_329, _T_330) node _T_350 = or(_T_349, _T_331) node _T_351 = or(_T_350, _T_332) node _T_352 = or(_T_351, _T_333) node _T_353 = or(_T_352, _T_334) node _T_354 = or(_T_353, _T_335) node _T_355 = or(_T_354, _T_336) node _T_356 = or(_T_355, _T_337) node _T_357 = or(_T_356, _T_338) node _T_358 = or(_T_357, _T_339) node _T_359 = or(_T_358, _T_340) node _T_360 = or(_T_359, _T_341) node _T_361 = or(_T_360, _T_342) node _T_362 = or(_T_361, _T_343) node _T_363 = or(_T_362, _T_344) node _T_364 = or(_T_363, _T_345) node _T_365 = or(_T_364, _T_346) node _T_366 = or(_T_365, _T_347) node _T_367 = or(_T_366, _T_348) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_1, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_379, UInt<1>(0h1), "") : assert_3 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_386, UInt<1>(0h1), "") : assert_5 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_393, UInt<1>(0h1), "") : assert_7 node _T_397 = not(io.in.a.bits.mask) node _T_398 = eq(_T_397, UInt<1>(0h0)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_398, UInt<1>(0h1), "") : assert_8 node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_402, UInt<1>(0h1), "") : assert_9 node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_406 : node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_409 = and(_T_407, _T_408) node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_411 = shr(io.in.a.bits.source, 2) node _T_412 = eq(_T_411, UInt<1>(0h0)) node _T_413 = leq(UInt<1>(0h0), uncommonBits_12) node _T_414 = and(_T_412, _T_413) node _T_415 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_416 = and(_T_414, _T_415) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_417 = shr(io.in.a.bits.source, 2) node _T_418 = eq(_T_417, UInt<1>(0h1)) node _T_419 = leq(UInt<1>(0h0), uncommonBits_13) node _T_420 = and(_T_418, _T_419) node _T_421 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_422 = and(_T_420, _T_421) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_423 = shr(io.in.a.bits.source, 2) node _T_424 = eq(_T_423, UInt<2>(0h2)) node _T_425 = leq(UInt<1>(0h0), uncommonBits_14) node _T_426 = and(_T_424, _T_425) node _T_427 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_428 = and(_T_426, _T_427) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_429 = shr(io.in.a.bits.source, 2) node _T_430 = eq(_T_429, UInt<2>(0h3)) node _T_431 = leq(UInt<1>(0h0), uncommonBits_15) node _T_432 = and(_T_430, _T_431) node _T_433 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_450 = or(_T_410, _T_416) node _T_451 = or(_T_450, _T_422) node _T_452 = or(_T_451, _T_428) node _T_453 = or(_T_452, _T_434) node _T_454 = or(_T_453, _T_435) node _T_455 = or(_T_454, _T_436) node _T_456 = or(_T_455, _T_437) node _T_457 = or(_T_456, _T_438) node _T_458 = or(_T_457, _T_439) node _T_459 = or(_T_458, _T_440) node _T_460 = or(_T_459, _T_441) node _T_461 = or(_T_460, _T_442) node _T_462 = or(_T_461, _T_443) node _T_463 = or(_T_462, _T_444) node _T_464 = or(_T_463, _T_445) node _T_465 = or(_T_464, _T_446) node _T_466 = or(_T_465, _T_447) node _T_467 = or(_T_466, _T_448) node _T_468 = or(_T_467, _T_449) node _T_469 = and(_T_409, _T_468) node _T_470 = or(UInt<1>(0h0), _T_469) node _T_471 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<17>(0h10000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = and(_T_471, _T_476) node _T_478 = or(UInt<1>(0h0), _T_477) node _T_479 = and(_T_470, _T_478) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_479, UInt<1>(0h1), "") : assert_10 node _T_483 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<1>(0h0)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_16) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<1>(0h1)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_17) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_496 = shr(io.in.a.bits.source, 2) node _T_497 = eq(_T_496, UInt<2>(0h2)) node _T_498 = leq(UInt<1>(0h0), uncommonBits_18) node _T_499 = and(_T_497, _T_498) node _T_500 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_501 = and(_T_499, _T_500) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_502 = shr(io.in.a.bits.source, 2) node _T_503 = eq(_T_502, UInt<2>(0h3)) node _T_504 = leq(UInt<1>(0h0), uncommonBits_19) node _T_505 = and(_T_503, _T_504) node _T_506 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_507 = and(_T_505, _T_506) node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_510 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_511 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_513 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_514 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_515 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_516 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_517 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_519 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[20] connect _WIRE_2[0], _T_483 connect _WIRE_2[1], _T_489 connect _WIRE_2[2], _T_495 connect _WIRE_2[3], _T_501 connect _WIRE_2[4], _T_507 connect _WIRE_2[5], _T_508 connect _WIRE_2[6], _T_509 connect _WIRE_2[7], _T_510 connect _WIRE_2[8], _T_511 connect _WIRE_2[9], _T_512 connect _WIRE_2[10], _T_513 connect _WIRE_2[11], _T_514 connect _WIRE_2[12], _T_515 connect _WIRE_2[13], _T_516 connect _WIRE_2[14], _T_517 connect _WIRE_2[15], _T_518 connect _WIRE_2[16], _T_519 connect _WIRE_2[17], _T_520 connect _WIRE_2[18], _T_521 connect _WIRE_2[19], _T_522 node _T_523 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_525 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_526 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_527 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_528 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_529 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_530 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_531 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_532 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_533 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_534 = mux(_WIRE_2[5], _T_523, UInt<1>(0h0)) node _T_535 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_536 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_537 = mux(_WIRE_2[8], _T_524, UInt<1>(0h0)) node _T_538 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_539 = mux(_WIRE_2[10], _T_525, UInt<1>(0h0)) node _T_540 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0)) node _T_541 = mux(_WIRE_2[12], _T_526, UInt<1>(0h0)) node _T_542 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[14], _T_527, UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[17], _T_528, UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = or(_T_529, _T_530) node _T_550 = or(_T_549, _T_531) node _T_551 = or(_T_550, _T_532) node _T_552 = or(_T_551, _T_533) node _T_553 = or(_T_552, _T_534) node _T_554 = or(_T_553, _T_535) node _T_555 = or(_T_554, _T_536) node _T_556 = or(_T_555, _T_537) node _T_557 = or(_T_556, _T_538) node _T_558 = or(_T_557, _T_539) node _T_559 = or(_T_558, _T_540) node _T_560 = or(_T_559, _T_541) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_543) node _T_563 = or(_T_562, _T_544) node _T_564 = or(_T_563, _T_545) node _T_565 = or(_T_564, _T_546) node _T_566 = or(_T_565, _T_547) node _T_567 = or(_T_566, _T_548) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_567 node _T_568 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_569 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_570 = and(_T_568, _T_569) node _T_571 = or(UInt<1>(0h0), _T_570) node _T_572 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<17>(0h10000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = and(_T_571, _T_576) node _T_578 = or(UInt<1>(0h0), _T_577) node _T_579 = and(_WIRE_3, _T_578) node _T_580 = asUInt(reset) node _T_581 = eq(_T_580, UInt<1>(0h0)) when _T_581 : node _T_582 = eq(_T_579, UInt<1>(0h0)) when _T_582 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_579, UInt<1>(0h1), "") : assert_11 node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(source_ok, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_586 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_587 = asUInt(reset) node _T_588 = eq(_T_587, UInt<1>(0h0)) when _T_588 : node _T_589 = eq(_T_586, UInt<1>(0h0)) when _T_589 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_586, UInt<1>(0h1), "") : assert_13 node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(is_aligned, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_593 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_594 = asUInt(reset) node _T_595 = eq(_T_594, UInt<1>(0h0)) when _T_595 : node _T_596 = eq(_T_593, UInt<1>(0h0)) when _T_596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_593, UInt<1>(0h1), "") : assert_15 node _T_597 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_T_597, UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_597, UInt<1>(0h1), "") : assert_16 node _T_601 = not(io.in.a.bits.mask) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_602, UInt<1>(0h1), "") : assert_17 node _T_606 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_607 = asUInt(reset) node _T_608 = eq(_T_607, UInt<1>(0h0)) when _T_608 : node _T_609 = eq(_T_606, UInt<1>(0h0)) when _T_609 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_606, UInt<1>(0h1), "") : assert_18 node _T_610 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_610 : node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_613 = and(_T_611, _T_612) node _T_614 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_615 = shr(io.in.a.bits.source, 2) node _T_616 = eq(_T_615, UInt<1>(0h0)) node _T_617 = leq(UInt<1>(0h0), uncommonBits_20) node _T_618 = and(_T_616, _T_617) node _T_619 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_620 = and(_T_618, _T_619) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_621 = shr(io.in.a.bits.source, 2) node _T_622 = eq(_T_621, UInt<1>(0h1)) node _T_623 = leq(UInt<1>(0h0), uncommonBits_21) node _T_624 = and(_T_622, _T_623) node _T_625 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_626 = and(_T_624, _T_625) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_627 = shr(io.in.a.bits.source, 2) node _T_628 = eq(_T_627, UInt<2>(0h2)) node _T_629 = leq(UInt<1>(0h0), uncommonBits_22) node _T_630 = and(_T_628, _T_629) node _T_631 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_632 = and(_T_630, _T_631) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_633 = shr(io.in.a.bits.source, 2) node _T_634 = eq(_T_633, UInt<2>(0h3)) node _T_635 = leq(UInt<1>(0h0), uncommonBits_23) node _T_636 = and(_T_634, _T_635) node _T_637 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_638 = and(_T_636, _T_637) node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_654 = or(_T_614, _T_620) node _T_655 = or(_T_654, _T_626) node _T_656 = or(_T_655, _T_632) node _T_657 = or(_T_656, _T_638) node _T_658 = or(_T_657, _T_639) node _T_659 = or(_T_658, _T_640) node _T_660 = or(_T_659, _T_641) node _T_661 = or(_T_660, _T_642) node _T_662 = or(_T_661, _T_643) node _T_663 = or(_T_662, _T_644) node _T_664 = or(_T_663, _T_645) node _T_665 = or(_T_664, _T_646) node _T_666 = or(_T_665, _T_647) node _T_667 = or(_T_666, _T_648) node _T_668 = or(_T_667, _T_649) node _T_669 = or(_T_668, _T_650) node _T_670 = or(_T_669, _T_651) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_653) node _T_673 = and(_T_613, _T_672) node _T_674 = or(UInt<1>(0h0), _T_673) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_674, UInt<1>(0h1), "") : assert_19 node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_679 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_680 = and(_T_678, _T_679) node _T_681 = or(UInt<1>(0h0), _T_680) node _T_682 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_683 = cvt(_T_682) node _T_684 = and(_T_683, asSInt(UInt<17>(0h10000))) node _T_685 = asSInt(_T_684) node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0))) node _T_687 = and(_T_681, _T_686) node _T_688 = or(UInt<1>(0h0), _T_687) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_688, UInt<1>(0h1), "") : assert_20 node _T_692 = asUInt(reset) node _T_693 = eq(_T_692, UInt<1>(0h0)) when _T_693 : node _T_694 = eq(source_ok, UInt<1>(0h0)) when _T_694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(is_aligned, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_698, UInt<1>(0h1), "") : assert_23 node _T_702 = eq(io.in.a.bits.mask, mask) node _T_703 = asUInt(reset) node _T_704 = eq(_T_703, UInt<1>(0h0)) when _T_704 : node _T_705 = eq(_T_702, UInt<1>(0h0)) when _T_705 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_702, UInt<1>(0h1), "") : assert_24 node _T_706 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(_T_706, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_706, UInt<1>(0h1), "") : assert_25 node _T_710 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_710 : node _T_711 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_712 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_713 = and(_T_711, _T_712) node _T_714 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_715 = shr(io.in.a.bits.source, 2) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = leq(UInt<1>(0h0), uncommonBits_24) node _T_718 = and(_T_716, _T_717) node _T_719 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_720 = and(_T_718, _T_719) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_721 = shr(io.in.a.bits.source, 2) node _T_722 = eq(_T_721, UInt<1>(0h1)) node _T_723 = leq(UInt<1>(0h0), uncommonBits_25) node _T_724 = and(_T_722, _T_723) node _T_725 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_726 = and(_T_724, _T_725) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_727 = shr(io.in.a.bits.source, 2) node _T_728 = eq(_T_727, UInt<2>(0h2)) node _T_729 = leq(UInt<1>(0h0), uncommonBits_26) node _T_730 = and(_T_728, _T_729) node _T_731 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_732 = and(_T_730, _T_731) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_733 = shr(io.in.a.bits.source, 2) node _T_734 = eq(_T_733, UInt<2>(0h3)) node _T_735 = leq(UInt<1>(0h0), uncommonBits_27) node _T_736 = and(_T_734, _T_735) node _T_737 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_738 = and(_T_736, _T_737) node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_740 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_744 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_745 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_746 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_747 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_748 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_751 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_752 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_754 = or(_T_714, _T_720) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_732) node _T_757 = or(_T_756, _T_738) node _T_758 = or(_T_757, _T_739) node _T_759 = or(_T_758, _T_740) node _T_760 = or(_T_759, _T_741) node _T_761 = or(_T_760, _T_742) node _T_762 = or(_T_761, _T_743) node _T_763 = or(_T_762, _T_744) node _T_764 = or(_T_763, _T_745) node _T_765 = or(_T_764, _T_746) node _T_766 = or(_T_765, _T_747) node _T_767 = or(_T_766, _T_748) node _T_768 = or(_T_767, _T_749) node _T_769 = or(_T_768, _T_750) node _T_770 = or(_T_769, _T_751) node _T_771 = or(_T_770, _T_752) node _T_772 = or(_T_771, _T_753) node _T_773 = and(_T_713, _T_772) node _T_774 = or(UInt<1>(0h0), _T_773) node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_776 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_777 = and(_T_775, _T_776) node _T_778 = or(UInt<1>(0h0), _T_777) node _T_779 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<17>(0h10000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = and(_T_778, _T_783) node _T_785 = or(UInt<1>(0h0), _T_784) node _T_786 = and(_T_774, _T_785) node _T_787 = asUInt(reset) node _T_788 = eq(_T_787, UInt<1>(0h0)) when _T_788 : node _T_789 = eq(_T_786, UInt<1>(0h0)) when _T_789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_786, UInt<1>(0h1), "") : assert_26 node _T_790 = asUInt(reset) node _T_791 = eq(_T_790, UInt<1>(0h0)) when _T_791 : node _T_792 = eq(source_ok, UInt<1>(0h0)) when _T_792 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_793 = asUInt(reset) node _T_794 = eq(_T_793, UInt<1>(0h0)) when _T_794 : node _T_795 = eq(is_aligned, UInt<1>(0h0)) when _T_795 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_796 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_797 = asUInt(reset) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(_T_796, UInt<1>(0h0)) when _T_799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_796, UInt<1>(0h1), "") : assert_29 node _T_800 = eq(io.in.a.bits.mask, mask) node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(_T_800, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_800, UInt<1>(0h1), "") : assert_30 node _T_804 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_804 : node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_807 = and(_T_805, _T_806) node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<1>(0h0)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_28) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_815 = shr(io.in.a.bits.source, 2) node _T_816 = eq(_T_815, UInt<1>(0h1)) node _T_817 = leq(UInt<1>(0h0), uncommonBits_29) node _T_818 = and(_T_816, _T_817) node _T_819 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_820 = and(_T_818, _T_819) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_821 = shr(io.in.a.bits.source, 2) node _T_822 = eq(_T_821, UInt<2>(0h2)) node _T_823 = leq(UInt<1>(0h0), uncommonBits_30) node _T_824 = and(_T_822, _T_823) node _T_825 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_826 = and(_T_824, _T_825) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_827 = shr(io.in.a.bits.source, 2) node _T_828 = eq(_T_827, UInt<2>(0h3)) node _T_829 = leq(UInt<1>(0h0), uncommonBits_31) node _T_830 = and(_T_828, _T_829) node _T_831 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_832 = and(_T_830, _T_831) node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_847 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_848 = or(_T_808, _T_814) node _T_849 = or(_T_848, _T_820) node _T_850 = or(_T_849, _T_826) node _T_851 = or(_T_850, _T_832) node _T_852 = or(_T_851, _T_833) node _T_853 = or(_T_852, _T_834) node _T_854 = or(_T_853, _T_835) node _T_855 = or(_T_854, _T_836) node _T_856 = or(_T_855, _T_837) node _T_857 = or(_T_856, _T_838) node _T_858 = or(_T_857, _T_839) node _T_859 = or(_T_858, _T_840) node _T_860 = or(_T_859, _T_841) node _T_861 = or(_T_860, _T_842) node _T_862 = or(_T_861, _T_843) node _T_863 = or(_T_862, _T_844) node _T_864 = or(_T_863, _T_845) node _T_865 = or(_T_864, _T_846) node _T_866 = or(_T_865, _T_847) node _T_867 = and(_T_807, _T_866) node _T_868 = or(UInt<1>(0h0), _T_867) node _T_869 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_870 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_871 = and(_T_869, _T_870) node _T_872 = or(UInt<1>(0h0), _T_871) node _T_873 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<17>(0h10000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = and(_T_872, _T_877) node _T_879 = or(UInt<1>(0h0), _T_878) node _T_880 = and(_T_868, _T_879) node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_T_880, UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_880, UInt<1>(0h1), "") : assert_31 node _T_884 = asUInt(reset) node _T_885 = eq(_T_884, UInt<1>(0h0)) when _T_885 : node _T_886 = eq(source_ok, UInt<1>(0h0)) when _T_886 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_887 = asUInt(reset) node _T_888 = eq(_T_887, UInt<1>(0h0)) when _T_888 : node _T_889 = eq(is_aligned, UInt<1>(0h0)) when _T_889 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_890, UInt<1>(0h1), "") : assert_34 node _T_894 = not(mask) node _T_895 = and(io.in.a.bits.mask, _T_894) node _T_896 = eq(_T_895, UInt<1>(0h0)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_896, UInt<1>(0h1), "") : assert_35 node _T_900 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_900 : node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_903 = and(_T_901, _T_902) node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_905 = shr(io.in.a.bits.source, 2) node _T_906 = eq(_T_905, UInt<1>(0h0)) node _T_907 = leq(UInt<1>(0h0), uncommonBits_32) node _T_908 = and(_T_906, _T_907) node _T_909 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_910 = and(_T_908, _T_909) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_911 = shr(io.in.a.bits.source, 2) node _T_912 = eq(_T_911, UInt<1>(0h1)) node _T_913 = leq(UInt<1>(0h0), uncommonBits_33) node _T_914 = and(_T_912, _T_913) node _T_915 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_916 = and(_T_914, _T_915) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_917 = shr(io.in.a.bits.source, 2) node _T_918 = eq(_T_917, UInt<2>(0h2)) node _T_919 = leq(UInt<1>(0h0), uncommonBits_34) node _T_920 = and(_T_918, _T_919) node _T_921 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_922 = and(_T_920, _T_921) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_923 = shr(io.in.a.bits.source, 2) node _T_924 = eq(_T_923, UInt<2>(0h3)) node _T_925 = leq(UInt<1>(0h0), uncommonBits_35) node _T_926 = and(_T_924, _T_925) node _T_927 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_928 = and(_T_926, _T_927) node _T_929 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_933 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_936 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_939 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_942 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_943 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_944 = or(_T_904, _T_910) node _T_945 = or(_T_944, _T_916) node _T_946 = or(_T_945, _T_922) node _T_947 = or(_T_946, _T_928) node _T_948 = or(_T_947, _T_929) node _T_949 = or(_T_948, _T_930) node _T_950 = or(_T_949, _T_931) node _T_951 = or(_T_950, _T_932) node _T_952 = or(_T_951, _T_933) node _T_953 = or(_T_952, _T_934) node _T_954 = or(_T_953, _T_935) node _T_955 = or(_T_954, _T_936) node _T_956 = or(_T_955, _T_937) node _T_957 = or(_T_956, _T_938) node _T_958 = or(_T_957, _T_939) node _T_959 = or(_T_958, _T_940) node _T_960 = or(_T_959, _T_941) node _T_961 = or(_T_960, _T_942) node _T_962 = or(_T_961, _T_943) node _T_963 = and(_T_903, _T_962) node _T_964 = or(UInt<1>(0h0), _T_963) node _T_965 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_966 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_967 = cvt(_T_966) node _T_968 = and(_T_967, asSInt(UInt<17>(0h10000))) node _T_969 = asSInt(_T_968) node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0))) node _T_971 = and(_T_965, _T_970) node _T_972 = or(UInt<1>(0h0), _T_971) node _T_973 = and(_T_964, _T_972) node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(_T_973, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_973, UInt<1>(0h1), "") : assert_36 node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(source_ok, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(is_aligned, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_983 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_983, UInt<1>(0h1), "") : assert_39 node _T_987 = eq(io.in.a.bits.mask, mask) node _T_988 = asUInt(reset) node _T_989 = eq(_T_988, UInt<1>(0h0)) when _T_989 : node _T_990 = eq(_T_987, UInt<1>(0h0)) when _T_990 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_987, UInt<1>(0h1), "") : assert_40 node _T_991 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_991 : node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_993 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_994 = and(_T_992, _T_993) node _T_995 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<1>(0h0)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_36) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1002 = shr(io.in.a.bits.source, 2) node _T_1003 = eq(_T_1002, UInt<1>(0h1)) node _T_1004 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1005 = and(_T_1003, _T_1004) node _T_1006 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1007 = and(_T_1005, _T_1006) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1008 = shr(io.in.a.bits.source, 2) node _T_1009 = eq(_T_1008, UInt<2>(0h2)) node _T_1010 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1011 = and(_T_1009, _T_1010) node _T_1012 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1013 = and(_T_1011, _T_1012) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1014 = shr(io.in.a.bits.source, 2) node _T_1015 = eq(_T_1014, UInt<2>(0h3)) node _T_1016 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1017 = and(_T_1015, _T_1016) node _T_1018 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1019 = and(_T_1017, _T_1018) node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1031 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1032 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1033 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1034 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1035 = or(_T_995, _T_1001) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = or(_T_1036, _T_1013) node _T_1038 = or(_T_1037, _T_1019) node _T_1039 = or(_T_1038, _T_1020) node _T_1040 = or(_T_1039, _T_1021) node _T_1041 = or(_T_1040, _T_1022) node _T_1042 = or(_T_1041, _T_1023) node _T_1043 = or(_T_1042, _T_1024) node _T_1044 = or(_T_1043, _T_1025) node _T_1045 = or(_T_1044, _T_1026) node _T_1046 = or(_T_1045, _T_1027) node _T_1047 = or(_T_1046, _T_1028) node _T_1048 = or(_T_1047, _T_1029) node _T_1049 = or(_T_1048, _T_1030) node _T_1050 = or(_T_1049, _T_1031) node _T_1051 = or(_T_1050, _T_1032) node _T_1052 = or(_T_1051, _T_1033) node _T_1053 = or(_T_1052, _T_1034) node _T_1054 = and(_T_994, _T_1053) node _T_1055 = or(UInt<1>(0h0), _T_1054) node _T_1056 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1057 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1058 = cvt(_T_1057) node _T_1059 = and(_T_1058, asSInt(UInt<17>(0h10000))) node _T_1060 = asSInt(_T_1059) node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0))) node _T_1062 = and(_T_1056, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1055, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_41 node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(source_ok, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(is_aligned, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1074 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_44 node _T_1078 = eq(io.in.a.bits.mask, mask) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_45 node _T_1082 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1082 : node _T_1083 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1084 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1085 = and(_T_1083, _T_1084) node _T_1086 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1087 = shr(io.in.a.bits.source, 2) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) node _T_1089 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1090 = and(_T_1088, _T_1089) node _T_1091 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1092 = and(_T_1090, _T_1091) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1093 = shr(io.in.a.bits.source, 2) node _T_1094 = eq(_T_1093, UInt<1>(0h1)) node _T_1095 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1098 = and(_T_1096, _T_1097) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1099 = shr(io.in.a.bits.source, 2) node _T_1100 = eq(_T_1099, UInt<2>(0h2)) node _T_1101 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1104 = and(_T_1102, _T_1103) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1105 = shr(io.in.a.bits.source, 2) node _T_1106 = eq(_T_1105, UInt<2>(0h3)) node _T_1107 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2f)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2b)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1125 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1126 = or(_T_1086, _T_1092) node _T_1127 = or(_T_1126, _T_1098) node _T_1128 = or(_T_1127, _T_1104) node _T_1129 = or(_T_1128, _T_1110) node _T_1130 = or(_T_1129, _T_1111) node _T_1131 = or(_T_1130, _T_1112) node _T_1132 = or(_T_1131, _T_1113) node _T_1133 = or(_T_1132, _T_1114) node _T_1134 = or(_T_1133, _T_1115) node _T_1135 = or(_T_1134, _T_1116) node _T_1136 = or(_T_1135, _T_1117) node _T_1137 = or(_T_1136, _T_1118) node _T_1138 = or(_T_1137, _T_1119) node _T_1139 = or(_T_1138, _T_1120) node _T_1140 = or(_T_1139, _T_1121) node _T_1141 = or(_T_1140, _T_1122) node _T_1142 = or(_T_1141, _T_1123) node _T_1143 = or(_T_1142, _T_1124) node _T_1144 = or(_T_1143, _T_1125) node _T_1145 = and(_T_1085, _T_1144) node _T_1146 = or(UInt<1>(0h0), _T_1145) node _T_1147 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1148 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1149 = cvt(_T_1148) node _T_1150 = and(_T_1149, asSInt(UInt<17>(0h10000))) node _T_1151 = asSInt(_T_1150) node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0))) node _T_1153 = and(_T_1147, _T_1152) node _T_1154 = or(UInt<1>(0h0), _T_1153) node _T_1155 = and(_T_1146, _T_1154) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_46 node _T_1159 = asUInt(reset) node _T_1160 = eq(_T_1159, UInt<1>(0h0)) when _T_1160 : node _T_1161 = eq(source_ok, UInt<1>(0h0)) when _T_1161 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(is_aligned, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1165 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_49 node _T_1169 = eq(io.in.a.bits.mask, mask) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_50 node _T_1173 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_T_1173, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1173, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1177 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_52 node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_59 = shr(io.in.d.bits.source, 2) node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0)) node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_65 = shr(io.in.d.bits.source, 2) node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1)) node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_T_69 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_71 = shr(io.in.d.bits.source, 2) node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2)) node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 2) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h2f)) node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h2b)) node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[20] connect _source_ok_WIRE_1[0], _source_ok_T_58 connect _source_ok_WIRE_1[1], _source_ok_T_64 connect _source_ok_WIRE_1[2], _source_ok_T_70 connect _source_ok_WIRE_1[3], _source_ok_T_76 connect _source_ok_WIRE_1[4], _source_ok_T_82 connect _source_ok_WIRE_1[5], _source_ok_T_83 connect _source_ok_WIRE_1[6], _source_ok_T_84 connect _source_ok_WIRE_1[7], _source_ok_T_85 connect _source_ok_WIRE_1[8], _source_ok_T_86 connect _source_ok_WIRE_1[9], _source_ok_T_87 connect _source_ok_WIRE_1[10], _source_ok_T_88 connect _source_ok_WIRE_1[11], _source_ok_T_89 connect _source_ok_WIRE_1[12], _source_ok_T_90 connect _source_ok_WIRE_1[13], _source_ok_T_91 connect _source_ok_WIRE_1[14], _source_ok_T_92 connect _source_ok_WIRE_1[15], _source_ok_T_93 connect _source_ok_WIRE_1[16], _source_ok_T_94 connect _source_ok_WIRE_1[17], _source_ok_T_95 connect _source_ok_WIRE_1[18], _source_ok_T_96 connect _source_ok_WIRE_1[19], _source_ok_T_97 node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2]) node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3]) node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4]) node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5]) node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6]) node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7]) node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8]) node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[9]) node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[10]) node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[11]) node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[12]) node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[13]) node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[14]) node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[15]) node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[16]) node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[17]) node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[18]) node source_ok_1 = or(_source_ok_T_115, _source_ok_WIRE_1[19]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1181 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1181 : node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(source_ok_1, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1185 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1186 = asUInt(reset) node _T_1187 = eq(_T_1186, UInt<1>(0h0)) when _T_1187 : node _T_1188 = eq(_T_1185, UInt<1>(0h0)) when _T_1188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1185, UInt<1>(0h1), "") : assert_54 node _T_1189 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1190 = asUInt(reset) node _T_1191 = eq(_T_1190, UInt<1>(0h0)) when _T_1191 : node _T_1192 = eq(_T_1189, UInt<1>(0h0)) when _T_1192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1189, UInt<1>(0h1), "") : assert_55 node _T_1193 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1194 = asUInt(reset) node _T_1195 = eq(_T_1194, UInt<1>(0h0)) when _T_1195 : node _T_1196 = eq(_T_1193, UInt<1>(0h0)) when _T_1196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1193, UInt<1>(0h1), "") : assert_56 node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1198 = asUInt(reset) node _T_1199 = eq(_T_1198, UInt<1>(0h0)) when _T_1199 : node _T_1200 = eq(_T_1197, UInt<1>(0h0)) when _T_1200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1197, UInt<1>(0h1), "") : assert_57 node _T_1201 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1201 : node _T_1202 = asUInt(reset) node _T_1203 = eq(_T_1202, UInt<1>(0h0)) when _T_1203 : node _T_1204 = eq(source_ok_1, UInt<1>(0h0)) when _T_1204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(sink_ok, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1208 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_60 node _T_1212 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_61 node _T_1216 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_62 node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_63 node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1225 = or(UInt<1>(0h0), _T_1224) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_64 node _T_1229 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1229 : node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(source_ok_1, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(sink_ok, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1236 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_67 node _T_1240 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_68 node _T_1244 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_69 node _T_1248 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1249 = or(_T_1248, io.in.d.bits.corrupt) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_70 node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1254 = or(UInt<1>(0h0), _T_1253) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_71 node _T_1258 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1258 : node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(source_ok_1, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1262 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_73 node _T_1266 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_74 node _T_1270 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1271 = or(UInt<1>(0h0), _T_1270) node _T_1272 = asUInt(reset) node _T_1273 = eq(_T_1272, UInt<1>(0h0)) when _T_1273 : node _T_1274 = eq(_T_1271, UInt<1>(0h0)) when _T_1274 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1271, UInt<1>(0h1), "") : assert_75 node _T_1275 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1275 : node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(source_ok_1, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1279 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_77 node _T_1283 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1284 = or(_T_1283, io.in.d.bits.corrupt) node _T_1285 = asUInt(reset) node _T_1286 = eq(_T_1285, UInt<1>(0h0)) when _T_1286 : node _T_1287 = eq(_T_1284, UInt<1>(0h0)) when _T_1287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1284, UInt<1>(0h1), "") : assert_78 node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1289 = or(UInt<1>(0h0), _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_79 node _T_1293 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1293 : node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(source_ok_1, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1297 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1298 = asUInt(reset) node _T_1299 = eq(_T_1298, UInt<1>(0h0)) when _T_1299 : node _T_1300 = eq(_T_1297, UInt<1>(0h0)) when _T_1300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1297, UInt<1>(0h1), "") : assert_81 node _T_1301 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_82 node _T_1305 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1306 = or(UInt<1>(0h0), _T_1305) node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(_T_1306, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1306, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<26>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1310 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1314 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1318 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(_T_1318, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1318, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1322 = eq(a_first, UInt<1>(0h0)) node _T_1323 = and(io.in.a.valid, _T_1322) when _T_1323 : node _T_1324 = eq(io.in.a.bits.opcode, opcode) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_87 node _T_1328 = eq(io.in.a.bits.param, param) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_88 node _T_1332 = eq(io.in.a.bits.size, size) node _T_1333 = asUInt(reset) node _T_1334 = eq(_T_1333, UInt<1>(0h0)) when _T_1334 : node _T_1335 = eq(_T_1332, UInt<1>(0h0)) when _T_1335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1332, UInt<1>(0h1), "") : assert_89 node _T_1336 = eq(io.in.a.bits.source, source) node _T_1337 = asUInt(reset) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(_T_1336, UInt<1>(0h0)) when _T_1339 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1336, UInt<1>(0h1), "") : assert_90 node _T_1340 = eq(io.in.a.bits.address, address) node _T_1341 = asUInt(reset) node _T_1342 = eq(_T_1341, UInt<1>(0h0)) when _T_1342 : node _T_1343 = eq(_T_1340, UInt<1>(0h0)) when _T_1343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1340, UInt<1>(0h1), "") : assert_91 node _T_1344 = and(io.in.a.ready, io.in.a.valid) node _T_1345 = and(_T_1344, a_first) when _T_1345 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1346 = eq(d_first, UInt<1>(0h0)) node _T_1347 = and(io.in.d.valid, _T_1346) when _T_1347 : node _T_1348 = eq(io.in.d.bits.opcode, opcode_1) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_92 node _T_1352 = eq(io.in.d.bits.param, param_1) node _T_1353 = asUInt(reset) node _T_1354 = eq(_T_1353, UInt<1>(0h0)) when _T_1354 : node _T_1355 = eq(_T_1352, UInt<1>(0h0)) when _T_1355 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1352, UInt<1>(0h1), "") : assert_93 node _T_1356 = eq(io.in.d.bits.size, size_1) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_94 node _T_1360 = eq(io.in.d.bits.source, source_1) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_95 node _T_1364 = eq(io.in.d.bits.sink, sink) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_96 node _T_1368 = eq(io.in.d.bits.denied, denied) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_97 node _T_1372 = and(io.in.d.ready, io.in.d.valid) node _T_1373 = and(_T_1372, d_first) when _T_1373 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1374 = and(io.in.a.valid, a_first_1) node _T_1375 = and(_T_1374, UInt<1>(0h1)) when _T_1375 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1376 = and(io.in.a.ready, io.in.a.valid) node _T_1377 = and(_T_1376, a_first_1) node _T_1378 = and(_T_1377, UInt<1>(0h1)) when _T_1378 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1379 = dshr(inflight, io.in.a.bits.source) node _T_1380 = bits(_T_1379, 0, 0) node _T_1381 = eq(_T_1380, UInt<1>(0h0)) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1385 = and(io.in.d.valid, d_first_1) node _T_1386 = and(_T_1385, UInt<1>(0h1)) node _T_1387 = eq(d_release_ack, UInt<1>(0h0)) node _T_1388 = and(_T_1386, _T_1387) when _T_1388 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1389 = and(io.in.d.ready, io.in.d.valid) node _T_1390 = and(_T_1389, d_first_1) node _T_1391 = and(_T_1390, UInt<1>(0h1)) node _T_1392 = eq(d_release_ack, UInt<1>(0h0)) node _T_1393 = and(_T_1391, _T_1392) when _T_1393 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1394 = and(io.in.d.valid, d_first_1) node _T_1395 = and(_T_1394, UInt<1>(0h1)) node _T_1396 = eq(d_release_ack, UInt<1>(0h0)) node _T_1397 = and(_T_1395, _T_1396) when _T_1397 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1398 = dshr(inflight, io.in.d.bits.source) node _T_1399 = bits(_T_1398, 0, 0) node _T_1400 = or(_T_1399, same_cycle_resp) node _T_1401 = asUInt(reset) node _T_1402 = eq(_T_1401, UInt<1>(0h0)) when _T_1402 : node _T_1403 = eq(_T_1400, UInt<1>(0h0)) when _T_1403 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1400, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1404 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1406 = or(_T_1404, _T_1405) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_100 node _T_1410 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_101 else : node _T_1414 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1415 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1416 = or(_T_1414, _T_1415) node _T_1417 = asUInt(reset) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) when _T_1418 : node _T_1419 = eq(_T_1416, UInt<1>(0h0)) when _T_1419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1416, UInt<1>(0h1), "") : assert_102 node _T_1420 = eq(io.in.d.bits.size, a_size_lookup) node _T_1421 = asUInt(reset) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(_T_1420, UInt<1>(0h0)) when _T_1423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1420, UInt<1>(0h1), "") : assert_103 node _T_1424 = and(io.in.d.valid, d_first_1) node _T_1425 = and(_T_1424, a_first_1) node _T_1426 = and(_T_1425, io.in.a.valid) node _T_1427 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1428 = and(_T_1426, _T_1427) node _T_1429 = eq(d_release_ack, UInt<1>(0h0)) node _T_1430 = and(_T_1428, _T_1429) when _T_1430 : node _T_1431 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1432 = or(_T_1431, io.in.a.ready) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_66 node _T_1436 = orr(inflight) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) node _T_1438 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1439 = or(_T_1437, _T_1438) node _T_1440 = lt(watchdog, plusarg_reader.out) node _T_1441 = or(_T_1439, _T_1440) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1445 = and(io.in.a.ready, io.in.a.valid) node _T_1446 = and(io.in.d.ready, io.in.d.valid) node _T_1447 = or(_T_1445, _T_1446) when _T_1447 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<26>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<26>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<26>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1448 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<26>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1449 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1450 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1451 = and(_T_1449, _T_1450) node _T_1452 = and(_T_1448, _T_1451) when _T_1452 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<26>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1453 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1454 = and(_T_1453, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<26>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1455 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1456 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1457 = and(_T_1455, _T_1456) node _T_1458 = and(_T_1454, _T_1457) when _T_1458 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<26>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<26>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1459 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1460 = bits(_T_1459, 0, 0) node _T_1461 = eq(_T_1460, UInt<1>(0h0)) node _T_1462 = asUInt(reset) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) when _T_1463 : node _T_1464 = eq(_T_1461, UInt<1>(0h0)) when _T_1464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1461, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1465 = and(io.in.d.valid, d_first_2) node _T_1466 = and(_T_1465, UInt<1>(0h1)) node _T_1467 = and(_T_1466, d_release_ack_1) when _T_1467 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1468 = and(io.in.d.ready, io.in.d.valid) node _T_1469 = and(_T_1468, d_first_2) node _T_1470 = and(_T_1469, UInt<1>(0h1)) node _T_1471 = and(_T_1470, d_release_ack_1) when _T_1471 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1472 = and(io.in.d.valid, d_first_2) node _T_1473 = and(_T_1472, UInt<1>(0h1)) node _T_1474 = and(_T_1473, d_release_ack_1) when _T_1474 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1475 = dshr(inflight_1, io.in.d.bits.source) node _T_1476 = bits(_T_1475, 0, 0) node _T_1477 = or(_T_1476, same_cycle_resp_1) node _T_1478 = asUInt(reset) node _T_1479 = eq(_T_1478, UInt<1>(0h0)) when _T_1479 : node _T_1480 = eq(_T_1477, UInt<1>(0h0)) when _T_1480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1477, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<26>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1481 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1482 = asUInt(reset) node _T_1483 = eq(_T_1482, UInt<1>(0h0)) when _T_1483 : node _T_1484 = eq(_T_1481, UInt<1>(0h0)) when _T_1484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1481, UInt<1>(0h1), "") : assert_108 else : node _T_1485 = eq(io.in.d.bits.size, c_size_lookup) node _T_1486 = asUInt(reset) node _T_1487 = eq(_T_1486, UInt<1>(0h0)) when _T_1487 : node _T_1488 = eq(_T_1485, UInt<1>(0h0)) when _T_1488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1485, UInt<1>(0h1), "") : assert_109 node _T_1489 = and(io.in.d.valid, d_first_2) node _T_1490 = and(_T_1489, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<26>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1491 = and(_T_1490, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<26>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1492 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1493 = and(_T_1491, _T_1492) node _T_1494 = and(_T_1493, d_release_ack_1) node _T_1495 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1496 = and(_T_1494, _T_1495) when _T_1496 : node _T_1497 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<26>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1498 = or(_T_1497, _WIRE_27.ready) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_67 node _T_1502 = orr(inflight_1) node _T_1503 = eq(_T_1502, UInt<1>(0h0)) node _T_1504 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1505 = or(_T_1503, _T_1504) node _T_1506 = lt(watchdog_1, plusarg_reader_1.out) node _T_1507 = or(_T_1505, _T_1506) node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(_T_1507, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1507, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<26>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1511 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1512 = and(io.in.d.ready, io.in.d.valid) node _T_1513 = or(_T_1511, _T_1512) when _T_1513 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_33( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74] wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_57 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31] wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31] wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31] wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31] wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31] wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31] wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31] wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31] wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31] wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31] wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_111 = _source_ok_T_110 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_115 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _T_1445 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1445; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1445; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [25:0] address; // @[Monitor.scala:391:22] wire _T_1513 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1513; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1513; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1513; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1378 = _T_1445 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1378 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1378 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1378 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1378 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1378 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1424 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1424 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1393 = _T_1513 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1393 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1393 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1393 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1489 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1489 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1471 = _T_1513 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1471 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1471 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1471 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_8 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_8( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TageTable_7 : input clock : Clock input reset : Reset output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f2_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]} regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<7>, clock, reset, UInt<7>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T = eq(reset_idx, UInt<7>(0h7f)) when _T : connect doing_reset, UInt<1>(0h0) node _T_1 = shr(io.f1_req_pc, 4) node idx_history = bits(io.f1_req_ghist, 3, 0) node _idx_T = xor(_T_1, idx_history) node s1_hashed_idx = bits(_idx_T, 6, 0) node tag_history = bits(io.f1_req_ghist, 3, 0) node _tag_T = shr(_T_1, 7) node _tag_T_1 = xor(_tag_T, tag_history) node s1_tag = bits(_tag_T_1, 6, 0) smem tage_u_4 : UInt<1>[8] [128] smem tage_table_4 : UInt<11>[4] [128] reg s2_tag : UInt, clock connect s2_tag, s1_tag wire s2_req_rtage : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] wire s2_req_rus : UInt<1>[8] node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag) node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T) node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2) node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag) node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4) node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6) node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag) node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8) node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10) node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag) node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12) node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0)) node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14) wire s2_req_rhits : UInt<1>[4] connect s2_req_rhits[0], _s2_req_rhits_T_3 connect s2_req_rhits[1], _s2_req_rhits_T_7 connect s2_req_rhits[2], _s2_req_rhits_T_11 connect s2_req_rhits[3], _s2_req_rhits_T_15 connect io.f2_resp[0].valid, s2_req_rhits[0] node _io_f2_resp_0_bits_u_T = cat(s2_req_rus[1], s2_req_rus[0]) connect io.f2_resp[0].bits.u, _io_f2_resp_0_bits_u_T connect io.f2_resp[0].bits.ctr, s2_req_rtage[0].ctr connect io.f2_resp[1].valid, s2_req_rhits[1] node _io_f2_resp_1_bits_u_T = cat(s2_req_rus[3], s2_req_rus[2]) connect io.f2_resp[1].bits.u, _io_f2_resp_1_bits_u_T connect io.f2_resp[1].bits.ctr, s2_req_rtage[1].ctr connect io.f2_resp[2].valid, s2_req_rhits[2] node _io_f2_resp_2_bits_u_T = cat(s2_req_rus[5], s2_req_rus[4]) connect io.f2_resp[2].bits.u, _io_f2_resp_2_bits_u_T connect io.f2_resp[2].bits.ctr, s2_req_rtage[2].ctr connect io.f2_resp[3].valid, s2_req_rhits[3] node _io_f2_resp_3_bits_u_T = cat(s2_req_rus[7], s2_req_rus[6]) connect io.f2_resp[3].bits.u, _io_f2_resp_3_bits_u_T connect io.f2_resp[3].bits.ctr, s2_req_rtage[3].ctr regreset clear_u_ctr : UInt<19>, clock, reset, UInt<19>(0h0) when doing_reset : connect clear_u_ctr, UInt<1>(0h1) else : node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1)) node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1) connect clear_u_ctr, _clear_u_ctr_T_1 node _doing_clear_u_T = bits(clear_u_ctr, 10, 0) node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0)) node _clear_u_hi_T = bits(clear_u_ctr, 18, 18) node clear_u_hi = eq(_clear_u_hi_T, UInt<1>(0h1)) node _clear_u_lo_T = bits(clear_u_ctr, 18, 18) node clear_u_lo = eq(_clear_u_lo_T, UInt<1>(0h0)) node clear_u_idx = shr(clear_u_ctr, 11) wire _clear_u_mask_WIRE : UInt<1>[8] connect _clear_u_mask_WIRE[0], clear_u_lo connect _clear_u_mask_WIRE[1], clear_u_hi connect _clear_u_mask_WIRE[2], clear_u_lo connect _clear_u_mask_WIRE[3], clear_u_hi connect _clear_u_mask_WIRE[4], clear_u_lo connect _clear_u_mask_WIRE[5], clear_u_hi connect _clear_u_mask_WIRE[6], clear_u_lo connect _clear_u_mask_WIRE[7], clear_u_hi node clear_u_mask_lo_lo = cat(_clear_u_mask_WIRE[1], _clear_u_mask_WIRE[0]) node clear_u_mask_lo_hi = cat(_clear_u_mask_WIRE[3], _clear_u_mask_WIRE[2]) node clear_u_mask_lo = cat(clear_u_mask_lo_hi, clear_u_mask_lo_lo) node clear_u_mask_hi_lo = cat(_clear_u_mask_WIRE[5], _clear_u_mask_WIRE[4]) node clear_u_mask_hi_hi = cat(_clear_u_mask_WIRE[7], _clear_u_mask_WIRE[6]) node clear_u_mask_hi = cat(clear_u_mask_hi_hi, clear_u_mask_hi_lo) node clear_u_mask = cat(clear_u_mask_hi, clear_u_mask_lo) node _T_2 = shr(io.update_pc, 4) node idx_history_1 = bits(io.update_hist, 3, 0) node _idx_T_1 = xor(_T_2, idx_history_1) node update_idx = bits(_idx_T_1, 6, 0) node tag_history_1 = bits(io.update_hist, 3, 0) node _tag_T_2 = shr(_T_2, 7) node _tag_T_3 = xor(_tag_T_2, tag_history_1) node update_tag = bits(_tag_T_3, 6, 0) wire update_wdata : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] node _wen_T = or(io.update_mask[0], io.update_mask[1]) node _wen_T_1 = or(_wen_T, io.update_mask[2]) node _wen_T_2 = or(_wen_T_1, io.update_mask[3]) node _wen_T_3 = or(doing_reset, _wen_T_2) wire wen : UInt<1> connect wen, _wen_T_3 wire _rdata_WIRE : UInt<7> invalidate _rdata_WIRE when io.f1_req_valid : connect _rdata_WIRE, s1_hashed_idx read mport rdata = tage_table_4[_rdata_WIRE], clock reg REG : UInt<1>, clock connect REG, wen node _T_3 = and(REG, UInt<1>(0h0)) when _T_3 : wire _WIRE : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] connect _WIRE[0].ctr, UInt<3>(0h0) connect _WIRE[0].tag, UInt<7>(0h0) connect _WIRE[0].valid, UInt<1>(0h0) connect _WIRE[1].ctr, UInt<3>(0h0) connect _WIRE[1].tag, UInt<7>(0h0) connect _WIRE[1].valid, UInt<1>(0h0) connect _WIRE[2].ctr, UInt<3>(0h0) connect _WIRE[2].tag, UInt<7>(0h0) connect _WIRE[2].valid, UInt<1>(0h0) connect _WIRE[3].ctr, UInt<3>(0h0) connect _WIRE[3].tag, UInt<7>(0h0) connect _WIRE[3].valid, UInt<1>(0h0) connect s2_req_rtage, _WIRE else : wire _WIRE_1 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_2 : UInt<11> connect _WIRE_2, rdata[0] node _T_4 = bits(_WIRE_2, 2, 0) connect _WIRE_1.ctr, _T_4 node _T_5 = bits(_WIRE_2, 9, 3) connect _WIRE_1.tag, _T_5 node _T_6 = bits(_WIRE_2, 10, 10) connect _WIRE_1.valid, _T_6 wire _WIRE_3 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_4 : UInt<11> connect _WIRE_4, rdata[1] node _T_7 = bits(_WIRE_4, 2, 0) connect _WIRE_3.ctr, _T_7 node _T_8 = bits(_WIRE_4, 9, 3) connect _WIRE_3.tag, _T_8 node _T_9 = bits(_WIRE_4, 10, 10) connect _WIRE_3.valid, _T_9 wire _WIRE_5 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_6 : UInt<11> connect _WIRE_6, rdata[2] node _T_10 = bits(_WIRE_6, 2, 0) connect _WIRE_5.ctr, _T_10 node _T_11 = bits(_WIRE_6, 9, 3) connect _WIRE_5.tag, _T_11 node _T_12 = bits(_WIRE_6, 10, 10) connect _WIRE_5.valid, _T_12 wire _WIRE_7 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>} wire _WIRE_8 : UInt<11> connect _WIRE_8, rdata[3] node _T_13 = bits(_WIRE_8, 2, 0) connect _WIRE_7.ctr, _T_13 node _T_14 = bits(_WIRE_8, 9, 3) connect _WIRE_7.tag, _T_14 node _T_15 = bits(_WIRE_8, 10, 10) connect _WIRE_7.valid, _T_15 wire _WIRE_9 : { valid : UInt<1>, tag : UInt<7>, ctr : UInt<3>}[4] connect _WIRE_9[0].ctr, _WIRE_1.ctr connect _WIRE_9[0].tag, _WIRE_1.tag connect _WIRE_9[0].valid, _WIRE_1.valid connect _WIRE_9[1].ctr, _WIRE_3.ctr connect _WIRE_9[1].tag, _WIRE_3.tag connect _WIRE_9[1].valid, _WIRE_3.valid connect _WIRE_9[2].ctr, _WIRE_5.ctr connect _WIRE_9[2].tag, _WIRE_5.tag connect _WIRE_9[2].valid, _WIRE_5.valid connect _WIRE_9[3].ctr, _WIRE_7.ctr connect _WIRE_9[3].tag, _WIRE_7.tag connect _WIRE_9[3].valid, _WIRE_7.valid connect s2_req_rtage, _WIRE_9 when wen : node widx = mux(doing_reset, reset_idx, update_idx) wire _wdata_WIRE : UInt<11>[4] connect _wdata_WIRE[0], UInt<11>(0h0) connect _wdata_WIRE[1], UInt<11>(0h0) connect _wdata_WIRE[2], UInt<11>(0h0) connect _wdata_WIRE[3], UInt<11>(0h0) node wdata_hi = cat(update_wdata[0].valid, update_wdata[0].tag) node _wdata_T = cat(wdata_hi, update_wdata[0].ctr) node wdata_hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag) node _wdata_T_1 = cat(wdata_hi_1, update_wdata[1].ctr) node wdata_hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag) node _wdata_T_2 = cat(wdata_hi_2, update_wdata[2].ctr) node wdata_hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag) node _wdata_T_3 = cat(wdata_hi_3, update_wdata[3].ctr) wire _wdata_WIRE_1 : UInt<11>[4] connect _wdata_WIRE_1[0], _wdata_T connect _wdata_WIRE_1[1], _wdata_T_1 connect _wdata_WIRE_1[2], _wdata_T_2 connect _wdata_WIRE_1[3], _wdata_T_3 node wdata = mux(doing_reset, _wdata_WIRE, _wdata_WIRE_1) node _wmask_T = not(UInt<4>(0h0)) node wmask_lo = cat(io.update_mask[1], io.update_mask[0]) node wmask_hi = cat(io.update_mask[3], io.update_mask[2]) node _wmask_T_1 = cat(wmask_hi, wmask_lo) node wmask = mux(doing_reset, _wmask_T, _wmask_T_1) node _T_16 = bits(wmask, 0, 0) node _T_17 = bits(wmask, 1, 1) node _T_18 = bits(wmask, 2, 2) node _T_19 = bits(wmask, 3, 3) write mport MPORT = tage_table_4[widx], clock when _T_16 : connect MPORT[0], wdata[0] when _T_17 : connect MPORT[1], wdata[1] when _T_18 : connect MPORT[2], wdata[2] when _T_19 : connect MPORT[3], wdata[3] wire update_u_mask : UInt<1>[8] connect update_u_mask[0], io.update_u_mask[0] connect update_u_mask[1], io.update_u_mask[0] connect update_u_mask[2], io.update_u_mask[1] connect update_u_mask[3], io.update_u_mask[1] connect update_u_mask[4], io.update_u_mask[2] connect update_u_mask[5], io.update_u_mask[2] connect update_u_mask[6], io.update_u_mask[3] connect update_u_mask[7], io.update_u_mask[3] node _update_u_wen_T = or(doing_reset, doing_clear_u) node _update_u_wen_T_1 = or(update_u_mask[0], update_u_mask[1]) node _update_u_wen_T_2 = or(_update_u_wen_T_1, update_u_mask[2]) node _update_u_wen_T_3 = or(_update_u_wen_T_2, update_u_mask[3]) node _update_u_wen_T_4 = or(_update_u_wen_T_3, update_u_mask[4]) node _update_u_wen_T_5 = or(_update_u_wen_T_4, update_u_mask[5]) node _update_u_wen_T_6 = or(_update_u_wen_T_5, update_u_mask[6]) node _update_u_wen_T_7 = or(_update_u_wen_T_6, update_u_mask[7]) node _update_u_wen_T_8 = or(_update_u_wen_T, _update_u_wen_T_7) wire update_u_wen : UInt<1> connect update_u_wen, _update_u_wen_T_8 wire _u_rdata_WIRE : UInt<7> invalidate _u_rdata_WIRE when io.f1_req_valid : connect _u_rdata_WIRE, s1_hashed_idx read mport u_rdata = tage_u_4[_u_rdata_WIRE], clock connect s2_req_rus, u_rdata when update_u_wen : node _widx_T = mux(doing_clear_u, clear_u_idx, update_idx) node widx_1 = mux(doing_reset, reset_idx, _widx_T) node _wdata_T_4 = or(doing_reset, doing_clear_u) wire _wdata_WIRE_2 : UInt<1>[8] connect _wdata_WIRE_2[0], UInt<1>(0h0) connect _wdata_WIRE_2[1], UInt<1>(0h0) connect _wdata_WIRE_2[2], UInt<1>(0h0) connect _wdata_WIRE_2[3], UInt<1>(0h0) connect _wdata_WIRE_2[4], UInt<1>(0h0) connect _wdata_WIRE_2[5], UInt<1>(0h0) connect _wdata_WIRE_2[6], UInt<1>(0h0) connect _wdata_WIRE_2[7], UInt<1>(0h0) node wdata_lo = cat(io.update_u[1], io.update_u[0]) node wdata_hi_4 = cat(io.update_u[3], io.update_u[2]) node _wdata_T_5 = cat(wdata_hi_4, wdata_lo) node _wdata_T_6 = bits(_wdata_T_5, 0, 0) node _wdata_T_7 = bits(_wdata_T_5, 1, 1) node _wdata_T_8 = bits(_wdata_T_5, 2, 2) node _wdata_T_9 = bits(_wdata_T_5, 3, 3) node _wdata_T_10 = bits(_wdata_T_5, 4, 4) node _wdata_T_11 = bits(_wdata_T_5, 5, 5) node _wdata_T_12 = bits(_wdata_T_5, 6, 6) node _wdata_T_13 = bits(_wdata_T_5, 7, 7) wire _wdata_WIRE_3 : UInt<1>[8] connect _wdata_WIRE_3[0], _wdata_T_6 connect _wdata_WIRE_3[1], _wdata_T_7 connect _wdata_WIRE_3[2], _wdata_T_8 connect _wdata_WIRE_3[3], _wdata_T_9 connect _wdata_WIRE_3[4], _wdata_T_10 connect _wdata_WIRE_3[5], _wdata_T_11 connect _wdata_WIRE_3[6], _wdata_T_12 connect _wdata_WIRE_3[7], _wdata_T_13 node wdata_1 = mux(_wdata_T_4, _wdata_WIRE_2, _wdata_WIRE_3) node _wmask_T_2 = not(UInt<8>(0h0)) node wmask_lo_lo = cat(update_u_mask[1], update_u_mask[0]) node wmask_lo_hi = cat(update_u_mask[3], update_u_mask[2]) node wmask_lo_1 = cat(wmask_lo_hi, wmask_lo_lo) node wmask_hi_lo = cat(update_u_mask[5], update_u_mask[4]) node wmask_hi_hi = cat(update_u_mask[7], update_u_mask[6]) node wmask_hi_1 = cat(wmask_hi_hi, wmask_hi_lo) node _wmask_T_3 = cat(wmask_hi_1, wmask_lo_1) node _wmask_T_4 = mux(doing_clear_u, clear_u_mask, _wmask_T_3) node wmask_1 = mux(doing_reset, _wmask_T_2, _wmask_T_4) node _T_20 = bits(wmask_1, 0, 0) node _T_21 = bits(wmask_1, 1, 1) node _T_22 = bits(wmask_1, 2, 2) node _T_23 = bits(wmask_1, 3, 3) node _T_24 = bits(wmask_1, 4, 4) node _T_25 = bits(wmask_1, 5, 5) node _T_26 = bits(wmask_1, 6, 6) node _T_27 = bits(wmask_1, 7, 7) node _T_28 = bits(widx_1, 6, 0) write mport MPORT_1 = tage_u_4[_T_28], clock when _T_20 : connect MPORT_1[0], wdata_1[0] when _T_21 : connect MPORT_1[1], wdata_1[1] when _T_22 : connect MPORT_1[2], wdata_1[2] when _T_23 : connect MPORT_1[3], wdata_1[3] when _T_24 : connect MPORT_1[4], wdata_1[4] when _T_25 : connect MPORT_1[5], wdata_1[5] when _T_26 : connect MPORT_1[6], wdata_1[6] when _T_27 : connect MPORT_1[7], wdata_1[7] reg wrbypass_tags : UInt<7>[2], clock reg wrbypass_idxs : UInt<7>[2], clock reg wrbypass : UInt<3>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag) node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx) node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3) node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6) node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx) node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_4 connect wrbypass_hits[1], _wrbypass_hits_T_9 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1) node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4) node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1) node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8) node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9) node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0)) node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1) node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14) node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7)) node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1)) node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1) node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18) node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19) node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20) node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21) connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22 connect update_wdata[0].valid, UInt<1>(0h1) connect update_wdata[0].tag, update_tag node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1) node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4) node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1) node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8) node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9) node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0)) node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1) node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14) node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7)) node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1)) node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1) node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18) node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19) node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20) node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21) connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22 connect update_wdata[1].valid, UInt<1>(0h1) connect update_wdata[1].tag, update_tag node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1) node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4) node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1) node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8) node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9) node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0)) node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1) node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14) node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7)) node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1)) node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1) node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18) node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19) node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20) node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21) connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22 connect update_wdata[2].valid, UInt<1>(0h1) connect update_wdata[2].tag, update_tag node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3)) node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1) node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4) node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1) node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8) node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9) node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0)) node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1) node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14) node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7)) node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1)) node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1) node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18) node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19) node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20) node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21) connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22 connect update_wdata[3].valid, UInt<1>(0h1) connect update_wdata[3].tag, update_tag node _T_29 = or(io.update_mask[0], io.update_mask[1]) node _T_30 = or(_T_29, io.update_mask[2]) node _T_31 = or(_T_30, io.update_mask[3]) when _T_31 : node _T_32 = or(wrbypass_hits[0], wrbypass_hits[1]) when _T_32 : wire _WIRE_10 : UInt<3>[4] connect _WIRE_10[0], update_wdata[0].ctr connect _WIRE_10[1], update_wdata[1].ctr connect _WIRE_10[2], update_wdata[2].ctr connect _WIRE_10[3], update_wdata[3].ctr connect wrbypass[wrbypass_hit_idx], _WIRE_10 else : wire _WIRE_11 : UInt<3>[4] connect _WIRE_11[0], update_wdata[0].ctr connect _WIRE_11[1], update_wdata[1].ctr connect _WIRE_11[2], update_wdata[2].ctr connect _WIRE_11[3], update_wdata[3].ctr connect wrbypass[wrbypass_enq_idx], _WIRE_11 connect wrbypass_tags[wrbypass_enq_idx], update_tag connect wrbypass_idxs[wrbypass_enq_idx], update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2
module TageTable_7( // @[tage.scala:24:7] input clock, // @[tage.scala:24:7] input reset, // @[tage.scala:24:7] input io_f1_req_valid, // @[tage.scala:31:14] input [39:0] io_f1_req_pc, // @[tage.scala:31:14] input [63:0] io_f1_req_ghist, // @[tage.scala:31:14] output io_f2_resp_0_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_0_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_0_bits_u, // @[tage.scala:31:14] output io_f2_resp_1_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_1_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_1_bits_u, // @[tage.scala:31:14] output io_f2_resp_2_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_2_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_2_bits_u, // @[tage.scala:31:14] output io_f2_resp_3_valid, // @[tage.scala:31:14] output [2:0] io_f2_resp_3_bits_ctr, // @[tage.scala:31:14] output [1:0] io_f2_resp_3_bits_u, // @[tage.scala:31:14] input io_update_mask_0, // @[tage.scala:31:14] input io_update_mask_1, // @[tage.scala:31:14] input io_update_mask_2, // @[tage.scala:31:14] input io_update_mask_3, // @[tage.scala:31:14] input io_update_taken_0, // @[tage.scala:31:14] input io_update_taken_1, // @[tage.scala:31:14] input io_update_taken_2, // @[tage.scala:31:14] input io_update_taken_3, // @[tage.scala:31:14] input io_update_alloc_0, // @[tage.scala:31:14] input io_update_alloc_1, // @[tage.scala:31:14] input io_update_alloc_2, // @[tage.scala:31:14] input io_update_alloc_3, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14] input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14] input [39:0] io_update_pc, // @[tage.scala:31:14] input [63:0] io_update_hist, // @[tage.scala:31:14] input io_update_u_mask_0, // @[tage.scala:31:14] input io_update_u_mask_1, // @[tage.scala:31:14] input io_update_u_mask_2, // @[tage.scala:31:14] input io_update_u_mask_3, // @[tage.scala:31:14] input [1:0] io_update_u_0, // @[tage.scala:31:14] input [1:0] io_update_u_1, // @[tage.scala:31:14] input [1:0] io_update_u_2, // @[tage.scala:31:14] input [1:0] io_update_u_3 // @[tage.scala:31:14] ); wire [43:0] _tage_table_4_R0_data; // @[tage.scala:90:27] wire [7:0] _tage_u_4_R0_data; // @[tage.scala:89:27] wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7] wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7] wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7] wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7] wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7] wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7] wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7] wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7] wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7] wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7] wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7] wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7] wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7] wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7] wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7] wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7] wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7] wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7] wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7] wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7] wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7] wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7] wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7] wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7] wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7] wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7] wire update_wdata_0_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_1_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_2_valid = 1'h1; // @[tage.scala:120:26] wire update_wdata_3_valid = 1'h1; // @[tage.scala:120:26] wire [10:0] _wdata_WIRE_0 = 11'h0; // @[tage.scala:130:41] wire [10:0] _wdata_WIRE_1 = 11'h0; // @[tage.scala:130:41] wire [10:0] _wdata_WIRE_2 = 11'h0; // @[tage.scala:130:41] wire [10:0] _wdata_WIRE_3 = 11'h0; // @[tage.scala:130:41] wire [3:0] _wmask_T = 4'hF; // @[tage.scala:131:34] wire _wdata_WIRE_2_0 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_1 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_2 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_3 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_4 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_5 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_6 = 1'h0; // @[tage.scala:145:58] wire _wdata_WIRE_2_7 = 1'h0; // @[tage.scala:145:58] wire [7:0] _wmask_T_2 = 8'hFF; // @[tage.scala:146:34] wire s2_req_rhits_0; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_0_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_0_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_1; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_1_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_1_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_2; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_2_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_2_bits_u_T; // @[tage.scala:105:34] wire s2_req_rhits_3; // @[tage.scala:100:29] wire [2:0] s2_req_rtage_3_ctr; // @[tage.scala:98:26] wire [1:0] _io_f2_resp_3_bits_u_T; // @[tage.scala:105:34] wire update_u_mask_0 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_1 = io_update_u_mask_0_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_2 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_3 = io_update_u_mask_1_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_4 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_5 = io_update_u_mask_2_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_6 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire update_u_mask_7 = io_update_u_mask_3_0; // @[tage.scala:24:7, :135:30] wire [2:0] io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_0_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_1_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_2_valid_0; // @[tage.scala:24:7] wire [2:0] io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] wire [1:0] io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] wire io_f2_resp_3_valid_0; // @[tage.scala:24:7] reg doing_reset; // @[tage.scala:72:28] reg [6:0] reset_idx; // @[tage.scala:73:26] wire [7:0] _GEN = {1'h0, reset_idx}; // @[tage.scala:73:26, :74:26] wire [7:0] _reset_idx_T = _GEN + {7'h0, doing_reset}; // @[tage.scala:72:28, :74:26] wire [6:0] _reset_idx_T_1 = _reset_idx_T[6:0]; // @[tage.scala:74:26] wire [3:0] idx_history = io_f1_req_ghist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [3:0] tag_history = io_f1_req_ghist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [35:0] _idx_T = {io_f1_req_pc_0[39:8], io_f1_req_pc_0[7:4] ^ idx_history}; // @[frontend.scala:149:35] wire [6:0] s1_hashed_idx = _idx_T[6:0]; // @[tage.scala:60:{29,43}] wire [6:0] _rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :122:99] wire [6:0] _u_rdata_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :140:12] wire [28:0] _tag_T = io_f1_req_pc_0[39:11]; // @[frontend.scala:149:35] wire [28:0] _tag_T_1 = {_tag_T[28:4], _tag_T[3:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] s1_tag = _tag_T_1[6:0]; // @[tage.scala:62:{50,64}] wire wdata_1_0; // @[tage.scala:145:20] wire wdata_1_1; // @[tage.scala:145:20] wire wdata_1_2; // @[tage.scala:145:20] wire wdata_1_3; // @[tage.scala:145:20] wire wdata_1_4; // @[tage.scala:145:20] wire wdata_1_5; // @[tage.scala:145:20] wire wdata_1_6; // @[tage.scala:145:20] wire wdata_1_7; // @[tage.scala:145:20] wire s2_req_rus_0 = _tage_u_4_R0_data[0]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_1 = _tage_u_4_R0_data[1]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_2 = _tage_u_4_R0_data[2]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_3 = _tage_u_4_R0_data[3]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_4 = _tage_u_4_R0_data[4]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_5 = _tage_u_4_R0_data[5]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_6 = _tage_u_4_R0_data[6]; // @[tage.scala:89:27, :99:24] wire s2_req_rus_7 = _tage_u_4_R0_data[7]; // @[tage.scala:89:27, :99:24] wire [10:0] wdata_0; // @[tage.scala:130:20] wire [10:0] wdata_1; // @[tage.scala:130:20] wire [10:0] wdata_2; // @[tage.scala:130:20] wire [10:0] wdata_3; // @[tage.scala:130:20] reg [6:0] s2_tag; // @[tage.scala:96:29] assign io_f2_resp_0_bits_ctr_0 = s2_req_rtage_0_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_1_bits_ctr_0 = s2_req_rtage_1_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_2_bits_ctr_0 = s2_req_rtage_2_ctr; // @[tage.scala:24:7, :98:26] assign io_f2_resp_3_bits_ctr_0 = s2_req_rtage_3_ctr; // @[tage.scala:24:7, :98:26] wire s2_req_rtage_0_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_0_tag; // @[tage.scala:98:26] wire s2_req_rtage_1_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_1_tag; // @[tage.scala:98:26] wire s2_req_rtage_2_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_2_tag; // @[tage.scala:98:26] wire s2_req_rtage_3_valid; // @[tage.scala:98:26] wire [6:0] s2_req_rtage_3_tag; // @[tage.scala:98:26] wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}] wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:96:29, :98:26, :100:69] wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:98:26, :100:{60,69}] wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83] wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}] assign s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}] assign io_f2_resp_0_valid_0 = s2_req_rhits_0; // @[tage.scala:24:7, :100:29] assign io_f2_resp_1_valid_0 = s2_req_rhits_1; // @[tage.scala:24:7, :100:29] assign io_f2_resp_2_valid_0 = s2_req_rhits_2; // @[tage.scala:24:7, :100:29] assign io_f2_resp_3_valid_0 = s2_req_rhits_3; // @[tage.scala:24:7, :100:29] assign _io_f2_resp_0_bits_u_T = {s2_req_rus_1, s2_req_rus_0}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_0_bits_u_0 = _io_f2_resp_0_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_1_bits_u_T = {s2_req_rus_3, s2_req_rus_2}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_1_bits_u_0 = _io_f2_resp_1_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_2_bits_u_T = {s2_req_rus_5, s2_req_rus_4}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_2_bits_u_0 = _io_f2_resp_2_bits_u_T; // @[tage.scala:24:7, :105:34] assign _io_f2_resp_3_bits_u_T = {s2_req_rus_7, s2_req_rus_6}; // @[tage.scala:99:24, :105:34] assign io_f2_resp_3_bits_u_0 = _io_f2_resp_3_bits_u_T; // @[tage.scala:24:7, :105:34] reg [18:0] clear_u_ctr; // @[tage.scala:109:28] wire [19:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 20'h1; // @[tage.scala:109:28, :110:85] wire [18:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[18:0]; // @[tage.scala:110:85] wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34] wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}] wire _clear_u_hi_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31] wire _clear_u_lo_T = clear_u_ctr[18]; // @[tage.scala:109:28, :113:31, :114:31] wire clear_u_hi = _clear_u_hi_T; // @[tage.scala:113:{31,72}] wire _clear_u_mask_WIRE_1 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_3 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_5 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire _clear_u_mask_WIRE_7 = clear_u_hi; // @[tage.scala:113:72, :116:29] wire clear_u_lo = ~_clear_u_lo_T; // @[tage.scala:114:{31,72}] wire _clear_u_mask_WIRE_0 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_2 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_4 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire _clear_u_mask_WIRE_6 = clear_u_lo; // @[tage.scala:114:72, :116:29] wire [7:0] clear_u_idx = clear_u_ctr[18:11]; // @[tage.scala:109:28, :115:33] wire [1:0] clear_u_mask_lo_lo = {_clear_u_mask_WIRE_1, _clear_u_mask_WIRE_0}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_lo_hi = {_clear_u_mask_WIRE_3, _clear_u_mask_WIRE_2}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_lo = {clear_u_mask_lo_hi, clear_u_mask_lo_lo}; // @[tage.scala:116:109] wire [1:0] clear_u_mask_hi_lo = {_clear_u_mask_WIRE_5, _clear_u_mask_WIRE_4}; // @[tage.scala:116:{29,109}] wire [1:0] clear_u_mask_hi_hi = {_clear_u_mask_WIRE_7, _clear_u_mask_WIRE_6}; // @[tage.scala:116:{29,109}] wire [3:0] clear_u_mask_hi = {clear_u_mask_hi_hi, clear_u_mask_hi_lo}; // @[tage.scala:116:109] wire [7:0] clear_u_mask = {clear_u_mask_hi, clear_u_mask_lo}; // @[tage.scala:116:109] wire [3:0] idx_history_1 = io_update_hist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [3:0] tag_history_1 = io_update_hist_0[3:0]; // @[tage.scala:24:7, :53:11] wire [35:0] _idx_T_1 = {io_update_pc_0[39:8], io_update_pc_0[7:4] ^ idx_history_1}; // @[frontend.scala:149:35] wire [6:0] update_idx = _idx_T_1[6:0]; // @[tage.scala:60:{29,43}] wire [28:0] _tag_T_2 = io_update_pc_0[39:11]; // @[frontend.scala:149:35] wire [28:0] _tag_T_3 = {_tag_T_2[28:4], _tag_T_2[3:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}] wire [6:0] update_tag = _tag_T_3[6:0]; // @[tage.scala:62:{50,64}] wire [6:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [6:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [6:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [6:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :120:26] wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:168:33] wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:168:33] wire [2:0] update_wdata_0_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_1_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_2_ctr; // @[tage.scala:120:26] wire [2:0] update_wdata_3_ctr; // @[tage.scala:120:26] wire _wen_T = io_update_mask_0_0 | io_update_mask_1_0; // @[tage.scala:24:7, :121:60] wire _wen_T_1 = _wen_T | io_update_mask_2_0; // @[tage.scala:24:7, :121:60] wire _wen_T_2 = _wen_T_1 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60] wire _wen_T_3 = doing_reset | _wen_T_2; // @[tage.scala:72:28, :121:{34,60}] wire wen = _wen_T_3; // @[tage.scala:121:{21,34}] reg REG; // @[tage.scala:123:16] assign s2_req_rtage_0_ctr = _tage_table_4_R0_data[2:0]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_tag = _tage_table_4_R0_data[9:3]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_0_valid = _tage_table_4_R0_data[10]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_ctr = _tage_table_4_R0_data[13:11]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_tag = _tage_table_4_R0_data[20:14]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_1_valid = _tage_table_4_R0_data[21]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_ctr = _tage_table_4_R0_data[24:22]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_tag = _tage_table_4_R0_data[31:25]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_2_valid = _tage_table_4_R0_data[32]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_ctr = _tage_table_4_R0_data[35:33]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_tag = _tage_table_4_R0_data[42:36]; // @[tage.scala:90:27, :98:26, :126:49] assign s2_req_rtage_3_valid = _tage_table_4_R0_data[43]; // @[tage.scala:90:27, :98:26, :126:49] wire [6:0] widx = doing_reset ? reset_idx : update_idx; // @[tage.scala:60:43, :72:28, :73:26, :129:19] wire [7:0] wdata_hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T = {wdata_hi, update_wdata_0_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_0 = _wdata_T; // @[tage.scala:130:{94,114}] wire [7:0] wdata_hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T_1 = {wdata_hi_1, update_wdata_1_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_1 = _wdata_T_1; // @[tage.scala:130:{94,114}] wire [7:0] wdata_hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T_2 = {wdata_hi_2, update_wdata_2_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_2 = _wdata_T_2; // @[tage.scala:130:{94,114}] wire [7:0] wdata_hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_T_3 = {wdata_hi_3, update_wdata_3_ctr}; // @[tage.scala:120:26, :130:114] wire [10:0] _wdata_WIRE_1_3 = _wdata_T_3; // @[tage.scala:130:{94,114}] assign wdata_0 = doing_reset ? 11'h0 : _wdata_WIRE_1_0; // @[tage.scala:72:28, :130:{20,94}] assign wdata_1 = doing_reset ? 11'h0 : _wdata_WIRE_1_1; // @[tage.scala:72:28, :130:{20,94}] assign wdata_2 = doing_reset ? 11'h0 : _wdata_WIRE_1_2; // @[tage.scala:72:28, :130:{20,94}] assign wdata_3 = doing_reset ? 11'h0 : _wdata_WIRE_1_3; // @[tage.scala:72:28, :130:{20,94}] wire [1:0] wmask_lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :131:70] wire [1:0] wmask_hi = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :131:70] wire [3:0] _wmask_T_1 = {wmask_hi, wmask_lo}; // @[tage.scala:131:70] wire [3:0] wmask = doing_reset ? 4'hF : _wmask_T_1; // @[tage.scala:72:28, :131:{20,70}] wire _GEN_0 = doing_reset | doing_clear_u; // @[tage.scala:72:28, :112:61, :136:43] wire _update_u_wen_T; // @[tage.scala:136:43] assign _update_u_wen_T = _GEN_0; // @[tage.scala:136:43] wire _wdata_T_4; // @[tage.scala:145:33] assign _wdata_T_4 = _GEN_0; // @[tage.scala:136:43, :145:33] wire _update_u_wen_T_1 = update_u_mask_0 | update_u_mask_1; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_2 = _update_u_wen_T_1 | update_u_mask_2; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_3 = _update_u_wen_T_2 | update_u_mask_3; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_4 = _update_u_wen_T_3 | update_u_mask_4; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_5 = _update_u_wen_T_4 | update_u_mask_5; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_6 = _update_u_wen_T_5 | update_u_mask_6; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_7 = _update_u_wen_T_6 | update_u_mask_7; // @[tage.scala:135:30, :136:85] wire _update_u_wen_T_8 = _update_u_wen_T | _update_u_wen_T_7; // @[tage.scala:136:{43,60,85}] wire update_u_wen = _update_u_wen_T_8; // @[tage.scala:136:{30,60}] wire [7:0] _widx_T = doing_clear_u ? clear_u_idx : {1'h0, update_idx}; // @[tage.scala:60:43, :112:61, :115:33, :144:47] wire [7:0] widx_1 = doing_reset ? _GEN : _widx_T; // @[tage.scala:72:28, :74:26, :144:{19,47}] wire [3:0] wdata_lo = {io_update_u_1_0, io_update_u_0_0}; // @[tage.scala:24:7, :145:110] wire [3:0] wdata_hi_4 = {io_update_u_3_0, io_update_u_2_0}; // @[tage.scala:24:7, :145:110] wire [7:0] _wdata_T_5 = {wdata_hi_4, wdata_lo}; // @[tage.scala:145:110] wire _wdata_T_6 = _wdata_T_5[0]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_0 = _wdata_T_6; // @[tage.scala:145:{97,117}] wire _wdata_T_7 = _wdata_T_5[1]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_1 = _wdata_T_7; // @[tage.scala:145:{97,117}] wire _wdata_T_8 = _wdata_T_5[2]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_2 = _wdata_T_8; // @[tage.scala:145:{97,117}] wire _wdata_T_9 = _wdata_T_5[3]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_3 = _wdata_T_9; // @[tage.scala:145:{97,117}] wire _wdata_T_10 = _wdata_T_5[4]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_4 = _wdata_T_10; // @[tage.scala:145:{97,117}] wire _wdata_T_11 = _wdata_T_5[5]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_5 = _wdata_T_11; // @[tage.scala:145:{97,117}] wire _wdata_T_12 = _wdata_T_5[6]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_6 = _wdata_T_12; // @[tage.scala:145:{97,117}] wire _wdata_T_13 = _wdata_T_5[7]; // @[tage.scala:145:{110,117}] wire _wdata_WIRE_3_7 = _wdata_T_13; // @[tage.scala:145:{97,117}] assign wdata_1_0 = ~_wdata_T_4 & _wdata_WIRE_3_0; // @[tage.scala:145:{20,33,97}] assign wdata_1_1 = ~_wdata_T_4 & _wdata_WIRE_3_1; // @[tage.scala:145:{20,33,97}] assign wdata_1_2 = ~_wdata_T_4 & _wdata_WIRE_3_2; // @[tage.scala:145:{20,33,97}] assign wdata_1_3 = ~_wdata_T_4 & _wdata_WIRE_3_3; // @[tage.scala:145:{20,33,97}] assign wdata_1_4 = ~_wdata_T_4 & _wdata_WIRE_3_4; // @[tage.scala:145:{20,33,97}] assign wdata_1_5 = ~_wdata_T_4 & _wdata_WIRE_3_5; // @[tage.scala:145:{20,33,97}] assign wdata_1_6 = ~_wdata_T_4 & _wdata_WIRE_3_6; // @[tage.scala:145:{20,33,97}] assign wdata_1_7 = ~_wdata_T_4 & _wdata_WIRE_3_7; // @[tage.scala:145:{20,33,97}] wire [1:0] wmask_lo_lo = {update_u_mask_1, update_u_mask_0}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_lo_hi = {update_u_mask_3, update_u_mask_2}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_lo_1 = {wmask_lo_hi, wmask_lo_lo}; // @[tage.scala:146:106] wire [1:0] wmask_hi_lo = {update_u_mask_5, update_u_mask_4}; // @[tage.scala:135:30, :146:106] wire [1:0] wmask_hi_hi = {update_u_mask_7, update_u_mask_6}; // @[tage.scala:135:30, :146:106] wire [3:0] wmask_hi_1 = {wmask_hi_hi, wmask_hi_lo}; // @[tage.scala:146:106] wire [7:0] _wmask_T_3 = {wmask_hi_1, wmask_lo_1}; // @[tage.scala:146:106] wire [7:0] _wmask_T_4 = doing_clear_u ? clear_u_mask : _wmask_T_3; // @[tage.scala:112:61, :116:109, :146:{62,106}] wire [7:0] wmask_1 = doing_reset ? 8'hFF : _wmask_T_4; // @[tage.scala:72:28, :146:{20,62}] reg [6:0] wrbypass_tags_0; // @[tage.scala:154:29] reg [6:0] wrbypass_tags_1; // @[tage.scala:154:29] reg [6:0] wrbypass_idxs_0; // @[tage.scala:155:29] reg [6:0] wrbypass_idxs_1; // @[tage.scala:155:29] reg [2:0] wrbypass_0_0; // @[tage.scala:156:29] reg [2:0] wrbypass_0_1; // @[tage.scala:156:29] reg [2:0] wrbypass_0_2; // @[tage.scala:156:29] reg [2:0] wrbypass_0_3; // @[tage.scala:156:29] reg [2:0] wrbypass_1_0; // @[tage.scala:156:29] reg [2:0] wrbypass_1_1; // @[tage.scala:156:29] reg [2:0] wrbypass_1_2; // @[tage.scala:156:29] reg [2:0] wrbypass_1_3; // @[tage.scala:156:29] reg wrbypass_enq_idx; // @[tage.scala:157:33] wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:159:33, :161:37] wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :160:5] wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :154:29, :161:22] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:160:{5,18}, :161:22] wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :155:29, :162:22] wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:160:18, :161:37, :162:22] wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:159:33, :161:37] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:159:33, :164:48] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70] wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70] wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70] wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70] wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :169:10] wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25] wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}] wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25] wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20] wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9] wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25] wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43] wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43] wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}] wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25] wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43] wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43] wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}] wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20] wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :164:48, :172:10] assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :168:33, :169:10, :172:10] assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:120:26, :168:33] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:211:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:211:{14,20}] wire _T_31 = _wen_T | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :121:60, :180:32] wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] wire _GEN_14 = ~_T_31 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] wire _GEN_15 = ~_T_31 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:154:29, :156:29, :157:33, :164:48, :180:{32,38}, :181:39, :185:39] always @(posedge clock) begin // @[tage.scala:24:7] if (reset) begin // @[tage.scala:24:7] doing_reset <= 1'h1; // @[tage.scala:72:28] reset_idx <= 7'h0; // @[tage.scala:73:26] clear_u_ctr <= 19'h0; // @[tage.scala:109:28] wrbypass_enq_idx <= 1'h0; // @[tage.scala:157:33] end else begin // @[tage.scala:24:7] doing_reset <= reset_idx != 7'h7F & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26] clear_u_ctr <= doing_reset ? 19'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}] if (~_T_31 | wrbypass_hit) begin // @[tage.scala:156:29, :157:33, :164:48, :180:{32,38}, :181:39] end else // @[tage.scala:157:33, :180:38, :181:39] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:211:20] end s2_tag <= s1_tag; // @[tage.scala:62:64, :96:29] REG <= wen; // @[tage.scala:121:21, :123:16] if (_GEN_14) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_15) begin // @[tage.scala:154:29, :180:38, :181:39, :185:39] end else // @[tage.scala:154:29, :180:38, :181:39, :185:39] wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :154:29] if (_GEN_14) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :155:29] if (_GEN_15) begin // @[tage.scala:154:29, :155:29, :180:38, :181:39, :185:39, :186:39] end else // @[tage.scala:155:29, :180:38, :181:39, :186:39] wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :155:29] if (~_T_31 | _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] end else begin // @[tage.scala:156:29, :180:38, :181:39] wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end if (_T_31 & _GEN_13) begin // @[tage.scala:156:29, :180:{32,38}, :181:39, :182:34, :184:39] wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:120:26, :156:29] wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:120:26, :156:29] end always @(posedge) tage_u_4_0 tage_u_4 ( // @[tage.scala:89:27] .R0_addr (_u_rdata_WIRE), // @[tage.scala:140:12] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_u_4_R0_data), .W0_addr (widx_1[6:0]), // @[tage.scala:144:19, :147:13] .W0_en (update_u_wen), // @[tage.scala:136:30] .W0_clk (clock), .W0_data ({wdata_1_7, wdata_1_6, wdata_1_5, wdata_1_4, wdata_1_3, wdata_1_2, wdata_1_1, wdata_1_0}), // @[tage.scala:89:27, :145:20] .W0_mask (wmask_1) // @[tage.scala:146:20] ); // @[tage.scala:89:27] tage_table_4_0 tage_table_4 ( // @[tage.scala:90:27] .R0_addr (_rdata_WIRE), // @[tage.scala:122:99] .R0_en (io_f1_req_valid_0), // @[tage.scala:24:7] .R0_clk (clock), .R0_data (_tage_table_4_R0_data), .W0_addr (widx), // @[tage.scala:129:19] .W0_en (wen), // @[tage.scala:121:21] .W0_clk (clock), .W0_data ({wdata_3, wdata_2, wdata_1, wdata_0}), // @[tage.scala:90:27, :130:20] .W0_mask (wmask) // @[tage.scala:131:20] ); // @[tage.scala:90:27] assign io_f2_resp_0_valid = io_f2_resp_0_valid_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_ctr = io_f2_resp_0_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_0_bits_u = io_f2_resp_0_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_1_valid = io_f2_resp_1_valid_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_ctr = io_f2_resp_1_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_1_bits_u = io_f2_resp_1_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_2_valid = io_f2_resp_2_valid_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_ctr = io_f2_resp_2_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_2_bits_u = io_f2_resp_2_bits_u_0; // @[tage.scala:24:7] assign io_f2_resp_3_valid = io_f2_resp_3_valid_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_ctr = io_f2_resp_3_bits_ctr_0; // @[tage.scala:24:7] assign io_f2_resp_3_bits_u = io_f2_resp_3_bits_u_0; // @[tage.scala:24:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BIMBranchPredictorBank_3 : input clock : Clock input reset : Reset output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}} connect io.resp, io.resp_in[0] connect io.f3_meta, UInt<1>(0h0) node s0_idx = shr(io.f0_pc, 4) reg s1_idx : UInt, clock connect s1_idx, s0_idx reg s2_idx : UInt, clock connect s2_idx, s1_idx reg s3_idx : UInt, clock connect s3_idx, s2_idx reg s1_valid : UInt<1>, clock connect s1_valid, io.f0_valid reg s2_valid : UInt<1>, clock connect s2_valid, s1_valid reg s3_valid : UInt<1>, clock connect s3_valid, s2_valid reg s1_mask : UInt, clock connect s1_mask, io.f0_mask reg s2_mask : UInt, clock connect s2_mask, s1_mask reg s3_mask : UInt, clock connect s3_mask, s2_mask reg s1_pc : UInt, clock connect s1_pc, io.f0_pc node s0_update_idx = shr(io.update.bits.pc, 4) reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock connect s1_update.bits.meta, io.update.bits.meta connect s1_update.bits.target, io.update.bits.target connect s1_update.bits.lhist, io.update.bits.lhist connect s1_update.bits.ghist, io.update.bits.ghist connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid connect s1_update.bits.br_mask, io.update.bits.br_mask connect s1_update.bits.pc, io.update.bits.pc connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update connect s1_update.valid, io.update.valid reg s1_update_idx : UInt, clock connect s1_update_idx, s0_update_idx reg s1_update_valid : UInt<1>, clock connect s1_update_valid, io.update.valid wire s2_meta : { bims : UInt<2>[4]} node lo = cat(s2_meta.bims[1], s2_meta.bims[0]) node hi = cat(s2_meta.bims[3], s2_meta.bims[2]) node _T = cat(hi, lo) regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1) regreset reset_idx : UInt<11>, clock, reset, UInt<11>(0h0) node _reset_idx_T = add(reset_idx, doing_reset) node _reset_idx_T_1 = tail(_reset_idx_T, 1) connect reset_idx, _reset_idx_T_1 node _T_1 = eq(reset_idx, UInt<11>(0h7ff)) when _T_1 : connect doing_reset, UInt<1>(0h0) smem data : UInt<2>[4] [2048] wire _s2_req_rdata_WIRE : UInt<36> invalidate _s2_req_rdata_WIRE when io.f0_valid : connect _s2_req_rdata_WIRE, s0_idx node _s2_req_rdata_T = bits(_s2_req_rdata_WIRE, 10, 0) read mport s2_req_rdata_MPORT = data[_s2_req_rdata_T], clock reg s2_req_rdata : UInt<2>[4], clock connect s2_req_rdata, s2_req_rdata_MPORT wire s2_resp : UInt<1>[4] node _s2_resp_0_T = bits(s2_req_rdata[0], 1, 1) node _s2_resp_0_T_1 = and(s2_valid, _s2_resp_0_T) node _s2_resp_0_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_0_T_3 = and(_s2_resp_0_T_1, _s2_resp_0_T_2) connect s2_resp[0], _s2_resp_0_T_3 connect s2_meta.bims[0], s2_req_rdata[0] node _s2_resp_1_T = bits(s2_req_rdata[1], 1, 1) node _s2_resp_1_T_1 = and(s2_valid, _s2_resp_1_T) node _s2_resp_1_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_1_T_3 = and(_s2_resp_1_T_1, _s2_resp_1_T_2) connect s2_resp[1], _s2_resp_1_T_3 connect s2_meta.bims[1], s2_req_rdata[1] node _s2_resp_2_T = bits(s2_req_rdata[2], 1, 1) node _s2_resp_2_T_1 = and(s2_valid, _s2_resp_2_T) node _s2_resp_2_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_2_T_3 = and(_s2_resp_2_T_1, _s2_resp_2_T_2) connect s2_resp[2], _s2_resp_2_T_3 connect s2_meta.bims[2], s2_req_rdata[2] node _s2_resp_3_T = bits(s2_req_rdata[3], 1, 1) node _s2_resp_3_T_1 = and(s2_valid, _s2_resp_3_T) node _s2_resp_3_T_2 = eq(doing_reset, UInt<1>(0h0)) node _s2_resp_3_T_3 = and(_s2_resp_3_T_1, _s2_resp_3_T_2) connect s2_resp[3], _s2_resp_3_T_3 connect s2_meta.bims[3], s2_req_rdata[3] wire s1_update_wdata : UInt<2>[4] wire s1_update_wmask : UInt<1>[4] wire s1_update_meta : { bims : UInt<2>[4]} wire _s1_update_meta_WIRE : UInt<8> connect _s1_update_meta_WIRE, s1_update.bits.meta node _s1_update_meta_T = bits(_s1_update_meta_WIRE, 1, 0) connect s1_update_meta.bims[0], _s1_update_meta_T node _s1_update_meta_T_1 = bits(_s1_update_meta_WIRE, 3, 2) connect s1_update_meta.bims[1], _s1_update_meta_T_1 node _s1_update_meta_T_2 = bits(_s1_update_meta_WIRE, 5, 4) connect s1_update_meta.bims[2], _s1_update_meta_T_2 node _s1_update_meta_T_3 = bits(_s1_update_meta_WIRE, 7, 6) connect s1_update_meta.bims[3], _s1_update_meta_T_3 reg wrbypass_idxs : UInt<11>[2], clock reg wrbypass : UInt<2>[4][2], clock regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0) node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_1 = bits(s1_update_idx, 10, 0) node _wrbypass_hits_T_2 = eq(wrbypass_idxs[0], _wrbypass_hits_T_1) node _wrbypass_hits_T_3 = and(_wrbypass_hits_T, _wrbypass_hits_T_2) node _wrbypass_hits_T_4 = eq(doing_reset, UInt<1>(0h0)) node _wrbypass_hits_T_5 = bits(s1_update_idx, 10, 0) node _wrbypass_hits_T_6 = eq(wrbypass_idxs[1], _wrbypass_hits_T_5) node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_4, _wrbypass_hits_T_6) wire wrbypass_hits : UInt<1>[2] connect wrbypass_hits[0], _wrbypass_hits_T_3 connect wrbypass_hits[1], _wrbypass_hits_T_7 node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1]) node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1)) connect s1_update_wmask[0], UInt<1>(0h0) invalidate s1_update_wdata[0] node _update_pc_T = add(s1_update.bits.pc, UInt<1>(0h0)) node update_pc = tail(_update_pc_T, 1) node _T_2 = bits(s1_update.bits.br_mask, 0, 0) node _T_3 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _T_4 = and(s1_update.bits.cfi_idx.valid, _T_3) node _T_5 = or(_T_2, _T_4) when _T_5 : node _was_taken_T = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h0)) node _was_taken_T_1 = and(s1_update.bits.cfi_idx.valid, _was_taken_T) node _was_taken_T_2 = bits(s1_update.bits.br_mask, 0, 0) node _was_taken_T_3 = and(s1_update.bits.cfi_is_br, _was_taken_T_2) node _was_taken_T_4 = and(_was_taken_T_3, s1_update.bits.cfi_taken) node _was_taken_T_5 = or(_was_taken_T_4, s1_update.bits.cfi_is_jal) node was_taken = and(_was_taken_T_1, _was_taken_T_5) node old_bim_value = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][0], s1_update_meta.bims[0]) connect s1_update_wmask[0], UInt<1>(0h1) node s1_update_wdata_0_old_bim_sat_taken = eq(old_bim_value, UInt<2>(0h3)) node s1_update_wdata_0_old_bim_sat_ntaken = eq(old_bim_value, UInt<1>(0h0)) node _s1_update_wdata_0_T = and(s1_update_wdata_0_old_bim_sat_taken, was_taken) node _s1_update_wdata_0_T_1 = eq(was_taken, UInt<1>(0h0)) node _s1_update_wdata_0_T_2 = and(s1_update_wdata_0_old_bim_sat_ntaken, _s1_update_wdata_0_T_1) node _s1_update_wdata_0_T_3 = add(old_bim_value, UInt<1>(0h1)) node _s1_update_wdata_0_T_4 = tail(_s1_update_wdata_0_T_3, 1) node _s1_update_wdata_0_T_5 = sub(old_bim_value, UInt<1>(0h1)) node _s1_update_wdata_0_T_6 = tail(_s1_update_wdata_0_T_5, 1) node _s1_update_wdata_0_T_7 = mux(was_taken, _s1_update_wdata_0_T_4, _s1_update_wdata_0_T_6) node _s1_update_wdata_0_T_8 = mux(_s1_update_wdata_0_T_2, UInt<1>(0h0), _s1_update_wdata_0_T_7) node _s1_update_wdata_0_T_9 = mux(_s1_update_wdata_0_T, UInt<2>(0h3), _s1_update_wdata_0_T_8) connect s1_update_wdata[0], _s1_update_wdata_0_T_9 connect s1_update_wmask[1], UInt<1>(0h0) invalidate s1_update_wdata[1] node _update_pc_T_1 = add(s1_update.bits.pc, UInt<2>(0h2)) node update_pc_1 = tail(_update_pc_T_1, 1) node _T_6 = bits(s1_update.bits.br_mask, 1, 1) node _T_7 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _T_8 = and(s1_update.bits.cfi_idx.valid, _T_7) node _T_9 = or(_T_6, _T_8) when _T_9 : node _was_taken_T_6 = eq(s1_update.bits.cfi_idx.bits, UInt<1>(0h1)) node _was_taken_T_7 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_6) node _was_taken_T_8 = bits(s1_update.bits.br_mask, 1, 1) node _was_taken_T_9 = and(s1_update.bits.cfi_is_br, _was_taken_T_8) node _was_taken_T_10 = and(_was_taken_T_9, s1_update.bits.cfi_taken) node _was_taken_T_11 = or(_was_taken_T_10, s1_update.bits.cfi_is_jal) node was_taken_1 = and(_was_taken_T_7, _was_taken_T_11) node old_bim_value_1 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][1], s1_update_meta.bims[1]) connect s1_update_wmask[1], UInt<1>(0h1) node s1_update_wdata_1_old_bim_sat_taken = eq(old_bim_value_1, UInt<2>(0h3)) node s1_update_wdata_1_old_bim_sat_ntaken = eq(old_bim_value_1, UInt<1>(0h0)) node _s1_update_wdata_1_T = and(s1_update_wdata_1_old_bim_sat_taken, was_taken_1) node _s1_update_wdata_1_T_1 = eq(was_taken_1, UInt<1>(0h0)) node _s1_update_wdata_1_T_2 = and(s1_update_wdata_1_old_bim_sat_ntaken, _s1_update_wdata_1_T_1) node _s1_update_wdata_1_T_3 = add(old_bim_value_1, UInt<1>(0h1)) node _s1_update_wdata_1_T_4 = tail(_s1_update_wdata_1_T_3, 1) node _s1_update_wdata_1_T_5 = sub(old_bim_value_1, UInt<1>(0h1)) node _s1_update_wdata_1_T_6 = tail(_s1_update_wdata_1_T_5, 1) node _s1_update_wdata_1_T_7 = mux(was_taken_1, _s1_update_wdata_1_T_4, _s1_update_wdata_1_T_6) node _s1_update_wdata_1_T_8 = mux(_s1_update_wdata_1_T_2, UInt<1>(0h0), _s1_update_wdata_1_T_7) node _s1_update_wdata_1_T_9 = mux(_s1_update_wdata_1_T, UInt<2>(0h3), _s1_update_wdata_1_T_8) connect s1_update_wdata[1], _s1_update_wdata_1_T_9 connect s1_update_wmask[2], UInt<1>(0h0) invalidate s1_update_wdata[2] node _update_pc_T_2 = add(s1_update.bits.pc, UInt<3>(0h4)) node update_pc_2 = tail(_update_pc_T_2, 1) node _T_10 = bits(s1_update.bits.br_mask, 2, 2) node _T_11 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _T_12 = and(s1_update.bits.cfi_idx.valid, _T_11) node _T_13 = or(_T_10, _T_12) when _T_13 : node _was_taken_T_12 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h2)) node _was_taken_T_13 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_12) node _was_taken_T_14 = bits(s1_update.bits.br_mask, 2, 2) node _was_taken_T_15 = and(s1_update.bits.cfi_is_br, _was_taken_T_14) node _was_taken_T_16 = and(_was_taken_T_15, s1_update.bits.cfi_taken) node _was_taken_T_17 = or(_was_taken_T_16, s1_update.bits.cfi_is_jal) node was_taken_2 = and(_was_taken_T_13, _was_taken_T_17) node old_bim_value_2 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][2], s1_update_meta.bims[2]) connect s1_update_wmask[2], UInt<1>(0h1) node s1_update_wdata_2_old_bim_sat_taken = eq(old_bim_value_2, UInt<2>(0h3)) node s1_update_wdata_2_old_bim_sat_ntaken = eq(old_bim_value_2, UInt<1>(0h0)) node _s1_update_wdata_2_T = and(s1_update_wdata_2_old_bim_sat_taken, was_taken_2) node _s1_update_wdata_2_T_1 = eq(was_taken_2, UInt<1>(0h0)) node _s1_update_wdata_2_T_2 = and(s1_update_wdata_2_old_bim_sat_ntaken, _s1_update_wdata_2_T_1) node _s1_update_wdata_2_T_3 = add(old_bim_value_2, UInt<1>(0h1)) node _s1_update_wdata_2_T_4 = tail(_s1_update_wdata_2_T_3, 1) node _s1_update_wdata_2_T_5 = sub(old_bim_value_2, UInt<1>(0h1)) node _s1_update_wdata_2_T_6 = tail(_s1_update_wdata_2_T_5, 1) node _s1_update_wdata_2_T_7 = mux(was_taken_2, _s1_update_wdata_2_T_4, _s1_update_wdata_2_T_6) node _s1_update_wdata_2_T_8 = mux(_s1_update_wdata_2_T_2, UInt<1>(0h0), _s1_update_wdata_2_T_7) node _s1_update_wdata_2_T_9 = mux(_s1_update_wdata_2_T, UInt<2>(0h3), _s1_update_wdata_2_T_8) connect s1_update_wdata[2], _s1_update_wdata_2_T_9 connect s1_update_wmask[3], UInt<1>(0h0) invalidate s1_update_wdata[3] node _update_pc_T_3 = add(s1_update.bits.pc, UInt<3>(0h6)) node update_pc_3 = tail(_update_pc_T_3, 1) node _T_14 = bits(s1_update.bits.br_mask, 3, 3) node _T_15 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _T_16 = and(s1_update.bits.cfi_idx.valid, _T_15) node _T_17 = or(_T_14, _T_16) when _T_17 : node _was_taken_T_18 = eq(s1_update.bits.cfi_idx.bits, UInt<2>(0h3)) node _was_taken_T_19 = and(s1_update.bits.cfi_idx.valid, _was_taken_T_18) node _was_taken_T_20 = bits(s1_update.bits.br_mask, 3, 3) node _was_taken_T_21 = and(s1_update.bits.cfi_is_br, _was_taken_T_20) node _was_taken_T_22 = and(_was_taken_T_21, s1_update.bits.cfi_taken) node _was_taken_T_23 = or(_was_taken_T_22, s1_update.bits.cfi_is_jal) node was_taken_3 = and(_was_taken_T_19, _was_taken_T_23) node old_bim_value_3 = mux(wrbypass_hit, wrbypass[wrbypass_hit_idx][3], s1_update_meta.bims[3]) connect s1_update_wmask[3], UInt<1>(0h1) node s1_update_wdata_3_old_bim_sat_taken = eq(old_bim_value_3, UInt<2>(0h3)) node s1_update_wdata_3_old_bim_sat_ntaken = eq(old_bim_value_3, UInt<1>(0h0)) node _s1_update_wdata_3_T = and(s1_update_wdata_3_old_bim_sat_taken, was_taken_3) node _s1_update_wdata_3_T_1 = eq(was_taken_3, UInt<1>(0h0)) node _s1_update_wdata_3_T_2 = and(s1_update_wdata_3_old_bim_sat_ntaken, _s1_update_wdata_3_T_1) node _s1_update_wdata_3_T_3 = add(old_bim_value_3, UInt<1>(0h1)) node _s1_update_wdata_3_T_4 = tail(_s1_update_wdata_3_T_3, 1) node _s1_update_wdata_3_T_5 = sub(old_bim_value_3, UInt<1>(0h1)) node _s1_update_wdata_3_T_6 = tail(_s1_update_wdata_3_T_5, 1) node _s1_update_wdata_3_T_7 = mux(was_taken_3, _s1_update_wdata_3_T_4, _s1_update_wdata_3_T_6) node _s1_update_wdata_3_T_8 = mux(_s1_update_wdata_3_T_2, UInt<1>(0h0), _s1_update_wdata_3_T_7) node _s1_update_wdata_3_T_9 = mux(_s1_update_wdata_3_T, UInt<2>(0h3), _s1_update_wdata_3_T_8) connect s1_update_wdata[3], _s1_update_wdata_3_T_9 node _T_18 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_19 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_20 = or(_T_18, _T_19) node _T_21 = eq(_T_20, UInt<1>(0h0)) node _T_22 = and(s1_update.valid, _T_21) node _T_23 = or(doing_reset, _T_22) when _T_23 : node _T_24 = mux(doing_reset, reset_idx, s1_update_idx) wire _WIRE : UInt<2>[4] connect _WIRE[0], UInt<2>(0h2) connect _WIRE[1], UInt<2>(0h2) connect _WIRE[2], UInt<2>(0h2) connect _WIRE[3], UInt<2>(0h2) node _T_25 = mux(doing_reset, _WIRE, s1_update_wdata) node _T_26 = not(UInt<4>(0h0)) node lo_1 = cat(s1_update_wmask[1], s1_update_wmask[0]) node hi_1 = cat(s1_update_wmask[3], s1_update_wmask[2]) node _T_27 = cat(hi_1, lo_1) node _T_28 = mux(doing_reset, _T_26, _T_27) node _T_29 = bits(_T_28, 0, 0) node _T_30 = bits(_T_28, 1, 1) node _T_31 = bits(_T_28, 2, 2) node _T_32 = bits(_T_28, 3, 3) node _T_33 = or(_T_24, UInt<11>(0h0)) node _T_34 = bits(_T_33, 10, 0) write mport MPORT = data[_T_34], clock when _T_29 : connect MPORT[0], _T_25[0] when _T_30 : connect MPORT[1], _T_25[1] when _T_31 : connect MPORT[2], _T_25[2] when _T_32 : connect MPORT[3], _T_25[3] node _T_35 = or(s1_update_wmask[0], s1_update_wmask[1]) node _T_36 = or(_T_35, s1_update_wmask[2]) node _T_37 = or(_T_36, s1_update_wmask[3]) node _T_38 = and(_T_37, s1_update.valid) node _T_39 = or(s1_update.bits.is_mispredict_update, s1_update.bits.is_repair_update) node _T_40 = neq(s1_update.bits.btb_mispredicts, UInt<1>(0h0)) node _T_41 = or(_T_39, _T_40) node _T_42 = eq(_T_41, UInt<1>(0h0)) node _T_43 = and(_T_38, _T_42) when _T_43 : when wrbypass_hit : connect wrbypass[wrbypass_hit_idx], s1_update_wdata else : connect wrbypass[wrbypass_enq_idx], s1_update_wdata connect wrbypass_idxs[wrbypass_enq_idx], s1_update_idx node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1)) node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1) node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0) connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 connect io.resp.f2[0].taken, s2_resp[0] reg io_resp_f3_0_taken_REG : UInt<1>, clock connect io_resp_f3_0_taken_REG, io.resp.f2[0].taken connect io.resp.f3[0].taken, io_resp_f3_0_taken_REG connect io.resp.f2[1].taken, s2_resp[1] reg io_resp_f3_1_taken_REG : UInt<1>, clock connect io_resp_f3_1_taken_REG, io.resp.f2[1].taken connect io.resp.f3[1].taken, io_resp_f3_1_taken_REG connect io.resp.f2[2].taken, s2_resp[2] reg io_resp_f3_2_taken_REG : UInt<1>, clock connect io_resp_f3_2_taken_REG, io.resp.f2[2].taken connect io.resp.f3[2].taken, io_resp_f3_2_taken_REG connect io.resp.f2[3].taken, s2_resp[3] reg io_resp_f3_3_taken_REG : UInt<1>, clock connect io_resp_f3_3_taken_REG, io.resp.f2[3].taken connect io.resp.f3[3].taken, io_resp_f3_3_taken_REG node io_f3_meta_lo = cat(s2_meta.bims[1], s2_meta.bims[0]) node io_f3_meta_hi = cat(s2_meta.bims[3], s2_meta.bims[2]) node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo) reg io_f3_meta_REG : UInt, clock connect io_f3_meta_REG, _io_f3_meta_T connect io.f3_meta, io_f3_meta_REG
module BIMBranchPredictorBank_3( // @[bim.scala:26:7] input clock, // @[bim.scala:26:7] input reset, // @[bim.scala:26:7] input io_f0_valid, // @[predictor.scala:140:14] input [39:0] io_f0_pc, // @[predictor.scala:140:14] input [3:0] io_f0_mask, // @[predictor.scala:140:14] input [63:0] io_f1_ghist, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14] input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_0_taken, // @[predictor.scala:140:14] output io_resp_f1_0_is_br, // @[predictor.scala:140:14] output io_resp_f1_0_is_jal, // @[predictor.scala:140:14] output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_1_taken, // @[predictor.scala:140:14] output io_resp_f1_1_is_br, // @[predictor.scala:140:14] output io_resp_f1_1_is_jal, // @[predictor.scala:140:14] output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_2_taken, // @[predictor.scala:140:14] output io_resp_f1_2_is_br, // @[predictor.scala:140:14] output io_resp_f1_2_is_jal, // @[predictor.scala:140:14] output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f1_3_taken, // @[predictor.scala:140:14] output io_resp_f1_3_is_br, // @[predictor.scala:140:14] output io_resp_f1_3_is_jal, // @[predictor.scala:140:14] output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_0_taken, // @[predictor.scala:140:14] output io_resp_f2_0_is_br, // @[predictor.scala:140:14] output io_resp_f2_0_is_jal, // @[predictor.scala:140:14] output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_1_taken, // @[predictor.scala:140:14] output io_resp_f2_1_is_br, // @[predictor.scala:140:14] output io_resp_f2_1_is_jal, // @[predictor.scala:140:14] output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_2_taken, // @[predictor.scala:140:14] output io_resp_f2_2_is_br, // @[predictor.scala:140:14] output io_resp_f2_2_is_jal, // @[predictor.scala:140:14] output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f2_3_taken, // @[predictor.scala:140:14] output io_resp_f2_3_is_br, // @[predictor.scala:140:14] output io_resp_f2_3_is_jal, // @[predictor.scala:140:14] output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_0_taken, // @[predictor.scala:140:14] output io_resp_f3_0_is_br, // @[predictor.scala:140:14] output io_resp_f3_0_is_jal, // @[predictor.scala:140:14] output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_1_taken, // @[predictor.scala:140:14] output io_resp_f3_1_is_br, // @[predictor.scala:140:14] output io_resp_f3_1_is_jal, // @[predictor.scala:140:14] output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_2_taken, // @[predictor.scala:140:14] output io_resp_f3_2_is_br, // @[predictor.scala:140:14] output io_resp_f3_2_is_jal, // @[predictor.scala:140:14] output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14] output io_resp_f3_3_taken, // @[predictor.scala:140:14] output io_resp_f3_3_is_br, // @[predictor.scala:140:14] output io_resp_f3_3_is_jal, // @[predictor.scala:140:14] output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14] output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14] output [119:0] io_f3_meta, // @[predictor.scala:140:14] input io_f3_fire, // @[predictor.scala:140:14] input io_update_valid, // @[predictor.scala:140:14] input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14] input io_update_bits_is_repair_update, // @[predictor.scala:140:14] input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14] input [39:0] io_update_bits_pc, // @[predictor.scala:140:14] input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14] input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14] input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14] input io_update_bits_cfi_taken, // @[predictor.scala:140:14] input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14] input io_update_bits_cfi_is_br, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14] input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14] input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14] input io_update_bits_lhist, // @[predictor.scala:140:14] input [39:0] io_update_bits_target, // @[predictor.scala:140:14] input [119:0] io_update_bits_meta // @[predictor.scala:140:14] ); wire [1:0] data_MPORT_data_3; // @[bim.scala:112:10] wire [1:0] data_MPORT_data_2; // @[bim.scala:112:10] wire [1:0] data_MPORT_data_1; // @[bim.scala:112:10] wire [1:0] data_MPORT_data_0; // @[bim.scala:112:10] wire [7:0] _data_R0_data; // @[bim.scala:50:26] wire io_f0_valid_0 = io_f0_valid; // @[bim.scala:26:7] wire [39:0] io_f0_pc_0 = io_f0_pc; // @[bim.scala:26:7] wire [3:0] io_f0_mask_0 = io_f0_mask; // @[bim.scala:26:7] wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[bim.scala:26:7] wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[bim.scala:26:7] wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[bim.scala:26:7] wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[bim.scala:26:7] wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[bim.scala:26:7] wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[bim.scala:26:7] wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[bim.scala:26:7] wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[bim.scala:26:7] wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[bim.scala:26:7] wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[bim.scala:26:7] wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[bim.scala:26:7] wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[bim.scala:26:7] wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[bim.scala:26:7] wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[bim.scala:26:7] wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[bim.scala:26:7] wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[bim.scala:26:7] wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[bim.scala:26:7] wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[bim.scala:26:7] wire io_f3_fire_0 = io_f3_fire; // @[bim.scala:26:7] wire io_update_valid_0 = io_update_valid; // @[bim.scala:26:7] wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[bim.scala:26:7] wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[bim.scala:26:7] wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[bim.scala:26:7] wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[bim.scala:26:7] wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[bim.scala:26:7] wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[bim.scala:26:7] wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[bim.scala:26:7] wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[bim.scala:26:7] wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[bim.scala:26:7] wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[bim.scala:26:7] wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[bim.scala:26:7] wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[bim.scala:26:7] wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[bim.scala:26:7] wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[bim.scala:26:7] wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[bim.scala:26:7] wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[bim.scala:26:7] wire io_f1_lhist = 1'h0; // @[bim.scala:26:7] wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[bim.scala:26:7] wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[bim.scala:26:7] wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[bim.scala:26:7] wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[bim.scala:26:7] wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[bim.scala:26:7] wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[bim.scala:26:7] wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[bim.scala:26:7] wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[bim.scala:26:7] wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[bim.scala:26:7] wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[bim.scala:26:7] wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[bim.scala:26:7] wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[bim.scala:26:7] wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[bim.scala:26:7] wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[bim.scala:26:7] wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[bim.scala:26:7] wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[bim.scala:26:7] wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[bim.scala:26:7] wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[bim.scala:26:7] wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[bim.scala:26:7] wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[bim.scala:26:7] wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[bim.scala:26:7] wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[bim.scala:26:7] wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[bim.scala:26:7] wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[bim.scala:26:7] wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[bim.scala:26:7] wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[bim.scala:26:7] wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[bim.scala:26:7] wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[bim.scala:26:7] wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[bim.scala:26:7] wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[bim.scala:26:7] wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[bim.scala:26:7] wire s2_resp_0; // @[bim.scala:56:29] wire s2_resp_1; // @[bim.scala:56:29] wire s2_resp_2; // @[bim.scala:56:29] wire s2_resp_3; // @[bim.scala:56:29] wire io_resp_f2_0_taken_0; // @[bim.scala:26:7] wire io_resp_f2_1_taken_0; // @[bim.scala:26:7] wire io_resp_f2_2_taken_0; // @[bim.scala:26:7] wire io_resp_f2_3_taken_0; // @[bim.scala:26:7] wire io_resp_f3_0_taken_0; // @[bim.scala:26:7] wire io_resp_f3_1_taken_0; // @[bim.scala:26:7] wire io_resp_f3_2_taken_0; // @[bim.scala:26:7] wire io_resp_f3_3_taken_0; // @[bim.scala:26:7] wire [119:0] io_f3_meta_0; // @[bim.scala:26:7] wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35] wire [35:0] _s2_req_rdata_WIRE = s0_idx; // @[frontend.scala:162:35] reg [35:0] s1_idx; // @[predictor.scala:163:29] reg [35:0] s2_idx; // @[predictor.scala:164:29] reg [35:0] s3_idx; // @[predictor.scala:165:29] reg s1_valid; // @[predictor.scala:168:25] reg s2_valid; // @[predictor.scala:169:25] reg s3_valid; // @[predictor.scala:170:25] reg [3:0] s1_mask; // @[predictor.scala:173:24] reg [3:0] s2_mask; // @[predictor.scala:174:24] reg [3:0] s3_mask; // @[predictor.scala:175:24] reg [39:0] s1_pc; // @[predictor.scala:178:22] wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35] reg s1_update_valid; // @[predictor.scala:184:30] reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30] reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30] reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30] reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30] reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30] reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30] reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30] reg s1_update_bits_lhist; // @[predictor.scala:184:30] reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30] reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30] reg [35:0] s1_update_idx; // @[predictor.scala:185:30] reg s1_update_valid_0; // @[predictor.scala:186:32] wire [1:0] s2_meta_bims_0; // @[bim.scala:41:31] wire [1:0] s2_meta_bims_1; // @[bim.scala:41:31] wire [1:0] s2_meta_bims_2; // @[bim.scala:41:31] wire [1:0] s2_meta_bims_3; // @[bim.scala:41:31] wire [3:0] _GEN = {s2_meta_bims_1, s2_meta_bims_0}; // @[bim.scala:41:31, :42:35] wire [3:0] lo; // @[bim.scala:42:35] assign lo = _GEN; // @[bim.scala:42:35] wire [3:0] io_f3_meta_lo; // @[bim.scala:130:33] assign io_f3_meta_lo = _GEN; // @[bim.scala:42:35, :130:33] wire [3:0] _GEN_0 = {s2_meta_bims_3, s2_meta_bims_2}; // @[bim.scala:41:31, :42:35] wire [3:0] hi; // @[bim.scala:42:35] assign hi = _GEN_0; // @[bim.scala:42:35] wire [3:0] io_f3_meta_hi; // @[bim.scala:130:33] assign io_f3_meta_hi = _GEN_0; // @[bim.scala:42:35, :130:33] reg doing_reset; // @[bim.scala:44:28] reg [10:0] reset_idx; // @[bim.scala:45:26] wire [11:0] _reset_idx_T = {1'h0, reset_idx} + {11'h0, doing_reset}; // @[bim.scala:44:28, :45:26, :46:26] wire [10:0] _reset_idx_T_1 = _reset_idx_T[10:0]; // @[bim.scala:46:26] wire [10:0] _s2_req_rdata_T = _s2_req_rdata_WIRE[10:0]; // @[bim.scala:54:42] reg [1:0] s2_req_rdata_0; // @[bim.scala:54:32] assign s2_meta_bims_0 = s2_req_rdata_0; // @[bim.scala:41:31, :54:32] reg [1:0] s2_req_rdata_1; // @[bim.scala:54:32] assign s2_meta_bims_1 = s2_req_rdata_1; // @[bim.scala:41:31, :54:32] reg [1:0] s2_req_rdata_2; // @[bim.scala:54:32] assign s2_meta_bims_2 = s2_req_rdata_2; // @[bim.scala:41:31, :54:32] reg [1:0] s2_req_rdata_3; // @[bim.scala:54:32] assign s2_meta_bims_3 = s2_req_rdata_3; // @[bim.scala:41:31, :54:32] wire _s2_resp_0_T_3; // @[bim.scala:60:57] assign io_resp_f2_0_taken_0 = s2_resp_0; // @[bim.scala:26:7, :56:29] wire _s2_resp_1_T_3; // @[bim.scala:60:57] assign io_resp_f2_1_taken_0 = s2_resp_1; // @[bim.scala:26:7, :56:29] wire _s2_resp_2_T_3; // @[bim.scala:60:57] assign io_resp_f2_2_taken_0 = s2_resp_2; // @[bim.scala:26:7, :56:29] wire _s2_resp_3_T_3; // @[bim.scala:60:57] assign io_resp_f2_3_taken_0 = s2_resp_3; // @[bim.scala:26:7, :56:29] wire _s2_resp_0_T = s2_req_rdata_0[1]; // @[bim.scala:54:32, :60:53] wire _s2_resp_0_T_1 = s2_valid & _s2_resp_0_T; // @[predictor.scala:169:25] wire _s2_resp_0_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60] assign _s2_resp_0_T_3 = _s2_resp_0_T_1 & _s2_resp_0_T_2; // @[bim.scala:60:{35,57,60}] assign s2_resp_0 = _s2_resp_0_T_3; // @[bim.scala:56:29, :60:57] wire _s2_resp_1_T = s2_req_rdata_1[1]; // @[bim.scala:54:32, :60:53] wire _s2_resp_1_T_1 = s2_valid & _s2_resp_1_T; // @[predictor.scala:169:25] wire _s2_resp_1_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60] assign _s2_resp_1_T_3 = _s2_resp_1_T_1 & _s2_resp_1_T_2; // @[bim.scala:60:{35,57,60}] assign s2_resp_1 = _s2_resp_1_T_3; // @[bim.scala:56:29, :60:57] wire _s2_resp_2_T = s2_req_rdata_2[1]; // @[bim.scala:54:32, :60:53] wire _s2_resp_2_T_1 = s2_valid & _s2_resp_2_T; // @[predictor.scala:169:25] wire _s2_resp_2_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60] assign _s2_resp_2_T_3 = _s2_resp_2_T_1 & _s2_resp_2_T_2; // @[bim.scala:60:{35,57,60}] assign s2_resp_2 = _s2_resp_2_T_3; // @[bim.scala:56:29, :60:57] wire _s2_resp_3_T = s2_req_rdata_3[1]; // @[bim.scala:54:32, :60:53] wire _s2_resp_3_T_1 = s2_valid & _s2_resp_3_T; // @[predictor.scala:169:25] wire _s2_resp_3_T_2 = ~doing_reset; // @[bim.scala:44:28, :60:60] assign _s2_resp_3_T_3 = _s2_resp_3_T_1 & _s2_resp_3_T_2; // @[bim.scala:60:{35,57,60}] assign s2_resp_3 = _s2_resp_3_T_3; // @[bim.scala:56:29, :60:57] wire [1:0] _s1_update_wdata_0_T_9; // @[bim.scala:37:8] wire [1:0] _s1_update_wdata_1_T_9; // @[bim.scala:37:8] wire [1:0] _s1_update_wdata_2_T_9; // @[bim.scala:37:8] wire [1:0] _s1_update_wdata_3_T_9; // @[bim.scala:37:8] wire [1:0] s1_update_wdata_0; // @[bim.scala:65:31] wire [1:0] s1_update_wdata_1; // @[bim.scala:65:31] wire [1:0] s1_update_wdata_2; // @[bim.scala:65:31] wire [1:0] s1_update_wdata_3; // @[bim.scala:65:31] wire s1_update_wmask_0; // @[bim.scala:66:31] wire s1_update_wmask_1; // @[bim.scala:66:31] wire s1_update_wmask_2; // @[bim.scala:66:31] wire s1_update_wmask_3; // @[bim.scala:66:31] wire [1:0] _s1_update_meta_T; // @[bim.scala:67:55] wire [1:0] _s1_update_meta_T_1; // @[bim.scala:67:55] wire [1:0] _s1_update_meta_T_2; // @[bim.scala:67:55] wire [1:0] _s1_update_meta_T_3; // @[bim.scala:67:55] wire [1:0] s1_update_meta_bims_0; // @[bim.scala:67:55] wire [1:0] s1_update_meta_bims_1; // @[bim.scala:67:55] wire [1:0] s1_update_meta_bims_2; // @[bim.scala:67:55] wire [1:0] s1_update_meta_bims_3; // @[bim.scala:67:55] wire [7:0] _s1_update_meta_WIRE = s1_update_bits_meta[7:0]; // @[predictor.scala:184:30] assign _s1_update_meta_T = _s1_update_meta_WIRE[1:0]; // @[bim.scala:67:55] assign s1_update_meta_bims_0 = _s1_update_meta_T; // @[bim.scala:67:55] assign _s1_update_meta_T_1 = _s1_update_meta_WIRE[3:2]; // @[bim.scala:67:55] assign s1_update_meta_bims_1 = _s1_update_meta_T_1; // @[bim.scala:67:55] assign _s1_update_meta_T_2 = _s1_update_meta_WIRE[5:4]; // @[bim.scala:67:55] assign s1_update_meta_bims_2 = _s1_update_meta_T_2; // @[bim.scala:67:55] assign _s1_update_meta_T_3 = _s1_update_meta_WIRE[7:6]; // @[bim.scala:67:55] assign s1_update_meta_bims_3 = _s1_update_meta_T_3; // @[bim.scala:67:55] reg [10:0] wrbypass_idxs_0; // @[bim.scala:70:26] reg [10:0] wrbypass_idxs_1; // @[bim.scala:70:26] reg [1:0] wrbypass_0_0; // @[bim.scala:71:26] reg [1:0] wrbypass_0_1; // @[bim.scala:71:26] reg [1:0] wrbypass_0_2; // @[bim.scala:71:26] reg [1:0] wrbypass_0_3; // @[bim.scala:71:26] reg [1:0] wrbypass_1_0; // @[bim.scala:71:26] reg [1:0] wrbypass_1_1; // @[bim.scala:71:26] reg [1:0] wrbypass_1_2; // @[bim.scala:71:26] reg [1:0] wrbypass_1_3; // @[bim.scala:71:26] reg wrbypass_enq_idx; // @[bim.scala:72:33] wire _wrbypass_hits_T = ~doing_reset; // @[bim.scala:44:28, :60:60, :75:5] wire [10:0] _wrbypass_hits_T_1 = s1_update_idx[10:0]; // @[predictor.scala:185:30] wire [10:0] _wrbypass_hits_T_5 = s1_update_idx[10:0]; // @[predictor.scala:185:30] wire _wrbypass_hits_T_2 = wrbypass_idxs_0 == _wrbypass_hits_T_1; // @[bim.scala:70:26, :76:{22,41}] wire _wrbypass_hits_T_3 = _wrbypass_hits_T & _wrbypass_hits_T_2; // @[bim.scala:75:{5,18}, :76:22] wire wrbypass_hits_0 = _wrbypass_hits_T_3; // @[bim.scala:74:30, :75:18] wire _wrbypass_hits_T_4 = ~doing_reset; // @[bim.scala:44:28, :60:60, :75:5] wire _wrbypass_hits_T_6 = wrbypass_idxs_1 == _wrbypass_hits_T_5; // @[bim.scala:70:26, :76:{22,41}] wire _wrbypass_hits_T_7 = _wrbypass_hits_T_4 & _wrbypass_hits_T_6; // @[bim.scala:75:{5,18}, :76:22] wire wrbypass_hits_1 = _wrbypass_hits_T_7; // @[bim.scala:74:30, :75:18] wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[bim.scala:74:30, :78:44] wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70] wire [40:0] _update_pc_T = {1'h0, s1_update_bits_pc}; // @[predictor.scala:184:30] wire [39:0] update_pc = _update_pc_T[39:0]; // @[bim.scala:87:39] wire _was_taken_T_2 = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30] wire _was_taken_T = s1_update_bits_cfi_idx_bits == 2'h0; // @[predictor.scala:184:30] assign s1_update_wmask_0 = _was_taken_T_2 | s1_update_bits_cfi_idx_valid & _was_taken_T; // @[predictor.scala:184:30] wire _was_taken_T_1 = s1_update_bits_cfi_idx_valid & _was_taken_T; // @[predictor.scala:184:30] wire _was_taken_T_3 = s1_update_bits_cfi_is_br & _was_taken_T_2; // @[predictor.scala:184:30] wire _was_taken_T_4 = _was_taken_T_3 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _was_taken_T_5 = _was_taken_T_4 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] wire was_taken = _was_taken_T_1 & _was_taken_T_5; // @[bim.scala:92:38, :93:47, :95:95] wire [1:0] old_bim_value = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0) : s1_update_meta_bims_0; // @[Mux.scala:50:70] wire s1_update_wdata_0_old_bim_sat_taken = &old_bim_value; // @[bim.scala:35:32, :99:30] wire s1_update_wdata_0_old_bim_sat_ntaken = old_bim_value == 2'h0; // @[bim.scala:36:32, :99:30] wire _s1_update_wdata_0_T = s1_update_wdata_0_old_bim_sat_taken & was_taken; // @[bim.scala:35:32, :37:28, :93:47] wire _s1_update_wdata_0_T_1 = ~was_taken; // @[bim.scala:38:33, :93:47] wire _s1_update_wdata_0_T_2 = s1_update_wdata_0_old_bim_sat_ntaken & _s1_update_wdata_0_T_1; // @[bim.scala:36:32, :38:{30,33}] wire [2:0] _GEN_1 = {1'h0, old_bim_value}; // @[bim.scala:39:20, :99:30] wire [2:0] _s1_update_wdata_0_T_3 = _GEN_1 + 3'h1; // @[bim.scala:39:20] wire [1:0] _s1_update_wdata_0_T_4 = _s1_update_wdata_0_T_3[1:0]; // @[bim.scala:39:20] wire [2:0] _s1_update_wdata_0_T_5 = _GEN_1 - 3'h1; // @[bim.scala:39:{20,29}] wire [1:0] _s1_update_wdata_0_T_6 = _s1_update_wdata_0_T_5[1:0]; // @[bim.scala:39:29] wire [1:0] _s1_update_wdata_0_T_7 = was_taken ? _s1_update_wdata_0_T_4 : _s1_update_wdata_0_T_6; // @[bim.scala:39:{10,20,29}, :93:47] wire [1:0] _s1_update_wdata_0_T_8 = _s1_update_wdata_0_T_2 ? 2'h0 : _s1_update_wdata_0_T_7; // @[bim.scala:38:{10,30}, :39:10] assign _s1_update_wdata_0_T_9 = _s1_update_wdata_0_T ? 2'h3 : _s1_update_wdata_0_T_8; // @[bim.scala:37:{8,28}, :38:10] assign s1_update_wdata_0 = _s1_update_wdata_0_T_9; // @[bim.scala:37:8, :65:31] wire [40:0] _update_pc_T_1 = _update_pc_T + 41'h2; // @[bim.scala:87:39] wire [39:0] update_pc_1 = _update_pc_T_1[39:0]; // @[bim.scala:87:39] wire _was_taken_T_8 = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30] wire _was_taken_T_6 = s1_update_bits_cfi_idx_bits == 2'h1; // @[predictor.scala:184:30] assign s1_update_wmask_1 = _was_taken_T_8 | s1_update_bits_cfi_idx_valid & _was_taken_T_6; // @[predictor.scala:184:30] wire _was_taken_T_7 = s1_update_bits_cfi_idx_valid & _was_taken_T_6; // @[predictor.scala:184:30] wire _was_taken_T_9 = s1_update_bits_cfi_is_br & _was_taken_T_8; // @[predictor.scala:184:30] wire _was_taken_T_10 = _was_taken_T_9 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _was_taken_T_11 = _was_taken_T_10 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] wire was_taken_1 = _was_taken_T_7 & _was_taken_T_11; // @[bim.scala:92:38, :93:47, :95:95] wire [1:0] old_bim_value_1 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1) : s1_update_meta_bims_1; // @[Mux.scala:50:70] wire s1_update_wdata_1_old_bim_sat_taken = &old_bim_value_1; // @[bim.scala:35:32, :99:30] wire s1_update_wdata_1_old_bim_sat_ntaken = old_bim_value_1 == 2'h0; // @[bim.scala:36:32, :99:30] wire _s1_update_wdata_1_T = s1_update_wdata_1_old_bim_sat_taken & was_taken_1; // @[bim.scala:35:32, :37:28, :93:47] wire _s1_update_wdata_1_T_1 = ~was_taken_1; // @[bim.scala:38:33, :93:47] wire _s1_update_wdata_1_T_2 = s1_update_wdata_1_old_bim_sat_ntaken & _s1_update_wdata_1_T_1; // @[bim.scala:36:32, :38:{30,33}] wire [2:0] _GEN_2 = {1'h0, old_bim_value_1}; // @[bim.scala:39:20, :99:30] wire [2:0] _s1_update_wdata_1_T_3 = _GEN_2 + 3'h1; // @[bim.scala:39:20] wire [1:0] _s1_update_wdata_1_T_4 = _s1_update_wdata_1_T_3[1:0]; // @[bim.scala:39:20] wire [2:0] _s1_update_wdata_1_T_5 = _GEN_2 - 3'h1; // @[bim.scala:39:{20,29}] wire [1:0] _s1_update_wdata_1_T_6 = _s1_update_wdata_1_T_5[1:0]; // @[bim.scala:39:29] wire [1:0] _s1_update_wdata_1_T_7 = was_taken_1 ? _s1_update_wdata_1_T_4 : _s1_update_wdata_1_T_6; // @[bim.scala:39:{10,20,29}, :93:47] wire [1:0] _s1_update_wdata_1_T_8 = _s1_update_wdata_1_T_2 ? 2'h0 : _s1_update_wdata_1_T_7; // @[bim.scala:38:{10,30}, :39:10] assign _s1_update_wdata_1_T_9 = _s1_update_wdata_1_T ? 2'h3 : _s1_update_wdata_1_T_8; // @[bim.scala:37:{8,28}, :38:10] assign s1_update_wdata_1 = _s1_update_wdata_1_T_9; // @[bim.scala:37:8, :65:31] wire [40:0] _update_pc_T_2 = _update_pc_T + 41'h4; // @[bim.scala:87:39] wire [39:0] update_pc_2 = _update_pc_T_2[39:0]; // @[bim.scala:87:39] wire _was_taken_T_14 = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30] wire _was_taken_T_12 = s1_update_bits_cfi_idx_bits == 2'h2; // @[predictor.scala:184:30] assign s1_update_wmask_2 = _was_taken_T_14 | s1_update_bits_cfi_idx_valid & _was_taken_T_12; // @[predictor.scala:184:30] wire _was_taken_T_13 = s1_update_bits_cfi_idx_valid & _was_taken_T_12; // @[predictor.scala:184:30] wire _was_taken_T_15 = s1_update_bits_cfi_is_br & _was_taken_T_14; // @[predictor.scala:184:30] wire _was_taken_T_16 = _was_taken_T_15 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _was_taken_T_17 = _was_taken_T_16 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] wire was_taken_2 = _was_taken_T_13 & _was_taken_T_17; // @[bim.scala:92:38, :93:47, :95:95] wire [1:0] old_bim_value_2 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2) : s1_update_meta_bims_2; // @[Mux.scala:50:70] wire s1_update_wdata_2_old_bim_sat_taken = &old_bim_value_2; // @[bim.scala:35:32, :99:30] wire s1_update_wdata_2_old_bim_sat_ntaken = old_bim_value_2 == 2'h0; // @[bim.scala:36:32, :99:30] wire _s1_update_wdata_2_T = s1_update_wdata_2_old_bim_sat_taken & was_taken_2; // @[bim.scala:35:32, :37:28, :93:47] wire _s1_update_wdata_2_T_1 = ~was_taken_2; // @[bim.scala:38:33, :93:47] wire _s1_update_wdata_2_T_2 = s1_update_wdata_2_old_bim_sat_ntaken & _s1_update_wdata_2_T_1; // @[bim.scala:36:32, :38:{30,33}] wire [2:0] _GEN_3 = {1'h0, old_bim_value_2}; // @[bim.scala:39:20, :99:30] wire [2:0] _s1_update_wdata_2_T_3 = _GEN_3 + 3'h1; // @[bim.scala:39:20] wire [1:0] _s1_update_wdata_2_T_4 = _s1_update_wdata_2_T_3[1:0]; // @[bim.scala:39:20] wire [2:0] _s1_update_wdata_2_T_5 = _GEN_3 - 3'h1; // @[bim.scala:39:{20,29}] wire [1:0] _s1_update_wdata_2_T_6 = _s1_update_wdata_2_T_5[1:0]; // @[bim.scala:39:29] wire [1:0] _s1_update_wdata_2_T_7 = was_taken_2 ? _s1_update_wdata_2_T_4 : _s1_update_wdata_2_T_6; // @[bim.scala:39:{10,20,29}, :93:47] wire [1:0] _s1_update_wdata_2_T_8 = _s1_update_wdata_2_T_2 ? 2'h0 : _s1_update_wdata_2_T_7; // @[bim.scala:38:{10,30}, :39:10] assign _s1_update_wdata_2_T_9 = _s1_update_wdata_2_T ? 2'h3 : _s1_update_wdata_2_T_8; // @[bim.scala:37:{8,28}, :38:10] assign s1_update_wdata_2 = _s1_update_wdata_2_T_9; // @[bim.scala:37:8, :65:31] wire [40:0] _update_pc_T_3 = _update_pc_T + 41'h6; // @[bim.scala:87:39] wire [39:0] update_pc_3 = _update_pc_T_3[39:0]; // @[bim.scala:87:39] wire _was_taken_T_20 = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30] assign s1_update_wmask_3 = _was_taken_T_20 | s1_update_bits_cfi_idx_valid & (&s1_update_bits_cfi_idx_bits); // @[predictor.scala:184:30] wire _was_taken_T_18 = &s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30] wire _was_taken_T_19 = s1_update_bits_cfi_idx_valid & _was_taken_T_18; // @[predictor.scala:184:30] wire _was_taken_T_21 = s1_update_bits_cfi_is_br & _was_taken_T_20; // @[predictor.scala:184:30] wire _was_taken_T_22 = _was_taken_T_21 & s1_update_bits_cfi_taken; // @[predictor.scala:184:30] wire _was_taken_T_23 = _was_taken_T_22 | s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30] wire was_taken_3 = _was_taken_T_19 & _was_taken_T_23; // @[bim.scala:92:38, :93:47, :95:95] wire [1:0] old_bim_value_3 = wrbypass_hit ? (wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3) : s1_update_meta_bims_3; // @[Mux.scala:50:70] wire s1_update_wdata_3_old_bim_sat_taken = &old_bim_value_3; // @[bim.scala:35:32, :99:30] wire s1_update_wdata_3_old_bim_sat_ntaken = old_bim_value_3 == 2'h0; // @[bim.scala:36:32, :99:30] wire _s1_update_wdata_3_T = s1_update_wdata_3_old_bim_sat_taken & was_taken_3; // @[bim.scala:35:32, :37:28, :93:47] wire _s1_update_wdata_3_T_1 = ~was_taken_3; // @[bim.scala:38:33, :93:47] wire _s1_update_wdata_3_T_2 = s1_update_wdata_3_old_bim_sat_ntaken & _s1_update_wdata_3_T_1; // @[bim.scala:36:32, :38:{30,33}] wire [2:0] _GEN_4 = {1'h0, old_bim_value_3}; // @[bim.scala:39:20, :99:30] wire [2:0] _s1_update_wdata_3_T_3 = _GEN_4 + 3'h1; // @[bim.scala:39:20] wire [1:0] _s1_update_wdata_3_T_4 = _s1_update_wdata_3_T_3[1:0]; // @[bim.scala:39:20] wire [2:0] _s1_update_wdata_3_T_5 = _GEN_4 - 3'h1; // @[bim.scala:39:{20,29}] wire [1:0] _s1_update_wdata_3_T_6 = _s1_update_wdata_3_T_5[1:0]; // @[bim.scala:39:29] wire [1:0] _s1_update_wdata_3_T_7 = was_taken_3 ? _s1_update_wdata_3_T_4 : _s1_update_wdata_3_T_6; // @[bim.scala:39:{10,20,29}, :93:47] wire [1:0] _s1_update_wdata_3_T_8 = _s1_update_wdata_3_T_2 ? 2'h0 : _s1_update_wdata_3_T_7; // @[bim.scala:38:{10,30}, :39:10] assign _s1_update_wdata_3_T_9 = _s1_update_wdata_3_T ? 2'h3 : _s1_update_wdata_3_T_8; // @[bim.scala:37:{8,28}, :38:10] assign s1_update_wdata_3 = _s1_update_wdata_3_T_9; // @[bim.scala:37:8, :65:31] wire [4:0] _GEN_5 = {s1_update_bits_is_mispredict_update | s1_update_bits_is_repair_update, s1_update_bits_btb_mispredicts}; // @[predictor.scala:94:50, :96:{49,69}, :184:30] assign data_MPORT_data_0 = doing_reset ? 2'h2 : s1_update_wdata_0; // @[bim.scala:44:28, :65:31, :112:10] assign data_MPORT_data_1 = doing_reset ? 2'h2 : s1_update_wdata_1; // @[bim.scala:44:28, :65:31, :112:10] assign data_MPORT_data_2 = doing_reset ? 2'h2 : s1_update_wdata_2; // @[bim.scala:44:28, :65:31, :112:10] assign data_MPORT_data_3 = doing_reset ? 2'h2 : s1_update_wdata_3; // @[bim.scala:44:28, :65:31, :112:10] wire [1:0] lo_1 = {s1_update_wmask_1, s1_update_wmask_0}; // @[bim.scala:66:31, :113:63] wire [1:0] hi_1 = {s1_update_wmask_3, s1_update_wmask_2}; // @[bim.scala:66:31, :113:63] wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14] wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}] reg io_resp_f3_0_taken_REG; // @[bim.scala:128:35] assign io_resp_f3_0_taken_0 = io_resp_f3_0_taken_REG; // @[bim.scala:26:7, :128:35] reg io_resp_f3_1_taken_REG; // @[bim.scala:128:35] assign io_resp_f3_1_taken_0 = io_resp_f3_1_taken_REG; // @[bim.scala:26:7, :128:35] reg io_resp_f3_2_taken_REG; // @[bim.scala:128:35] assign io_resp_f3_2_taken_0 = io_resp_f3_2_taken_REG; // @[bim.scala:26:7, :128:35] reg io_resp_f3_3_taken_REG; // @[bim.scala:128:35] assign io_resp_f3_3_taken_0 = io_resp_f3_3_taken_REG; // @[bim.scala:26:7, :128:35] wire [7:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[bim.scala:130:33] reg [7:0] io_f3_meta_REG; // @[bim.scala:130:24] assign io_f3_meta_0 = {112'h0, io_f3_meta_REG}; // @[bim.scala:26:7, :130:{14,24}] wire _T_43 = (s1_update_wmask_0 | s1_update_wmask_1 | s1_update_wmask_2 | s1_update_wmask_3) & s1_update_valid & _GEN_5 == 5'h0; // @[predictor.scala:94:50, :96:69, :184:30] wire _GEN_6 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70] always @(posedge clock) begin // @[bim.scala:26:7] s1_idx <= s0_idx; // @[frontend.scala:162:35] s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29] s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29] s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25] s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25] s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25] s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24] s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24] s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24] s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22] s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30] s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30] s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30] s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30] s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30] s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30] s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30] s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30] s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30] s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30] s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30] s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30] s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30] s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30] s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35] s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32] s2_req_rdata_0 <= _data_R0_data[1:0]; // @[bim.scala:50:26, :54:32] s2_req_rdata_1 <= _data_R0_data[3:2]; // @[bim.scala:50:26, :54:32] s2_req_rdata_2 <= _data_R0_data[5:4]; // @[bim.scala:50:26, :54:32] s2_req_rdata_3 <= _data_R0_data[7:6]; // @[bim.scala:50:26, :54:32] if (~_T_43 | wrbypass_hit | wrbypass_enq_idx) begin // @[bim.scala:70:26, :71:26, :72:33, :78:44, :116:{38,57,93}, :117:25, :121:39] end else // @[bim.scala:70:26, :116:93, :117:25, :121:39] wrbypass_idxs_0 <= s1_update_idx[10:0]; // @[predictor.scala:185:30] if (~_T_43 | wrbypass_hit | ~wrbypass_enq_idx) begin // @[bim.scala:70:26, :71:26, :72:33, :78:44, :116:{38,57,93}, :117:25, :121:39] end else // @[bim.scala:70:26, :116:93, :117:25, :121:39] wrbypass_idxs_1 <= s1_update_idx[10:0]; // @[predictor.scala:185:30] if (~_T_43 | _GEN_6) begin // @[bim.scala:71:26, :116:{38,57,93}, :117:25, :118:34, :120:39] end else begin // @[bim.scala:71:26, :116:93, :117:25] wrbypass_0_0 <= s1_update_wdata_0; // @[bim.scala:65:31, :71:26] wrbypass_0_1 <= s1_update_wdata_1; // @[bim.scala:65:31, :71:26] wrbypass_0_2 <= s1_update_wdata_2; // @[bim.scala:65:31, :71:26] wrbypass_0_3 <= s1_update_wdata_3; // @[bim.scala:65:31, :71:26] end if (_T_43 & _GEN_6) begin // @[bim.scala:71:26, :116:{38,57,93}, :117:25, :118:34, :120:39] wrbypass_1_0 <= s1_update_wdata_0; // @[bim.scala:65:31, :71:26] wrbypass_1_1 <= s1_update_wdata_1; // @[bim.scala:65:31, :71:26] wrbypass_1_2 <= s1_update_wdata_2; // @[bim.scala:65:31, :71:26] wrbypass_1_3 <= s1_update_wdata_3; // @[bim.scala:65:31, :71:26] end io_resp_f3_0_taken_REG <= io_resp_f2_0_taken_0; // @[bim.scala:26:7, :128:35] io_resp_f3_1_taken_REG <= io_resp_f2_1_taken_0; // @[bim.scala:26:7, :128:35] io_resp_f3_2_taken_REG <= io_resp_f2_2_taken_0; // @[bim.scala:26:7, :128:35] io_resp_f3_3_taken_REG <= io_resp_f2_3_taken_0; // @[bim.scala:26:7, :128:35] io_f3_meta_REG <= _io_f3_meta_T; // @[bim.scala:130:{24,33}] if (reset) begin // @[bim.scala:26:7] doing_reset <= 1'h1; // @[bim.scala:44:28] reset_idx <= 11'h0; // @[bim.scala:45:26] wrbypass_enq_idx <= 1'h0; // @[bim.scala:72:33] end else begin // @[bim.scala:26:7] doing_reset <= reset_idx != 11'h7FF & doing_reset; // @[bim.scala:44:28, :45:26, :47:{19,36,50}] reset_idx <= _reset_idx_T_1; // @[bim.scala:45:26, :46:26] if (~_T_43 | wrbypass_hit) begin // @[bim.scala:71:26, :72:33, :78:44, :116:{38,57,93}, :117:25] end else // @[bim.scala:72:33, :116:93, :117:25] wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20] end always @(posedge) data_2 data ( // @[bim.scala:50:26] .R0_addr (_s2_req_rdata_T), // @[bim.scala:54:42] .R0_en (io_f0_valid_0), // @[bim.scala:26:7] .R0_clk (clock), .R0_data (_data_R0_data), .W0_addr (doing_reset ? reset_idx : s1_update_idx[10:0]), // @[predictor.scala:185:30] .W0_en (doing_reset | s1_update_valid & _GEN_5 == 5'h0), // @[predictor.scala:94:50, :96:69, :184:30] .W0_clk (clock), .W0_data ({data_MPORT_data_3, data_MPORT_data_2, data_MPORT_data_1, data_MPORT_data_0}), // @[bim.scala:50:26, :112:10] .W0_mask (doing_reset ? 4'hF : {hi_1, lo_1}) // @[bim.scala:44:28, :113:{10,63}] ); // @[bim.scala:50:26] assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[bim.scala:26:7] assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[bim.scala:26:7] assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[bim.scala:26:7] assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[bim.scala:26:7] assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[bim.scala:26:7] assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[bim.scala:26:7] assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[bim.scala:26:7] assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[bim.scala:26:7] assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[bim.scala:26:7] assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[bim.scala:26:7] assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[bim.scala:26:7] assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[bim.scala:26:7] assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[bim.scala:26:7] assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[bim.scala:26:7] assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[bim.scala:26:7] assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[bim.scala:26:7] assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[bim.scala:26:7] assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[bim.scala:26:7] assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[bim.scala:26:7] assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[bim.scala:26:7] assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[bim.scala:26:7] assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[bim.scala:26:7] assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[bim.scala:26:7] assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[bim.scala:26:7] assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[bim.scala:26:7] assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[bim.scala:26:7] assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[bim.scala:26:7] assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[bim.scala:26:7] assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[bim.scala:26:7] assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[bim.scala:26:7] assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[bim.scala:26:7] assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[bim.scala:26:7] assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[bim.scala:26:7] assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[bim.scala:26:7] assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[bim.scala:26:7] assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[bim.scala:26:7] assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[bim.scala:26:7] assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[bim.scala:26:7] assign io_f3_meta = io_f3_meta_0; // @[bim.scala:26:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_213 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_213( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPToInt : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in, io.in.bits reg valid : UInt<1>, clock connect valid, io.in.valid inst dcmp of CompareRecFN connect dcmp.io.a, in.in1 connect dcmp.io.b, in.in2 node _dcmp_io_signaling_T = bits(in.rm, 1, 1) node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) connect dcmp.io.signaling, _dcmp_io_signaling_T_1 node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T) node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut) node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut) node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1) node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut) node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut) node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16) node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29) node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1) node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0) node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3) node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4) node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) node _toint_ieee_T_1 = bits(in.in1, 63, 61) node _toint_ieee_T_2 = andr(_toint_ieee_T_1) node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0) node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15) node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0)) node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6) node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9) node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1) node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4) node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1) node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16) node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29) node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6) node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0) node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8) node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9) node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32) node _toint_ieee_T_12 = bits(in.in1, 63, 61) node _toint_ieee_T_13 = andr(_toint_ieee_T_12) node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0) node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14) node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15) node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0) node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17) node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2 node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2) connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11 node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4) node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1) node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2) node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0) node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1) node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14) node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf) node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17) node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4) node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5) node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2) node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2) node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7) node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2) node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7) node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2) node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16) node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29) node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11) node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0) node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13) node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14) node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32) node _toint_ieee_T_20 = bits(in.in1, 63, 61) node _toint_ieee_T_21 = andr(_toint_ieee_T_20) node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0) node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22) node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23) node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0) node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1)) node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10) node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2)) node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27) node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3)) node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29) wire toint : UInt connect toint, toint_ieee node _intType_T = bits(in.fmt, 0, 0) wire intType : UInt<1> connect intType, _intType_T node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut) node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1) node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut) node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16) node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29) node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1) node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0) node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3) node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4) node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0) node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7) node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4) node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16) node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29) node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6) node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0) node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8) node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9) node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32) node _io_out_bits_store_T_10 = bits(in.in1, 63, 61) node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10) node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0) node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12) node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13) node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0) node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15) node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2) connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4) node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2) node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1) node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14) node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf) node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17) node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4) node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5) node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2) node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2) node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7) node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7) node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16) node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29) node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11) node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0) node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13) node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14) node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32) node _io_out_bits_store_T_18 = bits(in.in1, 63, 61) node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18) node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0) node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20) node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21) node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0) node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1)) node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8) node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2)) node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25) node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3)) node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27) connect io.out.bits.store, _io_out_bits_store_T_29 node _io_out_bits_toint_T = bits(toint, 31, 0) node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) node _io_out_bits_toint_T_4 = bits(toint, 63, 0) node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) connect io.out.bits.toint, _io_out_bits_toint_T_6 connect io.out.bits.exc, UInt<1>(0h0) node _T = bits(in.rm, 0, 0) when _T : node classify_out_sign = bits(in.in1, 64, 64) node classify_out_fractIn = bits(in.in1, 51, 0) node classify_out_expIn = bits(in.in1, 63, 52) node _classify_out_fractOut_T = shl(classify_out_fractIn, 11) node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20)) node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0) node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0) node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) node classify_out_hi = cat(classify_out_sign, classify_out_expOut) node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) node classify_out_sign_1 = bits(_classify_out_T, 16, 16) node classify_out_code = bits(_classify_out_T, 15, 13) node classify_out_codeHi = bits(classify_out_code, 2, 1) node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10) node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) node _classify_out_isInf_T = bits(classify_out_code, 0, 0) node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) node classify_out_isNaN = andr(classify_out_code) node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9) node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9) node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) node classify_out_sign_2 = bits(in.in1, 64, 64) node classify_out_fractIn_1 = bits(in.in1, 51, 0) node classify_out_expIn_1 = bits(in.in1, 63, 52) node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24) node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53) node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9) node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100)) node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1) node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800)) node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1) node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0)) node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6)) node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7) node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0) node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9) node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0) node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11) node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1) node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1) node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32) node classify_out_code_1 = bits(_classify_out_T_14, 31, 29) node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23) node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) node classify_out_isNaN_1 = andr(classify_out_code_1) node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22) node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22) node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15) node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17) node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19) node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21) node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3) node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3) node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3) node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3) node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26) node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23) node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24) node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20) node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16) node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1) node classify_out_sign_4 = bits(in.in1, 64, 64) node classify_out_code_2 = bits(in.in1, 63, 61) node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1) node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52) node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2)) node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2) node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8) node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0)) node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9) node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2)) node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11) node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0)) node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0) node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0)) node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5) node classify_out_isNaN_2 = andr(classify_out_code_2) node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51) node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0)) node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5) node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51) node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2) node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28) node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30) node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32) node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34) node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4) node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4) node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4) node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4) node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39) node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36) node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37) node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2) node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33) node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2) node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29) node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2) node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2) node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1)) node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13) node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2)) node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42) node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3)) node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44) node _toint_T = shr(toint_ieee, 32) node _toint_T_1 = shl(_toint_T, 32) node _toint_T_2 = or(classify_out, _toint_T_1) connect toint, _toint_T_2 connect intType, UInt<1>(0h0) when in.wflags : node _toint_T_3 = not(in.rm) node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) node _toint_T_5 = and(_toint_T_3, _toint_T_4) node _toint_T_6 = orr(_toint_T_5) node _toint_T_7 = shr(toint_ieee, 32) node _toint_T_8 = shl(_toint_T_7, 32) node _toint_T_9 = or(_toint_T_6, _toint_T_8) connect toint, _toint_T_9 connect io.out.bits.exc, dcmp.io.exceptionFlags connect intType, UInt<1>(0h0) node _T_1 = eq(in.ren2, UInt<1>(0h0)) when _T_1 : node cvtType = bits(in.typ, 1, 1) connect intType, cvtType inst conv of RecFNToIN_e11_s53_i64 connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 connect conv.io.roundingMode, in.rm node _conv_io_signedOut_T = bits(in.typ, 0, 0) node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) connect conv.io.signedOut, _conv_io_signedOut_T_1 connect toint, conv.io.out node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) connect io.out.bits.exc, _io_out_bits_exc_T_3 node _T_2 = eq(cvtType, UInt<1>(0h0)) when _T_2 : inst narrow of RecFNToIN_e11_s53_i32 connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 connect narrow.io.roundingMode, in.rm node _narrow_io_signedOut_T = bits(in.typ, 0, 0) node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) connect narrow.io.signedOut, _narrow_io_signedOut_T_1 node _excSign_T = bits(in.in1, 64, 64) node _excSign_T_1 = bits(in.in1, 63, 61) node _excSign_T_2 = andr(_excSign_T_1) node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) node excSign = and(_excSign_T, _excSign_T_3) node _excOut_T = eq(conv.io.signedOut, excSign) node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) node excOut = cat(_excOut_T, _excOut_T_2) node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) node invalid = or(_invalid_T, _invalid_T_1) when invalid : node _toint_T_10 = shr(conv.io.out, 32) node _toint_T_11 = cat(_toint_T_10, excOut) connect toint, _toint_T_11 node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) connect io.out.bits.exc, _io_out_bits_exc_T_7 connect io.out.valid, valid node _io_out_bits_lt_T = asSInt(dcmp.io.a) node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) connect io.out.bits.lt, _io_out_bits_lt_T_5 connect io.out.bits.in, in
module FPToInt( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14] output io_out_bits_lt, // @[FPU.scala:461:14] output [63:0] io_out_bits_store, // @[FPU.scala:461:14] output [63:0] io_out_bits_toint, // @[FPU.scala:461:14] output [4:0] io_out_bits_exc // @[FPU.scala:461:14] ); wire [63:0] toint; // @[FPU.scala:484:19, :490:20, :495:21] wire _narrow_io_signedOut_T; // @[FPU.scala:501:35] wire intType; // @[FPU.scala:484:19, :490:20, :495:21] wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] reg in_ren2; // @[FPU.scala:466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] reg in_wflags; // @[FPU.scala:466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] reg [1:0] in_fmt; // @[FPU.scala:466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] reg [64:0] in_in2; // @[FPU.scala:466:21] wire [12:0] toint_ieee_unrecoded_rawIn_sExp = {1'h0, in_in1[63:52]}; // @[FPU.scala:466:21] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52]; // @[FPU.scala:466:21] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23]; // @[FPU.scala:443:10, :466:21] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = {in_in1[23], in_in1[14]}; // @[FPU.scala:443:10, :466:21] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = (&_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T) & ~(in_in1[13]); // @[FPU.scala:466:21] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed({1'h0, in_in1[23], in_in1[14:10]}) < 7'sh12; // @[FPU.scala:443:10, :466:21] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = {1'h0, |{in_in1[23], in_in1[14:13]}, in_in1[9:1]} >> 4'h1 - in_in1[13:10]; // @[FPU.scala:443:10, :466:21] wire [15:0] _toint_ieee_T_4 = (&(in_in1[63:61])) ? ((&{in_in1[52], in_in1[30:29]}) ? {in_in1[15], (toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : in_in1[14:10] + 5'hF) | {5{(&_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T) & in_in1[13] | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf}}, toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0] : toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : in_in1[9:0]} : $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82 ? _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[15:0] : (&{in_in1[52], in_in1[30]}) & ~(in_in1[29]) ? 16'h0 : in_in1[15:0]) : $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402 ? _toint_ieee_unrecoded_denormFract_T_1[15:0] : (&(in_in1[63:62])) & ~(in_in1[61]) ? 16'h0 : in_in1[15:0]; // @[FPU.scala:249:{25,56}, :442:10, :443:10, :446:44, :466:21] wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_4[15]}}; // @[package.scala:132:{20,38}] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52]; // @[FPU.scala:466:21] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = {in_in1[52], in_in1[30]}; // @[FPU.scala:443:10, :466:21] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = (&_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1) & ~(in_in1[29]); // @[FPU.scala:466:21] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82; // @[FPU.scala:443:10, :466:21] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23]; // @[FPU.scala:443:10, :466:21] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0] : toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]; // @[FPU.scala:466:21] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = {in_in1[23], in_in1[14]}; // @[FPU.scala:443:10, :466:21] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = (&_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1) & ~(in_in1[13]); // @[FPU.scala:466:21] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed({1'h0, in_in1[23], in_in1[14:10]}) < 7'sh12; // @[FPU.scala:443:10, :466:21] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = {1'h0, |{in_in1[23], in_in1[14:13]}, in_in1[9:1]} >> 4'h1 - in_in1[13:10]; // @[FPU.scala:443:10, :466:21] wire toint_ieee_unrecoded_rawIn_2_isInf = (&(in_in1[63:62])) & ~(in_in1[61]); // @[FPU.scala:466:21] wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:60:27] wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52]; // @[FPU.scala:466:21] wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? _toint_ieee_unrecoded_denormFract_T_5[51:0] : toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : in_in1[51:0]; // @[FPU.scala:466:21] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = {in_in1[52], in_in1[30]}; // @[FPU.scala:443:10, :466:21] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = (&_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2) & ~(in_in1[29]); // @[FPU.scala:466:21] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82; // @[FPU.scala:443:10, :466:21] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23]; // @[FPU.scala:443:10, :466:21] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0] : toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : in_in1[22:0]; // @[FPU.scala:466:21] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = {in_in1[23], in_in1[14]}; // @[FPU.scala:443:10, :466:21] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = (&_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2) & ~(in_in1[13]); // @[FPU.scala:466:21] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed({1'h0, in_in1[23], in_in1[14:10]}) < 7'sh12; // @[FPU.scala:443:10, :466:21] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = {1'h0, |{in_in1[23], in_in1[14:13]}, in_in1[9:1]} >> 4'h1 - in_in1[13:10]; // @[FPU.scala:443:10, :466:21] wire _classify_out_T_41 = in_typeTagOut == 2'h1; // @[package.scala:39:86] wire _GEN = (&in_typeTagOut) | in_typeTagOut == 2'h2; // @[package.scala:39:{76,86}] wire [63:0] toint_ieee = _GEN ? {in_in1[64], (toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : in_in1[62:52] + 11'h3FF) | {11{(&(in_in1[63:62])) & in_in1[61] | toint_ieee_unrecoded_rawIn_2_isInf}}, toint_ieee_unrecoded_fractOut_2[51:32], (&(in_in1[63:61])) ? {in_in1[31], (toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : in_in1[30:23] + 8'h7F) | {8{(&_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2) & in_in1[29] | toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf}}, toint_ieee_prevUnrecoded_unrecoded_fractOut_2[22:16], (&{in_in1[52], in_in1[30:29]}) ? {in_in1[15], (toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : in_in1[14:10] + 5'hF) | {5{(&_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2) & in_in1[13] | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf}}, toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0] : toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : in_in1[9:0]} : toint_ieee_prevUnrecoded_unrecoded_fractOut_2[15:0]} : toint_ieee_unrecoded_fractOut_2[31:0]} : _classify_out_T_41 ? {2{(&(in_in1[63:61])) ? {in_in1[31], (toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : in_in1[30:23] + 8'h7F) | {8{(&_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1) & in_in1[29] | toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf}}, toint_ieee_prevUnrecoded_unrecoded_fractOut_1[22:16], (&{in_in1[52], in_in1[30:29]}) ? {in_in1[15], (toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : in_in1[14:10] + 5'hF) | {5{(&_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1) & in_in1[13] | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf}}, toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0] : toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : in_in1[9:0]} : toint_ieee_prevUnrecoded_unrecoded_fractOut_1[15:0]} : $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402 ? _toint_ieee_unrecoded_denormFract_T_3[31:0] : (&(in_in1[63:62])) & ~(in_in1[61]) ? 32'h0 : in_in1[31:0]}} : {_toint_ieee_T_8, _toint_ieee_T_4, _toint_ieee_T_8, _toint_ieee_T_4}; // @[package.scala:39:{76,86}, :132:20] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52]; // @[FPU.scala:466:21] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23]; // @[FPU.scala:443:10, :466:21] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = {in_in1[23], in_in1[14]}; // @[FPU.scala:443:10, :466:21] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = (&_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T) & ~(in_in1[13]); // @[FPU.scala:466:21] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed({1'h0, in_in1[23], in_in1[14:10]}) < 7'sh12; // @[FPU.scala:443:10, :466:21] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = {1'h0, |{in_in1[23], in_in1[14:13]}, in_in1[9:1]} >> 4'h1 - in_in1[13:10]; // @[FPU.scala:443:10, :466:21] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52]; // @[FPU.scala:466:21] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = {in_in1[52], in_in1[30]}; // @[FPU.scala:443:10, :466:21] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = (&_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1) & ~(in_in1[29]); // @[FPU.scala:466:21] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82; // @[FPU.scala:443:10, :466:21] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23]; // @[FPU.scala:443:10, :466:21] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0] : io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : in_in1[22:0]; // @[FPU.scala:466:21] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = {in_in1[23], in_in1[14]}; // @[FPU.scala:443:10, :466:21] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = (&_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1) & ~(in_in1[13]); // @[FPU.scala:466:21] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed({1'h0, in_in1[23], in_in1[14:10]}) < 7'sh12; // @[FPU.scala:443:10, :466:21] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = {1'h0, |{in_in1[23], in_in1[14:13]}, in_in1[9:1]} >> 4'h1 - in_in1[13:10]; // @[FPU.scala:443:10, :466:21] wire io_out_bits_store_unrecoded_rawIn_2_isInf = (&(in_in1[63:62])) & ~(in_in1[61]); // @[FPU.scala:466:21] wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:60:27] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = {1'h0, |(in_in1[63:61]), in_in1[51:1]} >> 6'h1 - in_in1[57:52]; // @[FPU.scala:466:21] wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? _io_out_bits_store_unrecoded_denormFract_T_5[51:0] : io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : in_in1[51:0]; // @[FPU.scala:466:21] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = {in_in1[52], in_in1[30]}; // @[FPU.scala:443:10, :466:21] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = (&_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2) & ~(in_in1[29]); // @[FPU.scala:466:21] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed({1'h0, in_in1[52], in_in1[30:23]}) < 10'sh82; // @[FPU.scala:443:10, :466:21] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = {1'h0, |{in_in1[52], in_in1[30:29]}, in_in1[22:1]} >> 5'h1 - in_in1[27:23]; // @[FPU.scala:443:10, :466:21] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0] : io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : in_in1[22:0]; // @[FPU.scala:466:21] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = {in_in1[23], in_in1[14]}; // @[FPU.scala:443:10, :466:21] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = (&_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2) & ~(in_in1[13]); // @[FPU.scala:466:21] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed({1'h0, in_in1[23], in_in1[14:10]}) < 7'sh12; // @[FPU.scala:443:10, :466:21] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = {1'h0, |{in_in1[23], in_in1[14:13]}, in_in1[9:1]} >> 4'h1 - in_in1[13:10]; // @[FPU.scala:443:10, :466:21] wire [5:0] _classify_out_expOut_commonCase_T = in_in1[57:52] - 6'h20; // @[FPU.scala:280:31, :466:21] wire [5:0] classify_out_expOut = in_in1[63:61] == 3'h0 | in_in1[63:61] > 3'h5 ? {in_in1[63:61], _classify_out_expOut_commonCase_T[2:0]} : _classify_out_expOut_commonCase_T; // @[FPU.scala:279:26, :280:{31,50}, :281:{10,19,27,38,49,69}, :453:7, :466:21] wire _classify_out_isNormal_T = classify_out_expOut[5:4] == 2'h1; // @[FPU.scala:254:17, :255:22, :259:46, :281:10] wire classify_out_isSubnormal = classify_out_expOut[5:3] == 3'h1 | _classify_out_isNormal_T & classify_out_expOut[3:0] < 4'h2; // @[FPU.scala:254:17, :258:{30,55}, :259:{28,36,46,54}, :281:10, :453:7] wire classify_out_isNormal = _classify_out_isNormal_T & (|(classify_out_expOut[3:1])) | classify_out_expOut[5:4] == 2'h2; // @[FPU.scala:254:17, :255:22, :258:55, :259:46, :260:{35,38,57,67}, :281:10] wire classify_out_isZero = classify_out_expOut[5:3] == 3'h0; // @[FPU.scala:254:17, :261:23, :281:10, :453:7] wire classify_out_isInf = (&(classify_out_expOut[5:4])) & ~(classify_out_expOut[3]); // @[FPU.scala:254:17, :255:22, :256:28, :262:{27,30,35}, :281:10] wire [8:0] _classify_out_expOut_commonCase_T_3 = in_in1[60:52] - 9'h100; // @[FPU.scala:280:31, :466:21] wire [8:0] classify_out_expOut_1 = in_in1[63:61] == 3'h0 | in_in1[63:61] > 3'h5 ? {in_in1[63:61], _classify_out_expOut_commonCase_T_3[5:0]} : _classify_out_expOut_commonCase_T_3; // @[FPU.scala:279:26, :280:{31,50}, :281:{10,19,27,38,49,69}, :453:7, :466:21] wire _classify_out_isNormal_T_4 = classify_out_expOut_1[8:7] == 2'h1; // @[FPU.scala:254:17, :255:22, :259:46, :281:10] wire classify_out_isSubnormal_1 = classify_out_expOut_1[8:6] == 3'h1 | _classify_out_isNormal_T_4 & classify_out_expOut_1[6:0] < 7'h2; // @[FPU.scala:254:17, :258:{30,55}, :259:{28,36,46,54}, :281:10, :453:7] wire classify_out_isNormal_1 = _classify_out_isNormal_T_4 & (|(classify_out_expOut_1[6:1])) | classify_out_expOut_1[8:7] == 2'h2; // @[FPU.scala:254:17, :255:22, :258:55, :259:46, :260:{35,38,57,67}, :281:10] wire classify_out_isZero_1 = classify_out_expOut_1[8:6] == 3'h0; // @[FPU.scala:254:17, :261:23, :281:10, :453:7] wire classify_out_isInf_1 = (&(classify_out_expOut_1[8:7])) & ~(classify_out_expOut_1[6]); // @[FPU.scala:254:17, :255:22, :256:28, :262:{27,30,35}, :281:10] wire _classify_out_isNormal_T_8 = in_in1[63:62] == 2'h1; // @[FPU.scala:249:25, :255:22, :259:46, :466:21] wire classify_out_isSubnormal_2 = in_in1[63:61] == 3'h1 | _classify_out_isNormal_T_8 & in_in1[61:52] < 10'h2; // @[FPU.scala:249:25, :258:{30,55}, :259:{28,36,46,54}, :453:7, :466:21] wire classify_out_isNormal_2 = _classify_out_isNormal_T_8 & (|(in_in1[61:53])) | in_in1[63:62] == 2'h2; // @[FPU.scala:249:25, :255:22, :258:55, :259:46, :260:{35,38,57,67}, :466:21] wire classify_out_isZero_2 = in_in1[63:61] == 3'h0; // @[FPU.scala:249:25, :261:23, :453:7, :466:21] wire classify_out_isInf_2 = (&(in_in1[63:62])) & ~(in_in1[61]); // @[FPU.scala:249:25, :255:22, :256:28, :262:{27,30,35}, :466:21] assign intType = in_wflags ? ~in_ren2 & in_typ[1] : ~(in_rm[0]) & in_fmt[0]; // @[package.scala:163:13] assign _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire excSign = in_in1[64] & in_in1[63:61] != 3'h7; // @[FPU.scala:249:{25,56}, :466:21, :513:59] wire invalid = _conv_io_intExceptionFlags[2] | _narrow_io_intExceptionFlags[1]; // @[FPU.scala:498:24, :508:30, :515:{50,54,84}] assign toint = in_wflags ? (in_ren2 ? {toint_ieee[63:32], 31'h0, |(~(in_rm[1:0]) & {_dcmp_io_lt, _dcmp_io_eq})} : ~(in_typ[1]) & invalid ? {_conv_io_out[63:32], ~_narrow_io_signedOut_T == excSign, {31{~excSign}}} : _conv_io_out) : in_rm[0] ? {toint_ieee[63:32], 22'h0, _GEN ? {(&(in_in1[63:61])) & in_in1[51], (&(in_in1[63:61])) & ~(in_in1[51]), classify_out_isInf_2 & ~(in_in1[64]), classify_out_isNormal_2 & ~(in_in1[64]), classify_out_isSubnormal_2 & ~(in_in1[64]), classify_out_isZero_2 & ~(in_in1[64]), classify_out_isZero_2 & in_in1[64], classify_out_isSubnormal_2 & in_in1[64], classify_out_isNormal_2 & in_in1[64], classify_out_isInf_2 & in_in1[64]} : _classify_out_T_41 ? {(&(classify_out_expOut_1[8:6])) & in_in1[51], (&(classify_out_expOut_1[8:6])) & ~(in_in1[51]), classify_out_isInf_1 & ~(in_in1[64]), classify_out_isNormal_1 & ~(in_in1[64]), classify_out_isSubnormal_1 & ~(in_in1[64]), classify_out_isZero_1 & ~(in_in1[64]), classify_out_isZero_1 & in_in1[64], classify_out_isSubnormal_1 & in_in1[64], classify_out_isNormal_1 & in_in1[64], classify_out_isInf_1 & in_in1[64]} : {(&(classify_out_expOut[5:3])) & in_in1[51], (&(classify_out_expOut[5:3])) & ~(in_in1[51]), classify_out_isInf & ~(in_in1[64]), classify_out_isNormal & ~(in_in1[64]), classify_out_isSubnormal & ~(in_in1[64]), classify_out_isZero & ~(in_in1[64]), classify_out_isZero & in_in1[64], classify_out_isSubnormal & in_in1[64], classify_out_isNormal & in_in1[64], classify_out_isInf & in_in1[64]}} : toint_ieee; // @[package.scala:39:{76,86}, :163:13] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid) begin // @[FPU.scala:461:14] in_ren2 <= io_in_bits_ren2; // @[FPU.scala:466:21] in_typeTagOut <= io_in_bits_typeTagOut; // @[FPU.scala:466:21] in_wflags <= io_in_bits_wflags; // @[FPU.scala:466:21] in_rm <= io_in_bits_rm; // @[FPU.scala:466:21] in_typ <= io_in_bits_typ; // @[FPU.scala:466:21] in_fmt <= io_in_bits_fmt; // @[FPU.scala:466:21] in_in1 <= io_in_bits_in1; // @[FPU.scala:466:21] in_in2 <= io_in_bits_in2; // @[FPU.scala:466:21] end always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_39 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_351 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_352 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_354 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_39( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_351 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_352 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_353 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_354 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_33 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<29>(0h10000000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = and(_T_32, _T_37) node _T_39 = or(UInt<1>(0h0), _T_38) node _T_40 = and(_T_31, _T_39) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_40, UInt<1>(0h1), "") : assert_2 node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_46 = and(_T_44, _T_45) node _T_47 = or(UInt<1>(0h0), _T_46) node _T_48 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<29>(0h10000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = and(_T_47, _T_52) node _T_54 = or(UInt<1>(0h0), _T_53) node _T_55 = and(UInt<1>(0h0), _T_54) node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(_T_55, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_55, UInt<1>(0h1), "") : assert_3 node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_62, UInt<1>(0h1), "") : assert_5 node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(is_aligned, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_69, UInt<1>(0h1), "") : assert_7 node _T_73 = not(io.in.a.bits.mask) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_74, UInt<1>(0h1), "") : assert_8 node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_78, UInt<1>(0h1), "") : assert_9 node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_82 : node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_85 = and(_T_83, _T_84) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_86 = shr(io.in.a.bits.source, 4) node _T_87 = eq(_T_86, UInt<1>(0h0)) node _T_88 = leq(UInt<1>(0h0), uncommonBits_2) node _T_89 = and(_T_87, _T_88) node _T_90 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_91 = and(_T_89, _T_90) node _T_92 = and(_T_85, _T_91) node _T_93 = or(UInt<1>(0h0), _T_92) node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<29>(0h10000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(_T_93, _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_102, UInt<1>(0h1), "") : assert_10 node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_108 = and(_T_106, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<29>(0h10000000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = and(_T_109, _T_114) node _T_116 = or(UInt<1>(0h0), _T_115) node _T_117 = and(UInt<1>(0h0), _T_116) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_117, UInt<1>(0h1), "") : assert_11 node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_125 = asUInt(reset) node _T_126 = eq(_T_125, UInt<1>(0h0)) when _T_126 : node _T_127 = eq(_T_124, UInt<1>(0h0)) when _T_127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_124, UInt<1>(0h1), "") : assert_13 node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(is_aligned, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_131, UInt<1>(0h1), "") : assert_15 node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_136 = asUInt(reset) node _T_137 = eq(_T_136, UInt<1>(0h0)) when _T_137 : node _T_138 = eq(_T_135, UInt<1>(0h0)) when _T_138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_135, UInt<1>(0h1), "") : assert_16 node _T_139 = not(io.in.a.bits.mask) node _T_140 = eq(_T_139, UInt<1>(0h0)) node _T_141 = asUInt(reset) node _T_142 = eq(_T_141, UInt<1>(0h0)) when _T_142 : node _T_143 = eq(_T_140, UInt<1>(0h0)) when _T_143 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_140, UInt<1>(0h1), "") : assert_17 node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_T_144, UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_144, UInt<1>(0h1), "") : assert_18 node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_148 : node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_152 = shr(io.in.a.bits.source, 4) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_3) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_157 = and(_T_155, _T_156) node _T_158 = and(_T_151, _T_157) node _T_159 = or(UInt<1>(0h0), _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_159, UInt<1>(0h1), "") : assert_19 node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_164 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_165 = and(_T_163, _T_164) node _T_166 = or(UInt<1>(0h0), _T_165) node _T_167 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_168 = cvt(_T_167) node _T_169 = and(_T_168, asSInt(UInt<29>(0h10000000))) node _T_170 = asSInt(_T_169) node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0))) node _T_172 = and(_T_166, _T_171) node _T_173 = or(UInt<1>(0h0), _T_172) node _T_174 = asUInt(reset) node _T_175 = eq(_T_174, UInt<1>(0h0)) when _T_175 : node _T_176 = eq(_T_173, UInt<1>(0h0)) when _T_176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_173, UInt<1>(0h1), "") : assert_20 node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(is_aligned, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(io.in.a.bits.mask, mask) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_187, UInt<1>(0h1), "") : assert_24 node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_191, UInt<1>(0h1), "") : assert_25 node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_195 : node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_198 = and(_T_196, _T_197) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_199 = shr(io.in.a.bits.source, 4) node _T_200 = eq(_T_199, UInt<1>(0h0)) node _T_201 = leq(UInt<1>(0h0), uncommonBits_4) node _T_202 = and(_T_200, _T_201) node _T_203 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_204 = and(_T_202, _T_203) node _T_205 = and(_T_198, _T_204) node _T_206 = or(UInt<1>(0h0), _T_205) node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_208 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_209 = and(_T_207, _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<29>(0h10000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = and(_T_210, _T_215) node _T_217 = or(UInt<1>(0h0), _T_216) node _T_218 = and(_T_206, _T_217) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_218, UInt<1>(0h1), "") : assert_26 node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_225 = asUInt(reset) node _T_226 = eq(_T_225, UInt<1>(0h0)) when _T_226 : node _T_227 = eq(is_aligned, UInt<1>(0h0)) when _T_227 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(_T_228, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_228, UInt<1>(0h1), "") : assert_29 node _T_232 = eq(io.in.a.bits.mask, mask) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_236 : node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_239 = and(_T_237, _T_238) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_240 = shr(io.in.a.bits.source, 4) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = leq(UInt<1>(0h0), uncommonBits_5) node _T_243 = and(_T_241, _T_242) node _T_244 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_245 = and(_T_243, _T_244) node _T_246 = and(_T_239, _T_245) node _T_247 = or(UInt<1>(0h0), _T_246) node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_249 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_250 = and(_T_248, _T_249) node _T_251 = or(UInt<1>(0h0), _T_250) node _T_252 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_253 = cvt(_T_252) node _T_254 = and(_T_253, asSInt(UInt<29>(0h10000000))) node _T_255 = asSInt(_T_254) node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0))) node _T_257 = and(_T_251, _T_256) node _T_258 = or(UInt<1>(0h0), _T_257) node _T_259 = and(_T_247, _T_258) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_259, UInt<1>(0h1), "") : assert_31 node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(is_aligned, UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_270 = asUInt(reset) node _T_271 = eq(_T_270, UInt<1>(0h0)) when _T_271 : node _T_272 = eq(_T_269, UInt<1>(0h0)) when _T_272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_269, UInt<1>(0h1), "") : assert_34 node _T_273 = not(mask) node _T_274 = and(io.in.a.bits.mask, _T_273) node _T_275 = eq(_T_274, UInt<1>(0h0)) node _T_276 = asUInt(reset) node _T_277 = eq(_T_276, UInt<1>(0h0)) when _T_277 : node _T_278 = eq(_T_275, UInt<1>(0h0)) when _T_278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_275, UInt<1>(0h1), "") : assert_35 node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_279 : node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_282 = and(_T_280, _T_281) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_283 = shr(io.in.a.bits.source, 4) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = leq(UInt<1>(0h0), uncommonBits_6) node _T_286 = and(_T_284, _T_285) node _T_287 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_288 = and(_T_286, _T_287) node _T_289 = and(_T_282, _T_288) node _T_290 = or(UInt<1>(0h0), _T_289) node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_293 = cvt(_T_292) node _T_294 = and(_T_293, asSInt(UInt<29>(0h10000000))) node _T_295 = asSInt(_T_294) node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0))) node _T_297 = and(_T_291, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = and(_T_290, _T_298) node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_T_299, UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_299, UInt<1>(0h1), "") : assert_36 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_306 = asUInt(reset) node _T_307 = eq(_T_306, UInt<1>(0h0)) when _T_307 : node _T_308 = eq(is_aligned, UInt<1>(0h0)) when _T_308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_309, UInt<1>(0h1), "") : assert_39 node _T_313 = eq(io.in.a.bits.mask, mask) node _T_314 = asUInt(reset) node _T_315 = eq(_T_314, UInt<1>(0h0)) when _T_315 : node _T_316 = eq(_T_313, UInt<1>(0h0)) when _T_316 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_313, UInt<1>(0h1), "") : assert_40 node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_317 : node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_320 = and(_T_318, _T_319) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_321 = shr(io.in.a.bits.source, 4) node _T_322 = eq(_T_321, UInt<1>(0h0)) node _T_323 = leq(UInt<1>(0h0), uncommonBits_7) node _T_324 = and(_T_322, _T_323) node _T_325 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_326 = and(_T_324, _T_325) node _T_327 = and(_T_320, _T_326) node _T_328 = or(UInt<1>(0h0), _T_327) node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_330 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_331 = cvt(_T_330) node _T_332 = and(_T_331, asSInt(UInt<29>(0h10000000))) node _T_333 = asSInt(_T_332) node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0))) node _T_335 = and(_T_329, _T_334) node _T_336 = or(UInt<1>(0h0), _T_335) node _T_337 = and(_T_328, _T_336) node _T_338 = asUInt(reset) node _T_339 = eq(_T_338, UInt<1>(0h0)) when _T_339 : node _T_340 = eq(_T_337, UInt<1>(0h0)) when _T_340 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_337, UInt<1>(0h1), "") : assert_41 node _T_341 = asUInt(reset) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_343 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(is_aligned, UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_347, UInt<1>(0h1), "") : assert_44 node _T_351 = eq(io.in.a.bits.mask, mask) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_351, UInt<1>(0h1), "") : assert_45 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_359 = shr(io.in.a.bits.source, 4) node _T_360 = eq(_T_359, UInt<1>(0h0)) node _T_361 = leq(UInt<1>(0h0), uncommonBits_8) node _T_362 = and(_T_360, _T_361) node _T_363 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_364 = and(_T_362, _T_363) node _T_365 = and(_T_358, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_368 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_369 = cvt(_T_368) node _T_370 = and(_T_369, asSInt(UInt<29>(0h10000000))) node _T_371 = asSInt(_T_370) node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0))) node _T_373 = and(_T_367, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = and(_T_366, _T_374) node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_T_375, UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_375, UInt<1>(0h1), "") : assert_46 node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(is_aligned, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_385, UInt<1>(0h1), "") : assert_49 node _T_389 = eq(io.in.a.bits.mask, mask) node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(_T_389, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_389, UInt<1>(0h1), "") : assert_50 node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_393, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_397, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_401 : node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(_T_405, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_405, UInt<1>(0h1), "") : assert_54 node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_409, UInt<1>(0h1), "") : assert_55 node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_413, UInt<1>(0h1), "") : assert_56 node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(_T_417, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_417, UInt<1>(0h1), "") : assert_57 node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_421 : node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(sink_ok, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_428, UInt<1>(0h1), "") : assert_60 node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_433 = asUInt(reset) node _T_434 = eq(_T_433, UInt<1>(0h0)) when _T_434 : node _T_435 = eq(_T_432, UInt<1>(0h0)) when _T_435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_432, UInt<1>(0h1), "") : assert_61 node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_436, UInt<1>(0h1), "") : assert_62 node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(_T_440, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_440, UInt<1>(0h1), "") : assert_63 node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_445 = or(UInt<1>(0h1), _T_444) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_445, UInt<1>(0h1), "") : assert_64 node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_449 : node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(sink_ok, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_457 = asUInt(reset) node _T_458 = eq(_T_457, UInt<1>(0h0)) when _T_458 : node _T_459 = eq(_T_456, UInt<1>(0h0)) when _T_459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_456, UInt<1>(0h1), "") : assert_67 node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_461 = asUInt(reset) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(_T_460, UInt<1>(0h0)) when _T_463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_460, UInt<1>(0h1), "") : assert_68 node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_465 = asUInt(reset) node _T_466 = eq(_T_465, UInt<1>(0h0)) when _T_466 : node _T_467 = eq(_T_464, UInt<1>(0h0)) when _T_467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_464, UInt<1>(0h1), "") : assert_69 node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_469 = or(_T_468, io.in.d.bits.corrupt) node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_T_469, UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_469, UInt<1>(0h1), "") : assert_70 node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_474 = or(UInt<1>(0h1), _T_473) node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(_T_474, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_474, UInt<1>(0h1), "") : assert_71 node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_478 : node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_482, UInt<1>(0h1), "") : assert_73 node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_486, UInt<1>(0h1), "") : assert_74 node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_491 = or(UInt<1>(0h1), _T_490) node _T_492 = asUInt(reset) node _T_493 = eq(_T_492, UInt<1>(0h0)) when _T_493 : node _T_494 = eq(_T_491, UInt<1>(0h0)) when _T_494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_491, UInt<1>(0h1), "") : assert_75 node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_495 : node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_499, UInt<1>(0h1), "") : assert_77 node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_504 = or(_T_503, io.in.d.bits.corrupt) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_504, UInt<1>(0h1), "") : assert_78 node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_509 = or(UInt<1>(0h1), _T_508) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_509, UInt<1>(0h1), "") : assert_79 node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_513 : node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_T_517, UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_517, UInt<1>(0h1), "") : assert_81 node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_522 = asUInt(reset) node _T_523 = eq(_T_522, UInt<1>(0h0)) when _T_523 : node _T_524 = eq(_T_521, UInt<1>(0h0)) when _T_524 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_521, UInt<1>(0h1), "") : assert_82 node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_526 = or(UInt<1>(0h1), _T_525) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_526, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_530, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_535 = asUInt(reset) node _T_536 = eq(_T_535, UInt<1>(0h0)) when _T_536 : node _T_537 = eq(_T_534, UInt<1>(0h0)) when _T_537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_534, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_T_538, UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_538, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_542 = eq(a_first, UInt<1>(0h0)) node _T_543 = and(io.in.a.valid, _T_542) when _T_543 : node _T_544 = eq(io.in.a.bits.opcode, opcode) node _T_545 = asUInt(reset) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(_T_544, UInt<1>(0h0)) when _T_547 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_544, UInt<1>(0h1), "") : assert_87 node _T_548 = eq(io.in.a.bits.param, param) node _T_549 = asUInt(reset) node _T_550 = eq(_T_549, UInt<1>(0h0)) when _T_550 : node _T_551 = eq(_T_548, UInt<1>(0h0)) when _T_551 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_548, UInt<1>(0h1), "") : assert_88 node _T_552 = eq(io.in.a.bits.size, size) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_552, UInt<1>(0h1), "") : assert_89 node _T_556 = eq(io.in.a.bits.source, source) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_556, UInt<1>(0h1), "") : assert_90 node _T_560 = eq(io.in.a.bits.address, address) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_560, UInt<1>(0h1), "") : assert_91 node _T_564 = and(io.in.a.ready, io.in.a.valid) node _T_565 = and(_T_564, a_first) when _T_565 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_566 = eq(d_first, UInt<1>(0h0)) node _T_567 = and(io.in.d.valid, _T_566) when _T_567 : node _T_568 = eq(io.in.d.bits.opcode, opcode_1) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_568, UInt<1>(0h1), "") : assert_92 node _T_572 = eq(io.in.d.bits.param, param_1) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_572, UInt<1>(0h1), "") : assert_93 node _T_576 = eq(io.in.d.bits.size, size_1) node _T_577 = asUInt(reset) node _T_578 = eq(_T_577, UInt<1>(0h0)) when _T_578 : node _T_579 = eq(_T_576, UInt<1>(0h0)) when _T_579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_576, UInt<1>(0h1), "") : assert_94 node _T_580 = eq(io.in.d.bits.source, source_1) node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(_T_580, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_580, UInt<1>(0h1), "") : assert_95 node _T_584 = eq(io.in.d.bits.sink, sink) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_584, UInt<1>(0h1), "") : assert_96 node _T_588 = eq(io.in.d.bits.denied, denied) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_588, UInt<1>(0h1), "") : assert_97 node _T_592 = and(io.in.d.ready, io.in.d.valid) node _T_593 = and(_T_592, d_first) when _T_593 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_594 = and(io.in.a.valid, a_first_1) node _T_595 = and(_T_594, UInt<1>(0h1)) when _T_595 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_596 = and(io.in.a.ready, io.in.a.valid) node _T_597 = and(_T_596, a_first_1) node _T_598 = and(_T_597, UInt<1>(0h1)) when _T_598 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_599 = dshr(inflight, io.in.a.bits.source) node _T_600 = bits(_T_599, 0, 0) node _T_601 = eq(_T_600, UInt<1>(0h0)) node _T_602 = asUInt(reset) node _T_603 = eq(_T_602, UInt<1>(0h0)) when _T_603 : node _T_604 = eq(_T_601, UInt<1>(0h0)) when _T_604 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_601, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_605 = and(io.in.d.valid, d_first_1) node _T_606 = and(_T_605, UInt<1>(0h1)) node _T_607 = eq(d_release_ack, UInt<1>(0h0)) node _T_608 = and(_T_606, _T_607) when _T_608 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_609 = and(io.in.d.ready, io.in.d.valid) node _T_610 = and(_T_609, d_first_1) node _T_611 = and(_T_610, UInt<1>(0h1)) node _T_612 = eq(d_release_ack, UInt<1>(0h0)) node _T_613 = and(_T_611, _T_612) when _T_613 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_614 = and(io.in.d.valid, d_first_1) node _T_615 = and(_T_614, UInt<1>(0h1)) node _T_616 = eq(d_release_ack, UInt<1>(0h0)) node _T_617 = and(_T_615, _T_616) when _T_617 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_618 = dshr(inflight, io.in.d.bits.source) node _T_619 = bits(_T_618, 0, 0) node _T_620 = or(_T_619, same_cycle_resp) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_620, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_626 = or(_T_624, _T_625) node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(_T_626, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_626, UInt<1>(0h1), "") : assert_100 node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_630, UInt<1>(0h1), "") : assert_101 else : node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_636 = or(_T_634, _T_635) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_636, UInt<1>(0h1), "") : assert_102 node _T_640 = eq(io.in.d.bits.size, a_size_lookup) node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(_T_640, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_640, UInt<1>(0h1), "") : assert_103 node _T_644 = and(io.in.d.valid, d_first_1) node _T_645 = and(_T_644, a_first_1) node _T_646 = and(_T_645, io.in.a.valid) node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_648 = and(_T_646, _T_647) node _T_649 = eq(d_release_ack, UInt<1>(0h0)) node _T_650 = and(_T_648, _T_649) when _T_650 : node _T_651 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_652 = or(_T_651, io.in.a.ready) node _T_653 = asUInt(reset) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(_T_652, UInt<1>(0h0)) when _T_655 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_652, UInt<1>(0h1), "") : assert_104 node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_657 = orr(a_set_wo_ready) node _T_658 = eq(_T_657, UInt<1>(0h0)) node _T_659 = or(_T_656, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_659, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_22 node _T_663 = orr(inflight) node _T_664 = eq(_T_663, UInt<1>(0h0)) node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_666 = or(_T_664, _T_665) node _T_667 = lt(watchdog, plusarg_reader.out) node _T_668 = or(_T_666, _T_667) node _T_669 = asUInt(reset) node _T_670 = eq(_T_669, UInt<1>(0h0)) when _T_670 : node _T_671 = eq(_T_668, UInt<1>(0h0)) when _T_671 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_668, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_672 = and(io.in.a.ready, io.in.a.valid) node _T_673 = and(io.in.d.ready, io.in.d.valid) node _T_674 = or(_T_672, _T_673) when _T_674 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_675 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<3>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_678 = and(_T_676, _T_677) node _T_679 = and(_T_675, _T_678) when _T_679 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_681 = and(_T_680, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_684 = and(_T_682, _T_683) node _T_685 = and(_T_681, _T_684) when _T_685 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_686 = dshr(inflight_1, _WIRE_15.bits.source) node _T_687 = bits(_T_686, 0, 0) node _T_688 = eq(_T_687, UInt<1>(0h0)) node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(_T_688, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_688, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_692 = and(io.in.d.valid, d_first_2) node _T_693 = and(_T_692, UInt<1>(0h1)) node _T_694 = and(_T_693, d_release_ack_1) when _T_694 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_695 = and(io.in.d.ready, io.in.d.valid) node _T_696 = and(_T_695, d_first_2) node _T_697 = and(_T_696, UInt<1>(0h1)) node _T_698 = and(_T_697, d_release_ack_1) when _T_698 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_699 = and(io.in.d.valid, d_first_2) node _T_700 = and(_T_699, UInt<1>(0h1)) node _T_701 = and(_T_700, d_release_ack_1) when _T_701 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_702 = dshr(inflight_1, io.in.d.bits.source) node _T_703 = bits(_T_702, 0, 0) node _T_704 = or(_T_703, same_cycle_resp_1) node _T_705 = asUInt(reset) node _T_706 = eq(_T_705, UInt<1>(0h0)) when _T_706 : node _T_707 = eq(_T_704, UInt<1>(0h0)) when _T_707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_704, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_709 = asUInt(reset) node _T_710 = eq(_T_709, UInt<1>(0h0)) when _T_710 : node _T_711 = eq(_T_708, UInt<1>(0h0)) when _T_711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_708, UInt<1>(0h1), "") : assert_109 else : node _T_712 = eq(io.in.d.bits.size, c_size_lookup) node _T_713 = asUInt(reset) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(_T_712, UInt<1>(0h0)) when _T_715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_712, UInt<1>(0h1), "") : assert_110 node _T_716 = and(io.in.d.valid, d_first_2) node _T_717 = and(_T_716, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_718 = and(_T_717, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_720 = and(_T_718, _T_719) node _T_721 = and(_T_720, d_release_ack_1) node _T_722 = eq(c_probe_ack, UInt<1>(0h0)) node _T_723 = and(_T_721, _T_722) when _T_723 : node _T_724 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_725 = or(_T_724, _WIRE_23.ready) node _T_726 = asUInt(reset) node _T_727 = eq(_T_726, UInt<1>(0h0)) when _T_727 : node _T_728 = eq(_T_725, UInt<1>(0h0)) when _T_728 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_725, UInt<1>(0h1), "") : assert_111 node _T_729 = orr(c_set_wo_ready) when _T_729 : node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_731 = asUInt(reset) node _T_732 = eq(_T_731, UInt<1>(0h0)) when _T_732 : node _T_733 = eq(_T_730, UInt<1>(0h0)) when _T_733 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_730, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_23 node _T_734 = orr(inflight_1) node _T_735 = eq(_T_734, UInt<1>(0h0)) node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_737 = or(_T_735, _T_736) node _T_738 = lt(watchdog_1, plusarg_reader_1.out) node _T_739 = or(_T_737, _T_738) node _T_740 = asUInt(reset) node _T_741 = eq(_T_740, UInt<1>(0h0)) when _T_741 : node _T_742 = eq(_T_739, UInt<1>(0h0)) when _T_742 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/Ports.scala:112:9)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_739, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_744 = and(io.in.d.ready, io.in.d.valid) node _T_745 = or(_T_743, _T_744) when _T_745 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_11( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [130:0] _c_sizes_set_T_1 = 131'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [39:0] c_opcodes_set = 40'h0; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set = 40'h0; // @[Monitor.scala:741:34] wire [9:0] c_set = 10'h0; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready = 10'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire _T_672 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_672; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_672; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_745 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_745; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_745; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg denied; // @[Monitor.scala:543:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_2 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_598 = _T_672 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_598 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_5 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_613 = _T_745 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_613 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] wire [9:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_716 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_716 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_698 = _T_745 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_698 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_698 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_698 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OutputUnit : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_available : UInt<1>[3], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[3], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[3], out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} reg states : { `2` : { occupied : UInt<1>, c : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `1` : { occupied : UInt<1>, c : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}, `0` : { occupied : UInt<1>, c : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, clock connect io.channel_status[0].occupied, states.`0`.occupied connect io.channel_status[0].flow, states.`0`.flow connect io.channel_status[1].occupied, states.`1`.occupied connect io.channel_status[1].flow, states.`1`.flow connect io.channel_status[2].occupied, states.`2`.occupied connect io.channel_status[2].flow, states.`2`.flow connect io.out.flit, io.in node _T = bits(io.out.vc_free, 0, 0) when _T : node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(states.`0`.occupied, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf assert(clock, states.`0`.occupied, UInt<1>(0h1), "") : assert connect states.`0`.occupied, UInt<1>(0h0) node _T_4 = bits(io.out.vc_free, 1, 1) when _T_4 : node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : node _T_7 = eq(states.`1`.occupied, UInt<1>(0h0)) when _T_7 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_1 assert(clock, states.`1`.occupied, UInt<1>(0h1), "") : assert_1 connect states.`1`.occupied, UInt<1>(0h0) node _T_8 = bits(io.out.vc_free, 2, 2) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : node _T_11 = eq(states.`2`.occupied, UInt<1>(0h0)) when _T_11 : printf(clock, UInt<1>(0h1), "Assertion failed\n at OutputUnit.scala:75 assert(s.occupied)\n") : printf_2 assert(clock, states.`2`.occupied, UInt<1>(0h1), "") : assert_2 connect states.`2`.occupied, UInt<1>(0h0) when io.allocs[0].alloc : connect states.`0`.occupied, UInt<1>(0h1) connect states.`0`.flow, io.allocs[0].flow when io.allocs[1].alloc : connect states.`1`.occupied, UInt<1>(0h1) connect states.`1`.flow, io.allocs[1].flow when io.allocs[2].alloc : connect states.`2`.occupied, UInt<1>(0h1) connect states.`2`.flow, io.allocs[2].flow node _io_credit_available_0_T = neq(states.`0`.c, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_credit_available_1_T = neq(states.`1`.c, UInt<1>(0h0)) connect io.credit_available[1], _io_credit_available_1_T node _io_credit_available_2_T = neq(states.`2`.c, UInt<1>(0h0)) connect io.credit_available[2], _io_credit_available_2_T node free = bits(io.out.credit_return, 0, 0) node _states_0_c_T = add(states.`0`.c, free) node _states_0_c_T_1 = sub(_states_0_c_T, io.credit_alloc[0].alloc) node _states_0_c_T_2 = tail(_states_0_c_T_1, 1) connect states.`0`.c, _states_0_c_T_2 node free_1 = bits(io.out.credit_return, 1, 1) node _states_1_c_T = add(states.`1`.c, free_1) node _states_1_c_T_1 = sub(_states_1_c_T, io.credit_alloc[1].alloc) node _states_1_c_T_2 = tail(_states_1_c_T_1, 1) connect states.`1`.c, _states_1_c_T_2 node free_2 = bits(io.out.credit_return, 2, 2) node _states_2_c_T = add(states.`2`.c, free_2) node _states_2_c_T_1 = sub(_states_2_c_T, io.credit_alloc[2].alloc) node _states_2_c_T_2 = tail(_states_2_c_T_1, 1) connect states.`2`.c, _states_2_c_T_2 node _T_12 = asUInt(reset) when _T_12 : connect states.`0`.occupied, UInt<1>(0h0) connect states.`1`.occupied, UInt<1>(0h0) connect states.`2`.occupied, UInt<1>(0h0) connect states.`0`.c, UInt<2>(0h3) connect states.`1`.c, UInt<2>(0h3) connect states.`2`.c, UInt<2>(0h3)
module OutputUnit( // @[OutputUnit.scala:52:7] input clock, // @[OutputUnit.scala:52:7] input reset, // @[OutputUnit.scala:52:7] input io_in_0_valid, // @[OutputUnit.scala:58:14] input io_in_0_bits_head, // @[OutputUnit.scala:58:14] input io_in_0_bits_tail, // @[OutputUnit.scala:58:14] input [144:0] io_in_0_bits_payload, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] input [2:0] io_in_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] input [3:0] io_in_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] input [1:0] io_in_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] output io_credit_available_0, // @[OutputUnit.scala:58:14] output io_credit_available_1, // @[OutputUnit.scala:58:14] output io_credit_available_2, // @[OutputUnit.scala:58:14] output io_channel_status_0_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_1_occupied, // @[OutputUnit.scala:58:14] output io_channel_status_2_occupied, // @[OutputUnit.scala:58:14] input io_allocs_0_alloc, // @[OutputUnit.scala:58:14] input io_allocs_1_alloc, // @[OutputUnit.scala:58:14] input io_allocs_2_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_0_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_1_alloc, // @[OutputUnit.scala:58:14] input io_credit_alloc_2_alloc, // @[OutputUnit.scala:58:14] output io_out_flit_0_valid, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_head, // @[OutputUnit.scala:58:14] output io_out_flit_0_bits_tail, // @[OutputUnit.scala:58:14] output [144:0] io_out_flit_0_bits_payload, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_vnet_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_ingress_node, // @[OutputUnit.scala:58:14] output [2:0] io_out_flit_0_bits_flow_ingress_node_id, // @[OutputUnit.scala:58:14] output [3:0] io_out_flit_0_bits_flow_egress_node, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_flow_egress_node_id, // @[OutputUnit.scala:58:14] output [1:0] io_out_flit_0_bits_virt_channel_id, // @[OutputUnit.scala:58:14] input [2:0] io_out_credit_return, // @[OutputUnit.scala:58:14] input [2:0] io_out_vc_free // @[OutputUnit.scala:58:14] ); reg states_2_occupied; // @[OutputUnit.scala:66:19] reg [1:0] states_2_c; // @[OutputUnit.scala:66:19] reg states_1_occupied; // @[OutputUnit.scala:66:19] reg [1:0] states_1_c; // @[OutputUnit.scala:66:19] reg states_0_occupied; // @[OutputUnit.scala:66:19] reg [1:0] states_0_c; // @[OutputUnit.scala:66:19]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_175 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_311 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_175( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_311 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_464 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_464( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module PE_251 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_251( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_45 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>} node _reg_T = asAsyncReset(reset) regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0) when io.en : connect reg, io.d connect io.q, reg
module AsyncResetRegVec_w1_i0_45( // @[AsyncResetReg.scala:56:7] input clock, // @[AsyncResetReg.scala:56:7] input reset, // @[AsyncResetReg.scala:56:7] input io_d, // @[AsyncResetReg.scala:59:14] output io_q // @[AsyncResetReg.scala:59:14] ); wire io_d_0 = io_d; // @[AsyncResetReg.scala:56:7] wire _reg_T = reset; // @[AsyncResetReg.scala:61:29] wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14] wire io_q_0; // @[AsyncResetReg.scala:56:7] reg reg_0; // @[AsyncResetReg.scala:61:50] assign io_q_0 = reg_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge clock or posedge _reg_T) begin // @[AsyncResetReg.scala:56:7, :61:29] if (_reg_T) // @[AsyncResetReg.scala:56:7, :61:29] reg_0 <= 1'h0; // @[AsyncResetReg.scala:61:50] else // @[AsyncResetReg.scala:56:7] reg_0 <= io_d_0; // @[AsyncResetReg.scala:56:7, :61:50] always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i1_e8_s24_9 : output io : { flip signedIn : UInt<1>, flip in : UInt<1>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node _intAsRawFloat_sign_T = bits(io.in, 0, 0) node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) node _intAsRawFloat_extAbsIn_T = cat(UInt<2>(0h0), intAsRawFloat_absIn) node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 1, 0) node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<1>(0h0), UInt<1>(0h1)) node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 1, 1) wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<4>, sig : UInt<2>} connect intAsRawFloat.isNaN, UInt<1>(0h0) connect intAsRawFloat.isInf, UInt<1>(0h0) node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 0, 0) node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 connect intAsRawFloat.sign, intAsRawFloat_sign node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 0, 0) node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 connect intAsRawFloat.sig, intAsRawFloat_sig inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_9 connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module INToRecFN_i1_e8_s24_9(); // @[INToRecFN.scala:43:7] wire [1:0] _intAsRawFloat_absIn_T = 2'h3; // @[rawFloatFromIN.scala:52:31] wire [2:0] _intAsRawFloat_extAbsIn_T = 3'h1; // @[rawFloatFromIN.scala:53:44] wire [2:0] _intAsRawFloat_sig_T = 3'h2; // @[rawFloatFromIN.scala:56:22] wire [2:0] _intAsRawFloat_out_sExp_T_2 = 3'h4; // @[rawFloatFromIN.scala:64:33] wire [3:0] intAsRawFloat_sExp = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [3:0] _intAsRawFloat_out_sExp_T_3 = 4'h4; // @[rawFloatFromIN.scala:59:23, :64:72] wire [1:0] intAsRawFloat_extAbsIn = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [1:0] intAsRawFloat_sig = 2'h1; // @[rawFloatFromIN.scala:53:53, :59:23, :65:20] wire [4:0] io_exceptionFlags = 5'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [32:0] io_out = 33'h80000000; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15] wire io_in = 1'h1; // @[Mux.scala:50:70] wire io_detectTininess = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_sign_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_absIn_T_1 = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_absIn = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_adjustedNormDist_T = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_adjustedNormDist = 1'h1; // @[Mux.scala:50:70] wire intAsRawFloat_sig_0 = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_isZero_T = 1'h1; // @[Mux.scala:50:70] wire _intAsRawFloat_out_sExp_T = 1'h1; // @[Mux.scala:50:70] wire io_signedIn = 1'h0; // @[INToRecFN.scala:43:7] wire intAsRawFloat_sign = 1'h0; // @[rawFloatFromIN.scala:51:29] wire _intAsRawFloat_adjustedNormDist_T_1 = 1'h0; // @[primitives.scala:91:52] wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_isZero = 1'h0; // @[rawFloatFromIN.scala:59:23] wire intAsRawFloat_sign_0 = 1'h0; // @[rawFloatFromIN.scala:59:23] wire _intAsRawFloat_out_isZero_T_1 = 1'h0; // @[rawFloatFromIN.scala:62:23] wire _intAsRawFloat_out_sExp_T_1 = 1'h0; // @[rawFloatFromIN.scala:64:36] RoundAnyRawFNToRecFN_ie2_is1_oe8_os24_9 roundAnyRawFNToRecFN (); // @[INToRecFN.scala:60:15] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_108 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_184 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_108( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_184 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a26d64s12k1z2u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_23 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue1_TLBundleA_a26d64s12k1z2u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue1_TLBundleD_a26d64s12k1z2u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<26>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<26>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<26>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<26>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) extmodule plusarg_reader_48 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_49 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLBuffer_a26d64s12k1z2u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [25:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [25:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9] wire [25:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9] wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9] wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9] wire [11:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9] wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_sink = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_denied = 1'h0; // @[Decoupled.scala:362:21] wire nodeOut_d_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire [1:0] auto_out_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [1:0] nodeOut_d_bits_param = 2'h0; // @[Decoupled.scala:362:21] wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [11:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [25:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9] wire [11:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9] wire [11:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9] wire [11:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9] wire [25:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] TLMonitor_23 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue1_TLBundleA_a26d64s12k1z2u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue1_TLBundleD_a26d64s12k1z2u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_9 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_18 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_19 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tilelink/BusWrapper.scala:109:33)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_20 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_21 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_9( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1135 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1135; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1135; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1184 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_288 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_288( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_189 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<20>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_189( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [19:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [19:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_3; // @[Arithmetic.scala:93:54] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [20:0] _io_out_d_T_1 = {{5{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[19], io_in_c_0}; // @[PE.scala:14:7] wire [19:0] _io_out_d_T_2 = _io_out_d_T_1[19:0]; // @[Arithmetic.scala:93:54] assign _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3; // @[PE.scala:14:7] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) wire _source_ok_WIRE : UInt<1>[5] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 node _source_ok_T_25 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_26 = or(_source_ok_T_25, _source_ok_WIRE[2]) node _source_ok_T_27 = or(_source_ok_T_26, _source_ok_WIRE[3]) node source_ok = or(_source_ok_T_27, _source_ok_WIRE[4]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = and(_T_11, _T_24) node _T_65 = and(_T_64, _T_37) node _T_66 = and(_T_65, _T_50) node _T_67 = and(_T_66, _T_63) node _T_68 = asUInt(reset) node _T_69 = eq(_T_68, UInt<1>(0h0)) when _T_69 : node _T_70 = eq(_T_67, UInt<1>(0h0)) when _T_70 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_67, UInt<1>(0h1), "") : assert_1 node _T_71 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_71 : node _T_72 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_73 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_74 = and(_T_72, _T_73) node _T_75 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_76 = shr(io.in.a.bits.source, 2) node _T_77 = eq(_T_76, UInt<1>(0h0)) node _T_78 = leq(UInt<1>(0h0), uncommonBits_4) node _T_79 = and(_T_77, _T_78) node _T_80 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_81 = and(_T_79, _T_80) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_82 = shr(io.in.a.bits.source, 2) node _T_83 = eq(_T_82, UInt<1>(0h1)) node _T_84 = leq(UInt<1>(0h0), uncommonBits_5) node _T_85 = and(_T_83, _T_84) node _T_86 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_87 = and(_T_85, _T_86) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_88 = shr(io.in.a.bits.source, 2) node _T_89 = eq(_T_88, UInt<2>(0h2)) node _T_90 = leq(UInt<1>(0h0), uncommonBits_6) node _T_91 = and(_T_89, _T_90) node _T_92 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_93 = and(_T_91, _T_92) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_94 = shr(io.in.a.bits.source, 2) node _T_95 = eq(_T_94, UInt<2>(0h3)) node _T_96 = leq(UInt<1>(0h0), uncommonBits_7) node _T_97 = and(_T_95, _T_96) node _T_98 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_99 = and(_T_97, _T_98) node _T_100 = or(_T_75, _T_81) node _T_101 = or(_T_100, _T_87) node _T_102 = or(_T_101, _T_93) node _T_103 = or(_T_102, _T_99) node _T_104 = and(_T_74, _T_103) node _T_105 = or(UInt<1>(0h0), _T_104) node _T_106 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<13>(0h1000))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<17>(0h10000))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<18>(0h2f000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<13>(0h1000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<27>(0h4000000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = or(_T_111, _T_116) node _T_148 = or(_T_147, _T_121) node _T_149 = or(_T_148, _T_126) node _T_150 = or(_T_149, _T_131) node _T_151 = or(_T_150, _T_136) node _T_152 = or(_T_151, _T_141) node _T_153 = or(_T_152, _T_146) node _T_154 = and(_T_106, _T_153) node _T_155 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_156 = or(UInt<1>(0h0), _T_155) node _T_157 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<17>(0h10000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = and(_T_156, _T_167) node _T_169 = or(UInt<1>(0h0), _T_154) node _T_170 = or(_T_169, _T_168) node _T_171 = and(_T_105, _T_170) node _T_172 = asUInt(reset) node _T_173 = eq(_T_172, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(_T_171, UInt<1>(0h0)) when _T_174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_171, UInt<1>(0h1), "") : assert_2 node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_177 = and(_T_175, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_180 = cvt(_T_179) node _T_181 = and(_T_180, asSInt(UInt<14>(0h2000))) node _T_182 = asSInt(_T_181) node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0))) node _T_184 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_185 = cvt(_T_184) node _T_186 = and(_T_185, asSInt(UInt<13>(0h1000))) node _T_187 = asSInt(_T_186) node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_190 = cvt(_T_189) node _T_191 = and(_T_190, asSInt(UInt<17>(0h10000))) node _T_192 = asSInt(_T_191) node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0))) node _T_194 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<18>(0h2f000))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<13>(0h1000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_210 = cvt(_T_209) node _T_211 = and(_T_210, asSInt(UInt<17>(0h10000))) node _T_212 = asSInt(_T_211) node _T_213 = eq(_T_212, asSInt(UInt<1>(0h0))) node _T_214 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_215 = cvt(_T_214) node _T_216 = and(_T_215, asSInt(UInt<27>(0h4000000))) node _T_217 = asSInt(_T_216) node _T_218 = eq(_T_217, asSInt(UInt<1>(0h0))) node _T_219 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_220 = cvt(_T_219) node _T_221 = and(_T_220, asSInt(UInt<13>(0h1000))) node _T_222 = asSInt(_T_221) node _T_223 = eq(_T_222, asSInt(UInt<1>(0h0))) node _T_224 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_225 = cvt(_T_224) node _T_226 = and(_T_225, asSInt(UInt<29>(0h10000000))) node _T_227 = asSInt(_T_226) node _T_228 = eq(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = or(_T_183, _T_188) node _T_230 = or(_T_229, _T_193) node _T_231 = or(_T_230, _T_198) node _T_232 = or(_T_231, _T_203) node _T_233 = or(_T_232, _T_208) node _T_234 = or(_T_233, _T_213) node _T_235 = or(_T_234, _T_218) node _T_236 = or(_T_235, _T_223) node _T_237 = or(_T_236, _T_228) node _T_238 = and(_T_178, _T_237) node _T_239 = or(UInt<1>(0h0), _T_238) node _T_240 = and(UInt<1>(0h0), _T_239) node _T_241 = asUInt(reset) node _T_242 = eq(_T_241, UInt<1>(0h0)) when _T_242 : node _T_243 = eq(_T_240, UInt<1>(0h0)) when _T_243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_240, UInt<1>(0h1), "") : assert_3 node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(source_ok, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_247 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_248 = asUInt(reset) node _T_249 = eq(_T_248, UInt<1>(0h0)) when _T_249 : node _T_250 = eq(_T_247, UInt<1>(0h0)) when _T_250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_247, UInt<1>(0h1), "") : assert_5 node _T_251 = asUInt(reset) node _T_252 = eq(_T_251, UInt<1>(0h0)) when _T_252 : node _T_253 = eq(is_aligned, UInt<1>(0h0)) when _T_253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_254 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_254, UInt<1>(0h1), "") : assert_7 node _T_258 = not(io.in.a.bits.mask) node _T_259 = eq(_T_258, UInt<1>(0h0)) node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(_T_259, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_259, UInt<1>(0h1), "") : assert_8 node _T_263 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_263, UInt<1>(0h1), "") : assert_9 node _T_267 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_267 : node _T_268 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_269 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h0)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_8) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<1>(0h1)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_9) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h2)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_10) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_290 = shr(io.in.a.bits.source, 2) node _T_291 = eq(_T_290, UInt<2>(0h3)) node _T_292 = leq(UInt<1>(0h0), uncommonBits_11) node _T_293 = and(_T_291, _T_292) node _T_294 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_295 = and(_T_293, _T_294) node _T_296 = or(_T_271, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_295) node _T_300 = and(_T_270, _T_299) node _T_301 = or(UInt<1>(0h0), _T_300) node _T_302 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_303 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<14>(0h2000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<13>(0h1000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<17>(0h10000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<18>(0h2f000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<13>(0h1000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<27>(0h4000000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = or(_T_307, _T_312) node _T_344 = or(_T_343, _T_317) node _T_345 = or(_T_344, _T_322) node _T_346 = or(_T_345, _T_327) node _T_347 = or(_T_346, _T_332) node _T_348 = or(_T_347, _T_337) node _T_349 = or(_T_348, _T_342) node _T_350 = and(_T_302, _T_349) node _T_351 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_352 = or(UInt<1>(0h0), _T_351) node _T_353 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_354 = cvt(_T_353) node _T_355 = and(_T_354, asSInt(UInt<17>(0h10000))) node _T_356 = asSInt(_T_355) node _T_357 = eq(_T_356, asSInt(UInt<1>(0h0))) node _T_358 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_359 = cvt(_T_358) node _T_360 = and(_T_359, asSInt(UInt<29>(0h10000000))) node _T_361 = asSInt(_T_360) node _T_362 = eq(_T_361, asSInt(UInt<1>(0h0))) node _T_363 = or(_T_357, _T_362) node _T_364 = and(_T_352, _T_363) node _T_365 = or(UInt<1>(0h0), _T_350) node _T_366 = or(_T_365, _T_364) node _T_367 = and(_T_301, _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_367, UInt<1>(0h1), "") : assert_10 node _T_371 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_372 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_373 = and(_T_371, _T_372) node _T_374 = or(UInt<1>(0h0), _T_373) node _T_375 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_376 = cvt(_T_375) node _T_377 = and(_T_376, asSInt(UInt<14>(0h2000))) node _T_378 = asSInt(_T_377) node _T_379 = eq(_T_378, asSInt(UInt<1>(0h0))) node _T_380 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_381 = cvt(_T_380) node _T_382 = and(_T_381, asSInt(UInt<13>(0h1000))) node _T_383 = asSInt(_T_382) node _T_384 = eq(_T_383, asSInt(UInt<1>(0h0))) node _T_385 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_386 = cvt(_T_385) node _T_387 = and(_T_386, asSInt(UInt<17>(0h10000))) node _T_388 = asSInt(_T_387) node _T_389 = eq(_T_388, asSInt(UInt<1>(0h0))) node _T_390 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_391 = cvt(_T_390) node _T_392 = and(_T_391, asSInt(UInt<18>(0h2f000))) node _T_393 = asSInt(_T_392) node _T_394 = eq(_T_393, asSInt(UInt<1>(0h0))) node _T_395 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_396 = cvt(_T_395) node _T_397 = and(_T_396, asSInt(UInt<17>(0h10000))) node _T_398 = asSInt(_T_397) node _T_399 = eq(_T_398, asSInt(UInt<1>(0h0))) node _T_400 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_401 = cvt(_T_400) node _T_402 = and(_T_401, asSInt(UInt<13>(0h1000))) node _T_403 = asSInt(_T_402) node _T_404 = eq(_T_403, asSInt(UInt<1>(0h0))) node _T_405 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_406 = cvt(_T_405) node _T_407 = and(_T_406, asSInt(UInt<17>(0h10000))) node _T_408 = asSInt(_T_407) node _T_409 = eq(_T_408, asSInt(UInt<1>(0h0))) node _T_410 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_411 = cvt(_T_410) node _T_412 = and(_T_411, asSInt(UInt<27>(0h4000000))) node _T_413 = asSInt(_T_412) node _T_414 = eq(_T_413, asSInt(UInt<1>(0h0))) node _T_415 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_416 = cvt(_T_415) node _T_417 = and(_T_416, asSInt(UInt<13>(0h1000))) node _T_418 = asSInt(_T_417) node _T_419 = eq(_T_418, asSInt(UInt<1>(0h0))) node _T_420 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_421 = cvt(_T_420) node _T_422 = and(_T_421, asSInt(UInt<29>(0h10000000))) node _T_423 = asSInt(_T_422) node _T_424 = eq(_T_423, asSInt(UInt<1>(0h0))) node _T_425 = or(_T_379, _T_384) node _T_426 = or(_T_425, _T_389) node _T_427 = or(_T_426, _T_394) node _T_428 = or(_T_427, _T_399) node _T_429 = or(_T_428, _T_404) node _T_430 = or(_T_429, _T_409) node _T_431 = or(_T_430, _T_414) node _T_432 = or(_T_431, _T_419) node _T_433 = or(_T_432, _T_424) node _T_434 = and(_T_374, _T_433) node _T_435 = or(UInt<1>(0h0), _T_434) node _T_436 = and(UInt<1>(0h0), _T_435) node _T_437 = asUInt(reset) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(_T_436, UInt<1>(0h0)) when _T_439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_436, UInt<1>(0h1), "") : assert_11 node _T_440 = asUInt(reset) node _T_441 = eq(_T_440, UInt<1>(0h0)) when _T_441 : node _T_442 = eq(source_ok, UInt<1>(0h0)) when _T_442 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_443 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_443, UInt<1>(0h1), "") : assert_13 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(is_aligned, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_450 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_450, UInt<1>(0h1), "") : assert_15 node _T_454 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_454, UInt<1>(0h1), "") : assert_16 node _T_458 = not(io.in.a.bits.mask) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_459, UInt<1>(0h1), "") : assert_17 node _T_463 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_463, UInt<1>(0h1), "") : assert_18 node _T_467 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_467 : node _T_468 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_469 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_470 = and(_T_468, _T_469) node _T_471 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_472 = shr(io.in.a.bits.source, 2) node _T_473 = eq(_T_472, UInt<1>(0h0)) node _T_474 = leq(UInt<1>(0h0), uncommonBits_12) node _T_475 = and(_T_473, _T_474) node _T_476 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_477 = and(_T_475, _T_476) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_478 = shr(io.in.a.bits.source, 2) node _T_479 = eq(_T_478, UInt<1>(0h1)) node _T_480 = leq(UInt<1>(0h0), uncommonBits_13) node _T_481 = and(_T_479, _T_480) node _T_482 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_483 = and(_T_481, _T_482) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_484 = shr(io.in.a.bits.source, 2) node _T_485 = eq(_T_484, UInt<2>(0h2)) node _T_486 = leq(UInt<1>(0h0), uncommonBits_14) node _T_487 = and(_T_485, _T_486) node _T_488 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_489 = and(_T_487, _T_488) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_490 = shr(io.in.a.bits.source, 2) node _T_491 = eq(_T_490, UInt<2>(0h3)) node _T_492 = leq(UInt<1>(0h0), uncommonBits_15) node _T_493 = and(_T_491, _T_492) node _T_494 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_495 = and(_T_493, _T_494) node _T_496 = or(_T_471, _T_477) node _T_497 = or(_T_496, _T_483) node _T_498 = or(_T_497, _T_489) node _T_499 = or(_T_498, _T_495) node _T_500 = and(_T_470, _T_499) node _T_501 = or(UInt<1>(0h0), _T_500) node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_T_501, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_501, UInt<1>(0h1), "") : assert_19 node _T_505 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_506 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_507 = and(_T_505, _T_506) node _T_508 = or(UInt<1>(0h0), _T_507) node _T_509 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<13>(0h1000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = and(_T_508, _T_513) node _T_515 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_516 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_517 = and(_T_515, _T_516) node _T_518 = or(UInt<1>(0h0), _T_517) node _T_519 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<14>(0h2000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<17>(0h10000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<18>(0h2f000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<17>(0h10000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<17>(0h10000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<27>(0h4000000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<13>(0h1000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<29>(0h10000000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = or(_T_523, _T_528) node _T_565 = or(_T_564, _T_533) node _T_566 = or(_T_565, _T_538) node _T_567 = or(_T_566, _T_543) node _T_568 = or(_T_567, _T_548) node _T_569 = or(_T_568, _T_553) node _T_570 = or(_T_569, _T_558) node _T_571 = or(_T_570, _T_563) node _T_572 = and(_T_518, _T_571) node _T_573 = or(UInt<1>(0h0), _T_514) node _T_574 = or(_T_573, _T_572) node _T_575 = asUInt(reset) node _T_576 = eq(_T_575, UInt<1>(0h0)) when _T_576 : node _T_577 = eq(_T_574, UInt<1>(0h0)) when _T_577 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_574, UInt<1>(0h1), "") : assert_20 node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(source_ok, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_581 = asUInt(reset) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(is_aligned, UInt<1>(0h0)) when _T_583 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_584 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(_T_584, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_584, UInt<1>(0h1), "") : assert_23 node _T_588 = eq(io.in.a.bits.mask, mask) node _T_589 = asUInt(reset) node _T_590 = eq(_T_589, UInt<1>(0h0)) when _T_590 : node _T_591 = eq(_T_588, UInt<1>(0h0)) when _T_591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_588, UInt<1>(0h1), "") : assert_24 node _T_592 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_593 = asUInt(reset) node _T_594 = eq(_T_593, UInt<1>(0h0)) when _T_594 : node _T_595 = eq(_T_592, UInt<1>(0h0)) when _T_595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_592, UInt<1>(0h1), "") : assert_25 node _T_596 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_596 : node _T_597 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_598 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_599 = and(_T_597, _T_598) node _T_600 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_601 = shr(io.in.a.bits.source, 2) node _T_602 = eq(_T_601, UInt<1>(0h0)) node _T_603 = leq(UInt<1>(0h0), uncommonBits_16) node _T_604 = and(_T_602, _T_603) node _T_605 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_606 = and(_T_604, _T_605) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_607 = shr(io.in.a.bits.source, 2) node _T_608 = eq(_T_607, UInt<1>(0h1)) node _T_609 = leq(UInt<1>(0h0), uncommonBits_17) node _T_610 = and(_T_608, _T_609) node _T_611 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_612 = and(_T_610, _T_611) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_613 = shr(io.in.a.bits.source, 2) node _T_614 = eq(_T_613, UInt<2>(0h2)) node _T_615 = leq(UInt<1>(0h0), uncommonBits_18) node _T_616 = and(_T_614, _T_615) node _T_617 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_618 = and(_T_616, _T_617) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_619 = shr(io.in.a.bits.source, 2) node _T_620 = eq(_T_619, UInt<2>(0h3)) node _T_621 = leq(UInt<1>(0h0), uncommonBits_19) node _T_622 = and(_T_620, _T_621) node _T_623 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_624 = and(_T_622, _T_623) node _T_625 = or(_T_600, _T_606) node _T_626 = or(_T_625, _T_612) node _T_627 = or(_T_626, _T_618) node _T_628 = or(_T_627, _T_624) node _T_629 = and(_T_599, _T_628) node _T_630 = or(UInt<1>(0h0), _T_629) node _T_631 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_632 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_633 = and(_T_631, _T_632) node _T_634 = or(UInt<1>(0h0), _T_633) node _T_635 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<13>(0h1000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = and(_T_634, _T_639) node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_643 = and(_T_641, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<14>(0h2000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<18>(0h2f000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<17>(0h10000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_661 = cvt(_T_660) node _T_662 = and(_T_661, asSInt(UInt<13>(0h1000))) node _T_663 = asSInt(_T_662) node _T_664 = eq(_T_663, asSInt(UInt<1>(0h0))) node _T_665 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_666 = cvt(_T_665) node _T_667 = and(_T_666, asSInt(UInt<17>(0h10000))) node _T_668 = asSInt(_T_667) node _T_669 = eq(_T_668, asSInt(UInt<1>(0h0))) node _T_670 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_671 = cvt(_T_670) node _T_672 = and(_T_671, asSInt(UInt<27>(0h4000000))) node _T_673 = asSInt(_T_672) node _T_674 = eq(_T_673, asSInt(UInt<1>(0h0))) node _T_675 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_676 = cvt(_T_675) node _T_677 = and(_T_676, asSInt(UInt<13>(0h1000))) node _T_678 = asSInt(_T_677) node _T_679 = eq(_T_678, asSInt(UInt<1>(0h0))) node _T_680 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_681 = cvt(_T_680) node _T_682 = and(_T_681, asSInt(UInt<29>(0h10000000))) node _T_683 = asSInt(_T_682) node _T_684 = eq(_T_683, asSInt(UInt<1>(0h0))) node _T_685 = or(_T_649, _T_654) node _T_686 = or(_T_685, _T_659) node _T_687 = or(_T_686, _T_664) node _T_688 = or(_T_687, _T_669) node _T_689 = or(_T_688, _T_674) node _T_690 = or(_T_689, _T_679) node _T_691 = or(_T_690, _T_684) node _T_692 = and(_T_644, _T_691) node _T_693 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_694 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_695 = cvt(_T_694) node _T_696 = and(_T_695, asSInt(UInt<17>(0h10000))) node _T_697 = asSInt(_T_696) node _T_698 = eq(_T_697, asSInt(UInt<1>(0h0))) node _T_699 = and(_T_693, _T_698) node _T_700 = or(UInt<1>(0h0), _T_640) node _T_701 = or(_T_700, _T_692) node _T_702 = or(_T_701, _T_699) node _T_703 = and(_T_630, _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_703, UInt<1>(0h1), "") : assert_26 node _T_707 = asUInt(reset) node _T_708 = eq(_T_707, UInt<1>(0h0)) when _T_708 : node _T_709 = eq(source_ok, UInt<1>(0h0)) when _T_709 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_710 = asUInt(reset) node _T_711 = eq(_T_710, UInt<1>(0h0)) when _T_711 : node _T_712 = eq(is_aligned, UInt<1>(0h0)) when _T_712 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_713 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_714 = asUInt(reset) node _T_715 = eq(_T_714, UInt<1>(0h0)) when _T_715 : node _T_716 = eq(_T_713, UInt<1>(0h0)) when _T_716 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_713, UInt<1>(0h1), "") : assert_29 node _T_717 = eq(io.in.a.bits.mask, mask) node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(_T_717, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_717, UInt<1>(0h1), "") : assert_30 node _T_721 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_721 : node _T_722 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_723 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_724 = and(_T_722, _T_723) node _T_725 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_20) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_732 = shr(io.in.a.bits.source, 2) node _T_733 = eq(_T_732, UInt<1>(0h1)) node _T_734 = leq(UInt<1>(0h0), uncommonBits_21) node _T_735 = and(_T_733, _T_734) node _T_736 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_737 = and(_T_735, _T_736) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_738 = shr(io.in.a.bits.source, 2) node _T_739 = eq(_T_738, UInt<2>(0h2)) node _T_740 = leq(UInt<1>(0h0), uncommonBits_22) node _T_741 = and(_T_739, _T_740) node _T_742 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_743 = and(_T_741, _T_742) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_744 = shr(io.in.a.bits.source, 2) node _T_745 = eq(_T_744, UInt<2>(0h3)) node _T_746 = leq(UInt<1>(0h0), uncommonBits_23) node _T_747 = and(_T_745, _T_746) node _T_748 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(_T_725, _T_731) node _T_751 = or(_T_750, _T_737) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_749) node _T_754 = and(_T_724, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = and(_T_759, _T_764) node _T_766 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_767 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_768 = and(_T_766, _T_767) node _T_769 = or(UInt<1>(0h0), _T_768) node _T_770 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<14>(0h2000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<18>(0h2f000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<13>(0h1000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<27>(0h4000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<13>(0h1000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_806 = cvt(_T_805) node _T_807 = and(_T_806, asSInt(UInt<29>(0h10000000))) node _T_808 = asSInt(_T_807) node _T_809 = eq(_T_808, asSInt(UInt<1>(0h0))) node _T_810 = or(_T_774, _T_779) node _T_811 = or(_T_810, _T_784) node _T_812 = or(_T_811, _T_789) node _T_813 = or(_T_812, _T_794) node _T_814 = or(_T_813, _T_799) node _T_815 = or(_T_814, _T_804) node _T_816 = or(_T_815, _T_809) node _T_817 = and(_T_769, _T_816) node _T_818 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_819 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = and(_T_818, _T_823) node _T_825 = or(UInt<1>(0h0), _T_765) node _T_826 = or(_T_825, _T_817) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_828, UInt<1>(0h1), "") : assert_31 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(source_ok, UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_838 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_838, UInt<1>(0h1), "") : assert_34 node _T_842 = not(mask) node _T_843 = and(io.in.a.bits.mask, _T_842) node _T_844 = eq(_T_843, UInt<1>(0h0)) node _T_845 = asUInt(reset) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(_T_844, UInt<1>(0h0)) when _T_847 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_844, UInt<1>(0h1), "") : assert_35 node _T_848 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_848 : node _T_849 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_850 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_851 = and(_T_849, _T_850) node _T_852 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_853 = shr(io.in.a.bits.source, 2) node _T_854 = eq(_T_853, UInt<1>(0h0)) node _T_855 = leq(UInt<1>(0h0), uncommonBits_24) node _T_856 = and(_T_854, _T_855) node _T_857 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_858 = and(_T_856, _T_857) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_859 = shr(io.in.a.bits.source, 2) node _T_860 = eq(_T_859, UInt<1>(0h1)) node _T_861 = leq(UInt<1>(0h0), uncommonBits_25) node _T_862 = and(_T_860, _T_861) node _T_863 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_865 = shr(io.in.a.bits.source, 2) node _T_866 = eq(_T_865, UInt<2>(0h2)) node _T_867 = leq(UInt<1>(0h0), uncommonBits_26) node _T_868 = and(_T_866, _T_867) node _T_869 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_870 = and(_T_868, _T_869) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_871 = shr(io.in.a.bits.source, 2) node _T_872 = eq(_T_871, UInt<2>(0h3)) node _T_873 = leq(UInt<1>(0h0), uncommonBits_27) node _T_874 = and(_T_872, _T_873) node _T_875 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_876 = and(_T_874, _T_875) node _T_877 = or(_T_852, _T_858) node _T_878 = or(_T_877, _T_864) node _T_879 = or(_T_878, _T_870) node _T_880 = or(_T_879, _T_876) node _T_881 = and(_T_851, _T_880) node _T_882 = or(UInt<1>(0h0), _T_881) node _T_883 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_884 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_885 = and(_T_883, _T_884) node _T_886 = or(UInt<1>(0h0), _T_885) node _T_887 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_888 = cvt(_T_887) node _T_889 = and(_T_888, asSInt(UInt<14>(0h2000))) node _T_890 = asSInt(_T_889) node _T_891 = eq(_T_890, asSInt(UInt<1>(0h0))) node _T_892 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_893 = cvt(_T_892) node _T_894 = and(_T_893, asSInt(UInt<13>(0h1000))) node _T_895 = asSInt(_T_894) node _T_896 = eq(_T_895, asSInt(UInt<1>(0h0))) node _T_897 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_898 = cvt(_T_897) node _T_899 = and(_T_898, asSInt(UInt<18>(0h2f000))) node _T_900 = asSInt(_T_899) node _T_901 = eq(_T_900, asSInt(UInt<1>(0h0))) node _T_902 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_903 = cvt(_T_902) node _T_904 = and(_T_903, asSInt(UInt<17>(0h10000))) node _T_905 = asSInt(_T_904) node _T_906 = eq(_T_905, asSInt(UInt<1>(0h0))) node _T_907 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_908 = cvt(_T_907) node _T_909 = and(_T_908, asSInt(UInt<13>(0h1000))) node _T_910 = asSInt(_T_909) node _T_911 = eq(_T_910, asSInt(UInt<1>(0h0))) node _T_912 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_913 = cvt(_T_912) node _T_914 = and(_T_913, asSInt(UInt<27>(0h4000000))) node _T_915 = asSInt(_T_914) node _T_916 = eq(_T_915, asSInt(UInt<1>(0h0))) node _T_917 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_918 = cvt(_T_917) node _T_919 = and(_T_918, asSInt(UInt<13>(0h1000))) node _T_920 = asSInt(_T_919) node _T_921 = eq(_T_920, asSInt(UInt<1>(0h0))) node _T_922 = or(_T_891, _T_896) node _T_923 = or(_T_922, _T_901) node _T_924 = or(_T_923, _T_906) node _T_925 = or(_T_924, _T_911) node _T_926 = or(_T_925, _T_916) node _T_927 = or(_T_926, _T_921) node _T_928 = and(_T_886, _T_927) node _T_929 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_930 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_931 = cvt(_T_930) node _T_932 = and(_T_931, asSInt(UInt<17>(0h10000))) node _T_933 = asSInt(_T_932) node _T_934 = eq(_T_933, asSInt(UInt<1>(0h0))) node _T_935 = and(_T_929, _T_934) node _T_936 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_937 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_938 = and(_T_936, _T_937) node _T_939 = or(UInt<1>(0h0), _T_938) node _T_940 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_941 = cvt(_T_940) node _T_942 = and(_T_941, asSInt(UInt<17>(0h10000))) node _T_943 = asSInt(_T_942) node _T_944 = eq(_T_943, asSInt(UInt<1>(0h0))) node _T_945 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_946 = cvt(_T_945) node _T_947 = and(_T_946, asSInt(UInt<29>(0h10000000))) node _T_948 = asSInt(_T_947) node _T_949 = eq(_T_948, asSInt(UInt<1>(0h0))) node _T_950 = or(_T_944, _T_949) node _T_951 = and(_T_939, _T_950) node _T_952 = or(UInt<1>(0h0), _T_928) node _T_953 = or(_T_952, _T_935) node _T_954 = or(_T_953, _T_951) node _T_955 = and(_T_882, _T_954) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_955, UInt<1>(0h1), "") : assert_36 node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(source_ok, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(is_aligned, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_965 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_965, UInt<1>(0h1), "") : assert_39 node _T_969 = eq(io.in.a.bits.mask, mask) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_969, UInt<1>(0h1), "") : assert_40 node _T_973 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_973 : node _T_974 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_975 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_976 = and(_T_974, _T_975) node _T_977 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_978 = shr(io.in.a.bits.source, 2) node _T_979 = eq(_T_978, UInt<1>(0h0)) node _T_980 = leq(UInt<1>(0h0), uncommonBits_28) node _T_981 = and(_T_979, _T_980) node _T_982 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_983 = and(_T_981, _T_982) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_984 = shr(io.in.a.bits.source, 2) node _T_985 = eq(_T_984, UInt<1>(0h1)) node _T_986 = leq(UInt<1>(0h0), uncommonBits_29) node _T_987 = and(_T_985, _T_986) node _T_988 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_989 = and(_T_987, _T_988) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_990 = shr(io.in.a.bits.source, 2) node _T_991 = eq(_T_990, UInt<2>(0h2)) node _T_992 = leq(UInt<1>(0h0), uncommonBits_30) node _T_993 = and(_T_991, _T_992) node _T_994 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_995 = and(_T_993, _T_994) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_996 = shr(io.in.a.bits.source, 2) node _T_997 = eq(_T_996, UInt<2>(0h3)) node _T_998 = leq(UInt<1>(0h0), uncommonBits_31) node _T_999 = and(_T_997, _T_998) node _T_1000 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1001 = and(_T_999, _T_1000) node _T_1002 = or(_T_977, _T_983) node _T_1003 = or(_T_1002, _T_989) node _T_1004 = or(_T_1003, _T_995) node _T_1005 = or(_T_1004, _T_1001) node _T_1006 = and(_T_976, _T_1005) node _T_1007 = or(UInt<1>(0h0), _T_1006) node _T_1008 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1009 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1010 = and(_T_1008, _T_1009) node _T_1011 = or(UInt<1>(0h0), _T_1010) node _T_1012 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<14>(0h2000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1023 = cvt(_T_1022) node _T_1024 = and(_T_1023, asSInt(UInt<18>(0h2f000))) node _T_1025 = asSInt(_T_1024) node _T_1026 = eq(_T_1025, asSInt(UInt<1>(0h0))) node _T_1027 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1028 = cvt(_T_1027) node _T_1029 = and(_T_1028, asSInt(UInt<17>(0h10000))) node _T_1030 = asSInt(_T_1029) node _T_1031 = eq(_T_1030, asSInt(UInt<1>(0h0))) node _T_1032 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<13>(0h1000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1038 = cvt(_T_1037) node _T_1039 = and(_T_1038, asSInt(UInt<27>(0h4000000))) node _T_1040 = asSInt(_T_1039) node _T_1041 = eq(_T_1040, asSInt(UInt<1>(0h0))) node _T_1042 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<13>(0h1000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = or(_T_1016, _T_1021) node _T_1048 = or(_T_1047, _T_1026) node _T_1049 = or(_T_1048, _T_1031) node _T_1050 = or(_T_1049, _T_1036) node _T_1051 = or(_T_1050, _T_1041) node _T_1052 = or(_T_1051, _T_1046) node _T_1053 = and(_T_1011, _T_1052) node _T_1054 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1055 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1056 = cvt(_T_1055) node _T_1057 = and(_T_1056, asSInt(UInt<17>(0h10000))) node _T_1058 = asSInt(_T_1057) node _T_1059 = eq(_T_1058, asSInt(UInt<1>(0h0))) node _T_1060 = and(_T_1054, _T_1059) node _T_1061 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1062 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_1063 = and(_T_1061, _T_1062) node _T_1064 = or(UInt<1>(0h0), _T_1063) node _T_1065 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1066 = cvt(_T_1065) node _T_1067 = and(_T_1066, asSInt(UInt<17>(0h10000))) node _T_1068 = asSInt(_T_1067) node _T_1069 = eq(_T_1068, asSInt(UInt<1>(0h0))) node _T_1070 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1071 = cvt(_T_1070) node _T_1072 = and(_T_1071, asSInt(UInt<29>(0h10000000))) node _T_1073 = asSInt(_T_1072) node _T_1074 = eq(_T_1073, asSInt(UInt<1>(0h0))) node _T_1075 = or(_T_1069, _T_1074) node _T_1076 = and(_T_1064, _T_1075) node _T_1077 = or(UInt<1>(0h0), _T_1053) node _T_1078 = or(_T_1077, _T_1060) node _T_1079 = or(_T_1078, _T_1076) node _T_1080 = and(_T_1007, _T_1079) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_41 node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(source_ok, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(is_aligned, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1090 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_44 node _T_1094 = eq(io.in.a.bits.mask, mask) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_45 node _T_1098 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1098 : node _T_1099 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1101 = and(_T_1099, _T_1100) node _T_1102 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1103 = shr(io.in.a.bits.source, 2) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) node _T_1105 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1106 = and(_T_1104, _T_1105) node _T_1107 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1108 = and(_T_1106, _T_1107) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1109 = shr(io.in.a.bits.source, 2) node _T_1110 = eq(_T_1109, UInt<1>(0h1)) node _T_1111 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1112 = and(_T_1110, _T_1111) node _T_1113 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1114 = and(_T_1112, _T_1113) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1115 = shr(io.in.a.bits.source, 2) node _T_1116 = eq(_T_1115, UInt<2>(0h2)) node _T_1117 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1118 = and(_T_1116, _T_1117) node _T_1119 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1120 = and(_T_1118, _T_1119) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1121 = shr(io.in.a.bits.source, 2) node _T_1122 = eq(_T_1121, UInt<2>(0h3)) node _T_1123 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1124 = and(_T_1122, _T_1123) node _T_1125 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1126 = and(_T_1124, _T_1125) node _T_1127 = or(_T_1102, _T_1108) node _T_1128 = or(_T_1127, _T_1114) node _T_1129 = or(_T_1128, _T_1120) node _T_1130 = or(_T_1129, _T_1126) node _T_1131 = and(_T_1101, _T_1130) node _T_1132 = or(UInt<1>(0h0), _T_1131) node _T_1133 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1134 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1135 = and(_T_1133, _T_1134) node _T_1136 = or(UInt<1>(0h0), _T_1135) node _T_1137 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1138 = cvt(_T_1137) node _T_1139 = and(_T_1138, asSInt(UInt<13>(0h1000))) node _T_1140 = asSInt(_T_1139) node _T_1141 = eq(_T_1140, asSInt(UInt<1>(0h0))) node _T_1142 = and(_T_1136, _T_1141) node _T_1143 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1144 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<14>(0h2000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<17>(0h10000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1155 = cvt(_T_1154) node _T_1156 = and(_T_1155, asSInt(UInt<18>(0h2f000))) node _T_1157 = asSInt(_T_1156) node _T_1158 = eq(_T_1157, asSInt(UInt<1>(0h0))) node _T_1159 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1160 = cvt(_T_1159) node _T_1161 = and(_T_1160, asSInt(UInt<17>(0h10000))) node _T_1162 = asSInt(_T_1161) node _T_1163 = eq(_T_1162, asSInt(UInt<1>(0h0))) node _T_1164 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1165 = cvt(_T_1164) node _T_1166 = and(_T_1165, asSInt(UInt<13>(0h1000))) node _T_1167 = asSInt(_T_1166) node _T_1168 = eq(_T_1167, asSInt(UInt<1>(0h0))) node _T_1169 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1170 = cvt(_T_1169) node _T_1171 = and(_T_1170, asSInt(UInt<27>(0h4000000))) node _T_1172 = asSInt(_T_1171) node _T_1173 = eq(_T_1172, asSInt(UInt<1>(0h0))) node _T_1174 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1175 = cvt(_T_1174) node _T_1176 = and(_T_1175, asSInt(UInt<13>(0h1000))) node _T_1177 = asSInt(_T_1176) node _T_1178 = eq(_T_1177, asSInt(UInt<1>(0h0))) node _T_1179 = or(_T_1148, _T_1153) node _T_1180 = or(_T_1179, _T_1158) node _T_1181 = or(_T_1180, _T_1163) node _T_1182 = or(_T_1181, _T_1168) node _T_1183 = or(_T_1182, _T_1173) node _T_1184 = or(_T_1183, _T_1178) node _T_1185 = and(_T_1143, _T_1184) node _T_1186 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1187 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = or(UInt<1>(0h0), _T_1188) node _T_1190 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1191 = cvt(_T_1190) node _T_1192 = and(_T_1191, asSInt(UInt<17>(0h10000))) node _T_1193 = asSInt(_T_1192) node _T_1194 = eq(_T_1193, asSInt(UInt<1>(0h0))) node _T_1195 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1196 = cvt(_T_1195) node _T_1197 = and(_T_1196, asSInt(UInt<29>(0h10000000))) node _T_1198 = asSInt(_T_1197) node _T_1199 = eq(_T_1198, asSInt(UInt<1>(0h0))) node _T_1200 = or(_T_1194, _T_1199) node _T_1201 = and(_T_1189, _T_1200) node _T_1202 = or(UInt<1>(0h0), _T_1142) node _T_1203 = or(_T_1202, _T_1185) node _T_1204 = or(_T_1203, _T_1201) node _T_1205 = and(_T_1132, _T_1204) node _T_1206 = asUInt(reset) node _T_1207 = eq(_T_1206, UInt<1>(0h0)) when _T_1207 : node _T_1208 = eq(_T_1205, UInt<1>(0h0)) when _T_1208 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1205, UInt<1>(0h1), "") : assert_46 node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(source_ok, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(is_aligned, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1215 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_49 node _T_1219 = eq(io.in.a.bits.mask, mask) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_50 node _T_1223 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1227 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_52 node _source_ok_T_28 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_29 = shr(io.in.d.bits.source, 2) node _source_ok_T_30 = eq(_source_ok_T_29, UInt<1>(0h0)) node _source_ok_T_31 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_T_33 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_35 = shr(io.in.d.bits.source, 2) node _source_ok_T_36 = eq(_source_ok_T_35, UInt<1>(0h1)) node _source_ok_T_37 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_40 = and(_source_ok_T_38, _source_ok_T_39) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_41 = shr(io.in.d.bits.source, 2) node _source_ok_T_42 = eq(_source_ok_T_41, UInt<2>(0h2)) node _source_ok_T_43 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_T_45 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_46 = and(_source_ok_T_44, _source_ok_T_45) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_47 = shr(io.in.d.bits.source, 2) node _source_ok_T_48 = eq(_source_ok_T_47, UInt<2>(0h3)) node _source_ok_T_49 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_T_51 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_52 = and(_source_ok_T_50, _source_ok_T_51) wire _source_ok_WIRE_1 : UInt<1>[5] connect _source_ok_WIRE_1[0], _source_ok_T_28 connect _source_ok_WIRE_1[1], _source_ok_T_34 connect _source_ok_WIRE_1[2], _source_ok_T_40 connect _source_ok_WIRE_1[3], _source_ok_T_46 connect _source_ok_WIRE_1[4], _source_ok_T_52 node _source_ok_T_53 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE_1[2]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE_1[3]) node source_ok_1 = or(_source_ok_T_55, _source_ok_WIRE_1[4]) node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1231 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1231 : node _T_1232 = asUInt(reset) node _T_1233 = eq(_T_1232, UInt<1>(0h0)) when _T_1233 : node _T_1234 = eq(source_ok_1, UInt<1>(0h0)) when _T_1234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1235 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_54 node _T_1239 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_55 node _T_1243 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_56 node _T_1247 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_57 node _T_1251 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1251 : node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(source_ok_1, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(sink_ok, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1258 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_60 node _T_1262 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_61 node _T_1266 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_62 node _T_1270 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_63 node _T_1274 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1275 = or(UInt<1>(0h1), _T_1274) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_64 node _T_1279 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1279 : node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(source_ok_1, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1283 = asUInt(reset) node _T_1284 = eq(_T_1283, UInt<1>(0h0)) when _T_1284 : node _T_1285 = eq(sink_ok, UInt<1>(0h0)) when _T_1285 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1286 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_67 node _T_1290 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_68 node _T_1294 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1295 = asUInt(reset) node _T_1296 = eq(_T_1295, UInt<1>(0h0)) when _T_1296 : node _T_1297 = eq(_T_1294, UInt<1>(0h0)) when _T_1297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1294, UInt<1>(0h1), "") : assert_69 node _T_1298 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1299 = or(_T_1298, io.in.d.bits.corrupt) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_70 node _T_1303 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1304 = or(UInt<1>(0h1), _T_1303) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_71 node _T_1308 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1308 : node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(source_ok_1, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1312 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_73 node _T_1316 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1317 = asUInt(reset) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) when _T_1318 : node _T_1319 = eq(_T_1316, UInt<1>(0h0)) when _T_1319 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1316, UInt<1>(0h1), "") : assert_74 node _T_1320 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1321 = or(UInt<1>(0h1), _T_1320) node _T_1322 = asUInt(reset) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) when _T_1323 : node _T_1324 = eq(_T_1321, UInt<1>(0h0)) when _T_1324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1321, UInt<1>(0h1), "") : assert_75 node _T_1325 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1325 : node _T_1326 = asUInt(reset) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) when _T_1327 : node _T_1328 = eq(source_ok_1, UInt<1>(0h0)) when _T_1328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1329 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1330 = asUInt(reset) node _T_1331 = eq(_T_1330, UInt<1>(0h0)) when _T_1331 : node _T_1332 = eq(_T_1329, UInt<1>(0h0)) when _T_1332 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1329, UInt<1>(0h1), "") : assert_77 node _T_1333 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1334 = or(_T_1333, io.in.d.bits.corrupt) node _T_1335 = asUInt(reset) node _T_1336 = eq(_T_1335, UInt<1>(0h0)) when _T_1336 : node _T_1337 = eq(_T_1334, UInt<1>(0h0)) when _T_1337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1334, UInt<1>(0h1), "") : assert_78 node _T_1338 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1339 = or(UInt<1>(0h1), _T_1338) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_79 node _T_1343 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1343 : node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(source_ok_1, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1347 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1348 = asUInt(reset) node _T_1349 = eq(_T_1348, UInt<1>(0h0)) when _T_1349 : node _T_1350 = eq(_T_1347, UInt<1>(0h0)) when _T_1350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1347, UInt<1>(0h1), "") : assert_81 node _T_1351 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_82 node _T_1355 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1356 = or(UInt<1>(0h1), _T_1355) node _T_1357 = asUInt(reset) node _T_1358 = eq(_T_1357, UInt<1>(0h0)) when _T_1358 : node _T_1359 = eq(_T_1356, UInt<1>(0h0)) when _T_1359 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1356, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1360 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1361 = asUInt(reset) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(_T_1360, UInt<1>(0h0)) when _T_1363 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1360, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1364 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1368 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1372 = eq(a_first, UInt<1>(0h0)) node _T_1373 = and(io.in.a.valid, _T_1372) when _T_1373 : node _T_1374 = eq(io.in.a.bits.opcode, opcode) node _T_1375 = asUInt(reset) node _T_1376 = eq(_T_1375, UInt<1>(0h0)) when _T_1376 : node _T_1377 = eq(_T_1374, UInt<1>(0h0)) when _T_1377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1374, UInt<1>(0h1), "") : assert_87 node _T_1378 = eq(io.in.a.bits.param, param) node _T_1379 = asUInt(reset) node _T_1380 = eq(_T_1379, UInt<1>(0h0)) when _T_1380 : node _T_1381 = eq(_T_1378, UInt<1>(0h0)) when _T_1381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1378, UInt<1>(0h1), "") : assert_88 node _T_1382 = eq(io.in.a.bits.size, size) node _T_1383 = asUInt(reset) node _T_1384 = eq(_T_1383, UInt<1>(0h0)) when _T_1384 : node _T_1385 = eq(_T_1382, UInt<1>(0h0)) when _T_1385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1382, UInt<1>(0h1), "") : assert_89 node _T_1386 = eq(io.in.a.bits.source, source) node _T_1387 = asUInt(reset) node _T_1388 = eq(_T_1387, UInt<1>(0h0)) when _T_1388 : node _T_1389 = eq(_T_1386, UInt<1>(0h0)) when _T_1389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1386, UInt<1>(0h1), "") : assert_90 node _T_1390 = eq(io.in.a.bits.address, address) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_91 node _T_1394 = and(io.in.a.ready, io.in.a.valid) node _T_1395 = and(_T_1394, a_first) when _T_1395 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1396 = eq(d_first, UInt<1>(0h0)) node _T_1397 = and(io.in.d.valid, _T_1396) when _T_1397 : node _T_1398 = eq(io.in.d.bits.opcode, opcode_1) node _T_1399 = asUInt(reset) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) when _T_1400 : node _T_1401 = eq(_T_1398, UInt<1>(0h0)) when _T_1401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1398, UInt<1>(0h1), "") : assert_92 node _T_1402 = eq(io.in.d.bits.param, param_1) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_93 node _T_1406 = eq(io.in.d.bits.size, size_1) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_94 node _T_1410 = eq(io.in.d.bits.source, source_1) node _T_1411 = asUInt(reset) node _T_1412 = eq(_T_1411, UInt<1>(0h0)) when _T_1412 : node _T_1413 = eq(_T_1410, UInt<1>(0h0)) when _T_1413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1410, UInt<1>(0h1), "") : assert_95 node _T_1414 = eq(io.in.d.bits.sink, sink) node _T_1415 = asUInt(reset) node _T_1416 = eq(_T_1415, UInt<1>(0h0)) when _T_1416 : node _T_1417 = eq(_T_1414, UInt<1>(0h0)) when _T_1417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1414, UInt<1>(0h1), "") : assert_96 node _T_1418 = eq(io.in.d.bits.denied, denied) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_97 node _T_1422 = and(io.in.d.ready, io.in.d.valid) node _T_1423 = and(_T_1422, d_first) when _T_1423 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes : UInt<136>, clock, reset, UInt<136>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<17> connect a_set, UInt<17>(0h0) wire a_set_wo_ready : UInt<17> connect a_set_wo_ready, UInt<17>(0h0) wire a_opcodes_set : UInt<68> connect a_opcodes_set, UInt<68>(0h0) wire a_sizes_set : UInt<136> connect a_sizes_set, UInt<136>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1424 = and(io.in.a.valid, a_first_1) node _T_1425 = and(_T_1424, UInt<1>(0h1)) when _T_1425 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1426 = and(io.in.a.ready, io.in.a.valid) node _T_1427 = and(_T_1426, a_first_1) node _T_1428 = and(_T_1427, UInt<1>(0h1)) when _T_1428 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1429 = dshr(inflight, io.in.a.bits.source) node _T_1430 = bits(_T_1429, 0, 0) node _T_1431 = eq(_T_1430, UInt<1>(0h0)) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<17> connect d_clr, UInt<17>(0h0) wire d_clr_wo_ready : UInt<17> connect d_clr_wo_ready, UInt<17>(0h0) wire d_opcodes_clr : UInt<68> connect d_opcodes_clr, UInt<68>(0h0) wire d_sizes_clr : UInt<136> connect d_sizes_clr, UInt<136>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1435 = and(io.in.d.valid, d_first_1) node _T_1436 = and(_T_1435, UInt<1>(0h1)) node _T_1437 = eq(d_release_ack, UInt<1>(0h0)) node _T_1438 = and(_T_1436, _T_1437) when _T_1438 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1439 = and(io.in.d.ready, io.in.d.valid) node _T_1440 = and(_T_1439, d_first_1) node _T_1441 = and(_T_1440, UInt<1>(0h1)) node _T_1442 = eq(d_release_ack, UInt<1>(0h0)) node _T_1443 = and(_T_1441, _T_1442) when _T_1443 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1444 = and(io.in.d.valid, d_first_1) node _T_1445 = and(_T_1444, UInt<1>(0h1)) node _T_1446 = eq(d_release_ack, UInt<1>(0h0)) node _T_1447 = and(_T_1445, _T_1446) when _T_1447 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1448 = dshr(inflight, io.in.d.bits.source) node _T_1449 = bits(_T_1448, 0, 0) node _T_1450 = or(_T_1449, same_cycle_resp) node _T_1451 = asUInt(reset) node _T_1452 = eq(_T_1451, UInt<1>(0h0)) when _T_1452 : node _T_1453 = eq(_T_1450, UInt<1>(0h0)) when _T_1453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1450, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1454 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1455 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1456 = or(_T_1454, _T_1455) node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(_T_1456, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1456, UInt<1>(0h1), "") : assert_100 node _T_1460 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_101 else : node _T_1464 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1465 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1466 = or(_T_1464, _T_1465) node _T_1467 = asUInt(reset) node _T_1468 = eq(_T_1467, UInt<1>(0h0)) when _T_1468 : node _T_1469 = eq(_T_1466, UInt<1>(0h0)) when _T_1469 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1466, UInt<1>(0h1), "") : assert_102 node _T_1470 = eq(io.in.d.bits.size, a_size_lookup) node _T_1471 = asUInt(reset) node _T_1472 = eq(_T_1471, UInt<1>(0h0)) when _T_1472 : node _T_1473 = eq(_T_1470, UInt<1>(0h0)) when _T_1473 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1470, UInt<1>(0h1), "") : assert_103 node _T_1474 = and(io.in.d.valid, d_first_1) node _T_1475 = and(_T_1474, a_first_1) node _T_1476 = and(_T_1475, io.in.a.valid) node _T_1477 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1478 = and(_T_1476, _T_1477) node _T_1479 = eq(d_release_ack, UInt<1>(0h0)) node _T_1480 = and(_T_1478, _T_1479) when _T_1480 : node _T_1481 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1482 = or(_T_1481, io.in.a.ready) node _T_1483 = asUInt(reset) node _T_1484 = eq(_T_1483, UInt<1>(0h0)) when _T_1484 : node _T_1485 = eq(_T_1482, UInt<1>(0h0)) when _T_1485 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1482, UInt<1>(0h1), "") : assert_104 node _T_1486 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1487 = orr(a_set_wo_ready) node _T_1488 = eq(_T_1487, UInt<1>(0h0)) node _T_1489 = or(_T_1486, _T_1488) node _T_1490 = asUInt(reset) node _T_1491 = eq(_T_1490, UInt<1>(0h0)) when _T_1491 : node _T_1492 = eq(_T_1489, UInt<1>(0h0)) when _T_1492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1489, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader node _T_1493 = orr(inflight) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) node _T_1495 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1496 = or(_T_1494, _T_1495) node _T_1497 = lt(watchdog, plusarg_reader.out) node _T_1498 = or(_T_1496, _T_1497) node _T_1499 = asUInt(reset) node _T_1500 = eq(_T_1499, UInt<1>(0h0)) when _T_1500 : node _T_1501 = eq(_T_1498, UInt<1>(0h0)) when _T_1501 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1498, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1502 = and(io.in.a.ready, io.in.a.valid) node _T_1503 = and(io.in.d.ready, io.in.d.valid) node _T_1504 = or(_T_1502, _T_1503) when _T_1504 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<17>, clock, reset, UInt<17>(0h0) regreset inflight_opcodes_1 : UInt<68>, clock, reset, UInt<68>(0h0) regreset inflight_sizes_1 : UInt<136>, clock, reset, UInt<136>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<10>, clock, reset, UInt<10>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<10>, clock, reset, UInt<10>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<17> connect c_set, UInt<17>(0h0) wire c_set_wo_ready : UInt<17> connect c_set_wo_ready, UInt<17>(0h0) wire c_opcodes_set : UInt<68> connect c_opcodes_set, UInt<68>(0h0) wire c_sizes_set : UInt<136> connect c_sizes_set, UInt<136>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1505 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1506 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1507 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1508 = and(_T_1506, _T_1507) node _T_1509 = and(_T_1505, _T_1508) when _T_1509 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1510 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1511 = and(_T_1510, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1512 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1513 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1514 = and(_T_1512, _T_1513) node _T_1515 = and(_T_1511, _T_1514) when _T_1515 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1516 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1517 = bits(_T_1516, 0, 0) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) node _T_1519 = asUInt(reset) node _T_1520 = eq(_T_1519, UInt<1>(0h0)) when _T_1520 : node _T_1521 = eq(_T_1518, UInt<1>(0h0)) when _T_1521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1518, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<17> connect d_clr_1, UInt<17>(0h0) wire d_clr_wo_ready_1 : UInt<17> connect d_clr_wo_ready_1, UInt<17>(0h0) wire d_opcodes_clr_1 : UInt<68> connect d_opcodes_clr_1, UInt<68>(0h0) wire d_sizes_clr_1 : UInt<136> connect d_sizes_clr_1, UInt<136>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1522 = and(io.in.d.valid, d_first_2) node _T_1523 = and(_T_1522, UInt<1>(0h1)) node _T_1524 = and(_T_1523, d_release_ack_1) when _T_1524 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1525 = and(io.in.d.ready, io.in.d.valid) node _T_1526 = and(_T_1525, d_first_2) node _T_1527 = and(_T_1526, UInt<1>(0h1)) node _T_1528 = and(_T_1527, d_release_ack_1) when _T_1528 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1529 = and(io.in.d.valid, d_first_2) node _T_1530 = and(_T_1529, UInt<1>(0h1)) node _T_1531 = and(_T_1530, d_release_ack_1) when _T_1531 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1532 = dshr(inflight_1, io.in.d.bits.source) node _T_1533 = bits(_T_1532, 0, 0) node _T_1534 = or(_T_1533, same_cycle_resp_1) node _T_1535 = asUInt(reset) node _T_1536 = eq(_T_1535, UInt<1>(0h0)) when _T_1536 : node _T_1537 = eq(_T_1534, UInt<1>(0h0)) when _T_1537 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1534, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1538 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(_T_1538, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1538, UInt<1>(0h1), "") : assert_109 else : node _T_1542 = eq(io.in.d.bits.size, c_size_lookup) node _T_1543 = asUInt(reset) node _T_1544 = eq(_T_1543, UInt<1>(0h0)) when _T_1544 : node _T_1545 = eq(_T_1542, UInt<1>(0h0)) when _T_1545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110 node _T_1546 = and(io.in.d.valid, d_first_2) node _T_1547 = and(_T_1546, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1548 = and(_T_1547, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1549 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1550 = and(_T_1548, _T_1549) node _T_1551 = and(_T_1550, d_release_ack_1) node _T_1552 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1553 = and(_T_1551, _T_1552) when _T_1553 : node _T_1554 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1555 = or(_T_1554, _WIRE_23.ready) node _T_1556 = asUInt(reset) node _T_1557 = eq(_T_1556, UInt<1>(0h0)) when _T_1557 : node _T_1558 = eq(_T_1555, UInt<1>(0h0)) when _T_1558 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1555, UInt<1>(0h1), "") : assert_111 node _T_1559 = orr(c_set_wo_ready) when _T_1559 : node _T_1560 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1561 = asUInt(reset) node _T_1562 = eq(_T_1561, UInt<1>(0h0)) when _T_1562 : node _T_1563 = eq(_T_1560, UInt<1>(0h0)) when _T_1563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1560, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_1 node _T_1564 = orr(inflight_1) node _T_1565 = eq(_T_1564, UInt<1>(0h0)) node _T_1566 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1567 = or(_T_1565, _T_1566) node _T_1568 = lt(watchdog_1, plusarg_reader_1.out) node _T_1569 = or(_T_1567, _T_1568) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/SystemBus.scala:48:55)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1573 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1574 = and(io.in.d.ready, io.in.d.valid) node _T_1575 = or(_T_1573, _T_1574) when _T_1575 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_2 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_3 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [9:0] c_first_beats1_decode = 10'h0; // @[Edges.scala:220:59] wire [9:0] c_first_beats1 = 10'h0; // @[Edges.scala:221:14] wire [9:0] _c_first_count_T = 10'h0; // @[Edges.scala:234:27] wire [9:0] c_first_count = 10'h0; // @[Edges.scala:234:25] wire [9:0] _c_first_counter_T = 10'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_39 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_43 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_45 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_49 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_51 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [9:0] c_first_counter1 = 10'h3FF; // @[Edges.scala:230:28] wire [10:0] _c_first_counter1_T = 11'h7FF; // @[Edges.scala:230:28] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [135:0] c_sizes_set = 136'h0; // @[Monitor.scala:741:34] wire [67:0] c_opcodes_set = 68'h0; // @[Monitor.scala:740:34] wire [16:0] c_set = 17'h0; // @[Monitor.scala:738:34] wire [16:0] c_set_wo_ready = 17'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_1 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_7 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_13 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_19 = io_in_a_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_26 = _source_ok_T_25 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_27 = _source_ok_T_26 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_27 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire mask_sizeOH_shiftAmount = _mask_sizeOH_T[0]; // @[OneHot.scala:64:49] wire [1:0] _mask_sizeOH_T_1 = 2'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [1:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [1:0] mask_sizeOH = {_mask_sizeOH_T_2[1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_0_1 = |(io_in_a_bits_size_0[3:1]); // @[Misc.scala:206:21] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_28 = io_in_d_bits_source_0 == 5'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] _source_ok_T_29 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_35 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_41 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire [2:0] _source_ok_T_47 = io_in_d_bits_source_0[4:2]; // @[Monitor.scala:36:7] wire _source_ok_T_30 = _source_ok_T_29 == 3'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_36 = _source_ok_T_35 == 3'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_40 = _source_ok_T_38; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_42 = _source_ok_T_41 == 3'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_44 = _source_ok_T_42; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_46 = _source_ok_T_44; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_48 = _source_ok_T_47 == 3'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_50 = _source_ok_T_48; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_52 = _source_ok_T_50; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_52; // @[Parameters.scala:1138:31] wire _source_ok_T_53 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_55 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _T_1502 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1502; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1502; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T = {1'h0, a_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1 = _a_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1575 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1575; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1575; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:2]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [9:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T = {1'h0, d_first_counter} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1 = _d_first_counter1_T[9:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [16:0] inflight; // @[Monitor.scala:614:27] reg [67:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [135:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [9:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 10'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [9:0] a_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] a_first_counter1_1 = _a_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_1; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_1 = _d_first_counter1_T_1[9:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [16:0] a_set; // @[Monitor.scala:626:34] wire [16:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [67:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [135:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [67:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [67:0] _a_opcode_lookup_T_6 = {64'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [67:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [135:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [135:0] _a_size_lookup_T_6 = {128'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [135:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[135:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = 32'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1428 = _T_1502 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1428 ? _a_set_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1428 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1428 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1428 ? _a_opcodes_set_T_1[67:0] : 68'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1428 ? _a_sizes_set_T_1[135:0] : 136'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [16:0] d_clr; // @[Monitor.scala:664:34] wire [16:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [67:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [135:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1474 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_5 = 32'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1474 & ~d_release_ack ? _d_clr_wo_ready_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1443 = _T_1575 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1443 ? _d_clr_T[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1443 ? _d_opcodes_clr_T_5[67:0] : 68'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1443 ? _d_sizes_clr_T_5[135:0] : 136'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [16:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [16:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [16:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [67:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [67:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [67:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [135:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [135:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [135:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [16:0] inflight_1; // @[Monitor.scala:726:35] wire [16:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [67:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [67:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [135:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [135:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [9:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:2]; // @[package.scala:243:46] wire [9:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 10'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [9:0] d_first_counter_2; // @[Edges.scala:229:27] wire [10:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 11'h1; // @[Edges.scala:229:27, :230:28] wire [9:0] d_first_counter1_2 = _d_first_counter1_T_2[9:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 10'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 10'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 10'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [9:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [9:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [9:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [67:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [67:0] _c_opcode_lookup_T_6 = {64'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [67:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[67:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [135:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [135:0] _c_size_lookup_T_6 = {128'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [135:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[135:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [16:0] d_clr_1; // @[Monitor.scala:774:34] wire [16:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [67:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [135:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1546 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1546 & d_release_ack_1 ? _d_clr_wo_ready_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire _T_1528 = _T_1575 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1528 ? _d_clr_T_1[16:0] : 17'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1528 ? _d_opcodes_clr_T_11[67:0] : 68'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1528 ? _d_sizes_clr_T_11[135:0] : 136'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [16:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [16:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [67:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [67:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [135:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [135:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_9 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut
module MulFullRawFN_9( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_195 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_195( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_355 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToIN_e11_s53_i32_3 : input clock : Clock input reset : Reset output io : { flip in : UInt<65>, flip roundingMode : UInt<3>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} node rawIn_exp = bits(io.in, 63, 52) node _rawIn_isZero_T = bits(rawIn_exp, 11, 9) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 11, 10) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 9, 9) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 64, 64) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 51, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node magGeOne = bits(rawIn.sExp, 11, 11) node posExp = bits(rawIn.sExp, 10, 0) node _magJustBelowOne_T = eq(magGeOne, UInt<1>(0h0)) node _magJustBelowOne_T_1 = andr(posExp) node magJustBelowOne = and(_magJustBelowOne_T, _magJustBelowOne_T_1) node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _shiftedSig_T = bits(rawIn.sig, 51, 0) node _shiftedSig_T_1 = cat(magGeOne, _shiftedSig_T) node _shiftedSig_T_2 = bits(rawIn.sExp, 4, 0) node _shiftedSig_T_3 = mux(magGeOne, _shiftedSig_T_2, UInt<1>(0h0)) node shiftedSig = dshl(_shiftedSig_T_1, _shiftedSig_T_3) node _alignedSig_T = shr(shiftedSig, 51) node _alignedSig_T_1 = bits(shiftedSig, 50, 0) node _alignedSig_T_2 = orr(_alignedSig_T_1) node alignedSig = cat(_alignedSig_T, _alignedSig_T_2) node _unroundedInt_T = shr(alignedSig, 2) node unroundedInt = or(UInt<32>(0h0), _unroundedInt_T) node _common_inexact_T = bits(alignedSig, 1, 0) node _common_inexact_T_1 = orr(_common_inexact_T) node _common_inexact_T_2 = eq(rawIn.isZero, UInt<1>(0h0)) node common_inexact = mux(magGeOne, _common_inexact_T_1, _common_inexact_T_2) node _roundIncr_near_even_T = bits(alignedSig, 2, 1) node _roundIncr_near_even_T_1 = andr(_roundIncr_near_even_T) node _roundIncr_near_even_T_2 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_3 = andr(_roundIncr_near_even_T_2) node _roundIncr_near_even_T_4 = or(_roundIncr_near_even_T_1, _roundIncr_near_even_T_3) node _roundIncr_near_even_T_5 = and(magGeOne, _roundIncr_near_even_T_4) node _roundIncr_near_even_T_6 = bits(alignedSig, 1, 0) node _roundIncr_near_even_T_7 = orr(_roundIncr_near_even_T_6) node _roundIncr_near_even_T_8 = and(magJustBelowOne, _roundIncr_near_even_T_7) node roundIncr_near_even = or(_roundIncr_near_even_T_5, _roundIncr_near_even_T_8) node _roundIncr_near_maxMag_T = bits(alignedSig, 1, 1) node _roundIncr_near_maxMag_T_1 = and(magGeOne, _roundIncr_near_maxMag_T) node roundIncr_near_maxMag = or(_roundIncr_near_maxMag_T_1, magJustBelowOne) node _roundIncr_T = and(roundingMode_near_even, roundIncr_near_even) node _roundIncr_T_1 = and(roundingMode_near_maxMag, roundIncr_near_maxMag) node _roundIncr_T_2 = or(_roundIncr_T, _roundIncr_T_1) node _roundIncr_T_3 = or(roundingMode_min, roundingMode_odd) node _roundIncr_T_4 = and(rawIn.sign, common_inexact) node _roundIncr_T_5 = and(_roundIncr_T_3, _roundIncr_T_4) node _roundIncr_T_6 = or(_roundIncr_T_2, _roundIncr_T_5) node _roundIncr_T_7 = eq(rawIn.sign, UInt<1>(0h0)) node _roundIncr_T_8 = and(_roundIncr_T_7, common_inexact) node _roundIncr_T_9 = and(roundingMode_max, _roundIncr_T_8) node roundIncr = or(_roundIncr_T_6, _roundIncr_T_9) node _complUnroundedInt_T = not(unroundedInt) node complUnroundedInt = mux(rawIn.sign, _complUnroundedInt_T, unroundedInt) node _roundedInt_T = xor(roundIncr, rawIn.sign) node _roundedInt_T_1 = add(complUnroundedInt, UInt<1>(0h1)) node _roundedInt_T_2 = tail(_roundedInt_T_1, 1) node _roundedInt_T_3 = mux(_roundedInt_T, _roundedInt_T_2, complUnroundedInt) node _roundedInt_T_4 = and(roundingMode_odd, common_inexact) node roundedInt = or(_roundedInt_T_3, _roundedInt_T_4) node magGeOne_atOverflowEdge = eq(posExp, UInt<5>(0h1f)) node _roundCarryBut2_T = bits(unroundedInt, 29, 0) node _roundCarryBut2_T_1 = andr(_roundCarryBut2_T) node roundCarryBut2 = and(_roundCarryBut2_T_1, roundIncr) node _common_overflow_T = geq(posExp, UInt<6>(0h20)) node _common_overflow_T_1 = bits(unroundedInt, 30, 0) node _common_overflow_T_2 = orr(_common_overflow_T_1) node _common_overflow_T_3 = or(_common_overflow_T_2, roundIncr) node _common_overflow_T_4 = and(magGeOne_atOverflowEdge, _common_overflow_T_3) node _common_overflow_T_5 = eq(posExp, UInt<5>(0h1e)) node _common_overflow_T_6 = and(_common_overflow_T_5, roundCarryBut2) node _common_overflow_T_7 = or(magGeOne_atOverflowEdge, _common_overflow_T_6) node _common_overflow_T_8 = mux(rawIn.sign, _common_overflow_T_4, _common_overflow_T_7) node _common_overflow_T_9 = bits(unroundedInt, 30, 30) node _common_overflow_T_10 = and(magGeOne_atOverflowEdge, _common_overflow_T_9) node _common_overflow_T_11 = and(_common_overflow_T_10, roundCarryBut2) node _common_overflow_T_12 = or(rawIn.sign, _common_overflow_T_11) node _common_overflow_T_13 = mux(io.signedOut, _common_overflow_T_8, _common_overflow_T_12) node _common_overflow_T_14 = or(_common_overflow_T, _common_overflow_T_13) node _common_overflow_T_15 = eq(io.signedOut, UInt<1>(0h0)) node _common_overflow_T_16 = and(_common_overflow_T_15, rawIn.sign) node _common_overflow_T_17 = and(_common_overflow_T_16, roundIncr) node common_overflow = mux(magGeOne, _common_overflow_T_14, _common_overflow_T_17) node invalidExc = or(rawIn.isNaN, rawIn.isInf) node _overflow_T = eq(invalidExc, UInt<1>(0h0)) node overflow = and(_overflow_T, common_overflow) node _inexact_T = eq(invalidExc, UInt<1>(0h0)) node _inexact_T_1 = eq(common_overflow, UInt<1>(0h0)) node _inexact_T_2 = and(_inexact_T, _inexact_T_1) node inexact = and(_inexact_T_2, common_inexact) node _excSign_T = eq(rawIn.isNaN, UInt<1>(0h0)) node excSign = and(_excSign_T, rawIn.sign) node _excOut_T = eq(io.signedOut, excSign) node _excOut_T_1 = mux(_excOut_T, UInt<32>(0h80000000), UInt<1>(0h0)) node _excOut_T_2 = eq(excSign, UInt<1>(0h0)) node _excOut_T_3 = mux(_excOut_T_2, UInt<31>(0h7fffffff), UInt<1>(0h0)) node excOut = or(_excOut_T_1, _excOut_T_3) node _io_out_T = or(invalidExc, common_overflow) node _io_out_T_1 = mux(_io_out_T, excOut, roundedInt) connect io.out, _io_out_T_1 node _io_intExceptionFlags_T = cat(invalidExc, overflow) node _io_intExceptionFlags_T_1 = cat(_io_intExceptionFlags_T, inexact) connect io.intExceptionFlags, _io_intExceptionFlags_T_1
module RecFNToIN_e11_s53_i32_3( // @[RecFNToIN.scala:46:7] input clock, // @[RecFNToIN.scala:46:7] input reset, // @[RecFNToIN.scala:46:7] input [64:0] io_in, // @[RecFNToIN.scala:49:16] input [2:0] io_roundingMode, // @[RecFNToIN.scala:49:16] input io_signedOut, // @[RecFNToIN.scala:49:16] output [2:0] io_intExceptionFlags // @[RecFNToIN.scala:49:16] ); wire [64:0] io_in_0 = io_in; // @[RecFNToIN.scala:46:7] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RecFNToIN.scala:46:7] wire io_signedOut_0 = io_signedOut; // @[RecFNToIN.scala:46:7] wire [31:0] _io_out_T_1; // @[RecFNToIN.scala:145:18] wire [2:0] _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:146:52] wire [31:0] io_out; // @[RecFNToIN.scala:46:7] wire [2:0] io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] wire [11:0] rawIn_exp = io_in_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawIn_out_sig_T_2 = io_in_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire magGeOne = rawIn_sExp[11]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] posExp = rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire _magJustBelowOne_T = ~magGeOne; // @[RecFNToIN.scala:61:30, :63:27] wire _magJustBelowOne_T_1 = &posExp; // @[RecFNToIN.scala:62:28, :63:47] wire magJustBelowOne = _magJustBelowOne_T & _magJustBelowOne_T_1; // @[RecFNToIN.scala:63:{27,37,47}] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[rawFloatFromRecFN.scala:52:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RecFNToIN.scala:46:7, :68:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RecFNToIN.scala:46:7, :69:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RecFNToIN.scala:46:7, :70:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RecFNToIN.scala:46:7, :71:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RecFNToIN.scala:46:7, :72:53] wire [51:0] _shiftedSig_T = rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _shiftedSig_T_1 = {magGeOne, _shiftedSig_T}; // @[RecFNToIN.scala:61:30, :83:{19,31}] wire [4:0] _shiftedSig_T_2 = rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _shiftedSig_T_3 = magGeOne ? _shiftedSig_T_2 : 5'h0; // @[RecFNToIN.scala:61:30, :84:16, :85:27] wire [83:0] shiftedSig = {31'h0, _shiftedSig_T_1} << _shiftedSig_T_3; // @[RecFNToIN.scala:83:{19,49}, :84:16] wire [32:0] _alignedSig_T = shiftedSig[83:51]; // @[RecFNToIN.scala:83:49, :89:20] wire [50:0] _alignedSig_T_1 = shiftedSig[50:0]; // @[RecFNToIN.scala:83:49, :89:51] wire _alignedSig_T_2 = |_alignedSig_T_1; // @[RecFNToIN.scala:89:{51,69}] wire [33:0] alignedSig = {_alignedSig_T, _alignedSig_T_2}; // @[RecFNToIN.scala:89:{20,38,69}] wire [31:0] _unroundedInt_T = alignedSig[33:2]; // @[RecFNToIN.scala:89:38, :90:52] wire [31:0] unroundedInt = _unroundedInt_T; // @[RecFNToIN.scala:90:{40,52}] wire [1:0] _common_inexact_T = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50] wire [1:0] _roundIncr_near_even_T_2 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :94:64] wire [1:0] _roundIncr_near_even_T_6 = alignedSig[1:0]; // @[RecFNToIN.scala:89:38, :92:50, :95:39] wire _common_inexact_T_1 = |_common_inexact_T; // @[RecFNToIN.scala:92:{50,57}] wire _common_inexact_T_2 = ~rawIn_isZero_0; // @[rawFloatFromRecFN.scala:55:23] wire common_inexact = magGeOne ? _common_inexact_T_1 : _common_inexact_T_2; // @[RecFNToIN.scala:61:30, :92:{29,57,62}] wire [1:0] _roundIncr_near_even_T = alignedSig[2:1]; // @[RecFNToIN.scala:89:38, :94:39] wire _roundIncr_near_even_T_1 = &_roundIncr_near_even_T; // @[RecFNToIN.scala:94:{39,46}] wire _roundIncr_near_even_T_3 = &_roundIncr_near_even_T_2; // @[RecFNToIN.scala:94:{64,71}] wire _roundIncr_near_even_T_4 = _roundIncr_near_even_T_1 | _roundIncr_near_even_T_3; // @[RecFNToIN.scala:94:{46,51,71}] wire _roundIncr_near_even_T_5 = magGeOne & _roundIncr_near_even_T_4; // @[RecFNToIN.scala:61:30, :94:{25,51}] wire _roundIncr_near_even_T_7 = |_roundIncr_near_even_T_6; // @[RecFNToIN.scala:95:{39,46}] wire _roundIncr_near_even_T_8 = magJustBelowOne & _roundIncr_near_even_T_7; // @[RecFNToIN.scala:63:37, :95:{26,46}] wire roundIncr_near_even = _roundIncr_near_even_T_5 | _roundIncr_near_even_T_8; // @[RecFNToIN.scala:94:{25,78}, :95:26] wire _roundIncr_near_maxMag_T = alignedSig[1]; // @[RecFNToIN.scala:89:38, :96:56] wire _roundIncr_near_maxMag_T_1 = magGeOne & _roundIncr_near_maxMag_T; // @[RecFNToIN.scala:61:30, :96:{43,56}] wire roundIncr_near_maxMag = _roundIncr_near_maxMag_T_1 | magJustBelowOne; // @[RecFNToIN.scala:63:37, :96:{43,61}] wire _roundIncr_T = roundingMode_near_even & roundIncr_near_even; // @[RecFNToIN.scala:67:53, :94:78, :98:35] wire _roundIncr_T_1 = roundingMode_near_maxMag & roundIncr_near_maxMag; // @[RecFNToIN.scala:71:53, :96:61, :99:35] wire _roundIncr_T_2 = _roundIncr_T | _roundIncr_T_1; // @[RecFNToIN.scala:98:{35,61}, :99:35] wire _roundIncr_T_3 = roundingMode_min | roundingMode_odd; // @[RecFNToIN.scala:69:53, :72:53, :100:28] wire _roundIncr_T_4 = rawIn_sign & common_inexact; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_5 = _roundIncr_T_3 & _roundIncr_T_4; // @[RecFNToIN.scala:100:{28,49}, :101:26] wire _roundIncr_T_6 = _roundIncr_T_2 | _roundIncr_T_5; // @[RecFNToIN.scala:98:61, :99:61, :100:49] wire _roundIncr_T_7 = ~rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _roundIncr_T_8 = _roundIncr_T_7 & common_inexact; // @[RecFNToIN.scala:92:29, :102:{31,43}] wire _roundIncr_T_9 = roundingMode_max & _roundIncr_T_8; // @[RecFNToIN.scala:70:53, :102:{27,43}] wire roundIncr = _roundIncr_T_6 | _roundIncr_T_9; // @[RecFNToIN.scala:99:61, :101:46, :102:27] wire [31:0] _complUnroundedInt_T = ~unroundedInt; // @[RecFNToIN.scala:90:40, :103:45] wire [31:0] complUnroundedInt = rawIn_sign ? _complUnroundedInt_T : unroundedInt; // @[rawFloatFromRecFN.scala:55:23] wire _roundedInt_T = roundIncr ^ rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [32:0] _roundedInt_T_1 = {1'h0, complUnroundedInt} + 33'h1; // @[RecFNToIN.scala:103:32, :106:31] wire [31:0] _roundedInt_T_2 = _roundedInt_T_1[31:0]; // @[RecFNToIN.scala:106:31] wire [31:0] _roundedInt_T_3 = _roundedInt_T ? _roundedInt_T_2 : complUnroundedInt; // @[RecFNToIN.scala:103:32, :105:{12,23}, :106:31] wire _roundedInt_T_4 = roundingMode_odd & common_inexact; // @[RecFNToIN.scala:72:53, :92:29, :108:31] wire [31:0] roundedInt = {_roundedInt_T_3[31:1], _roundedInt_T_3[0] | _roundedInt_T_4}; // @[RecFNToIN.scala:105:12, :108:{11,31}] wire magGeOne_atOverflowEdge = posExp == 11'h1F; // @[RecFNToIN.scala:62:28, :110:43] wire [29:0] _roundCarryBut2_T = unroundedInt[29:0]; // @[RecFNToIN.scala:90:40, :113:38] wire _roundCarryBut2_T_1 = &_roundCarryBut2_T; // @[RecFNToIN.scala:113:{38,56}] wire roundCarryBut2 = _roundCarryBut2_T_1 & roundIncr; // @[RecFNToIN.scala:101:46, :113:{56,61}] wire _common_overflow_T = |(posExp[10:5]); // @[RecFNToIN.scala:62:28, :116:21] wire [30:0] _common_overflow_T_1 = unroundedInt[30:0]; // @[RecFNToIN.scala:90:40, :120:42] wire _common_overflow_T_2 = |_common_overflow_T_1; // @[RecFNToIN.scala:120:{42,60}] wire _common_overflow_T_3 = _common_overflow_T_2 | roundIncr; // @[RecFNToIN.scala:101:46, :120:{60,64}] wire _common_overflow_T_4 = magGeOne_atOverflowEdge & _common_overflow_T_3; // @[RecFNToIN.scala:110:43, :119:49, :120:64] wire _common_overflow_T_5 = posExp == 11'h1E; // @[RecFNToIN.scala:62:28, :122:38] wire _common_overflow_T_6 = _common_overflow_T_5 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :122:{38,60}] wire _common_overflow_T_7 = magGeOne_atOverflowEdge | _common_overflow_T_6; // @[RecFNToIN.scala:110:43, :121:49, :122:60] wire _common_overflow_T_8 = rawIn_sign ? _common_overflow_T_4 : _common_overflow_T_7; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_9 = unroundedInt[30]; // @[RecFNToIN.scala:90:40, :126:42] wire _common_overflow_T_10 = magGeOne_atOverflowEdge & _common_overflow_T_9; // @[RecFNToIN.scala:110:43, :125:50, :126:42] wire _common_overflow_T_11 = _common_overflow_T_10 & roundCarryBut2; // @[RecFNToIN.scala:113:61, :125:50, :126:57] wire _common_overflow_T_12 = rawIn_sign | _common_overflow_T_11; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_13 = io_signedOut_0 ? _common_overflow_T_8 : _common_overflow_T_12; // @[RecFNToIN.scala:46:7, :117:20, :118:24, :124:32] wire _common_overflow_T_14 = _common_overflow_T | _common_overflow_T_13; // @[RecFNToIN.scala:116:{21,36}, :117:20] wire _common_overflow_T_15 = ~io_signedOut_0; // @[RecFNToIN.scala:46:7, :128:13] wire _common_overflow_T_16 = _common_overflow_T_15 & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _common_overflow_T_17 = _common_overflow_T_16 & roundIncr; // @[RecFNToIN.scala:101:46, :128:{27,41}] wire common_overflow = magGeOne ? _common_overflow_T_14 : _common_overflow_T_17; // @[RecFNToIN.scala:61:30, :115:12, :116:36, :128:41] wire invalidExc = rawIn_isNaN | rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire _overflow_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20] wire overflow = _overflow_T & common_overflow; // @[RecFNToIN.scala:115:12, :134:{20,32}] wire _inexact_T = ~invalidExc; // @[RecFNToIN.scala:133:34, :134:20, :135:20] wire _inexact_T_1 = ~common_overflow; // @[RecFNToIN.scala:115:12, :135:35] wire _inexact_T_2 = _inexact_T & _inexact_T_1; // @[RecFNToIN.scala:135:{20,32,35}] wire inexact = _inexact_T_2 & common_inexact; // @[RecFNToIN.scala:92:29, :135:{32,52}] wire _excSign_T = ~rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire excSign = _excSign_T & rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire _excOut_T = io_signedOut_0 == excSign; // @[RecFNToIN.scala:46:7, :137:32, :139:27] wire [31:0] _excOut_T_1 = {_excOut_T, 31'h0}; // @[RecFNToIN.scala:139:{12,27}] wire _excOut_T_2 = ~excSign; // @[RecFNToIN.scala:137:32, :143:13] wire [30:0] _excOut_T_3 = {31{_excOut_T_2}}; // @[RecFNToIN.scala:143:{12,13}] wire [31:0] excOut = {_excOut_T_1[31], _excOut_T_1[30:0] | _excOut_T_3}; // @[RecFNToIN.scala:139:12, :142:11, :143:12] wire _io_out_T = invalidExc | common_overflow; // @[RecFNToIN.scala:115:12, :133:34, :145:30] assign _io_out_T_1 = _io_out_T ? excOut : roundedInt; // @[RecFNToIN.scala:108:11, :142:11, :145:{18,30}] assign io_out = _io_out_T_1; // @[RecFNToIN.scala:46:7, :145:18] wire [1:0] _io_intExceptionFlags_T = {invalidExc, overflow}; // @[RecFNToIN.scala:133:34, :134:32, :146:40] assign _io_intExceptionFlags_T_1 = {_io_intExceptionFlags_T, inexact}; // @[RecFNToIN.scala:135:52, :146:{40,52}] assign io_intExceptionFlags_0 = _io_intExceptionFlags_T_1; // @[RecFNToIN.scala:46:7, :146:52] assign io_intExceptionFlags = io_intExceptionFlags_0; // @[RecFNToIN.scala:46:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_93 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} inst input_buffer of InputBuffer_93 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) inst route_arbiter of Arbiter5_RouteComputerReq_21 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id connect route_arbiter.io.in[1].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[1].bits.flow.egress_node_id invalidate route_arbiter.io.in[1].bits.flow.egress_node invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id invalidate route_arbiter.io.in[1].bits.flow.ingress_node invalidate route_arbiter.io.in[1].bits.flow.vnet_id invalidate route_arbiter.io.in[1].bits.src_virt_id connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_9 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_9 : connect states[4].g, UInt<3>(0h2) node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5] wire vcalloc_vals : UInt<1>[5] node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23) node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_22 = or(_T_21, vcalloc_vals[2]) node _T_23 = or(_T_22, vcalloc_vals[3]) node _T_24 = or(_T_23, vcalloc_vals[4]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = bits(vcalloc_sel, 0, 0) node _mask_T_9 = bits(vcalloc_sel, 1, 1) node _mask_T_10 = bits(vcalloc_sel, 2, 2) node _mask_T_11 = bits(vcalloc_sel, 3, 3) node _mask_T_12 = bits(vcalloc_sel, 4, 4) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0)) node _mask_T_18 = or(_mask_T_13, _mask_T_14) node _mask_T_19 = or(_mask_T_18, _mask_T_15) node _mask_T_20 = or(_mask_T_19, _mask_T_16) node _mask_T_21 = or(_mask_T_20, _mask_T_17) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_21 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5] node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5] node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76 connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94 connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[5] node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_103 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121 connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123) node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124) node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130 connect _io_vcalloc_req_bits_WIRE_14[3], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139 connect _io_vcalloc_req_bits_WIRE_14[4], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_21 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_152) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_153) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_21.egress_node_id, _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_164 = or(_io_vcalloc_req_bits_T_163, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_165 = or(_io_vcalloc_req_bits_T_164, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_165, _io_vcalloc_req_bits_T_162) wire _io_vcalloc_req_bits_WIRE_23 : UInt<5> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_166 connect _io_vcalloc_req_bits_WIRE_21.egress_node, _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_175 connect _io_vcalloc_req_bits_WIRE_21.ingress_node_id, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_25 : UInt<5> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_184 connect _io_vcalloc_req_bits_WIRE_21.ingress_node, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_190, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_189) wire _io_vcalloc_req_bits_WIRE_26 : UInt<3> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_193 connect _io_vcalloc_req_bits_WIRE_21.vnet_id, _io_vcalloc_req_bits_WIRE_26 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_21 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id connect vcalloc_vals[1], UInt<1>(0h0) invalidate vcalloc_reqs[1].vc_sel.`0`[0] invalidate vcalloc_reqs[1].vc_sel.`0`[1] invalidate vcalloc_reqs[1].vc_sel.`0`[2] invalidate vcalloc_reqs[1].vc_sel.`0`[3] invalidate vcalloc_reqs[1].vc_sel.`0`[4] invalidate vcalloc_reqs[1].vc_sel.`1`[0] invalidate vcalloc_reqs[1].vc_sel.`1`[1] invalidate vcalloc_reqs[1].vc_sel.`1`[2] invalidate vcalloc_reqs[1].vc_sel.`1`[3] invalidate vcalloc_reqs[1].vc_sel.`1`[4] invalidate vcalloc_reqs[1].vc_sel.`2`[0] invalidate vcalloc_reqs[1].vc_sel.`2`[1] invalidate vcalloc_reqs[1].vc_sel.`2`[2] invalidate vcalloc_reqs[1].vc_sel.`2`[3] invalidate vcalloc_reqs[1].vc_sel.`2`[4] invalidate vcalloc_reqs[1].in_vc invalidate vcalloc_reqs[1].flow.egress_node_id invalidate vcalloc_reqs[1].flow.egress_node invalidate vcalloc_reqs[1].flow.ingress_node_id invalidate vcalloc_reqs[1].flow.ingress_node invalidate vcalloc_reqs[1].flow.vnet_id connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[3] invalidate vcalloc_reqs[2].vc_sel.`2`[4] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].vc_sel.`2`[0] invalidate vcalloc_reqs[3].vc_sel.`2`[1] invalidate vcalloc_reqs[3].vc_sel.`2`[2] invalidate vcalloc_reqs[3].vc_sel.`2`[3] invalidate vcalloc_reqs[3].vc_sel.`2`[4] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_25 = bits(vcalloc_sel, 4, 4) node _T_26 = and(vcalloc_vals[4], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[4].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready) node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1) connect io.debug.va_stall, _io_debug_va_stall_T_9 node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_28 : node _T_29 = bits(vcalloc_sel, 0, 0) when _T_29 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_30 = eq(states[0].g, UInt<3>(0h2)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_35 = eq(states[1].g, UInt<3>(0h2)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_35, UInt<1>(0h1), "") : assert_4 node _T_39 = bits(vcalloc_sel, 2, 2) when _T_39 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_40 = eq(states[2].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = bits(vcalloc_sel, 3, 3) when _T_44 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_45 = eq(states[3].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_45, UInt<1>(0h1), "") : assert_6 node _T_49 = bits(vcalloc_sel, 4, 4) when _T_49 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_50 = eq(states[4].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_50, UInt<1>(0h1), "") : assert_7 inst salloc_arb of SwitchArbiter_244 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] connect salloc_arb.io.in[1].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[1].bits.tail invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[4] connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[4] node credit_available_lo = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[4].vc_sel.`0`[4], states[4].vc_sel.`0`[3]) node credit_available_hi = cat(credit_available_hi_hi, states[4].vc_sel.`0`[2]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_hi_hi_1 = cat(states[4].vc_sel.`1`[4], states[4].vc_sel.`1`[3]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[4].vc_sel.`1`[2]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_2 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_hi_hi_2 = cat(states[4].vc_sel.`2`[4], states[4].vc_sel.`2`[3]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, states[4].vc_sel.`2`[2]) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[2]) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, io.out_credit_available.`1`[2]) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, io.out_credit_available.`2`[2]) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_54 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_55 = and(_T_54, input_buffer.io.deq[4].bits.tail) when _T_55 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_17 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7) node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14 node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_16 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _vc_sel_WIRE : UInt<1>[5] node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6) node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_13 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_22 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25) node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26) node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_31 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34) node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_40 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_49 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_6 : UInt<1>[5] node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_58 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_67 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70) node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71) node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_76 connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9 node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_85 connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_94 connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11 connect vc_sel.`1`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_12 : UInt<1>[5] node _vc_sel_T_95 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_96 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_97 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_98 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_100 = or(_vc_sel_T_95, _vc_sel_T_96) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_97) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_98) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_99) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_103 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 node _vc_sel_T_104 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_109 = or(_vc_sel_T_104, _vc_sel_T_105) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_106) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_107) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_108) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_112 connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_118 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_115) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_116) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_117) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_121 connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15 node _vc_sel_T_122 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_123 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_124 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_127 = or(_vc_sel_T_122, _vc_sel_T_123) node _vc_sel_T_128 = or(_vc_sel_T_127, _vc_sel_T_124) node _vc_sel_T_129 = or(_vc_sel_T_128, _vc_sel_T_125) node _vc_sel_T_130 = or(_vc_sel_T_129, _vc_sel_T_126) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_130 connect _vc_sel_WIRE_12[3], _vc_sel_WIRE_16 node _vc_sel_T_131 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_131, _vc_sel_T_132) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_133) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_134) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_135) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_139 connect _vc_sel_WIRE_12[4], _vc_sel_WIRE_17 connect vc_sel.`2`, _vc_sel_WIRE_12 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3]) node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4]) node _channel_oh_T_6 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`2`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`2`[3]) node channel_oh_2 = or(_channel_oh_T_8, vc_sel.`2`[4]) node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2]) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_6 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, vc_sel.`2`[2]) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 4, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node _virt_channel_T_24 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_25 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_26 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_27 = or(_virt_channel_T_24, _virt_channel_T_25) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_26) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_28 node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_56 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6) node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6) node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6) node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].g invalidate states[1].fifo_deps invalidate states[1].flow.egress_node_id invalidate states[1].flow.egress_node invalidate states[1].flow.ingress_node_id invalidate states[1].flow.ingress_node invalidate states[1].flow.vnet_id invalidate states[1].vc_sel.`0`[0] invalidate states[1].vc_sel.`0`[1] invalidate states[1].vc_sel.`0`[2] invalidate states[1].vc_sel.`0`[3] invalidate states[1].vc_sel.`0`[4] invalidate states[1].vc_sel.`1`[0] invalidate states[1].vc_sel.`1`[1] invalidate states[1].vc_sel.`1`[2] invalidate states[1].vc_sel.`1`[3] invalidate states[1].vc_sel.`1`[4] invalidate states[1].vc_sel.`2`[0] invalidate states[1].vc_sel.`2`[1] invalidate states[1].vc_sel.`2`[2] invalidate states[1].vc_sel.`2`[3] invalidate states[1].vc_sel.`2`[4] invalidate states[1].g invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`2`[3] invalidate states[2].vc_sel.`2`[4] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].vc_sel.`2`[0] invalidate states[3].vc_sel.`2`[1] invalidate states[3].vc_sel.`2`[2] invalidate states[3].vc_sel.`2`[3] invalidate states[3].vc_sel.`2`[4] invalidate states[3].g connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`0`[1], UInt<1>(0h0) connect states[4].vc_sel.`0`[2], UInt<1>(0h0) connect states[4].vc_sel.`0`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[2], UInt<1>(0h0) connect states[4].vc_sel.`2`[3], UInt<1>(0h0) node _T_57 = asUInt(reset) when _T_57 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0)
module InputUnit_93( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {vcalloc_vals_4, 4'h0} & ~mask; // @[InputUnit.scala:158:7, :250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {vcalloc_vals_4, 9'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_4; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_25 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, clock inst q of Queue3_EgressFlit_25 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<6>(0h10), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_25 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<6>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_26 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<6>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_27 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<6>(0h16), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_28 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<6>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_29 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<6>(0h19), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_30 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<6>(0h13), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_31 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<6>(0hd), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_32 = or(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_33 = or(_q_io_enq_bits_ingress_id_T_32, _q_io_enq_bits_ingress_id_T_26) node _q_io_enq_bits_ingress_id_T_34 = or(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_27) node _q_io_enq_bits_ingress_id_T_35 = or(_q_io_enq_bits_ingress_id_T_34, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_36 = or(_q_io_enq_bits_ingress_id_T_35, _q_io_enq_bits_ingress_id_T_29) node _q_io_enq_bits_ingress_id_T_37 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_30) node _q_io_enq_bits_ingress_id_T_38 = or(_q_io_enq_bits_ingress_id_T_37, _q_io_enq_bits_ingress_id_T_31) wire _q_io_enq_bits_ingress_id_WIRE : UInt<6> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_38 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_25( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [72:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [4:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [72:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_22 = io_in_0_bits_flow_ingress_node_id == 2'h1; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_103 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>} node _io_out_d_T = mul(io.in_a, io.in_b) node _io_out_d_T_1 = add(_io_out_d_T, io.in_c) node _io_out_d_T_2 = tail(_io_out_d_T_1, 1) node _io_out_d_T_3 = asSInt(_io_out_d_T_2) connect io.out_d, _io_out_d_T_3
module MacUnit_103( // @[PE.scala:14:7] input clock, // @[PE.scala:14:7] input reset, // @[PE.scala:14:7] input [7:0] io_in_a, // @[PE.scala:16:14] input [7:0] io_in_b, // @[PE.scala:16:14] input [31:0] io_in_c, // @[PE.scala:16:14] output [19:0] io_out_d // @[PE.scala:16:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7] wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7] wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7] wire [19:0] io_out_d_0; // @[PE.scala:14:7] wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7] wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7] wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54] wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54] assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12] assign io_out_d = io_out_d_0; // @[PE.scala:14:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_17 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<1>(0h0)) node mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<13>(0h1000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<30>(0h20000000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<15>(0h4000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_27, _T_32) node _T_69 = or(_T_68, _T_37) node _T_70 = or(_T_69, _T_42) node _T_71 = or(_T_70, _T_47) node _T_72 = or(_T_71, _T_52) node _T_73 = or(_T_72, _T_57) node _T_74 = or(_T_73, _T_62) node _T_75 = or(_T_74, _T_67) node _T_76 = and(_T_22, _T_75) node _T_77 = or(UInt<1>(0h0), _T_76) node _T_78 = and(_T_21, _T_77) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_78, UInt<1>(0h1), "") : assert_2 node _T_82 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_83 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_84 = and(_T_82, _T_83) node _T_85 = or(UInt<1>(0h0), _T_84) node _T_86 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<14>(0h2000))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<13>(0h1000))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<17>(0h10000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<18>(0h2f000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<27>(0h4000000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<13>(0h1000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<30>(0h20000000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<15>(0h4000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = or(_T_90, _T_95) node _T_132 = or(_T_131, _T_100) node _T_133 = or(_T_132, _T_105) node _T_134 = or(_T_133, _T_110) node _T_135 = or(_T_134, _T_115) node _T_136 = or(_T_135, _T_120) node _T_137 = or(_T_136, _T_125) node _T_138 = or(_T_137, _T_130) node _T_139 = and(_T_85, _T_138) node _T_140 = or(UInt<1>(0h0), _T_139) node _T_141 = and(UInt<1>(0h0), _T_140) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_141, UInt<1>(0h1), "") : assert_3 node _T_145 = asUInt(reset) node _T_146 = eq(_T_145, UInt<1>(0h0)) when _T_146 : node _T_147 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_147 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_148 = geq(io.in.a.bits.size, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_148, UInt<1>(0h1), "") : assert_5 node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(is_aligned, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_155 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_155, UInt<1>(0h1), "") : assert_7 node _T_159 = not(io.in.a.bits.mask) node _T_160 = eq(_T_159, UInt<1>(0h0)) node _T_161 = asUInt(reset) node _T_162 = eq(_T_161, UInt<1>(0h0)) when _T_162 : node _T_163 = eq(_T_160, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_160, UInt<1>(0h1), "") : assert_8 node _T_164 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_165 = asUInt(reset) node _T_166 = eq(_T_165, UInt<1>(0h0)) when _T_166 : node _T_167 = eq(_T_164, UInt<1>(0h0)) when _T_167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_164, UInt<1>(0h1), "") : assert_9 node _T_168 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_168 : node _T_169 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_170 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_171 = and(_T_169, _T_170) node _T_172 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_173 = and(_T_171, _T_172) node _T_174 = or(UInt<1>(0h0), _T_173) node _T_175 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_176 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_177 = cvt(_T_176) node _T_178 = and(_T_177, asSInt(UInt<14>(0h2000))) node _T_179 = asSInt(_T_178) node _T_180 = eq(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_182 = cvt(_T_181) node _T_183 = and(_T_182, asSInt(UInt<13>(0h1000))) node _T_184 = asSInt(_T_183) node _T_185 = eq(_T_184, asSInt(UInt<1>(0h0))) node _T_186 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<17>(0h10000))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<18>(0h2f000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<17>(0h10000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<27>(0h4000000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<13>(0h1000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<30>(0h20000000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<15>(0h4000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = or(_T_180, _T_185) node _T_222 = or(_T_221, _T_190) node _T_223 = or(_T_222, _T_195) node _T_224 = or(_T_223, _T_200) node _T_225 = or(_T_224, _T_205) node _T_226 = or(_T_225, _T_210) node _T_227 = or(_T_226, _T_215) node _T_228 = or(_T_227, _T_220) node _T_229 = and(_T_175, _T_228) node _T_230 = or(UInt<1>(0h0), _T_229) node _T_231 = and(_T_174, _T_230) node _T_232 = asUInt(reset) node _T_233 = eq(_T_232, UInt<1>(0h0)) when _T_233 : node _T_234 = eq(_T_231, UInt<1>(0h0)) when _T_234 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_231, UInt<1>(0h1), "") : assert_10 node _T_235 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_236 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_237 = and(_T_235, _T_236) node _T_238 = or(UInt<1>(0h0), _T_237) node _T_239 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<14>(0h2000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<13>(0h1000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h10000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<18>(0h2f000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<17>(0h10000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<27>(0h4000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_275 = cvt(_T_274) node _T_276 = and(_T_275, asSInt(UInt<30>(0h20000000))) node _T_277 = asSInt(_T_276) node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0))) node _T_279 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_280 = cvt(_T_279) node _T_281 = and(_T_280, asSInt(UInt<15>(0h4000))) node _T_282 = asSInt(_T_281) node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0))) node _T_284 = or(_T_243, _T_248) node _T_285 = or(_T_284, _T_253) node _T_286 = or(_T_285, _T_258) node _T_287 = or(_T_286, _T_263) node _T_288 = or(_T_287, _T_268) node _T_289 = or(_T_288, _T_273) node _T_290 = or(_T_289, _T_278) node _T_291 = or(_T_290, _T_283) node _T_292 = and(_T_238, _T_291) node _T_293 = or(UInt<1>(0h0), _T_292) node _T_294 = and(UInt<1>(0h0), _T_293) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_294, UInt<1>(0h1), "") : assert_11 node _T_298 = asUInt(reset) node _T_299 = eq(_T_298, UInt<1>(0h0)) when _T_299 : node _T_300 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_300 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_301 = geq(io.in.a.bits.size, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_301, UInt<1>(0h1), "") : assert_13 node _T_305 = asUInt(reset) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(is_aligned, UInt<1>(0h0)) when _T_307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_308 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_308, UInt<1>(0h1), "") : assert_15 node _T_312 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_T_312, UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_312, UInt<1>(0h1), "") : assert_16 node _T_316 = not(io.in.a.bits.mask) node _T_317 = eq(_T_316, UInt<1>(0h0)) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_317, UInt<1>(0h1), "") : assert_17 node _T_321 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_322 = asUInt(reset) node _T_323 = eq(_T_322, UInt<1>(0h0)) when _T_323 : node _T_324 = eq(_T_321, UInt<1>(0h0)) when _T_324 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_321, UInt<1>(0h1), "") : assert_18 node _T_325 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_325 : node _T_326 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_327 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_328 = and(_T_326, _T_327) node _T_329 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_330 = and(_T_328, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_331, UInt<1>(0h1), "") : assert_19 node _T_335 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_336 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_337 = and(_T_335, _T_336) node _T_338 = or(UInt<1>(0h0), _T_337) node _T_339 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<13>(0h1000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = and(_T_338, _T_343) node _T_345 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_346 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_347 = and(_T_345, _T_346) node _T_348 = or(UInt<1>(0h0), _T_347) node _T_349 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<14>(0h2000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<17>(0h10000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_360 = cvt(_T_359) node _T_361 = and(_T_360, asSInt(UInt<18>(0h2f000))) node _T_362 = asSInt(_T_361) node _T_363 = eq(_T_362, asSInt(UInt<1>(0h0))) node _T_364 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_365 = cvt(_T_364) node _T_366 = and(_T_365, asSInt(UInt<17>(0h10000))) node _T_367 = asSInt(_T_366) node _T_368 = eq(_T_367, asSInt(UInt<1>(0h0))) node _T_369 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<27>(0h4000000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_375 = cvt(_T_374) node _T_376 = and(_T_375, asSInt(UInt<13>(0h1000))) node _T_377 = asSInt(_T_376) node _T_378 = eq(_T_377, asSInt(UInt<1>(0h0))) node _T_379 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<30>(0h20000000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<15>(0h4000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = or(_T_353, _T_358) node _T_390 = or(_T_389, _T_363) node _T_391 = or(_T_390, _T_368) node _T_392 = or(_T_391, _T_373) node _T_393 = or(_T_392, _T_378) node _T_394 = or(_T_393, _T_383) node _T_395 = or(_T_394, _T_388) node _T_396 = and(_T_348, _T_395) node _T_397 = or(UInt<1>(0h0), _T_344) node _T_398 = or(_T_397, _T_396) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_398, UInt<1>(0h1), "") : assert_20 node _T_402 = asUInt(reset) node _T_403 = eq(_T_402, UInt<1>(0h0)) when _T_403 : node _T_404 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_404 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(is_aligned, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_408 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_409 = asUInt(reset) node _T_410 = eq(_T_409, UInt<1>(0h0)) when _T_410 : node _T_411 = eq(_T_408, UInt<1>(0h0)) when _T_411 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_408, UInt<1>(0h1), "") : assert_23 node _T_412 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_413 = asUInt(reset) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(_T_412, UInt<1>(0h0)) when _T_415 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_412, UInt<1>(0h1), "") : assert_24 node _T_416 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_416, UInt<1>(0h1), "") : assert_25 node _T_420 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_422 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_428 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_429 = and(_T_427, _T_428) node _T_430 = or(UInt<1>(0h0), _T_429) node _T_431 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_432 = cvt(_T_431) node _T_433 = and(_T_432, asSInt(UInt<13>(0h1000))) node _T_434 = asSInt(_T_433) node _T_435 = eq(_T_434, asSInt(UInt<1>(0h0))) node _T_436 = and(_T_430, _T_435) node _T_437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_438 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_439 = and(_T_437, _T_438) node _T_440 = or(UInt<1>(0h0), _T_439) node _T_441 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_442 = cvt(_T_441) node _T_443 = and(_T_442, asSInt(UInt<14>(0h2000))) node _T_444 = asSInt(_T_443) node _T_445 = eq(_T_444, asSInt(UInt<1>(0h0))) node _T_446 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_447 = cvt(_T_446) node _T_448 = and(_T_447, asSInt(UInt<18>(0h2f000))) node _T_449 = asSInt(_T_448) node _T_450 = eq(_T_449, asSInt(UInt<1>(0h0))) node _T_451 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_452 = cvt(_T_451) node _T_453 = and(_T_452, asSInt(UInt<17>(0h10000))) node _T_454 = asSInt(_T_453) node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0))) node _T_456 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_457 = cvt(_T_456) node _T_458 = and(_T_457, asSInt(UInt<27>(0h4000000))) node _T_459 = asSInt(_T_458) node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0))) node _T_461 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_462 = cvt(_T_461) node _T_463 = and(_T_462, asSInt(UInt<13>(0h1000))) node _T_464 = asSInt(_T_463) node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0))) node _T_466 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_467 = cvt(_T_466) node _T_468 = and(_T_467, asSInt(UInt<15>(0h4000))) node _T_469 = asSInt(_T_468) node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0))) node _T_471 = or(_T_445, _T_450) node _T_472 = or(_T_471, _T_455) node _T_473 = or(_T_472, _T_460) node _T_474 = or(_T_473, _T_465) node _T_475 = or(_T_474, _T_470) node _T_476 = and(_T_440, _T_475) node _T_477 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_478 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_479 = cvt(_T_478) node _T_480 = and(_T_479, asSInt(UInt<17>(0h10000))) node _T_481 = asSInt(_T_480) node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0))) node _T_483 = and(_T_477, _T_482) node _T_484 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_485 = leq(io.in.a.bits.size, UInt<4>(0h8)) node _T_486 = and(_T_484, _T_485) node _T_487 = or(UInt<1>(0h0), _T_486) node _T_488 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_489 = cvt(_T_488) node _T_490 = and(_T_489, asSInt(UInt<30>(0h20000000))) node _T_491 = asSInt(_T_490) node _T_492 = eq(_T_491, asSInt(UInt<1>(0h0))) node _T_493 = and(_T_487, _T_492) node _T_494 = or(UInt<1>(0h0), _T_436) node _T_495 = or(_T_494, _T_476) node _T_496 = or(_T_495, _T_483) node _T_497 = or(_T_496, _T_493) node _T_498 = and(_T_426, _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_498, UInt<1>(0h1), "") : assert_26 node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(is_aligned, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_508 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_508, UInt<1>(0h1), "") : assert_29 node _T_512 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_512, UInt<1>(0h1), "") : assert_30 node _T_516 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_516 : node _T_517 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_518 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_519 = and(_T_517, _T_518) node _T_520 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_521 = and(_T_519, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_524 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_525 = and(_T_523, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<13>(0h1000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = and(_T_526, _T_531) node _T_533 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_534 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_535 = and(_T_533, _T_534) node _T_536 = or(UInt<1>(0h0), _T_535) node _T_537 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<14>(0h2000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<18>(0h2f000))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<17>(0h10000))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_553 = cvt(_T_552) node _T_554 = and(_T_553, asSInt(UInt<27>(0h4000000))) node _T_555 = asSInt(_T_554) node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0))) node _T_557 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<13>(0h1000))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<15>(0h4000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = or(_T_541, _T_546) node _T_568 = or(_T_567, _T_551) node _T_569 = or(_T_568, _T_556) node _T_570 = or(_T_569, _T_561) node _T_571 = or(_T_570, _T_566) node _T_572 = and(_T_536, _T_571) node _T_573 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_574 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<17>(0h10000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = and(_T_573, _T_578) node _T_580 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_581 = leq(io.in.a.bits.size, UInt<4>(0h8)) node _T_582 = and(_T_580, _T_581) node _T_583 = or(UInt<1>(0h0), _T_582) node _T_584 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<30>(0h20000000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = and(_T_583, _T_588) node _T_590 = or(UInt<1>(0h0), _T_532) node _T_591 = or(_T_590, _T_572) node _T_592 = or(_T_591, _T_579) node _T_593 = or(_T_592, _T_589) node _T_594 = and(_T_522, _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_594, UInt<1>(0h1), "") : assert_31 node _T_598 = asUInt(reset) node _T_599 = eq(_T_598, UInt<1>(0h0)) when _T_599 : node _T_600 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_600 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_601 = asUInt(reset) node _T_602 = eq(_T_601, UInt<1>(0h0)) when _T_602 : node _T_603 = eq(is_aligned, UInt<1>(0h0)) when _T_603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_604 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_605 = asUInt(reset) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(_T_604, UInt<1>(0h0)) when _T_607 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_604, UInt<1>(0h1), "") : assert_34 node _T_608 = not(UInt<1>(0h1)) node _T_609 = and(io.in.a.bits.mask, _T_608) node _T_610 = eq(_T_609, UInt<1>(0h0)) node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_T_610, UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_610, UInt<1>(0h1), "") : assert_35 node _T_614 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_614 : node _T_615 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_616 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_617 = and(_T_615, _T_616) node _T_618 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_619 = and(_T_617, _T_618) node _T_620 = or(UInt<1>(0h0), _T_619) node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_622 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_623 = and(_T_621, _T_622) node _T_624 = or(UInt<1>(0h0), _T_623) node _T_625 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_626 = cvt(_T_625) node _T_627 = and(_T_626, asSInt(UInt<14>(0h2000))) node _T_628 = asSInt(_T_627) node _T_629 = eq(_T_628, asSInt(UInt<1>(0h0))) node _T_630 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_631 = cvt(_T_630) node _T_632 = and(_T_631, asSInt(UInt<13>(0h1000))) node _T_633 = asSInt(_T_632) node _T_634 = eq(_T_633, asSInt(UInt<1>(0h0))) node _T_635 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_636 = cvt(_T_635) node _T_637 = and(_T_636, asSInt(UInt<18>(0h2f000))) node _T_638 = asSInt(_T_637) node _T_639 = eq(_T_638, asSInt(UInt<1>(0h0))) node _T_640 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_641 = cvt(_T_640) node _T_642 = and(_T_641, asSInt(UInt<17>(0h10000))) node _T_643 = asSInt(_T_642) node _T_644 = eq(_T_643, asSInt(UInt<1>(0h0))) node _T_645 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_646 = cvt(_T_645) node _T_647 = and(_T_646, asSInt(UInt<27>(0h4000000))) node _T_648 = asSInt(_T_647) node _T_649 = eq(_T_648, asSInt(UInt<1>(0h0))) node _T_650 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_651 = cvt(_T_650) node _T_652 = and(_T_651, asSInt(UInt<13>(0h1000))) node _T_653 = asSInt(_T_652) node _T_654 = eq(_T_653, asSInt(UInt<1>(0h0))) node _T_655 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_656 = cvt(_T_655) node _T_657 = and(_T_656, asSInt(UInt<15>(0h4000))) node _T_658 = asSInt(_T_657) node _T_659 = eq(_T_658, asSInt(UInt<1>(0h0))) node _T_660 = or(_T_629, _T_634) node _T_661 = or(_T_660, _T_639) node _T_662 = or(_T_661, _T_644) node _T_663 = or(_T_662, _T_649) node _T_664 = or(_T_663, _T_654) node _T_665 = or(_T_664, _T_659) node _T_666 = and(_T_624, _T_665) node _T_667 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_668 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<17>(0h10000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<30>(0h20000000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = or(_T_672, _T_677) node _T_679 = and(_T_667, _T_678) node _T_680 = or(UInt<1>(0h0), _T_666) node _T_681 = or(_T_680, _T_679) node _T_682 = and(_T_620, _T_681) node _T_683 = asUInt(reset) node _T_684 = eq(_T_683, UInt<1>(0h0)) when _T_684 : node _T_685 = eq(_T_682, UInt<1>(0h0)) when _T_685 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_682, UInt<1>(0h1), "") : assert_36 node _T_686 = asUInt(reset) node _T_687 = eq(_T_686, UInt<1>(0h0)) when _T_687 : node _T_688 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_689 = asUInt(reset) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(is_aligned, UInt<1>(0h0)) when _T_691 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_692 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(_T_692, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_692, UInt<1>(0h1), "") : assert_39 node _T_696 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_696, UInt<1>(0h1), "") : assert_40 node _T_700 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_700 : node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_702 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_703 = and(_T_701, _T_702) node _T_704 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_705 = and(_T_703, _T_704) node _T_706 = or(UInt<1>(0h0), _T_705) node _T_707 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_708 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_709 = and(_T_707, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<14>(0h2000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<13>(0h1000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<18>(0h2f000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<27>(0h4000000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<13>(0h1000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<15>(0h4000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = or(_T_715, _T_720) node _T_747 = or(_T_746, _T_725) node _T_748 = or(_T_747, _T_730) node _T_749 = or(_T_748, _T_735) node _T_750 = or(_T_749, _T_740) node _T_751 = or(_T_750, _T_745) node _T_752 = and(_T_710, _T_751) node _T_753 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_754 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<17>(0h10000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<30>(0h20000000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = or(_T_758, _T_763) node _T_765 = and(_T_753, _T_764) node _T_766 = or(UInt<1>(0h0), _T_752) node _T_767 = or(_T_766, _T_765) node _T_768 = and(_T_706, _T_767) node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(_T_768, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_768, UInt<1>(0h1), "") : assert_41 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(is_aligned, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_778 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_778, UInt<1>(0h1), "") : assert_44 node _T_782 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_782, UInt<1>(0h1), "") : assert_45 node _T_786 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_786 : node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_791 = and(_T_789, _T_790) node _T_792 = or(UInt<1>(0h0), _T_791) node _T_793 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_794 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_795 = and(_T_793, _T_794) node _T_796 = or(UInt<1>(0h0), _T_795) node _T_797 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<13>(0h1000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_804 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_805 = cvt(_T_804) node _T_806 = and(_T_805, asSInt(UInt<14>(0h2000))) node _T_807 = asSInt(_T_806) node _T_808 = eq(_T_807, asSInt(UInt<1>(0h0))) node _T_809 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_810 = cvt(_T_809) node _T_811 = and(_T_810, asSInt(UInt<17>(0h10000))) node _T_812 = asSInt(_T_811) node _T_813 = eq(_T_812, asSInt(UInt<1>(0h0))) node _T_814 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_815 = cvt(_T_814) node _T_816 = and(_T_815, asSInt(UInt<18>(0h2f000))) node _T_817 = asSInt(_T_816) node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0))) node _T_819 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_820 = cvt(_T_819) node _T_821 = and(_T_820, asSInt(UInt<17>(0h10000))) node _T_822 = asSInt(_T_821) node _T_823 = eq(_T_822, asSInt(UInt<1>(0h0))) node _T_824 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_825 = cvt(_T_824) node _T_826 = and(_T_825, asSInt(UInt<27>(0h4000000))) node _T_827 = asSInt(_T_826) node _T_828 = eq(_T_827, asSInt(UInt<1>(0h0))) node _T_829 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<13>(0h1000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.a.bits.address, UInt<31>(0h60000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<30>(0h20000000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_840 = cvt(_T_839) node _T_841 = and(_T_840, asSInt(UInt<15>(0h4000))) node _T_842 = asSInt(_T_841) node _T_843 = eq(_T_842, asSInt(UInt<1>(0h0))) node _T_844 = or(_T_808, _T_813) node _T_845 = or(_T_844, _T_818) node _T_846 = or(_T_845, _T_823) node _T_847 = or(_T_846, _T_828) node _T_848 = or(_T_847, _T_833) node _T_849 = or(_T_848, _T_838) node _T_850 = or(_T_849, _T_843) node _T_851 = and(_T_803, _T_850) node _T_852 = or(UInt<1>(0h0), _T_802) node _T_853 = or(_T_852, _T_851) node _T_854 = and(_T_792, _T_853) node _T_855 = asUInt(reset) node _T_856 = eq(_T_855, UInt<1>(0h0)) when _T_856 : node _T_857 = eq(_T_854, UInt<1>(0h0)) when _T_857 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_854, UInt<1>(0h1), "") : assert_46 node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_861 = asUInt(reset) node _T_862 = eq(_T_861, UInt<1>(0h0)) when _T_862 : node _T_863 = eq(is_aligned, UInt<1>(0h0)) when _T_863 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_864 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_865 = asUInt(reset) node _T_866 = eq(_T_865, UInt<1>(0h0)) when _T_866 : node _T_867 = eq(_T_864, UInt<1>(0h0)) when _T_867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_864, UInt<1>(0h1), "") : assert_49 node _T_868 = eq(io.in.a.bits.mask, UInt<1>(0h1)) node _T_869 = asUInt(reset) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(_T_868, UInt<1>(0h0)) when _T_871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_868, UInt<1>(0h1), "") : assert_50 node _T_872 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_873 = asUInt(reset) node _T_874 = eq(_T_873, UInt<1>(0h0)) when _T_874 : node _T_875 = eq(_T_872, UInt<1>(0h0)) when _T_875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_872, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_876 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_877 = asUInt(reset) node _T_878 = eq(_T_877, UInt<1>(0h0)) when _T_878 : node _T_879 = eq(_T_876, UInt<1>(0h0)) when _T_879 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_876, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_880 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_880 : node _T_881 = asUInt(reset) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_883 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_884 = geq(io.in.d.bits.size, UInt<1>(0h0)) node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(_T_884, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_884, UInt<1>(0h1), "") : assert_54 node _T_888 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_888, UInt<1>(0h1), "") : assert_55 node _T_892 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_892, UInt<1>(0h1), "") : assert_56 node _T_896 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_896, UInt<1>(0h1), "") : assert_57 node _T_900 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_900 : node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(sink_ok, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_907 = geq(io.in.d.bits.size, UInt<1>(0h0)) node _T_908 = asUInt(reset) node _T_909 = eq(_T_908, UInt<1>(0h0)) when _T_909 : node _T_910 = eq(_T_907, UInt<1>(0h0)) when _T_910 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_907, UInt<1>(0h1), "") : assert_60 node _T_911 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_912 = asUInt(reset) node _T_913 = eq(_T_912, UInt<1>(0h0)) when _T_913 : node _T_914 = eq(_T_911, UInt<1>(0h0)) when _T_914 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_911, UInt<1>(0h1), "") : assert_61 node _T_915 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_915, UInt<1>(0h1), "") : assert_62 node _T_919 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_920 = asUInt(reset) node _T_921 = eq(_T_920, UInt<1>(0h0)) when _T_921 : node _T_922 = eq(_T_919, UInt<1>(0h0)) when _T_922 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_919, UInt<1>(0h1), "") : assert_63 node _T_923 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_924 = or(UInt<1>(0h1), _T_923) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_924, UInt<1>(0h1), "") : assert_64 node _T_928 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_928 : node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(sink_ok, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_935 = geq(io.in.d.bits.size, UInt<1>(0h0)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_935, UInt<1>(0h1), "") : assert_67 node _T_939 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_939, UInt<1>(0h1), "") : assert_68 node _T_943 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_943, UInt<1>(0h1), "") : assert_69 node _T_947 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_948 = or(_T_947, io.in.d.bits.corrupt) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_948, UInt<1>(0h1), "") : assert_70 node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_953 = or(UInt<1>(0h1), _T_952) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_953, UInt<1>(0h1), "") : assert_71 node _T_957 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_957 : node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_961 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_T_961, UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_961, UInt<1>(0h1), "") : assert_73 node _T_965 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_966 = asUInt(reset) node _T_967 = eq(_T_966, UInt<1>(0h0)) when _T_967 : node _T_968 = eq(_T_965, UInt<1>(0h0)) when _T_968 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_965, UInt<1>(0h1), "") : assert_74 node _T_969 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_970 = or(UInt<1>(0h1), _T_969) node _T_971 = asUInt(reset) node _T_972 = eq(_T_971, UInt<1>(0h0)) when _T_972 : node _T_973 = eq(_T_970, UInt<1>(0h0)) when _T_973 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_970, UInt<1>(0h1), "") : assert_75 node _T_974 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_974 : node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_978 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_978, UInt<1>(0h1), "") : assert_77 node _T_982 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_983 = or(_T_982, io.in.d.bits.corrupt) node _T_984 = asUInt(reset) node _T_985 = eq(_T_984, UInt<1>(0h0)) when _T_985 : node _T_986 = eq(_T_983, UInt<1>(0h0)) when _T_986 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_983, UInt<1>(0h1), "") : assert_78 node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_988 = or(UInt<1>(0h1), _T_987) node _T_989 = asUInt(reset) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(_T_988, UInt<1>(0h0)) when _T_991 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_988, UInt<1>(0h1), "") : assert_79 node _T_992 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_992 : node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_996 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_996, UInt<1>(0h1), "") : assert_81 node _T_1000 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_82 node _T_1004 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1005 = or(UInt<1>(0h1), _T_1004) node _T_1006 = asUInt(reset) node _T_1007 = eq(_T_1006, UInt<1>(0h0)) when _T_1007 : node _T_1008 = eq(_T_1005, UInt<1>(0h0)) when _T_1008 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1005, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1009 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1013 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1017 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1018 = asUInt(reset) node _T_1019 = eq(_T_1018, UInt<1>(0h0)) when _T_1019 : node _T_1020 = eq(_T_1017, UInt<1>(0h0)) when _T_1020 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1017, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 0) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<12>, clock, reset, UInt<12>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1021 = eq(a_first, UInt<1>(0h0)) node _T_1022 = and(io.in.a.valid, _T_1021) when _T_1022 : node _T_1023 = eq(io.in.a.bits.opcode, opcode) node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(_T_1023, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1023, UInt<1>(0h1), "") : assert_87 node _T_1027 = eq(io.in.a.bits.param, param) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_88 node _T_1031 = eq(io.in.a.bits.size, size) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_89 node _T_1035 = eq(io.in.a.bits.source, source) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_90 node _T_1039 = eq(io.in.a.bits.address, address) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_91 node _T_1043 = and(io.in.a.ready, io.in.a.valid) node _T_1044 = and(_T_1043, a_first) when _T_1044 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 0) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1045 = eq(d_first, UInt<1>(0h0)) node _T_1046 = and(io.in.d.valid, _T_1045) when _T_1046 : node _T_1047 = eq(io.in.d.bits.opcode, opcode_1) node _T_1048 = asUInt(reset) node _T_1049 = eq(_T_1048, UInt<1>(0h0)) when _T_1049 : node _T_1050 = eq(_T_1047, UInt<1>(0h0)) when _T_1050 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1047, UInt<1>(0h1), "") : assert_92 node _T_1051 = eq(io.in.d.bits.param, param_1) node _T_1052 = asUInt(reset) node _T_1053 = eq(_T_1052, UInt<1>(0h0)) when _T_1053 : node _T_1054 = eq(_T_1051, UInt<1>(0h0)) when _T_1054 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1051, UInt<1>(0h1), "") : assert_93 node _T_1055 = eq(io.in.d.bits.size, size_1) node _T_1056 = asUInt(reset) node _T_1057 = eq(_T_1056, UInt<1>(0h0)) when _T_1057 : node _T_1058 = eq(_T_1055, UInt<1>(0h0)) when _T_1058 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1055, UInt<1>(0h1), "") : assert_94 node _T_1059 = eq(io.in.d.bits.source, source_1) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_95 node _T_1063 = eq(io.in.d.bits.sink, sink) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_96 node _T_1067 = eq(io.in.d.bits.denied, denied) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_97 node _T_1071 = and(io.in.d.ready, io.in.d.valid) node _T_1072 = and(_T_1071, d_first) when _T_1072 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 0) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<12>, clock, reset, UInt<12>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 0) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1073 = and(io.in.a.valid, a_first_1) node _T_1074 = and(_T_1073, UInt<1>(0h1)) when _T_1074 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1075 = and(io.in.a.ready, io.in.a.valid) node _T_1076 = and(_T_1075, a_first_1) node _T_1077 = and(_T_1076, UInt<1>(0h1)) when _T_1077 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1078 = dshr(inflight, io.in.a.bits.source) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1084 = and(io.in.d.valid, d_first_1) node _T_1085 = and(_T_1084, UInt<1>(0h1)) node _T_1086 = eq(d_release_ack, UInt<1>(0h0)) node _T_1087 = and(_T_1085, _T_1086) when _T_1087 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1088 = and(io.in.d.ready, io.in.d.valid) node _T_1089 = and(_T_1088, d_first_1) node _T_1090 = and(_T_1089, UInt<1>(0h1)) node _T_1091 = eq(d_release_ack, UInt<1>(0h0)) node _T_1092 = and(_T_1090, _T_1091) when _T_1092 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1093 = and(io.in.d.valid, d_first_1) node _T_1094 = and(_T_1093, UInt<1>(0h1)) node _T_1095 = eq(d_release_ack, UInt<1>(0h0)) node _T_1096 = and(_T_1094, _T_1095) when _T_1096 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1097 = dshr(inflight, io.in.d.bits.source) node _T_1098 = bits(_T_1097, 0, 0) node _T_1099 = or(_T_1098, same_cycle_resp) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1103 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1104 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1105 = or(_T_1103, _T_1104) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_100 node _T_1109 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_T_1109, UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1109, UInt<1>(0h1), "") : assert_101 else : node _T_1113 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1114 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1115 = or(_T_1113, _T_1114) node _T_1116 = asUInt(reset) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) when _T_1117 : node _T_1118 = eq(_T_1115, UInt<1>(0h0)) when _T_1118 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1115, UInt<1>(0h1), "") : assert_102 node _T_1119 = eq(io.in.d.bits.size, a_size_lookup) node _T_1120 = asUInt(reset) node _T_1121 = eq(_T_1120, UInt<1>(0h0)) when _T_1121 : node _T_1122 = eq(_T_1119, UInt<1>(0h0)) when _T_1122 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1119, UInt<1>(0h1), "") : assert_103 node _T_1123 = and(io.in.d.valid, d_first_1) node _T_1124 = and(_T_1123, a_first_1) node _T_1125 = and(_T_1124, io.in.a.valid) node _T_1126 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1127 = and(_T_1125, _T_1126) node _T_1128 = eq(d_release_ack, UInt<1>(0h0)) node _T_1129 = and(_T_1127, _T_1128) when _T_1129 : node _T_1130 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1131 = or(_T_1130, io.in.a.ready) node _T_1132 = asUInt(reset) node _T_1133 = eq(_T_1132, UInt<1>(0h0)) when _T_1133 : node _T_1134 = eq(_T_1131, UInt<1>(0h0)) when _T_1134 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1131, UInt<1>(0h1), "") : assert_104 node _T_1135 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1136 = orr(a_set_wo_ready) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) node _T_1138 = or(_T_1135, _T_1137) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_34 node _T_1142 = orr(inflight) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) node _T_1144 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1145 = or(_T_1143, _T_1144) node _T_1146 = lt(watchdog, plusarg_reader.out) node _T_1147 = or(_T_1145, _T_1146) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1151 = and(io.in.a.ready, io.in.a.valid) node _T_1152 = and(io.in.d.ready, io.in.d.valid) node _T_1153 = or(_T_1151, _T_1152) when _T_1153 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<8>(0h0) connect _c_first_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<8>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 0) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<12>, clock, reset, UInt<12>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 0) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<12>, clock, reset, UInt<12>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<8>(0h0) connect _WIRE_6.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_6.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1154 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<8>(0h0) connect _WIRE_8.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_8.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1155 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1156 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1157 = and(_T_1155, _T_1156) node _T_1158 = and(_T_1154, _T_1157) when _T_1158 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<8>(0h0) connect _WIRE_10.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_10.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1159 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1160 = and(_T_1159, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<8>(0h0) connect _WIRE_12.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_12.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1161 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1162 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = and(_T_1160, _T_1163) when _T_1164 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<8>(0h0) connect _c_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<8>(0h0) connect _WIRE_14.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_14.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1165 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1166 = bits(_T_1165, 0, 0) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1171 = and(io.in.d.valid, d_first_2) node _T_1172 = and(_T_1171, UInt<1>(0h1)) node _T_1173 = and(_T_1172, d_release_ack_1) when _T_1173 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1174 = and(io.in.d.ready, io.in.d.valid) node _T_1175 = and(_T_1174, d_first_2) node _T_1176 = and(_T_1175, UInt<1>(0h1)) node _T_1177 = and(_T_1176, d_release_ack_1) when _T_1177 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1178 = and(io.in.d.valid, d_first_2) node _T_1179 = and(_T_1178, UInt<1>(0h1)) node _T_1180 = and(_T_1179, d_release_ack_1) when _T_1180 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.secure, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1181 = dshr(inflight_1, io.in.d.bits.source) node _T_1182 = bits(_T_1181, 0, 0) node _T_1183 = or(_T_1182, same_cycle_resp_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<8>(0h0) connect _WIRE_16.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_16.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1187 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_109 else : node _T_1191 = eq(io.in.d.bits.size, c_size_lookup) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_110 node _T_1195 = and(io.in.d.valid, d_first_2) node _T_1196 = and(_T_1195, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<8>(0h0) connect _WIRE_18.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_18.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1197 = and(_T_1196, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<8>(0h0) connect _WIRE_20.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_20.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1198 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = and(_T_1199, d_release_ack_1) node _T_1201 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1202 = and(_T_1200, _T_1201) when _T_1202 : node _T_1203 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<8>(0h0) connect _WIRE_22.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_22.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1204 = or(_T_1203, _WIRE_23.ready) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_111 node _T_1208 = orr(c_set_wo_ready) when _T_1208 : node _T_1209 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_35 node _T_1213 = orr(inflight_1) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog_1, plusarg_reader_1.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Periphery.scala:99:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<8>(0h0) connect _WIRE_24.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_24.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1222 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_17( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_bufferable = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_modifiable = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_readalloc = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_writealloc = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_fetch = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_bufferable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_modifiable = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_readalloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_writealloc = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_privileged = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_secure = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire io_in_a_bits_user_amba_prot_privileged = 1'h1; // @[Monitor.scala:36:7] wire io_in_a_bits_user_amba_prot_secure = 1'h1; // @[Monitor.scala:36:7] wire io_in_a_bits_mask = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sizeOH = 1'h1; // @[Misc.scala:202:81] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [30:0] _d_sizes_clr_T_5 = 31'hFF; // @[Monitor.scala:681:74] wire [30:0] _d_sizes_clr_T_11 = 31'hFF; // @[Monitor.scala:791:74] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] c_first_beats1_decode = 12'h0; // @[Edges.scala:220:59] wire [11:0] c_first_beats1 = 12'h0; // @[Edges.scala:221:14] wire [11:0] _c_first_count_T = 12'h0; // @[Edges.scala:234:27] wire [11:0] c_first_count = 12'h0; // @[Edges.scala:234:25] wire [11:0] _c_first_counter_T = 12'h0; // @[Edges.scala:236:21] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [11:0] c_first_counter1 = 12'hFFF; // @[Edges.scala:230:28] wire [12:0] _c_first_counter1_T = 13'h1FFF; // @[Edges.scala:230:28] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [7:0] _c_set_wo_ready_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_data = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_data = 8'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire _T_1151 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1151; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1151; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode = _a_first_beats1_decode_T_2; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T = {1'h0, a_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1 = _a_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1224 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1224; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1224; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1224; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode = _d_first_beats1_decode_T_2; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [11:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T = {1'h0, d_first_counter} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1 = _d_first_counter1_T[11:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [7:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [11:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 12'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [11:0] a_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] a_first_counter1_1 = _a_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5; // @[package.scala:243:46] wire [11:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_1; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_1 = _d_first_counter1_T_1[11:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_1074 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_1074; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_1074; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_1151 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = a_set ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:{28,59}] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_1 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_1; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_1; // @[Monitor.scala:673:46, :783:46] wire _T_1123 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_1123 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_1224 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_opcodes_clr = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_sizes_clr = {8{d_clr}}; // @[Monitor.scala:664:34, :670:31, :678:89, :681:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [11:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8; // @[package.scala:243:46] wire [11:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 12'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [11:0] d_first_counter_2; // @[Edges.scala:229:27] wire [12:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 13'h1; // @[Edges.scala:229:27, :230:28] wire [11:0] d_first_counter1_2 = _d_first_counter1_T_2[11:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 12'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 12'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 12'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [11:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [11:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [11:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1195 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1195 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_1224 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_opcodes_clr_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_sizes_clr_1 = {8{d_clr_1}}; // @[Monitor.scala:774:34, :777:34, :788:88, :791:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_344( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFMToRaw_small_e11_s53_2 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} inst divSqrtRawFN of DivSqrtRawFN_small_e11_s53_2 connect divSqrtRawFN.clock, clock connect divSqrtRawFN.reset, reset connect io.inReady, divSqrtRawFN.io.inReady connect divSqrtRawFN.io.inValid, io.inValid connect divSqrtRawFN.io.sqrtOp, io.sqrtOp node divSqrtRawFN_io_a_exp = bits(io.a, 63, 52) node _divSqrtRawFN_io_a_isZero_T = bits(divSqrtRawFN_io_a_exp, 11, 9) node divSqrtRawFN_io_a_isZero = eq(_divSqrtRawFN_io_a_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_isSpecial_T = bits(divSqrtRawFN_io_a_exp, 11, 10) node divSqrtRawFN_io_a_isSpecial = eq(_divSqrtRawFN_io_a_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _divSqrtRawFN_io_a_out_isNaN_T = bits(divSqrtRawFN_io_a_exp, 9, 9) node _divSqrtRawFN_io_a_out_isNaN_T_1 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isNaN_T) connect divSqrtRawFN_io_a_out.isNaN, _divSqrtRawFN_io_a_out_isNaN_T_1 node _divSqrtRawFN_io_a_out_isInf_T = bits(divSqrtRawFN_io_a_exp, 9, 9) node _divSqrtRawFN_io_a_out_isInf_T_1 = eq(_divSqrtRawFN_io_a_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_isInf_T_2 = and(divSqrtRawFN_io_a_isSpecial, _divSqrtRawFN_io_a_out_isInf_T_1) connect divSqrtRawFN_io_a_out.isInf, _divSqrtRawFN_io_a_out_isInf_T_2 connect divSqrtRawFN_io_a_out.isZero, divSqrtRawFN_io_a_isZero node _divSqrtRawFN_io_a_out_sign_T = bits(io.a, 64, 64) connect divSqrtRawFN_io_a_out.sign, _divSqrtRawFN_io_a_out_sign_T node _divSqrtRawFN_io_a_out_sExp_T = cvt(divSqrtRawFN_io_a_exp) connect divSqrtRawFN_io_a_out.sExp, _divSqrtRawFN_io_a_out_sExp_T node _divSqrtRawFN_io_a_out_sig_T = eq(divSqrtRawFN_io_a_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_a_out_sig_T) node _divSqrtRawFN_io_a_out_sig_T_2 = bits(io.a, 51, 0) node _divSqrtRawFN_io_a_out_sig_T_3 = cat(_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2) connect divSqrtRawFN_io_a_out.sig, _divSqrtRawFN_io_a_out_sig_T_3 connect divSqrtRawFN.io.a.sig, divSqrtRawFN_io_a_out.sig connect divSqrtRawFN.io.a.sExp, divSqrtRawFN_io_a_out.sExp connect divSqrtRawFN.io.a.sign, divSqrtRawFN_io_a_out.sign connect divSqrtRawFN.io.a.isZero, divSqrtRawFN_io_a_out.isZero connect divSqrtRawFN.io.a.isInf, divSqrtRawFN_io_a_out.isInf connect divSqrtRawFN.io.a.isNaN, divSqrtRawFN_io_a_out.isNaN node divSqrtRawFN_io_b_exp = bits(io.b, 63, 52) node _divSqrtRawFN_io_b_isZero_T = bits(divSqrtRawFN_io_b_exp, 11, 9) node divSqrtRawFN_io_b_isZero = eq(_divSqrtRawFN_io_b_isZero_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_isSpecial_T = bits(divSqrtRawFN_io_b_exp, 11, 10) node divSqrtRawFN_io_b_isSpecial = eq(_divSqrtRawFN_io_b_isSpecial_T, UInt<2>(0h3)) wire divSqrtRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _divSqrtRawFN_io_b_out_isNaN_T = bits(divSqrtRawFN_io_b_exp, 9, 9) node _divSqrtRawFN_io_b_out_isNaN_T_1 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isNaN_T) connect divSqrtRawFN_io_b_out.isNaN, _divSqrtRawFN_io_b_out_isNaN_T_1 node _divSqrtRawFN_io_b_out_isInf_T = bits(divSqrtRawFN_io_b_exp, 9, 9) node _divSqrtRawFN_io_b_out_isInf_T_1 = eq(_divSqrtRawFN_io_b_out_isInf_T, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_isInf_T_2 = and(divSqrtRawFN_io_b_isSpecial, _divSqrtRawFN_io_b_out_isInf_T_1) connect divSqrtRawFN_io_b_out.isInf, _divSqrtRawFN_io_b_out_isInf_T_2 connect divSqrtRawFN_io_b_out.isZero, divSqrtRawFN_io_b_isZero node _divSqrtRawFN_io_b_out_sign_T = bits(io.b, 64, 64) connect divSqrtRawFN_io_b_out.sign, _divSqrtRawFN_io_b_out_sign_T node _divSqrtRawFN_io_b_out_sExp_T = cvt(divSqrtRawFN_io_b_exp) connect divSqrtRawFN_io_b_out.sExp, _divSqrtRawFN_io_b_out_sExp_T node _divSqrtRawFN_io_b_out_sig_T = eq(divSqrtRawFN_io_b_isZero, UInt<1>(0h0)) node _divSqrtRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _divSqrtRawFN_io_b_out_sig_T) node _divSqrtRawFN_io_b_out_sig_T_2 = bits(io.b, 51, 0) node _divSqrtRawFN_io_b_out_sig_T_3 = cat(_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2) connect divSqrtRawFN_io_b_out.sig, _divSqrtRawFN_io_b_out_sig_T_3 connect divSqrtRawFN.io.b.sig, divSqrtRawFN_io_b_out.sig connect divSqrtRawFN.io.b.sExp, divSqrtRawFN_io_b_out.sExp connect divSqrtRawFN.io.b.sign, divSqrtRawFN_io_b_out.sign connect divSqrtRawFN.io.b.isZero, divSqrtRawFN_io_b_out.isZero connect divSqrtRawFN.io.b.isInf, divSqrtRawFN_io_b_out.isInf connect divSqrtRawFN.io.b.isNaN, divSqrtRawFN_io_b_out.isNaN connect divSqrtRawFN.io.roundingMode, io.roundingMode connect io.rawOutValid_div, divSqrtRawFN.io.rawOutValid_div connect io.rawOutValid_sqrt, divSqrtRawFN.io.rawOutValid_sqrt connect io.roundingModeOut, divSqrtRawFN.io.roundingModeOut connect io.invalidExc, divSqrtRawFN.io.invalidExc connect io.infiniteExc, divSqrtRawFN.io.infiniteExc connect io.rawOut, divSqrtRawFN.io.rawOut
module DivSqrtRecFMToRaw_small_e11_s53_2( // @[DivSqrtRecFN_small.scala:422:5] input clock, // @[DivSqrtRecFN_small.scala:422:5] input reset, // @[DivSqrtRecFN_small.scala:422:5] output io_inReady, // @[DivSqrtRecFN_small.scala:426:16] input io_inValid, // @[DivSqrtRecFN_small.scala:426:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:426:16] input [64:0] io_a, // @[DivSqrtRecFN_small.scala:426:16] input [64:0] io_b, // @[DivSqrtRecFN_small.scala:426:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:426:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:426:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:426:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:426:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:426:16] output [12:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:426:16] output [55:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:426:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:422:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:422:5] wire [64:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:422:5] wire [64:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] wire [12:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] wire [55:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] wire [11:0] divSqrtRawFN_io_a_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_a_isZero_T = divSqrtRawFN_io_a_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_a_isZero = _divSqrtRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_a_out_isZero = divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_a_isSpecial_T = divSqrtRawFN_io_a_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_a_isSpecial = &_divSqrtRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] divSqrtRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] divSqrtRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_a_out_isNaN_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_a_out_isInf_T = divSqrtRawFN_io_a_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_a_out_isNaN_T_1 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_a_out_isNaN = _divSqrtRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_a_out_isInf_T_1 = ~_divSqrtRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_a_out_isInf_T_2 = divSqrtRawFN_io_a_isSpecial & _divSqrtRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_a_out_isInf = _divSqrtRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_a_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_a_out_sign = _divSqrtRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_a_out_sExp_T = {1'h0, divSqrtRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_a_out_sExp = _divSqrtRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_a_out_sig_T = ~divSqrtRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_a_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _divSqrtRawFN_io_a_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_a_out_sig_T_3 = {_divSqrtRawFN_io_a_out_sig_T_1, _divSqrtRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_a_out_sig = _divSqrtRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] divSqrtRawFN_io_b_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _divSqrtRawFN_io_b_isZero_T = divSqrtRawFN_io_b_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire divSqrtRawFN_io_b_isZero = _divSqrtRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire divSqrtRawFN_io_b_out_isZero = divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _divSqrtRawFN_io_b_isSpecial_T = divSqrtRawFN_io_b_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire divSqrtRawFN_io_b_isSpecial = &_divSqrtRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire divSqrtRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23] wire divSqrtRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] divSqrtRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] divSqrtRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23] wire _divSqrtRawFN_io_b_out_isNaN_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _divSqrtRawFN_io_b_out_isInf_T = divSqrtRawFN_io_b_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _divSqrtRawFN_io_b_out_isNaN_T_1 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign divSqrtRawFN_io_b_out_isNaN = _divSqrtRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _divSqrtRawFN_io_b_out_isInf_T_1 = ~_divSqrtRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _divSqrtRawFN_io_b_out_isInf_T_2 = divSqrtRawFN_io_b_isSpecial & _divSqrtRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign divSqrtRawFN_io_b_out_isInf = _divSqrtRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _divSqrtRawFN_io_b_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign divSqrtRawFN_io_b_out_sign = _divSqrtRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _divSqrtRawFN_io_b_out_sExp_T = {1'h0, divSqrtRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign divSqrtRawFN_io_b_out_sExp = _divSqrtRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _divSqrtRawFN_io_b_out_sig_T = ~divSqrtRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _divSqrtRawFN_io_b_out_sig_T_1 = {1'h0, _divSqrtRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _divSqrtRawFN_io_b_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _divSqrtRawFN_io_b_out_sig_T_3 = {_divSqrtRawFN_io_b_out_sig_T_1, _divSqrtRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign divSqrtRawFN_io_b_out_sig = _divSqrtRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] DivSqrtRawFN_small_e11_s53_2 divSqrtRawFN ( // @[DivSqrtRecFN_small.scala:446:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:422:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:422:5] .io_a_isNaN (divSqrtRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_a_isInf (divSqrtRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_a_isZero (divSqrtRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_a_sign (divSqrtRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_a_sExp (divSqrtRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_a_sig (divSqrtRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_b_isNaN (divSqrtRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23] .io_b_isInf (divSqrtRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23] .io_b_isZero (divSqrtRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23] .io_b_sign (divSqrtRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23] .io_b_sExp (divSqrtRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23] .io_b_sig (divSqrtRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:422:5] .io_rawOutValid_div (io_rawOutValid_div_0), .io_rawOutValid_sqrt (io_rawOutValid_sqrt_0), .io_roundingModeOut (io_roundingModeOut_0), .io_invalidExc (io_invalidExc_0), .io_infiniteExc (io_infiniteExc_0), .io_rawOut_isNaN (io_rawOut_isNaN_0), .io_rawOut_isInf (io_rawOut_isInf_0), .io_rawOut_isZero (io_rawOut_isZero_0), .io_rawOut_sign (io_rawOut_sign_0), .io_rawOut_sExp (io_rawOut_sExp_0), .io_rawOut_sig (io_rawOut_sig_0) ); // @[DivSqrtRecFN_small.scala:446:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:422:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:422:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_107 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_107( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_183 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_19 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<6>, poisoned : UInt<1>}}[3], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<4>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<6>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1) node _T_45 = and(io.wakeup_ports[2].valid, _T_44) when _T_45 : connect p1, UInt<1>(0h1) node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2) node _T_47 = and(io.wakeup_ports[2].valid, _T_46) when _T_47 : connect p2, UInt<1>(0h1) node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3) node _T_49 = and(io.wakeup_ports[2].valid, _T_48) when _T_49 : connect p3, UInt<1>(0h1) node _T_50 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_51 = and(io.pred_wakeup_port.valid, _T_50) when _T_51 : connect ppred, UInt<1>(0h1) node _T_52 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_59 = and(io.spec_ld_wakeup[0].valid, _T_58) node _T_60 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_61 = and(_T_59, _T_60) when _T_61 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_62 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_63 = asUInt(reset) node _T_64 = eq(_T_63, UInt<1>(0h0)) when _T_64 : node _T_65 = eq(_T_62, UInt<1>(0h0)) when _T_65 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_62, UInt<1>(0h1), "") : assert_4 node _T_66 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_67 = and(io.spec_ld_wakeup[0].valid, _T_66) node _T_68 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_69 = and(_T_67, _T_68) when _T_69 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_70 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_74 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_75 = neq(_T_74, UInt<1>(0h0)) when _T_75 : connect next_state, UInt<2>(0h0) node _T_76 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_76 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_77 = eq(state, UInt<2>(0h1)) when _T_77 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_78 = eq(state, UInt<2>(0h2)) when _T_78 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_79 = eq(state, UInt<2>(0h2)) when _T_79 : node _T_80 = and(p1, p2) node _T_81 = and(_T_80, ppred) when _T_81 : skip else : node _T_82 = and(p1, ppred) when _T_82 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_83 = and(p2, ppred) when _T_83 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_19( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_ldspec_miss, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14] input [5:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14] input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14] input [5:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [7:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [7:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [2:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [3:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [4:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [2:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [5:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [3:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [5:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7] wire [5:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7] wire [5:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [7:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire [3:0] io_pred_wakeup_port_bits = 4'h0; // @[issue-slot.scala:69:7] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ftq_idx = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_ppred = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_br_tag = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ldq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_stq_idx = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_rob_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_prs3 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_stale_pdst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [7:0] slot_uop_uop_br_mask = 8'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [7:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [7:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg p1_poisoned; // @[issue-slot.scala:95:28] assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28] reg p2_poisoned; // @[issue-slot.scala:96:28] assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28] wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29] wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [7:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [7:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}] wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18] wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23] assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17] assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17] wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11] wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11] wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11] wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14] wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24] wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24] wire _T_61 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27] wire _T_69 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27]
Generate the Verilog code corresponding to this FIRRTL code module PE_61 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_61( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_65 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_93 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_65( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] output io_q // @[ShiftReg.scala:36:14] ); wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_93 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n4x1_Registered : output auto : { flip in_3 : UInt<1>[1], flip in_2 : UInt<1>[1], flip in_1 : UInt<1>[1], flip in_0 : UInt<1>[1], out_3 : { sync : UInt<1>[1]}, out_2 : { sync : UInt<1>[1]}, out_1 : { sync : UInt<1>[1]}, out_0 : { sync : UInt<1>[1]}} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeIn : UInt<1>[1] invalidate nodeIn[0] wire nodeIn_1 : UInt<1>[1] invalidate nodeIn_1[0] wire nodeIn_2 : UInt<1>[1] invalidate nodeIn_2[0] wire nodeIn_3 : UInt<1>[1] invalidate nodeIn_3[0] wire nodeOut : { sync : UInt<1>[1]} invalidate nodeOut.sync[0] wire x1_nodeOut : { sync : UInt<1>[1]} invalidate x1_nodeOut.sync[0] wire x1_nodeOut_1 : { sync : UInt<1>[1]} invalidate x1_nodeOut_1.sync[0] wire x1_nodeOut_2 : { sync : UInt<1>[1]} invalidate x1_nodeOut_2.sync[0] connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeIn_2, auto.in_2 connect nodeIn_3, auto.in_3 connect nodeOut.sync, nodeIn connect x1_nodeOut.sync, nodeIn_1 connect x1_nodeOut_1.sync, nodeIn_2 connect x1_nodeOut_2.sync, nodeIn_3 extmodule plusarg_reader_157 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_158 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module IntSyncCrossingSource_n4x1_Registered( // @[Crossing.scala:48:9] input auto_in_3_0, // @[LazyModuleImp.scala:107:25] input auto_in_2_0, // @[LazyModuleImp.scala:107:25] input auto_in_1_0, // @[LazyModuleImp.scala:107:25] input auto_in_0_0, // @[LazyModuleImp.scala:107:25] output auto_out_3_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_2_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_1_sync_0, // @[LazyModuleImp.scala:107:25] output auto_out_0_sync_0 // @[LazyModuleImp.scala:107:25] ); assign auto_out_3_sync_0 = auto_in_3_0; // @[Crossing.scala:48:9] assign auto_out_2_sync_0 = auto_in_2_0; // @[Crossing.scala:48:9] assign auto_out_1_sync_0 = auto_in_1_0; // @[Crossing.scala:48:9] assign auto_out_0_sync_0 = auto_in_0_0; // @[Crossing.scala:48:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_20 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_20( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_406 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_150 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_406( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_150 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_11 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19) node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22) node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24) node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26) node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30 node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_31 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14) node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19) node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24) node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29) node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34) node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_42 = cvt(_io_resp_w_T_41) node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43) node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0))) node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_48 node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_49 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14) node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19) node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24) node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29) node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34) node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41) node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43) node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_48 node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_49 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14) node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19) node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24) node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29) node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34) node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_42 = cvt(_io_resp_al_T_41) node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43) node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0))) node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_48 node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_49 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14) node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19) node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24) node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29) node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34) node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41) node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43) node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_48 node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_49 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43) node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48) node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53) node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58) node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_66 node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_67 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14) node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19) node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24) node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29) node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35) node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37) node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40) node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42) node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45) node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47) node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50) node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52) node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44) node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49) node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54) node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_60 node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_61
module PMAChecker_11( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_121 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<27>(0h4000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<13>(0h1000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = or(_T_667, _T_672) node _T_699 = or(_T_698, _T_677) node _T_700 = or(_T_699, _T_682) node _T_701 = or(_T_700, _T_687) node _T_702 = or(_T_701, _T_692) node _T_703 = or(_T_702, _T_697) node _T_704 = and(_T_662, _T_703) node _T_705 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_706 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_707 = cvt(_T_706) node _T_708 = and(_T_707, asSInt(UInt<17>(0h10000))) node _T_709 = asSInt(_T_708) node _T_710 = eq(_T_709, asSInt(UInt<1>(0h0))) node _T_711 = and(_T_705, _T_710) node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_714 = and(_T_712, _T_713) node _T_715 = or(UInt<1>(0h0), _T_714) node _T_716 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_717 = cvt(_T_716) node _T_718 = and(_T_717, asSInt(UInt<17>(0h10000))) node _T_719 = asSInt(_T_718) node _T_720 = eq(_T_719, asSInt(UInt<1>(0h0))) node _T_721 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<29>(0h10000000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = or(_T_720, _T_725) node _T_727 = and(_T_715, _T_726) node _T_728 = or(UInt<1>(0h0), _T_704) node _T_729 = or(_T_728, _T_711) node _T_730 = or(_T_729, _T_727) node _T_731 = and(_T_658, _T_730) node _T_732 = asUInt(reset) node _T_733 = eq(_T_732, UInt<1>(0h0)) when _T_733 : node _T_734 = eq(_T_731, UInt<1>(0h0)) when _T_734 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_731, UInt<1>(0h1), "") : assert_36 node _T_735 = asUInt(reset) node _T_736 = eq(_T_735, UInt<1>(0h0)) when _T_736 : node _T_737 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_737 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_738 = asUInt(reset) node _T_739 = eq(_T_738, UInt<1>(0h0)) when _T_739 : node _T_740 = eq(is_aligned, UInt<1>(0h0)) when _T_740 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_741 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(_T_741, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_741, UInt<1>(0h1), "") : assert_39 node _T_745 = eq(io.in.a.bits.mask, mask) node _T_746 = asUInt(reset) node _T_747 = eq(_T_746, UInt<1>(0h0)) when _T_747 : node _T_748 = eq(_T_745, UInt<1>(0h0)) when _T_748 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_745, UInt<1>(0h1), "") : assert_40 node _T_749 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_749 : node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_752 = and(_T_750, _T_751) node _T_753 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_754 = and(_T_752, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_757 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_758 = and(_T_756, _T_757) node _T_759 = or(UInt<1>(0h0), _T_758) node _T_760 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<14>(0h2000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<13>(0h1000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<18>(0h2f000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<17>(0h10000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<13>(0h1000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = or(_T_764, _T_769) node _T_796 = or(_T_795, _T_774) node _T_797 = or(_T_796, _T_779) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_789) node _T_800 = or(_T_799, _T_794) node _T_801 = and(_T_759, _T_800) node _T_802 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_803 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_804 = cvt(_T_803) node _T_805 = and(_T_804, asSInt(UInt<17>(0h10000))) node _T_806 = asSInt(_T_805) node _T_807 = eq(_T_806, asSInt(UInt<1>(0h0))) node _T_808 = and(_T_802, _T_807) node _T_809 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_810 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_811 = and(_T_809, _T_810) node _T_812 = or(UInt<1>(0h0), _T_811) node _T_813 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_814 = cvt(_T_813) node _T_815 = and(_T_814, asSInt(UInt<17>(0h10000))) node _T_816 = asSInt(_T_815) node _T_817 = eq(_T_816, asSInt(UInt<1>(0h0))) node _T_818 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_819 = cvt(_T_818) node _T_820 = and(_T_819, asSInt(UInt<29>(0h10000000))) node _T_821 = asSInt(_T_820) node _T_822 = eq(_T_821, asSInt(UInt<1>(0h0))) node _T_823 = or(_T_817, _T_822) node _T_824 = and(_T_812, _T_823) node _T_825 = or(UInt<1>(0h0), _T_801) node _T_826 = or(_T_825, _T_808) node _T_827 = or(_T_826, _T_824) node _T_828 = and(_T_755, _T_827) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_828, UInt<1>(0h1), "") : assert_41 node _T_832 = asUInt(reset) node _T_833 = eq(_T_832, UInt<1>(0h0)) when _T_833 : node _T_834 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_834 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_835 = asUInt(reset) node _T_836 = eq(_T_835, UInt<1>(0h0)) when _T_836 : node _T_837 = eq(is_aligned, UInt<1>(0h0)) when _T_837 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_838 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(_T_838, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_838, UInt<1>(0h1), "") : assert_44 node _T_842 = eq(io.in.a.bits.mask, mask) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_842, UInt<1>(0h1), "") : assert_45 node _T_846 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_846 : node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_849 = and(_T_847, _T_848) node _T_850 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_851 = and(_T_849, _T_850) node _T_852 = or(UInt<1>(0h0), _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<13>(0h1000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = and(_T_856, _T_861) node _T_863 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_864 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<14>(0h2000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<18>(0h2f000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<17>(0h10000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_890 = cvt(_T_889) node _T_891 = and(_T_890, asSInt(UInt<27>(0h4000000))) node _T_892 = asSInt(_T_891) node _T_893 = eq(_T_892, asSInt(UInt<1>(0h0))) node _T_894 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<13>(0h1000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = or(_T_868, _T_873) node _T_900 = or(_T_899, _T_878) node _T_901 = or(_T_900, _T_883) node _T_902 = or(_T_901, _T_888) node _T_903 = or(_T_902, _T_893) node _T_904 = or(_T_903, _T_898) node _T_905 = and(_T_863, _T_904) node _T_906 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_907 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_908 = and(_T_906, _T_907) node _T_909 = or(UInt<1>(0h0), _T_908) node _T_910 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_911 = cvt(_T_910) node _T_912 = and(_T_911, asSInt(UInt<17>(0h10000))) node _T_913 = asSInt(_T_912) node _T_914 = eq(_T_913, asSInt(UInt<1>(0h0))) node _T_915 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_916 = cvt(_T_915) node _T_917 = and(_T_916, asSInt(UInt<29>(0h10000000))) node _T_918 = asSInt(_T_917) node _T_919 = eq(_T_918, asSInt(UInt<1>(0h0))) node _T_920 = or(_T_914, _T_919) node _T_921 = and(_T_909, _T_920) node _T_922 = or(UInt<1>(0h0), _T_862) node _T_923 = or(_T_922, _T_905) node _T_924 = or(_T_923, _T_921) node _T_925 = and(_T_852, _T_924) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_925, UInt<1>(0h1), "") : assert_46 node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(is_aligned, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_935 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(_T_935, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_935, UInt<1>(0h1), "") : assert_49 node _T_939 = eq(io.in.a.bits.mask, mask) node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(_T_939, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_939, UInt<1>(0h1), "") : assert_50 node _T_943 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_943, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_947 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_947, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<7>(0h40)) node _T_951 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_951 : node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_955 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_955, UInt<1>(0h1), "") : assert_54 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_959, UInt<1>(0h1), "") : assert_55 node _T_963 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_964 = asUInt(reset) node _T_965 = eq(_T_964, UInt<1>(0h0)) when _T_965 : node _T_966 = eq(_T_963, UInt<1>(0h0)) when _T_966 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_963, UInt<1>(0h1), "") : assert_56 node _T_967 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(_T_967, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_967, UInt<1>(0h1), "") : assert_57 node _T_971 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_971 : node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_975 = asUInt(reset) node _T_976 = eq(_T_975, UInt<1>(0h0)) when _T_976 : node _T_977 = eq(sink_ok, UInt<1>(0h0)) when _T_977 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_978 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_979 = asUInt(reset) node _T_980 = eq(_T_979, UInt<1>(0h0)) when _T_980 : node _T_981 = eq(_T_978, UInt<1>(0h0)) when _T_981 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_978, UInt<1>(0h1), "") : assert_60 node _T_982 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_983 = asUInt(reset) node _T_984 = eq(_T_983, UInt<1>(0h0)) when _T_984 : node _T_985 = eq(_T_982, UInt<1>(0h0)) when _T_985 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_982, UInt<1>(0h1), "") : assert_61 node _T_986 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_986, UInt<1>(0h1), "") : assert_62 node _T_990 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_990, UInt<1>(0h1), "") : assert_63 node _T_994 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_995 = or(UInt<1>(0h1), _T_994) node _T_996 = asUInt(reset) node _T_997 = eq(_T_996, UInt<1>(0h0)) when _T_997 : node _T_998 = eq(_T_995, UInt<1>(0h0)) when _T_998 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_995, UInt<1>(0h1), "") : assert_64 node _T_999 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_999 : node _T_1000 = asUInt(reset) node _T_1001 = eq(_T_1000, UInt<1>(0h0)) when _T_1001 : node _T_1002 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1002 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1003 = asUInt(reset) node _T_1004 = eq(_T_1003, UInt<1>(0h0)) when _T_1004 : node _T_1005 = eq(sink_ok, UInt<1>(0h0)) when _T_1005 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1006 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_67 node _T_1010 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(_T_1010, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1010, UInt<1>(0h1), "") : assert_68 node _T_1014 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_69 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_70 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h1), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_71 node _T_1028 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_73 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_74 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h1), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_75 node _T_1045 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1045 : node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1049 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_77 node _T_1053 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1054 = or(_T_1053, io.in.d.bits.corrupt) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_78 node _T_1058 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1059 = or(UInt<1>(0h1), _T_1058) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_79 node _T_1063 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1063 : node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1067 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_81 node _T_1071 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_82 node _T_1075 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1076 = or(UInt<1>(0h1), _T_1075) node _T_1077 = asUInt(reset) node _T_1078 = eq(_T_1077, UInt<1>(0h0)) when _T_1078 : node _T_1079 = eq(_T_1076, UInt<1>(0h0)) when _T_1079 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1076, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1080 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1084 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_4.bits.sink, UInt<6>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<6>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1088 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1092 = eq(a_first, UInt<1>(0h0)) node _T_1093 = and(io.in.a.valid, _T_1092) when _T_1093 : node _T_1094 = eq(io.in.a.bits.opcode, opcode) node _T_1095 = asUInt(reset) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) when _T_1096 : node _T_1097 = eq(_T_1094, UInt<1>(0h0)) when _T_1097 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1094, UInt<1>(0h1), "") : assert_87 node _T_1098 = eq(io.in.a.bits.param, param) node _T_1099 = asUInt(reset) node _T_1100 = eq(_T_1099, UInt<1>(0h0)) when _T_1100 : node _T_1101 = eq(_T_1098, UInt<1>(0h0)) when _T_1101 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1098, UInt<1>(0h1), "") : assert_88 node _T_1102 = eq(io.in.a.bits.size, size) node _T_1103 = asUInt(reset) node _T_1104 = eq(_T_1103, UInt<1>(0h0)) when _T_1104 : node _T_1105 = eq(_T_1102, UInt<1>(0h0)) when _T_1105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1102, UInt<1>(0h1), "") : assert_89 node _T_1106 = eq(io.in.a.bits.source, source) node _T_1107 = asUInt(reset) node _T_1108 = eq(_T_1107, UInt<1>(0h0)) when _T_1108 : node _T_1109 = eq(_T_1106, UInt<1>(0h0)) when _T_1109 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1106, UInt<1>(0h1), "") : assert_90 node _T_1110 = eq(io.in.a.bits.address, address) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_91 node _T_1114 = and(io.in.a.ready, io.in.a.valid) node _T_1115 = and(_T_1114, a_first) when _T_1115 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1116 = eq(d_first, UInt<1>(0h0)) node _T_1117 = and(io.in.d.valid, _T_1116) when _T_1117 : node _T_1118 = eq(io.in.d.bits.opcode, opcode_1) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_92 node _T_1122 = eq(io.in.d.bits.param, param_1) node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(_T_1122, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1122, UInt<1>(0h1), "") : assert_93 node _T_1126 = eq(io.in.d.bits.size, size_1) node _T_1127 = asUInt(reset) node _T_1128 = eq(_T_1127, UInt<1>(0h0)) when _T_1128 : node _T_1129 = eq(_T_1126, UInt<1>(0h0)) when _T_1129 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1126, UInt<1>(0h1), "") : assert_94 node _T_1130 = eq(io.in.d.bits.source, source_1) node _T_1131 = asUInt(reset) node _T_1132 = eq(_T_1131, UInt<1>(0h0)) when _T_1132 : node _T_1133 = eq(_T_1130, UInt<1>(0h0)) when _T_1133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1130, UInt<1>(0h1), "") : assert_95 node _T_1134 = eq(io.in.d.bits.sink, sink) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_96 node _T_1138 = eq(io.in.d.bits.denied, denied) node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_T_1138, UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1138, UInt<1>(0h1), "") : assert_97 node _T_1142 = and(io.in.d.ready, io.in.d.valid) node _T_1143 = and(_T_1142, d_first) when _T_1143 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1144 = and(io.in.a.valid, a_first_1) node _T_1145 = and(_T_1144, UInt<1>(0h1)) when _T_1145 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1146 = and(io.in.a.ready, io.in.a.valid) node _T_1147 = and(_T_1146, a_first_1) node _T_1148 = and(_T_1147, UInt<1>(0h1)) when _T_1148 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1149 = dshr(inflight, io.in.a.bits.source) node _T_1150 = bits(_T_1149, 0, 0) node _T_1151 = eq(_T_1150, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1155 = and(io.in.d.valid, d_first_1) node _T_1156 = and(_T_1155, UInt<1>(0h1)) node _T_1157 = eq(d_release_ack, UInt<1>(0h0)) node _T_1158 = and(_T_1156, _T_1157) when _T_1158 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1159 = and(io.in.d.ready, io.in.d.valid) node _T_1160 = and(_T_1159, d_first_1) node _T_1161 = and(_T_1160, UInt<1>(0h1)) node _T_1162 = eq(d_release_ack, UInt<1>(0h0)) node _T_1163 = and(_T_1161, _T_1162) when _T_1163 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1164 = and(io.in.d.valid, d_first_1) node _T_1165 = and(_T_1164, UInt<1>(0h1)) node _T_1166 = eq(d_release_ack, UInt<1>(0h0)) node _T_1167 = and(_T_1165, _T_1166) when _T_1167 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1168 = dshr(inflight, io.in.d.bits.source) node _T_1169 = bits(_T_1168, 0, 0) node _T_1170 = or(_T_1169, same_cycle_resp) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_100 node _T_1180 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_101 else : node _T_1184 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1185 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1186 = or(_T_1184, _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_102 node _T_1190 = eq(io.in.d.bits.size, a_size_lookup) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_103 node _T_1194 = and(io.in.d.valid, d_first_1) node _T_1195 = and(_T_1194, a_first_1) node _T_1196 = and(_T_1195, io.in.a.valid) node _T_1197 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1198 = and(_T_1196, _T_1197) node _T_1199 = eq(d_release_ack, UInt<1>(0h0)) node _T_1200 = and(_T_1198, _T_1199) when _T_1200 : node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1202 = or(_T_1201, io.in.a.ready) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_104 node _T_1206 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1207 = orr(a_set_wo_ready) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) node _T_1209 = or(_T_1206, _T_1208) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_292 node _T_1213 = orr(inflight) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) node _T_1215 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1216 = or(_T_1214, _T_1215) node _T_1217 = lt(watchdog, plusarg_reader.out) node _T_1218 = or(_T_1216, _T_1217) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1222 = and(io.in.a.ready, io.in.a.valid) node _T_1223 = and(io.in.d.ready, io.in.d.valid) node _T_1224 = or(_T_1222, _T_1223) when _T_1224 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1225 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1226 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1227 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1225, _T_1228) when _T_1229 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1230 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1231 = and(_T_1230, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1232 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1233 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1234 = and(_T_1232, _T_1233) node _T_1235 = and(_T_1231, _T_1234) when _T_1235 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1236 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1237 = bits(_T_1236, 0, 0) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = asUInt(reset) node _T_1240 = eq(_T_1239, UInt<1>(0h0)) when _T_1240 : node _T_1241 = eq(_T_1238, UInt<1>(0h0)) when _T_1241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1238, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1242 = and(io.in.d.valid, d_first_2) node _T_1243 = and(_T_1242, UInt<1>(0h1)) node _T_1244 = and(_T_1243, d_release_ack_1) when _T_1244 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1245 = and(io.in.d.ready, io.in.d.valid) node _T_1246 = and(_T_1245, d_first_2) node _T_1247 = and(_T_1246, UInt<1>(0h1)) node _T_1248 = and(_T_1247, d_release_ack_1) when _T_1248 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1249 = and(io.in.d.valid, d_first_2) node _T_1250 = and(_T_1249, UInt<1>(0h1)) node _T_1251 = and(_T_1250, d_release_ack_1) when _T_1251 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1252 = dshr(inflight_1, io.in.d.bits.source) node _T_1253 = bits(_T_1252, 0, 0) node _T_1254 = or(_T_1253, same_cycle_resp_1) node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(_T_1254, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1254, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1258 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1259 = asUInt(reset) node _T_1260 = eq(_T_1259, UInt<1>(0h0)) when _T_1260 : node _T_1261 = eq(_T_1258, UInt<1>(0h0)) when _T_1261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1258, UInt<1>(0h1), "") : assert_109 else : node _T_1262 = eq(io.in.d.bits.size, c_size_lookup) node _T_1263 = asUInt(reset) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) when _T_1264 : node _T_1265 = eq(_T_1262, UInt<1>(0h0)) when _T_1265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1262, UInt<1>(0h1), "") : assert_110 node _T_1266 = and(io.in.d.valid, d_first_2) node _T_1267 = and(_T_1266, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1268 = and(_T_1267, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1269 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1270 = and(_T_1268, _T_1269) node _T_1271 = and(_T_1270, d_release_ack_1) node _T_1272 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _T_1274 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1275 = or(_T_1274, _WIRE_23.ready) node _T_1276 = asUInt(reset) node _T_1277 = eq(_T_1276, UInt<1>(0h0)) when _T_1277 : node _T_1278 = eq(_T_1275, UInt<1>(0h0)) when _T_1278 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1275, UInt<1>(0h1), "") : assert_111 node _T_1279 = orr(c_set_wo_ready) when _T_1279 : node _T_1280 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_293 node _T_1284 = orr(inflight_1) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) node _T_1286 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1287 = or(_T_1285, _T_1286) node _T_1288 = lt(watchdog_1, plusarg_reader_1.out) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1293 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1294 = and(io.in.d.ready, io.in.d.valid) node _T_1295 = or(_T_1293, _T_1294) when _T_1295 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_121( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [5:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [5:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_39 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_295 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_39( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_295 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_375 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_119 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_375( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_119 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_1 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_49 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_50 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_51 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_52 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_1( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_49 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_50 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_51 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_52 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_458 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_202 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_458( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_202 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_108 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node adjustedSig = shl(io.in.sig, 0) node doShiftSigDown1 = bits(adjustedSig, 26, 26) wire common_expOut : UInt<9> wire common_fractOut : UInt<23> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = bits(io.in.sExp, 8, 0) node _roundMask_T_1 = not(_roundMask_T) node roundMask_msb = bits(_roundMask_T_1, 8, 8) node roundMask_lsbs = bits(_roundMask_T_1, 7, 0) node roundMask_msb_1 = bits(roundMask_lsbs, 7, 7) node roundMask_lsbs_1 = bits(roundMask_lsbs, 6, 0) node roundMask_msb_2 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_2 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_2) node _roundMask_T_2 = bits(roundMask_shift, 63, 42) node _roundMask_T_3 = bits(_roundMask_T_2, 15, 0) node _roundMask_T_4 = shl(UInt<8>(0hff), 8) node _roundMask_T_5 = xor(UInt<16>(0hffff), _roundMask_T_4) node _roundMask_T_6 = shr(_roundMask_T_3, 8) node _roundMask_T_7 = and(_roundMask_T_6, _roundMask_T_5) node _roundMask_T_8 = bits(_roundMask_T_3, 7, 0) node _roundMask_T_9 = shl(_roundMask_T_8, 8) node _roundMask_T_10 = not(_roundMask_T_5) node _roundMask_T_11 = and(_roundMask_T_9, _roundMask_T_10) node _roundMask_T_12 = or(_roundMask_T_7, _roundMask_T_11) node _roundMask_T_13 = bits(_roundMask_T_5, 11, 0) node _roundMask_T_14 = shl(_roundMask_T_13, 4) node _roundMask_T_15 = xor(_roundMask_T_5, _roundMask_T_14) node _roundMask_T_16 = shr(_roundMask_T_12, 4) node _roundMask_T_17 = and(_roundMask_T_16, _roundMask_T_15) node _roundMask_T_18 = bits(_roundMask_T_12, 11, 0) node _roundMask_T_19 = shl(_roundMask_T_18, 4) node _roundMask_T_20 = not(_roundMask_T_15) node _roundMask_T_21 = and(_roundMask_T_19, _roundMask_T_20) node _roundMask_T_22 = or(_roundMask_T_17, _roundMask_T_21) node _roundMask_T_23 = bits(_roundMask_T_15, 13, 0) node _roundMask_T_24 = shl(_roundMask_T_23, 2) node _roundMask_T_25 = xor(_roundMask_T_15, _roundMask_T_24) node _roundMask_T_26 = shr(_roundMask_T_22, 2) node _roundMask_T_27 = and(_roundMask_T_26, _roundMask_T_25) node _roundMask_T_28 = bits(_roundMask_T_22, 13, 0) node _roundMask_T_29 = shl(_roundMask_T_28, 2) node _roundMask_T_30 = not(_roundMask_T_25) node _roundMask_T_31 = and(_roundMask_T_29, _roundMask_T_30) node _roundMask_T_32 = or(_roundMask_T_27, _roundMask_T_31) node _roundMask_T_33 = bits(_roundMask_T_25, 14, 0) node _roundMask_T_34 = shl(_roundMask_T_33, 1) node _roundMask_T_35 = xor(_roundMask_T_25, _roundMask_T_34) node _roundMask_T_36 = shr(_roundMask_T_32, 1) node _roundMask_T_37 = and(_roundMask_T_36, _roundMask_T_35) node _roundMask_T_38 = bits(_roundMask_T_32, 14, 0) node _roundMask_T_39 = shl(_roundMask_T_38, 1) node _roundMask_T_40 = not(_roundMask_T_35) node _roundMask_T_41 = and(_roundMask_T_39, _roundMask_T_40) node _roundMask_T_42 = or(_roundMask_T_37, _roundMask_T_41) node _roundMask_T_43 = bits(_roundMask_T_2, 21, 16) node _roundMask_T_44 = bits(_roundMask_T_43, 3, 0) node _roundMask_T_45 = bits(_roundMask_T_44, 1, 0) node _roundMask_T_46 = bits(_roundMask_T_45, 0, 0) node _roundMask_T_47 = bits(_roundMask_T_45, 1, 1) node _roundMask_T_48 = cat(_roundMask_T_46, _roundMask_T_47) node _roundMask_T_49 = bits(_roundMask_T_44, 3, 2) node _roundMask_T_50 = bits(_roundMask_T_49, 0, 0) node _roundMask_T_51 = bits(_roundMask_T_49, 1, 1) node _roundMask_T_52 = cat(_roundMask_T_50, _roundMask_T_51) node _roundMask_T_53 = cat(_roundMask_T_48, _roundMask_T_52) node _roundMask_T_54 = bits(_roundMask_T_43, 5, 4) node _roundMask_T_55 = bits(_roundMask_T_54, 0, 0) node _roundMask_T_56 = bits(_roundMask_T_54, 1, 1) node _roundMask_T_57 = cat(_roundMask_T_55, _roundMask_T_56) node _roundMask_T_58 = cat(_roundMask_T_53, _roundMask_T_57) node _roundMask_T_59 = cat(_roundMask_T_42, _roundMask_T_58) node _roundMask_T_60 = not(_roundMask_T_59) node _roundMask_T_61 = mux(roundMask_msb_2, UInt<1>(0h0), _roundMask_T_60) node _roundMask_T_62 = not(_roundMask_T_61) node _roundMask_T_63 = cat(_roundMask_T_62, UInt<3>(0h7)) node roundMask_msb_3 = bits(roundMask_lsbs_1, 6, 6) node roundMask_lsbs_3 = bits(roundMask_lsbs_1, 5, 0) node roundMask_shift_1 = dshr(asSInt(UInt<65>(0h10000000000000000)), roundMask_lsbs_3) node _roundMask_T_64 = bits(roundMask_shift_1, 2, 0) node _roundMask_T_65 = bits(_roundMask_T_64, 1, 0) node _roundMask_T_66 = bits(_roundMask_T_65, 0, 0) node _roundMask_T_67 = bits(_roundMask_T_65, 1, 1) node _roundMask_T_68 = cat(_roundMask_T_66, _roundMask_T_67) node _roundMask_T_69 = bits(_roundMask_T_64, 2, 2) node _roundMask_T_70 = cat(_roundMask_T_68, _roundMask_T_69) node _roundMask_T_71 = mux(roundMask_msb_3, _roundMask_T_70, UInt<1>(0h0)) node _roundMask_T_72 = mux(roundMask_msb_1, _roundMask_T_63, _roundMask_T_71) node _roundMask_T_73 = mux(roundMask_msb, _roundMask_T_72, UInt<1>(0h0)) node _roundMask_T_74 = or(_roundMask_T_73, doShiftSigDown1) node roundMask = cat(_roundMask_T_74, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<26>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 24) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(io.in.sExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 8, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 23, 1) node _common_fractOut_T_1 = bits(roundedSig, 22, 0) node _common_fractOut_T_2 = mux(doShiftSigDown1, _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 7) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 node _common_totalUnderflow_T = lt(sRoundedExp, asSInt(UInt<8>(0h6b))) connect common_totalUnderflow, _common_totalUnderflow_T node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(doShiftSigDown1, _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(doShiftSigDown1, _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 25, 25) node _roundCarry_T_1 = bits(roundedSig, 24, 24) node roundCarry = mux(doShiftSigDown1, _roundCarry_T, _roundCarry_T_1) node _common_underflow_T = shr(io.in.sExp, 8) node _common_underflow_T_1 = leq(_common_underflow_T, asSInt(UInt<1>(0h0))) node _common_underflow_T_2 = and(anyRound, _common_underflow_T_1) node _common_underflow_T_3 = bits(roundMask, 3, 3) node _common_underflow_T_4 = bits(roundMask, 2, 2) node _common_underflow_T_5 = mux(doShiftSigDown1, _common_underflow_T_3, _common_underflow_T_4) node _common_underflow_T_6 = and(_common_underflow_T_2, _common_underflow_T_5) node _common_underflow_T_7 = eq(io.detectTininess, UInt<1>(0h1)) node _common_underflow_T_8 = bits(roundMask, 4, 4) node _common_underflow_T_9 = bits(roundMask, 3, 3) node _common_underflow_T_10 = mux(doShiftSigDown1, _common_underflow_T_8, _common_underflow_T_9) node _common_underflow_T_11 = eq(_common_underflow_T_10, UInt<1>(0h0)) node _common_underflow_T_12 = and(_common_underflow_T_7, _common_underflow_T_11) node _common_underflow_T_13 = and(_common_underflow_T_12, roundCarry) node _common_underflow_T_14 = and(_common_underflow_T_13, roundPosBit) node _common_underflow_T_15 = and(_common_underflow_T_14, unboundedRange_roundIncr) node _common_underflow_T_16 = eq(_common_underflow_T_15, UInt<1>(0h0)) node _common_underflow_T_17 = and(_common_underflow_T_6, _common_underflow_T_16) node _common_underflow_T_18 = or(common_totalUnderflow, _common_underflow_T_17) connect common_underflow, _common_underflow_T_18 node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<9>(0h1c0), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<9>(0h6b)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<9>(0h80), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<9>(0h40), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<9>(0h6b), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<9>(0h17f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<9>(0h180), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<9>(0h1c0), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<23>(0h400000), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<23>(0h7fffff), UInt<23>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_108( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] _expOut_T_4 = 9'h194; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [15:0] _roundMask_T_5 = 16'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_4 = 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_10 = 16'hFF00; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_13 = 12'hFF; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_14 = 16'hFF0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_15 = 16'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_20 = 16'hF0F0; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_23 = 14'hF0F; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_24 = 16'h3C3C; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_25 = 16'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_30 = 16'hCCCC; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_33 = 15'h3333; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_34 = 16'h6666; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_35 = 16'h5555; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_40 = 16'hAAAA; // @[primitives.scala:77:20] wire [25:0] _roundedSig_T_15 = 26'h0; // @[RoundAnyRawFNToRecFN.scala:181:24] wire [8:0] _expOut_T_6 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_9 = 9'h1FF; // @[RoundAnyRawFNToRecFN.scala:257:14, :261:14] wire [8:0] _expOut_T_5 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [8:0] _expOut_T_8 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:261:18] wire [8:0] _expOut_T_14 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [8:0] _expOut_T_16 = 9'h0; // @[RoundAnyRawFNToRecFN.scala:273:16] wire [22:0] _fractOut_T_4 = 23'h0; // @[RoundAnyRawFNToRecFN.scala:284:13] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = 1'h1; // @[RoundAnyRawFNToRecFN.scala:90:53] wire _roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:207:38] wire _common_underflow_T_7 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:222:49] wire _overflow_roundMagUp_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:32] wire overflow_roundMagUp = 1'h1; // @[RoundAnyRawFNToRecFN.scala:243:60] wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_minMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:91:53] wire roundingMode_min = 1'h0; // @[RoundAnyRawFNToRecFN.scala:92:53] wire roundingMode_max = 1'h0; // @[RoundAnyRawFNToRecFN.scala:93:53] wire roundingMode_near_maxMag = 1'h0; // @[RoundAnyRawFNToRecFN.scala:94:53] wire roundingMode_odd = 1'h0; // @[RoundAnyRawFNToRecFN.scala:95:53] wire _roundMagUp_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:27] wire _roundMagUp_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:63] wire roundMagUp = 1'h0; // @[RoundAnyRawFNToRecFN.scala:98:42] wire _roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:171:29] wire _roundedSig_T_13 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:181:42] wire _unboundedRange_roundIncr_T_2 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:209:29] wire _pegMinNonzeroMagOut_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:60] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _pegMaxFiniteMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:42] wire pegMaxFiniteMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:246:39] wire notNaN_isSpecialInfOut = io_in_isInf_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :236:49] wire [26:0] adjustedSig = io_in_sig_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :114:22] wire [32:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire doShiftSigDown1 = adjustedSig[26]; // @[RoundAnyRawFNToRecFN.scala:114:22, :120:57] wire [8:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [8:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [22:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [22:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:200:31] wire common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37] wire _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:217:40] wire common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [8:0] _roundMask_T = io_in_sExp_0[8:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :156:37] wire [8:0] _roundMask_T_1 = ~_roundMask_T; // @[primitives.scala:52:21] wire roundMask_msb = _roundMask_T_1[8]; // @[primitives.scala:52:21, :58:25] wire [7:0] roundMask_lsbs = _roundMask_T_1[7:0]; // @[primitives.scala:52:21, :59:26] wire roundMask_msb_1 = roundMask_lsbs[7]; // @[primitives.scala:58:25, :59:26] wire [6:0] roundMask_lsbs_1 = roundMask_lsbs[6:0]; // @[primitives.scala:59:26] wire roundMask_msb_2 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire roundMask_msb_3 = roundMask_lsbs_1[6]; // @[primitives.scala:58:25, :59:26] wire [5:0] roundMask_lsbs_2 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [5:0] roundMask_lsbs_3 = roundMask_lsbs_1[5:0]; // @[primitives.scala:59:26] wire [64:0] roundMask_shift = $signed(65'sh10000000000000000 >>> roundMask_lsbs_2); // @[primitives.scala:59:26, :76:56] wire [21:0] _roundMask_T_2 = roundMask_shift[63:42]; // @[primitives.scala:76:56, :78:22] wire [15:0] _roundMask_T_3 = _roundMask_T_2[15:0]; // @[primitives.scala:77:20, :78:22] wire [7:0] _roundMask_T_6 = _roundMask_T_3[15:8]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_7 = {8'h0, _roundMask_T_6}; // @[primitives.scala:77:20] wire [7:0] _roundMask_T_8 = _roundMask_T_3[7:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_9 = {_roundMask_T_8, 8'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_11 = _roundMask_T_9 & 16'hFF00; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_12 = _roundMask_T_7 | _roundMask_T_11; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_16 = _roundMask_T_12[15:4]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_17 = {4'h0, _roundMask_T_16 & 12'hF0F}; // @[primitives.scala:77:20] wire [11:0] _roundMask_T_18 = _roundMask_T_12[11:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_19 = {_roundMask_T_18, 4'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_21 = _roundMask_T_19 & 16'hF0F0; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_22 = _roundMask_T_17 | _roundMask_T_21; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_26 = _roundMask_T_22[15:2]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_27 = {2'h0, _roundMask_T_26 & 14'h3333}; // @[primitives.scala:77:20] wire [13:0] _roundMask_T_28 = _roundMask_T_22[13:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_29 = {_roundMask_T_28, 2'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_31 = _roundMask_T_29 & 16'hCCCC; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_32 = _roundMask_T_27 | _roundMask_T_31; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_36 = _roundMask_T_32[15:1]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_37 = {1'h0, _roundMask_T_36 & 15'h5555}; // @[primitives.scala:77:20] wire [14:0] _roundMask_T_38 = _roundMask_T_32[14:0]; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_39 = {_roundMask_T_38, 1'h0}; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_41 = _roundMask_T_39 & 16'hAAAA; // @[primitives.scala:77:20] wire [15:0] _roundMask_T_42 = _roundMask_T_37 | _roundMask_T_41; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_43 = _roundMask_T_2[21:16]; // @[primitives.scala:77:20, :78:22] wire [3:0] _roundMask_T_44 = _roundMask_T_43[3:0]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_45 = _roundMask_T_44[1:0]; // @[primitives.scala:77:20] wire _roundMask_T_46 = _roundMask_T_45[0]; // @[primitives.scala:77:20] wire _roundMask_T_47 = _roundMask_T_45[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_48 = {_roundMask_T_46, _roundMask_T_47}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_49 = _roundMask_T_44[3:2]; // @[primitives.scala:77:20] wire _roundMask_T_50 = _roundMask_T_49[0]; // @[primitives.scala:77:20] wire _roundMask_T_51 = _roundMask_T_49[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_52 = {_roundMask_T_50, _roundMask_T_51}; // @[primitives.scala:77:20] wire [3:0] _roundMask_T_53 = {_roundMask_T_48, _roundMask_T_52}; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_54 = _roundMask_T_43[5:4]; // @[primitives.scala:77:20] wire _roundMask_T_55 = _roundMask_T_54[0]; // @[primitives.scala:77:20] wire _roundMask_T_56 = _roundMask_T_54[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_57 = {_roundMask_T_55, _roundMask_T_56}; // @[primitives.scala:77:20] wire [5:0] _roundMask_T_58 = {_roundMask_T_53, _roundMask_T_57}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_59 = {_roundMask_T_42, _roundMask_T_58}; // @[primitives.scala:77:20] wire [21:0] _roundMask_T_60 = ~_roundMask_T_59; // @[primitives.scala:73:32, :77:20] wire [21:0] _roundMask_T_61 = roundMask_msb_2 ? 22'h0 : _roundMask_T_60; // @[primitives.scala:58:25, :73:{21,32}] wire [21:0] _roundMask_T_62 = ~_roundMask_T_61; // @[primitives.scala:73:{17,21}] wire [24:0] _roundMask_T_63 = {_roundMask_T_62, 3'h7}; // @[primitives.scala:68:58, :73:17] wire [64:0] roundMask_shift_1 = $signed(65'sh10000000000000000 >>> roundMask_lsbs_3); // @[primitives.scala:59:26, :76:56] wire [2:0] _roundMask_T_64 = roundMask_shift_1[2:0]; // @[primitives.scala:76:56, :78:22] wire [1:0] _roundMask_T_65 = _roundMask_T_64[1:0]; // @[primitives.scala:77:20, :78:22] wire _roundMask_T_66 = _roundMask_T_65[0]; // @[primitives.scala:77:20] wire _roundMask_T_67 = _roundMask_T_65[1]; // @[primitives.scala:77:20] wire [1:0] _roundMask_T_68 = {_roundMask_T_66, _roundMask_T_67}; // @[primitives.scala:77:20] wire _roundMask_T_69 = _roundMask_T_64[2]; // @[primitives.scala:77:20, :78:22] wire [2:0] _roundMask_T_70 = {_roundMask_T_68, _roundMask_T_69}; // @[primitives.scala:77:20] wire [2:0] _roundMask_T_71 = roundMask_msb_3 ? _roundMask_T_70 : 3'h0; // @[primitives.scala:58:25, :62:24, :77:20] wire [24:0] _roundMask_T_72 = roundMask_msb_1 ? _roundMask_T_63 : {22'h0, _roundMask_T_71}; // @[primitives.scala:58:25, :62:24, :67:24, :68:58] wire [24:0] _roundMask_T_73 = roundMask_msb ? _roundMask_T_72 : 25'h0; // @[primitives.scala:58:25, :62:24, :67:24] wire [24:0] _roundMask_T_74 = {_roundMask_T_73[24:1], _roundMask_T_73[0] | doShiftSigDown1}; // @[primitives.scala:62:24] wire [26:0] roundMask = {_roundMask_T_74, 2'h3}; // @[RoundAnyRawFNToRecFN.scala:159:{23,42}] wire [27:0] _shiftedRoundMask_T = {1'h0, roundMask}; // @[RoundAnyRawFNToRecFN.scala:159:42, :162:41] wire [26:0] shiftedRoundMask = _shiftedRoundMask_T[27:1]; // @[RoundAnyRawFNToRecFN.scala:162:{41,53}] wire [26:0] _roundPosMask_T = ~shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:162:53, :163:28] wire [26:0] roundPosMask = _roundPosMask_T & roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :163:{28,46}] wire [26:0] _roundPosBit_T = adjustedSig & roundPosMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire _roundIncr_T_1 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:67] wire _roundedSig_T_3 = roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :175:49] wire [26:0] _anyRoundExtra_T = adjustedSig & shiftedRoundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] wire roundIncr = _roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31] wire [26:0] _roundedSig_T = adjustedSig | roundMask; // @[RoundAnyRawFNToRecFN.scala:114:22, :159:42, :174:32] wire [24:0] _roundedSig_T_1 = _roundedSig_T[26:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [25:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 26'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [25:0] _roundedSig_T_6 = roundMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:159:42, :177:35] wire [25:0] _roundedSig_T_7 = _roundedSig_T_5 ? _roundedSig_T_6 : 26'h0; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}, :177:35] wire [25:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [25:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [26:0] _roundedSig_T_10 = ~roundMask; // @[RoundAnyRawFNToRecFN.scala:159:42, :180:32] wire [26:0] _roundedSig_T_11 = adjustedSig & _roundedSig_T_10; // @[RoundAnyRawFNToRecFN.scala:114:22, :180:{30,32}] wire [24:0] _roundedSig_T_12 = _roundedSig_T_11[26:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire [25:0] _roundedSig_T_14 = roundPosMask[26:1]; // @[RoundAnyRawFNToRecFN.scala:163:46, :181:67] wire [25:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12}; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}] wire [25:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[25:24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {io_in_sExp_0[9], io_in_sExp_0} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:48:5, :185:{40,76}] assign _common_expOut_T = sRoundedExp[8:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [22:0] _common_fractOut_T = roundedSig[23:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [22:0] _common_fractOut_T_1 = roundedSig[22:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = doShiftSigDown1 ? _common_fractOut_T : _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :189:16, :190:27, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [3:0] _common_overflow_T = sRoundedExp[10:7]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 4'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] assign _common_totalUnderflow_T = $signed(sRoundedExp) < 11'sh6B; // @[RoundAnyRawFNToRecFN.scala:185:40, :200:31] assign common_totalUnderflow = _common_totalUnderflow_T; // @[RoundAnyRawFNToRecFN.scala:125:37, :200:31] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:114:22, :203:61] wire unboundedRange_roundPosBit = doShiftSigDown1 ? _unboundedRange_roundPosBit_T : _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :203:{16,45,61}] wire _unboundedRange_roundIncr_T_1 = unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:67] wire _unboundedRange_anyRound_T_1 = doShiftSigDown1 & _unboundedRange_anyRound_T; // @[RoundAnyRawFNToRecFN.scala:120:57, :205:{30,44}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:114:22, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_1 | _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{30,49,70}] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46] wire _roundCarry_T = roundedSig[25]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[24]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = doShiftSigDown1 ? _roundCarry_T : _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:120:57, :211:16, :212:27, :213:27] wire [1:0] _common_underflow_T = io_in_sExp_0[9:8]; // @[RoundAnyRawFNToRecFN.scala:48:5, :220:49] wire _common_underflow_T_1 = _common_underflow_T != 2'h1; // @[RoundAnyRawFNToRecFN.scala:220:{49,64}] wire _common_underflow_T_2 = anyRound & _common_underflow_T_1; // @[RoundAnyRawFNToRecFN.scala:166:36, :220:{32,64}] wire _common_underflow_T_3 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57] wire _common_underflow_T_9 = roundMask[3]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:57, :225:49] wire _common_underflow_T_4 = roundMask[2]; // @[RoundAnyRawFNToRecFN.scala:159:42, :221:71] wire _common_underflow_T_5 = doShiftSigDown1 ? _common_underflow_T_3 : _common_underflow_T_4; // @[RoundAnyRawFNToRecFN.scala:120:57, :221:{30,57,71}] wire _common_underflow_T_6 = _common_underflow_T_2 & _common_underflow_T_5; // @[RoundAnyRawFNToRecFN.scala:220:{32,72}, :221:30] wire _common_underflow_T_8 = roundMask[4]; // @[RoundAnyRawFNToRecFN.scala:159:42, :224:49] wire _common_underflow_T_10 = doShiftSigDown1 ? _common_underflow_T_8 : _common_underflow_T_9; // @[RoundAnyRawFNToRecFN.scala:120:57, :223:39, :224:49, :225:49] wire _common_underflow_T_11 = ~_common_underflow_T_10; // @[RoundAnyRawFNToRecFN.scala:223:{34,39}] wire _common_underflow_T_12 = _common_underflow_T_11; // @[RoundAnyRawFNToRecFN.scala:222:77, :223:34] wire _common_underflow_T_13 = _common_underflow_T_12 & roundCarry; // @[RoundAnyRawFNToRecFN.scala:211:16, :222:77, :226:38] wire _common_underflow_T_14 = _common_underflow_T_13 & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :226:38, :227:45] wire _common_underflow_T_15 = _common_underflow_T_14 & unboundedRange_roundIncr; // @[RoundAnyRawFNToRecFN.scala:208:46, :227:{45,60}] wire _common_underflow_T_16 = ~_common_underflow_T_15; // @[RoundAnyRawFNToRecFN.scala:222:27, :227:60] wire _common_underflow_T_17 = _common_underflow_T_6 & _common_underflow_T_16; // @[RoundAnyRawFNToRecFN.scala:220:72, :221:76, :222:27] assign _common_underflow_T_18 = common_totalUnderflow | _common_underflow_T_17; // @[RoundAnyRawFNToRecFN.scala:125:37, :217:40, :221:76] assign common_underflow = _common_underflow_T_18; // @[RoundAnyRawFNToRecFN.scala:126:37, :217:40] assign _common_inexact_T = common_totalUnderflow | anyRound; // @[RoundAnyRawFNToRecFN.scala:125:37, :166:36, :230:49] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire isNaNOut = io_invalidExc_0 | io_in_isNaN_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34] wire _commonCase_T = ~isNaNOut; // @[RoundAnyRawFNToRecFN.scala:235:34, :237:22] wire _commonCase_T_1 = ~notNaN_isSpecialInfOut; // @[RoundAnyRawFNToRecFN.scala:236:49, :237:36] wire _commonCase_T_2 = _commonCase_T & _commonCase_T_1; // @[RoundAnyRawFNToRecFN.scala:237:{22,33,36}] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_2 & _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{33,61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _notNaN_isInfOut_T = overflow; // @[RoundAnyRawFNToRecFN.scala:238:32, :248:45] wire underflow = commonCase & common_underflow; // @[RoundAnyRawFNToRecFN.scala:126:37, :237:61, :239:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire _pegMinNonzeroMagOut_T = commonCase & common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :237:61, :245:20] wire notNaN_isInfOut = notNaN_isSpecialInfOut | _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:236:49, :248:{32,45}] wire signOut = ~isNaNOut & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :250:22] wire _expOut_T = io_in_isZero_0 | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:48:5, :125:37, :253:32] wire [8:0] _expOut_T_1 = _expOut_T ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [8:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [8:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [8:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [8:0] _expOut_T_10 = _expOut_T_7; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17] wire [8:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 6'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [8:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [8:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [8:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [8:0] _expOut_T_17 = _expOut_T_15; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15] wire [8:0] _expOut_T_18 = notNaN_isInfOut ? 9'h180 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [8:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [8:0] _expOut_T_20 = isNaNOut ? 9'h1C0 : 9'h0; // @[RoundAnyRawFNToRecFN.scala:235:34, :278:16] wire [8:0] expOut = _expOut_T_19 | _expOut_T_20; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73, :278:16] wire _fractOut_T = isNaNOut | io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :235:34, :280:22] wire _fractOut_T_1 = _fractOut_T | common_totalUnderflow; // @[RoundAnyRawFNToRecFN.scala:125:37, :280:{22,38}] wire [22:0] _fractOut_T_2 = {isNaNOut, 22'h0}; // @[RoundAnyRawFNToRecFN.scala:235:34, :281:16] wire [22:0] _fractOut_T_3 = _fractOut_T_1 ? _fractOut_T_2 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}, :281:16] wire [22:0] fractOut = _fractOut_T_3; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11] wire [9:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [1:0] _io_exceptionFlags_T = {io_invalidExc_0, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:23] wire [2:0] _io_exceptionFlags_T_1 = {_io_exceptionFlags_T, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:{23,41}] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, underflow}; // @[RoundAnyRawFNToRecFN.scala:239:32, :288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLROM : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_55 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready connect nodeIn, auto.in wire rom : UInt<64>[512] connect rom[0], UInt<64>(0h405051300000517) connect rom[1], UInt<64>(0h301022f330551073) connect rom[2], UInt<64>(0h12f2934122d293) connect rom[3], UInt<64>(0h3030107300028863) connect rom[4], UInt<64>(0h3445307322200513) connect rom[5], UInt<64>(0h3045107300800513) connect rom[6], UInt<64>(0h1050007330052073) connect rom[7], UInt<64>(0hffdff06f) connect rom[8], UInt<64>(0hf1402573020005b7) connect rom[9], UInt<64>(0h380006f00050463) connect rom[10], UInt<64>(0h10069300458613) connect rom[11], UInt<64>(0h46061300d62023) connect rom[12], UInt<64>(0hfe069ae3ffc62683) connect rom[13], UInt<64>(0h2c0006f) connect rom[14], UInt<64>(0h0) connect rom[15], UInt<64>(0h0) connect rom[16], UInt<64>(0h5a283f81ff06f) connect rom[17], UInt<64>(0h251513fe029ee3) connect rom[18], UInt<64>(0h5a02300b505b3) connect rom[19], UInt<64>(0h5350300001537) connect rom[20], UInt<64>(0hf140257334151073) connect rom[21], UInt<64>(0h185859300000597) connect rom[22], UInt<64>(0h3006307308000613) connect rom[23], UInt<64>(0h1330200073) connect rom[24], UInt<64>(0h780e0000edfe0dd0) connect rom[25], UInt<64>(0h180c000038000000) connect rom[26], UInt<64>(0h1100000028000000) connect rom[27], UInt<64>(0h10000000) connect rom[28], UInt<64>(0he00b000060020000) connect rom[29], UInt<64>(0h0) connect rom[30], UInt<64>(0h0) connect rom[31], UInt<64>(0h1000000) connect rom[32], UInt<64>(0h400000003000000) connect rom[33], UInt<64>(0h100000000000000) connect rom[34], UInt<64>(0h400000003000000) connect rom[35], UInt<64>(0h10000000f000000) connect rom[36], UInt<64>(0h1500000003000000) connect rom[37], UInt<64>(0h2d6263751b000000) connect rom[38], UInt<64>(0h706968632c726162) connect rom[39], UInt<64>(0h7665642d64726179) connect rom[40], UInt<64>(0h300000000000000) connect rom[41], UInt<64>(0h2600000011000000) connect rom[42], UInt<64>(0h2c7261622d626375) connect rom[43], UInt<64>(0h6472617970696863) connect rom[44], UInt<64>(0h100000000000000) connect rom[45], UInt<64>(0h73657361696c61) connect rom[46], UInt<64>(0h1500000003000000) connect rom[47], UInt<64>(0h636f732f2c000000) connect rom[48], UInt<64>(0h406c61697265732f) connect rom[49], UInt<64>(0h3030303032303031) connect rom[50], UInt<64>(0h200000000000000) connect rom[51], UInt<64>(0h736f686301000000) connect rom[52], UInt<64>(0h300000000006e65) connect rom[53], UInt<64>(0h3400000015000000) connect rom[54], UInt<64>(0h7265732f636f732f) connect rom[55], UInt<64>(0h32303031406c6169) connect rom[56], UInt<64>(0h30303030) connect rom[57], UInt<64>(0h100000002000000) connect rom[58], UInt<64>(0h73757063) connect rom[59], UInt<64>(0h400000003000000) connect rom[60], UInt<64>(0h100000000000000) connect rom[61], UInt<64>(0h400000003000000) connect rom[62], UInt<64>(0hf000000) connect rom[63], UInt<64>(0h400000003000000) connect rom[64], UInt<64>(0h20a1070040000000) connect rom[65], UInt<64>(0h4075706301000000) connect rom[66], UInt<64>(0h300000000000030) connect rom[67], UInt<64>(0h5300000004000000) connect rom[68], UInt<64>(0h300000000000000) connect rom[69], UInt<64>(0h1b00000014000000) connect rom[70], UInt<64>(0h2c7261622d626375) connect rom[71], UInt<64>(0h697200306d6f6f62) connect rom[72], UInt<64>(0h300000000766373) connect rom[73], UInt<64>(0h6300000004000000) connect rom[74], UInt<64>(0h300000040000000) connect rom[75], UInt<64>(0h7600000004000000) connect rom[76], UInt<64>(0h300000040000000) connect rom[77], UInt<64>(0h8300000004000000) connect rom[78], UInt<64>(0h300000000800000) connect rom[79], UInt<64>(0h9000000004000000) connect rom[80], UInt<64>(0h300000001000000) connect rom[81], UInt<64>(0h9b00000004000000) connect rom[82], UInt<64>(0h300000010000000) connect rom[83], UInt<64>(0ha600000004000000) connect rom[84], UInt<64>(0h300000000757063) connect rom[85], UInt<64>(0hb200000004000000) connect rom[86], UInt<64>(0h300000000000000) connect rom[87], UInt<64>(0hd100000004000000) connect rom[88], UInt<64>(0h300000040000000) connect rom[89], UInt<64>(0he400000004000000) connect rom[90], UInt<64>(0h300000040000000) connect rom[91], UInt<64>(0hf100000004000000) connect rom[92], UInt<64>(0h300000000800000) connect rom[93], UInt<64>(0hfe00000004000000) connect rom[94], UInt<64>(0h300000001000000) connect rom[95], UInt<64>(0h901000004000000) connect rom[96], UInt<64>(0h300000020000000) connect rom[97], UInt<64>(0h140100000b000000) connect rom[98], UInt<64>(0h76732c7663736972) connect rom[99], UInt<64>(0h300000000003933) connect rom[100], UInt<64>(0h1d01000004000000) connect rom[101], UInt<64>(0h300000001000000) connect rom[102], UInt<64>(0h2e01000004000000) connect rom[103], UInt<64>(0h300000000000000) connect rom[104], UInt<64>(0h320100001f000000) connect rom[105], UInt<64>(0h66616d6934367672) connect rom[106], UInt<64>(0h5f727363697a6364) connect rom[107], UInt<64>(0h6965636e6566697a) connect rom[108], UInt<64>(0h6d7068697a5f) connect rom[109], UInt<64>(0h400000003000000) connect rom[110], UInt<64>(0h40000003c010000) connect rom[111], UInt<64>(0h400000003000000) connect rom[112], UInt<64>(0h800000051010000) connect rom[113], UInt<64>(0h500000003000000) connect rom[114], UInt<64>(0h79616b6f62010000) connect rom[115], UInt<64>(0h300000000000000) connect rom[116], UInt<64>(0h4000000004000000) connect rom[117], UInt<64>(0h300000020a10700) connect rom[118], UInt<64>(0h6901000000000000) connect rom[119], UInt<64>(0h65746e6901000000) connect rom[120], UInt<64>(0h6f632d7470757272) connect rom[121], UInt<64>(0h72656c6c6f72746e) connect rom[122], UInt<64>(0h300000000000000) connect rom[123], UInt<64>(0h7301000004000000) connect rom[124], UInt<64>(0h300000001000000) connect rom[125], UInt<64>(0h1b0000000f000000) connect rom[126], UInt<64>(0h70632c7663736972) connect rom[127], UInt<64>(0h63746e692d75) connect rom[128], UInt<64>(0h3000000) connect rom[129], UInt<64>(0h300000084010000) connect rom[130], UInt<64>(0h9901000004000000) connect rom[131], UInt<64>(0h200000004000000) connect rom[132], UInt<64>(0h200000002000000) connect rom[133], UInt<64>(0h6669746801000000) connect rom[134], UInt<64>(0h300000000000000) connect rom[135], UInt<64>(0h1b0000000a000000) connect rom[136], UInt<64>(0h666974682c626375) connect rom[137], UInt<64>(0h200000000000030) connect rom[138], UInt<64>(0h6f6d656d01000000) connect rom[139], UInt<64>(0h3030303038407972) connect rom[140], UInt<64>(0h300000000003030) connect rom[141], UInt<64>(0ha600000007000000) connect rom[142], UInt<64>(0h79726f6d656d) connect rom[143], UInt<64>(0h800000003000000) connect rom[144], UInt<64>(0h82e010000) connect rom[145], UInt<64>(0h300000000000100) connect rom[146], UInt<64>(0h6201000009000000) connect rom[147], UInt<64>(0h64656c6261736964) connect rom[148], UInt<64>(0h300000000000000) connect rom[149], UInt<64>(0h9901000004000000) connect rom[150], UInt<64>(0h200000003000000) connect rom[151], UInt<64>(0h6f6d656d01000000) connect rom[152], UInt<64>(0h3030303038407972) connect rom[153], UInt<64>(0h300000000303030) connect rom[154], UInt<64>(0ha600000007000000) connect rom[155], UInt<64>(0h79726f6d656d) connect rom[156], UInt<64>(0h800000003000000) connect rom[157], UInt<64>(0h802e010000) connect rom[158], UInt<64>(0h300000000000010) connect rom[159], UInt<64>(0h9901000004000000) connect rom[160], UInt<64>(0h200000002000000) connect rom[161], UInt<64>(0h636f7301000000) connect rom[162], UInt<64>(0h400000003000000) connect rom[163], UInt<64>(0h100000000000000) connect rom[164], UInt<64>(0h400000003000000) connect rom[165], UInt<64>(0h10000000f000000) connect rom[166], UInt<64>(0h2000000003000000) connect rom[167], UInt<64>(0h2d6263751b000000) connect rom[168], UInt<64>(0h706968632c726162) connect rom[169], UInt<64>(0h636f732d64726179) connect rom[170], UInt<64>(0h2d656c706d697300) connect rom[171], UInt<64>(0h300000000737562) connect rom[172], UInt<64>(0ha101000000000000) connect rom[173], UInt<64>(0h746f6f6201000000) connect rom[174], UInt<64>(0h737365726464612d) connect rom[175], UInt<64>(0h303031406765722d) connect rom[176], UInt<64>(0h300000000000030) connect rom[177], UInt<64>(0h2e01000008000000) connect rom[178], UInt<64>(0h10000000100000) connect rom[179], UInt<64>(0h800000003000000) connect rom[180], UInt<64>(0h746e6f63a8010000) connect rom[181], UInt<64>(0h2000000006c6f72) connect rom[182], UInt<64>(0h6863616301000000) connect rom[183], UInt<64>(0h6f72746e6f632d65) connect rom[184], UInt<64>(0h3130324072656c6c) connect rom[185], UInt<64>(0h30303030) connect rom[186], UInt<64>(0h400000003000000) connect rom[187], UInt<64>(0h4000000065000000) connect rom[188], UInt<64>(0h400000003000000) connect rom[189], UInt<64>(0h2000000b2010000) connect rom[190], UInt<64>(0h400000003000000) connect rom[191], UInt<64>(0h4000078000000) connect rom[192], UInt<64>(0h400000003000000) connect rom[193], UInt<64>(0h80085000000) connect rom[194], UInt<64>(0h3000000) connect rom[195], UInt<64>(0h3000000be010000) connect rom[196], UInt<64>(0h1b0000001d000000) connect rom[197], UInt<64>(0h692c657669666973) connect rom[198], UInt<64>(0h65766973756c636e) connect rom[199], UInt<64>(0h6300306568636163) connect rom[200], UInt<64>(0h65686361) connect rom[201], UInt<64>(0h800000003000000) connect rom[202], UInt<64>(0h20000001d010000) connect rom[203], UInt<64>(0h300000003000000) connect rom[204], UInt<64>(0h2e01000008000000) connect rom[205], UInt<64>(0h10000000000102) connect rom[206], UInt<64>(0h800000003000000) connect rom[207], UInt<64>(0h746e6f63a8010000) connect rom[208], UInt<64>(0h3000000006c6f72) connect rom[209], UInt<64>(0hcc01000004000000) connect rom[210], UInt<64>(0h30000000c000000) connect rom[211], UInt<64>(0h9901000004000000) connect rom[212], UInt<64>(0h200000001000000) connect rom[213], UInt<64>(0h7375626301000000) connect rom[214], UInt<64>(0h6b636f6c635f) connect rom[215], UInt<64>(0h400000003000000) connect rom[216], UInt<64>(0hde010000) connect rom[217], UInt<64>(0h400000003000000) connect rom[218], UInt<64>(0h65cd1d53000000) connect rom[219], UInt<64>(0hb00000003000000) connect rom[220], UInt<64>(0h73756263eb010000) connect rom[221], UInt<64>(0h6b636f6c635f) connect rom[222], UInt<64>(0hc00000003000000) connect rom[223], UInt<64>(0h657869661b000000) connect rom[224], UInt<64>(0h6b636f6c632d64) connect rom[225], UInt<64>(0h100000002000000) connect rom[226], UInt<64>(0h303240746e696c63) connect rom[227], UInt<64>(0h3030303030) connect rom[228], UInt<64>(0hd00000003000000) connect rom[229], UInt<64>(0h637369721b000000) connect rom[230], UInt<64>(0h30746e696c632c76) connect rom[231], UInt<64>(0h300000000000000) connect rom[232], UInt<64>(0hfe01000010000000) connect rom[233], UInt<64>(0h300000004000000) connect rom[234], UInt<64>(0h700000004000000) connect rom[235], UInt<64>(0h800000003000000) connect rom[236], UInt<64>(0h22e010000) connect rom[237], UInt<64>(0h300000000000100) connect rom[238], UInt<64>(0ha801000008000000) connect rom[239], UInt<64>(0h6c6f72746e6f63) connect rom[240], UInt<64>(0h100000002000000) connect rom[241], UInt<64>(0h61672d6b636f6c63) connect rom[242], UInt<64>(0h3030303140726574) connect rom[243], UInt<64>(0h300000000003030) connect rom[244], UInt<64>(0h2e01000008000000) connect rom[245], UInt<64>(0h10000000001000) connect rom[246], UInt<64>(0h800000003000000) connect rom[247], UInt<64>(0h746e6f63a8010000) connect rom[248], UInt<64>(0h2000000006c6f72) connect rom[249], UInt<64>(0h7562656401000000) connect rom[250], UInt<64>(0h6f72746e6f632d67) connect rom[251], UInt<64>(0h304072656c6c) connect rom[252], UInt<64>(0h2100000003000000) connect rom[253], UInt<64>(0h696669731b000000) connect rom[254], UInt<64>(0h67756265642c6576) connect rom[255], UInt<64>(0h736972003331302d) connect rom[256], UInt<64>(0h67756265642c7663) connect rom[257], UInt<64>(0h3331302d) connect rom[258], UInt<64>(0h500000003000000) connect rom[259], UInt<64>(0h6761746a12020000) connect rom[260], UInt<64>(0h300000000000000) connect rom[261], UInt<64>(0hfe01000008000000) connect rom[262], UInt<64>(0hffff000004000000) connect rom[263], UInt<64>(0h800000003000000) connect rom[264], UInt<64>(0h2e010000) connect rom[265], UInt<64>(0h300000000100000) connect rom[266], UInt<64>(0ha801000008000000) connect rom[267], UInt<64>(0h6c6f72746e6f63) connect rom[268], UInt<64>(0h100000002000000) connect rom[269], UInt<64>(0h65642d726f727265) connect rom[270], UInt<64>(0h3030334065636976) connect rom[271], UInt<64>(0h300000000000030) connect rom[272], UInt<64>(0h1b0000000e000000) connect rom[273], UInt<64>(0h652c657669666973) connect rom[274], UInt<64>(0h30726f7272) connect rom[275], UInt<64>(0h800000003000000) connect rom[276], UInt<64>(0h3000002e010000) connect rom[277], UInt<64>(0h200000000100000) connect rom[278], UInt<64>(0h7375626601000000) connect rom[279], UInt<64>(0h6b636f6c635f) connect rom[280], UInt<64>(0h400000003000000) connect rom[281], UInt<64>(0hde010000) connect rom[282], UInt<64>(0h400000003000000) connect rom[283], UInt<64>(0h65cd1d53000000) connect rom[284], UInt<64>(0hb00000003000000) connect rom[285], UInt<64>(0h73756266eb010000) connect rom[286], UInt<64>(0h6b636f6c635f) connect rom[287], UInt<64>(0hc00000003000000) connect rom[288], UInt<64>(0h657869661b000000) connect rom[289], UInt<64>(0h6b636f6c632d64) connect rom[290], UInt<64>(0h100000002000000) connect rom[291], UInt<64>(0h4063696e2d656369) connect rom[292], UInt<64>(0h3030303631303031) connect rom[293], UInt<64>(0h300000000000000) connect rom[294], UInt<64>(0h1b00000010000000) connect rom[295], UInt<64>(0h2c7261622d626375) connect rom[296], UInt<64>(0h63696e2d656369) connect rom[297], UInt<64>(0h400000003000000) connect rom[298], UInt<64>(0h50000001f020000) connect rom[299], UInt<64>(0h800000003000000) connect rom[300], UInt<64>(0h200000030020000) connect rom[301], UInt<64>(0h300000003000000) connect rom[302], UInt<64>(0h2e01000008000000) connect rom[303], UInt<64>(0h10000000600110) connect rom[304], UInt<64>(0h800000003000000) connect rom[305], UInt<64>(0h746e6f63a8010000) connect rom[306], UInt<64>(0h2000000006c6f72) connect rom[307], UInt<64>(0h65746e6901000000) connect rom[308], UInt<64>(0h6f632d7470757272) connect rom[309], UInt<64>(0h72656c6c6f72746e) connect rom[310], UInt<64>(0h3030303030306340) connect rom[311], UInt<64>(0h300000000000000) connect rom[312], UInt<64>(0h7301000004000000) connect rom[313], UInt<64>(0h300000001000000) connect rom[314], UInt<64>(0h1b0000000c000000) connect rom[315], UInt<64>(0h6c702c7663736972) connect rom[316], UInt<64>(0h300000000306369) connect rom[317], UInt<64>(0h8401000000000000) connect rom[318], UInt<64>(0h1000000003000000) connect rom[319], UInt<64>(0h4000000fe010000) connect rom[320], UInt<64>(0h40000000b000000) connect rom[321], UInt<64>(0h300000009000000) connect rom[322], UInt<64>(0h2e01000008000000) connect rom[323], UInt<64>(0h40000000c) connect rom[324], UInt<64>(0h800000003000000) connect rom[325], UInt<64>(0h746e6f63a8010000) connect rom[326], UInt<64>(0h3000000006c6f72) connect rom[327], UInt<64>(0h3b02000004000000) connect rom[328], UInt<64>(0h300000003000000) connect rom[329], UInt<64>(0h4e02000004000000) connect rom[330], UInt<64>(0h300000003000000) connect rom[331], UInt<64>(0h9901000004000000) connect rom[332], UInt<64>(0h200000005000000) connect rom[333], UInt<64>(0h7375626d01000000) connect rom[334], UInt<64>(0h6b636f6c635f) connect rom[335], UInt<64>(0h400000003000000) connect rom[336], UInt<64>(0hde010000) connect rom[337], UInt<64>(0h400000003000000) connect rom[338], UInt<64>(0h65cd1d53000000) connect rom[339], UInt<64>(0hb00000003000000) connect rom[340], UInt<64>(0h7375626deb010000) connect rom[341], UInt<64>(0h6b636f6c635f) connect rom[342], UInt<64>(0hc00000003000000) connect rom[343], UInt<64>(0h657869661b000000) connect rom[344], UInt<64>(0h6b636f6c632d64) connect rom[345], UInt<64>(0h100000002000000) connect rom[346], UInt<64>(0h6f6c635f73756270) connect rom[347], UInt<64>(0h300000000006b63) connect rom[348], UInt<64>(0hde01000004000000) connect rom[349], UInt<64>(0h300000000000000) connect rom[350], UInt<64>(0h5300000004000000) connect rom[351], UInt<64>(0h30000000065cd1d) connect rom[352], UInt<64>(0heb0100000b000000) connect rom[353], UInt<64>(0h6f6c635f73756270) connect rom[354], UInt<64>(0h300000000006b63) connect rom[355], UInt<64>(0h1b0000000c000000) connect rom[356], UInt<64>(0h6c632d6465786966) connect rom[357], UInt<64>(0h3000000006b636f) connect rom[358], UInt<64>(0h9901000004000000) connect rom[359], UInt<64>(0h200000006000000) connect rom[360], UInt<64>(0h406d6f7201000000) connect rom[361], UInt<64>(0h3030303031) connect rom[362], UInt<64>(0hc00000003000000) connect rom[363], UInt<64>(0h696669731b000000) connect rom[364], UInt<64>(0h306d6f722c6576) connect rom[365], UInt<64>(0h800000003000000) connect rom[366], UInt<64>(0h1002e010000) connect rom[367], UInt<64>(0h300000000000100) connect rom[368], UInt<64>(0ha801000004000000) connect rom[369], UInt<64>(0h2000000006d656d) connect rom[370], UInt<64>(0h7375627301000000) connect rom[371], UInt<64>(0h6b636f6c635f) connect rom[372], UInt<64>(0h400000003000000) connect rom[373], UInt<64>(0hde010000) connect rom[374], UInt<64>(0h400000003000000) connect rom[375], UInt<64>(0h65cd1d53000000) connect rom[376], UInt<64>(0hb00000003000000) connect rom[377], UInt<64>(0h73756273eb010000) connect rom[378], UInt<64>(0h6b636f6c635f) connect rom[379], UInt<64>(0hc00000003000000) connect rom[380], UInt<64>(0h657869661b000000) connect rom[381], UInt<64>(0h6b636f6c632d64) connect rom[382], UInt<64>(0h100000002000000) connect rom[383], UInt<64>(0h31406c6169726573) connect rom[384], UInt<64>(0h30303030323030) connect rom[385], UInt<64>(0h400000003000000) connect rom[386], UInt<64>(0h600000059020000) connect rom[387], UInt<64>(0hd00000003000000) connect rom[388], UInt<64>(0h696669731b000000) connect rom[389], UInt<64>(0h30747261752c6576) connect rom[390], UInt<64>(0h300000000000000) connect rom[391], UInt<64>(0h1f02000004000000) connect rom[392], UInt<64>(0h300000005000000) connect rom[393], UInt<64>(0h3002000004000000) connect rom[394], UInt<64>(0h300000001000000) connect rom[395], UInt<64>(0h2e01000008000000) connect rom[396], UInt<64>(0h10000000000210) connect rom[397], UInt<64>(0h800000003000000) connect rom[398], UInt<64>(0h746e6f63a8010000) connect rom[399], UInt<64>(0h2000000006c6f72) connect rom[400], UInt<64>(0h656c697401000000) connect rom[401], UInt<64>(0h732d74657365722d) connect rom[402], UInt<64>(0h3131407265747465) connect rom[403], UInt<64>(0h30303030) connect rom[404], UInt<64>(0h800000003000000) connect rom[405], UInt<64>(0h11002e010000) connect rom[406], UInt<64>(0h300000000100000) connect rom[407], UInt<64>(0ha801000008000000) connect rom[408], UInt<64>(0h6c6f72746e6f63) connect rom[409], UInt<64>(0h200000002000000) connect rom[410], UInt<64>(0h900000002000000) connect rom[411], UInt<64>(0h7373657264646123) connect rom[412], UInt<64>(0h2300736c6c65632d) connect rom[413], UInt<64>(0h6c65632d657a6973) connect rom[414], UInt<64>(0h61706d6f6300736c) connect rom[415], UInt<64>(0h6f6d00656c626974) connect rom[416], UInt<64>(0h69726573006c6564) connect rom[417], UInt<64>(0h6f64747300306c61) connect rom[418], UInt<64>(0h687461702d7475) connect rom[419], UInt<64>(0h65736162656d6974) connect rom[420], UInt<64>(0h6e6575716572662d) connect rom[421], UInt<64>(0h6b636f6c63007963) connect rom[422], UInt<64>(0h6e6575716572662d) connect rom[423], UInt<64>(0h6361632d64007963) connect rom[424], UInt<64>(0h6b636f6c622d6568) connect rom[425], UInt<64>(0h2d6400657a69732d) connect rom[426], UInt<64>(0h65732d6568636163) connect rom[427], UInt<64>(0h6361632d64007374) connect rom[428], UInt<64>(0h657a69732d6568) connect rom[429], UInt<64>(0h65732d626c742d64) connect rom[430], UInt<64>(0h626c742d64007374) connect rom[431], UInt<64>(0h656400657a69732d) connect rom[432], UInt<64>(0h7079745f65636976) connect rom[433], UInt<64>(0h6177647261680065) connect rom[434], UInt<64>(0h2d636578652d6572) connect rom[435], UInt<64>(0h696f706b61657262) connect rom[436], UInt<64>(0h746e756f632d746e) connect rom[437], UInt<64>(0h65686361632d6900) connect rom[438], UInt<64>(0h732d6b636f6c622d) connect rom[439], UInt<64>(0h61632d6900657a69) connect rom[440], UInt<64>(0h737465732d656863) connect rom[441], UInt<64>(0h65686361632d6900) connect rom[442], UInt<64>(0h2d6900657a69732d) connect rom[443], UInt<64>(0h737465732d626c74) connect rom[444], UInt<64>(0h732d626c742d6900) connect rom[445], UInt<64>(0h2d756d6d00657a69) connect rom[446], UInt<64>(0h78656e0065707974) connect rom[447], UInt<64>(0h2d6c6576656c2d74) connect rom[448], UInt<64>(0h6572006568636163) connect rom[449], UInt<64>(0h2c76637369720067) connect rom[450], UInt<64>(0h6373697200617369) connect rom[451], UInt<64>(0h617267706d702c76) connect rom[452], UInt<64>(0h79746972616c756e) connect rom[453], UInt<64>(0h702c766373697200) connect rom[454], UInt<64>(0h6e6f69676572706d) connect rom[455], UInt<64>(0h7375746174730073) connect rom[456], UInt<64>(0h6c70732d626c7400) connect rom[457], UInt<64>(0h65746e6923007469) connect rom[458], UInt<64>(0h65632d7470757272) connect rom[459], UInt<64>(0h65746e6900736c6c) connect rom[460], UInt<64>(0h6f632d7470757272) connect rom[461], UInt<64>(0h72656c6c6f72746e) connect rom[462], UInt<64>(0h656c646e61687000) connect rom[463], UInt<64>(0h7365676e617200) connect rom[464], UInt<64>(0h656d616e2d676572) connect rom[465], UInt<64>(0h2d65686361630073) connect rom[466], UInt<64>(0h6163006c6576656c) connect rom[467], UInt<64>(0h66696e752d656863) connect rom[468], UInt<64>(0h6966697300646569) connect rom[469], UInt<64>(0h2d7268736d2c6576) connect rom[470], UInt<64>(0h632300746e756f63) connect rom[471], UInt<64>(0h6c65632d6b636f6c) connect rom[472], UInt<64>(0h6b636f6c6300736c) connect rom[473], UInt<64>(0h2d74757074756f2d) connect rom[474], UInt<64>(0h6e690073656d616e) connect rom[475], UInt<64>(0h7374707572726574) connect rom[476], UInt<64>(0h65646e657478652d) connect rom[477], UInt<64>(0h2d67756265640064) connect rom[478], UInt<64>(0h6900686361747461) connect rom[479], UInt<64>(0h747075727265746e) connect rom[480], UInt<64>(0h746e657261702d) connect rom[481], UInt<64>(0h7075727265746e69) connect rom[482], UInt<64>(0h7663736972007374) connect rom[483], UInt<64>(0h6972702d78616d2c) connect rom[484], UInt<64>(0h697200797469726f) connect rom[485], UInt<64>(0h7665646e2c766373) connect rom[486], UInt<64>(0h736b636f6c6300) connect rom[487], UInt<64>(0h0) connect rom[488], UInt<64>(0h0) connect rom[489], UInt<64>(0h0) connect rom[490], UInt<64>(0h0) connect rom[491], UInt<64>(0h0) connect rom[492], UInt<64>(0h0) connect rom[493], UInt<64>(0h0) connect rom[494], UInt<64>(0h0) connect rom[495], UInt<64>(0h0) connect rom[496], UInt<64>(0h0) connect rom[497], UInt<64>(0h0) connect rom[498], UInt<64>(0h0) connect rom[499], UInt<64>(0h0) connect rom[500], UInt<64>(0h0) connect rom[501], UInt<64>(0h0) connect rom[502], UInt<64>(0h0) connect rom[503], UInt<64>(0h0) connect rom[504], UInt<64>(0h0) connect rom[505], UInt<64>(0h0) connect rom[506], UInt<64>(0h0) connect rom[507], UInt<64>(0h0) connect rom[508], UInt<64>(0h0) connect rom[509], UInt<64>(0h0) connect rom[510], UInt<64>(0h0) connect rom[511], UInt<64>(0h0) connect nodeIn.d.valid, nodeIn.a.valid connect nodeIn.a.ready, nodeIn.d.ready node index = bits(nodeIn.a.bits.address, 11, 3) node high = bits(nodeIn.a.bits.address, 15, 12) node _nodeIn_d_bits_T = orr(high) node _nodeIn_d_bits_T_1 = mux(_nodeIn_d_bits_T, UInt<1>(0h0), rom[index]) wire nodeIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect nodeIn_d_bits_d.opcode, UInt<1>(0h1) connect nodeIn_d_bits_d.param, UInt<1>(0h0) connect nodeIn_d_bits_d.size, nodeIn.a.bits.size connect nodeIn_d_bits_d.source, nodeIn.a.bits.source connect nodeIn_d_bits_d.sink, UInt<1>(0h0) connect nodeIn_d_bits_d.denied, UInt<1>(0h0) connect nodeIn_d_bits_d.data, _nodeIn_d_bits_T_1 connect nodeIn_d_bits_d.corrupt, UInt<1>(0h0) connect nodeIn.d.bits.corrupt, nodeIn_d_bits_d.corrupt connect nodeIn.d.bits.data, nodeIn_d_bits_d.data connect nodeIn.d.bits.denied, nodeIn_d_bits_d.denied connect nodeIn.d.bits.sink, nodeIn_d_bits_d.sink connect nodeIn.d.bits.source, nodeIn_d_bits_d.source connect nodeIn.d.bits.size, nodeIn_d_bits_d.size connect nodeIn.d.bits.param, nodeIn_d_bits_d.param connect nodeIn.d.bits.opcode, nodeIn_d_bits_d.opcode wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<17>(0h0) connect _WIRE.bits.source, UInt<12>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<17>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<17>(0h0) connect _WIRE_2.bits.source, UInt<12>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<17>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1)
module TLROM( // @[BootROM.scala:41:9] input clock, // @[BootROM.scala:41:9] input reset, // @[BootROM.scala:41:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [16:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire auto_in_a_valid_0 = auto_in_a_valid; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[BootROM.scala:41:9] wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[BootROM.scala:41:9] wire [1:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[BootROM.scala:41:9] wire [11:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[BootROM.scala:41:9] wire [16:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[BootROM.scala:41:9] wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[BootROM.scala:41:9] wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[BootROM.scala:41:9] wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[BootROM.scala:41:9] wire auto_in_d_ready_0 = auto_in_d_ready; // @[BootROM.scala:41:9] wire [511:0][63:0] _GEN = '{64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h0, 64'h736B636F6C6300, 64'h7665646E2C766373, 64'h697200797469726F, 64'h6972702D78616D2C, 64'h7663736972007374, 64'h7075727265746E69, 64'h746E657261702D, 64'h747075727265746E, 64'h6900686361747461, 64'h2D67756265640064, 64'h65646E657478652D, 64'h7374707572726574, 64'h6E690073656D616E, 64'h2D74757074756F2D, 64'h6B636F6C6300736C, 64'h6C65632D6B636F6C, 64'h632300746E756F63, 64'h2D7268736D2C6576, 64'h6966697300646569, 64'h66696E752D656863, 64'h6163006C6576656C, 64'h2D65686361630073, 64'h656D616E2D676572, 64'h7365676E617200, 64'h656C646E61687000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6900736C6C, 64'h65632D7470757272, 64'h65746E6923007469, 64'h6C70732D626C7400, 64'h7375746174730073, 64'h6E6F69676572706D, 64'h702C766373697200, 64'h79746972616C756E, 64'h617267706D702C76, 64'h6373697200617369, 64'h2C76637369720067, 64'h6572006568636163, 64'h2D6C6576656C2D74, 64'h78656E0065707974, 64'h2D756D6D00657A69, 64'h732D626C742D6900, 64'h737465732D626C74, 64'h2D6900657A69732D, 64'h65686361632D6900, 64'h737465732D656863, 64'h61632D6900657A69, 64'h732D6B636F6C622D, 64'h65686361632D6900, 64'h746E756F632D746E, 64'h696F706B61657262, 64'h2D636578652D6572, 64'h6177647261680065, 64'h7079745F65636976, 64'h656400657A69732D, 64'h626C742D64007374, 64'h65732D626C742D64, 64'h657A69732D6568, 64'h6361632D64007374, 64'h65732D6568636163, 64'h2D6400657A69732D, 64'h6B636F6C622D6568, 64'h6361632D64007963, 64'h6E6575716572662D, 64'h6B636F6C63007963, 64'h6E6575716572662D, 64'h65736162656D6974, 64'h687461702D7475, 64'h6F64747300306C61, 64'h69726573006C6564, 64'h6F6D00656C626974, 64'h61706D6F6300736C, 64'h6C65632D657A6973, 64'h2300736C6C65632D, 64'h7373657264646123, 64'h900000002000000, 64'h200000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h11002E010000, 64'h800000003000000, 64'h30303030, 64'h3131407265747465, 64'h732D74657365722D, 64'h656C697401000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000000210, 64'h2E01000008000000, 64'h300000001000000, 64'h3002000004000000, 64'h300000005000000, 64'h1F02000004000000, 64'h300000000000000, 64'h30747261752C6576, 64'h696669731B000000, 64'hD00000003000000, 64'h600000059020000, 64'h400000003000000, 64'h30303030323030, 64'h31406C6169726573, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h73756273EB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375627301000000, 64'h2000000006D656D, 64'hA801000004000000, 64'h300000000000100, 64'h1002E010000, 64'h800000003000000, 64'h306D6F722C6576, 64'h696669731B000000, 64'hC00000003000000, 64'h3030303031, 64'h406D6F7201000000, 64'h200000006000000, 64'h9901000004000000, 64'h3000000006B636F, 64'h6C632D6465786966, 64'h1B0000000C000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'hEB0100000B000000, 64'h30000000065CD1D, 64'h5300000004000000, 64'h300000000000000, 64'hDE01000004000000, 64'h300000000006B63, 64'h6F6C635F73756270, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h7375626DEB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626D01000000, 64'h200000005000000, 64'h9901000004000000, 64'h300000003000000, 64'h4E02000004000000, 64'h300000003000000, 64'h3B02000004000000, 64'h3000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h40000000C, 64'h2E01000008000000, 64'h300000009000000, 64'h40000000B000000, 64'h4000000FE010000, 64'h1000000003000000, 64'h8401000000000000, 64'h300000000306369, 64'h6C702C7663736972, 64'h1B0000000C000000, 64'h300000001000000, 64'h7301000004000000, 64'h300000000000000, 64'h3030303030306340, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000600110, 64'h2E01000008000000, 64'h300000003000000, 64'h200000030020000, 64'h800000003000000, 64'h50000001F020000, 64'h400000003000000, 64'h63696E2D656369, 64'h2C7261622D626375, 64'h1B00000010000000, 64'h300000000000000, 64'h3030303631303031, 64'h4063696E2D656369, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h73756266EB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626601000000, 64'h200000000100000, 64'h3000002E010000, 64'h800000003000000, 64'h30726F7272, 64'h652C657669666973, 64'h1B0000000E000000, 64'h300000000000030, 64'h3030334065636976, 64'h65642D726F727265, 64'h100000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000100000, 64'h2E010000, 64'h800000003000000, 64'hFFFF000004000000, 64'hFE01000008000000, 64'h300000000000000, 64'h6761746A12020000, 64'h500000003000000, 64'h3331302D, 64'h67756265642C7663, 64'h736972003331302D, 64'h67756265642C6576, 64'h696669731B000000, 64'h2100000003000000, 64'h304072656C6C, 64'h6F72746E6F632D67, 64'h7562656401000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000001000, 64'h2E01000008000000, 64'h300000000003030, 64'h3030303140726574, 64'h61672D6B636F6C63, 64'h100000002000000, 64'h6C6F72746E6F63, 64'hA801000008000000, 64'h300000000000100, 64'h22E010000, 64'h800000003000000, 64'h700000004000000, 64'h300000004000000, 64'hFE01000010000000, 64'h300000000000000, 64'h30746E696C632C76, 64'h637369721B000000, 64'hD00000003000000, 64'h3030303030, 64'h303240746E696C63, 64'h100000002000000, 64'h6B636F6C632D64, 64'h657869661B000000, 64'hC00000003000000, 64'h6B636F6C635F, 64'h73756263EB010000, 64'hB00000003000000, 64'h65CD1D53000000, 64'h400000003000000, 64'hDE010000, 64'h400000003000000, 64'h6B636F6C635F, 64'h7375626301000000, 64'h200000001000000, 64'h9901000004000000, 64'h30000000C000000, 64'hCC01000004000000, 64'h3000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000000102, 64'h2E01000008000000, 64'h300000003000000, 64'h20000001D010000, 64'h800000003000000, 64'h65686361, 64'h6300306568636163, 64'h65766973756C636E, 64'h692C657669666973, 64'h1B0000001D000000, 64'h3000000BE010000, 64'h3000000, 64'h80085000000, 64'h400000003000000, 64'h4000078000000, 64'h400000003000000, 64'h2000000B2010000, 64'h400000003000000, 64'h4000000065000000, 64'h400000003000000, 64'h30303030, 64'h3130324072656C6C, 64'h6F72746E6F632D65, 64'h6863616301000000, 64'h2000000006C6F72, 64'h746E6F63A8010000, 64'h800000003000000, 64'h10000000100000, 64'h2E01000008000000, 64'h300000000000030, 64'h303031406765722D, 64'h737365726464612D, 64'h746F6F6201000000, 64'hA101000000000000, 64'h300000000737562, 64'h2D656C706D697300, 64'h636F732D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h2000000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h636F7301000000, 64'h200000002000000, 64'h9901000004000000, 64'h300000000000010, 64'h802E010000, 64'h800000003000000, 64'h79726F6D656D, 64'hA600000007000000, 64'h300000000303030, 64'h3030303038407972, 64'h6F6D656D01000000, 64'h200000003000000, 64'h9901000004000000, 64'h300000000000000, 64'h64656C6261736964, 64'h6201000009000000, 64'h300000000000100, 64'h82E010000, 64'h800000003000000, 64'h79726F6D656D, 64'hA600000007000000, 64'h300000000003030, 64'h3030303038407972, 64'h6F6D656D01000000, 64'h200000000000030, 64'h666974682C626375, 64'h1B0000000A000000, 64'h300000000000000, 64'h6669746801000000, 64'h200000002000000, 64'h200000004000000, 64'h9901000004000000, 64'h300000084010000, 64'h3000000, 64'h63746E692D75, 64'h70632C7663736972, 64'h1B0000000F000000, 64'h300000001000000, 64'h7301000004000000, 64'h300000000000000, 64'h72656C6C6F72746E, 64'h6F632D7470757272, 64'h65746E6901000000, 64'h6901000000000000, 64'h300000020A10700, 64'h4000000004000000, 64'h300000000000000, 64'h79616B6F62010000, 64'h500000003000000, 64'h800000051010000, 64'h400000003000000, 64'h40000003C010000, 64'h400000003000000, 64'h6D7068697A5F, 64'h6965636E6566697A, 64'h5F727363697A6364, 64'h66616D6934367672, 64'h320100001F000000, 64'h300000000000000, 64'h2E01000004000000, 64'h300000001000000, 64'h1D01000004000000, 64'h300000000003933, 64'h76732C7663736972, 64'h140100000B000000, 64'h300000020000000, 64'h901000004000000, 64'h300000001000000, 64'hFE00000004000000, 64'h300000000800000, 64'hF100000004000000, 64'h300000040000000, 64'hE400000004000000, 64'h300000040000000, 64'hD100000004000000, 64'h300000000000000, 64'hB200000004000000, 64'h300000000757063, 64'hA600000004000000, 64'h300000010000000, 64'h9B00000004000000, 64'h300000001000000, 64'h9000000004000000, 64'h300000000800000, 64'h8300000004000000, 64'h300000040000000, 64'h7600000004000000, 64'h300000040000000, 64'h6300000004000000, 64'h300000000766373, 64'h697200306D6F6F62, 64'h2C7261622D626375, 64'h1B00000014000000, 64'h300000000000000, 64'h5300000004000000, 64'h300000000000030, 64'h4075706301000000, 64'h20A1070040000000, 64'h400000003000000, 64'hF000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h73757063, 64'h100000002000000, 64'h30303030, 64'h32303031406C6169, 64'h7265732F636F732F, 64'h3400000015000000, 64'h300000000006E65, 64'h736F686301000000, 64'h200000000000000, 64'h3030303032303031, 64'h406C61697265732F, 64'h636F732F2C000000, 64'h1500000003000000, 64'h73657361696C61, 64'h100000000000000, 64'h6472617970696863, 64'h2C7261622D626375, 64'h2600000011000000, 64'h300000000000000, 64'h7665642D64726179, 64'h706968632C726162, 64'h2D6263751B000000, 64'h1500000003000000, 64'h10000000F000000, 64'h400000003000000, 64'h100000000000000, 64'h400000003000000, 64'h1000000, 64'h0, 64'h0, 64'hE00B000060020000, 64'h10000000, 64'h1100000028000000, 64'h180C000038000000, 64'h780E0000EDFE0DD0, 64'h1330200073, 64'h3006307308000613, 64'h185859300000597, 64'hF140257334151073, 64'h5350300001537, 64'h5A02300B505B3, 64'h251513FE029EE3, 64'h5A283F81FF06F, 64'h0, 64'h0, 64'h2C0006F, 64'hFE069AE3FFC62683, 64'h46061300D62023, 64'h10069300458613, 64'h380006F00050463, 64'hF1402573020005B7, 64'hFFDFF06F, 64'h1050007330052073, 64'h3045107300800513, 64'h3445307322200513, 64'h3030107300028863, 64'h12F2934122D293, 64'h301022F330551073, 64'h405051300000517}; wire [63:0] rom_0 = 64'h405051300000517; // @[BootROM.scala:50:22] wire [63:0] rom_1 = 64'h301022F330551073; // @[BootROM.scala:50:22] wire [63:0] rom_2 = 64'h12F2934122D293; // @[BootROM.scala:50:22] wire [63:0] rom_3 = 64'h3030107300028863; // @[BootROM.scala:50:22] wire [63:0] rom_4 = 64'h3445307322200513; // @[BootROM.scala:50:22] wire [63:0] rom_5 = 64'h3045107300800513; // @[BootROM.scala:50:22] wire [63:0] rom_6 = 64'h1050007330052073; // @[BootROM.scala:50:22] wire [63:0] rom_7 = 64'hFFDFF06F; // @[BootROM.scala:50:22] wire [63:0] rom_8 = 64'hF1402573020005B7; // @[BootROM.scala:50:22] wire [63:0] rom_9 = 64'h380006F00050463; // @[BootROM.scala:50:22] wire [63:0] rom_10 = 64'h10069300458613; // @[BootROM.scala:50:22] wire [63:0] rom_11 = 64'h46061300D62023; // @[BootROM.scala:50:22] wire [63:0] rom_12 = 64'hFE069AE3FFC62683; // @[BootROM.scala:50:22] wire [63:0] rom_13 = 64'h2C0006F; // @[BootROM.scala:50:22] wire [63:0] rom_16 = 64'h5A283F81FF06F; // @[BootROM.scala:50:22] wire [63:0] rom_17 = 64'h251513FE029EE3; // @[BootROM.scala:50:22] wire [63:0] rom_18 = 64'h5A02300B505B3; // @[BootROM.scala:50:22] wire [63:0] rom_19 = 64'h5350300001537; // @[BootROM.scala:50:22] wire [63:0] rom_20 = 64'hF140257334151073; // @[BootROM.scala:50:22] wire [63:0] rom_21 = 64'h185859300000597; // @[BootROM.scala:50:22] wire [63:0] rom_22 = 64'h3006307308000613; // @[BootROM.scala:50:22] wire [63:0] rom_23 = 64'h1330200073; // @[BootROM.scala:50:22] wire [63:0] rom_24 = 64'h780E0000EDFE0DD0; // @[BootROM.scala:50:22] wire [63:0] rom_25 = 64'h180C000038000000; // @[BootROM.scala:50:22] wire [63:0] rom_26 = 64'h1100000028000000; // @[BootROM.scala:50:22] wire [63:0] rom_27 = 64'h10000000; // @[BootROM.scala:50:22] wire [63:0] rom_28 = 64'hE00B000060020000; // @[BootROM.scala:50:22] wire [63:0] rom_31 = 64'h1000000; // @[BootROM.scala:50:22] wire [63:0] rom_39 = 64'h7665642D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_41 = 64'h2600000011000000; // @[BootROM.scala:50:22] wire [63:0] rom_43 = 64'h6472617970696863; // @[BootROM.scala:50:22] wire [63:0] rom_45 = 64'h73657361696C61; // @[BootROM.scala:50:22] wire [63:0] rom_36 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_46 = 64'h1500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_47 = 64'h636F732F2C000000; // @[BootROM.scala:50:22] wire [63:0] rom_48 = 64'h406C61697265732F; // @[BootROM.scala:50:22] wire [63:0] rom_49 = 64'h3030303032303031; // @[BootROM.scala:50:22] wire [63:0] rom_50 = 64'h200000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_51 = 64'h736F686301000000; // @[BootROM.scala:50:22] wire [63:0] rom_52 = 64'h300000000006E65; // @[BootROM.scala:50:22] wire [63:0] rom_53 = 64'h3400000015000000; // @[BootROM.scala:50:22] wire [63:0] rom_54 = 64'h7265732F636F732F; // @[BootROM.scala:50:22] wire [63:0] rom_55 = 64'h32303031406C6169; // @[BootROM.scala:50:22] wire [63:0] rom_58 = 64'h73757063; // @[BootROM.scala:50:22] wire [63:0] rom_62 = 64'hF000000; // @[BootROM.scala:50:22] wire [63:0] rom_64 = 64'h20A1070040000000; // @[BootROM.scala:50:22] wire [63:0] rom_65 = 64'h4075706301000000; // @[BootROM.scala:50:22] wire [63:0] rom_69 = 64'h1B00000014000000; // @[BootROM.scala:50:22] wire [63:0] rom_71 = 64'h697200306D6F6F62; // @[BootROM.scala:50:22] wire [63:0] rom_72 = 64'h300000000766373; // @[BootROM.scala:50:22] wire [63:0] rom_73 = 64'h6300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_75 = 64'h7600000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_77 = 64'h8300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_79 = 64'h9000000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_81 = 64'h9B00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_82 = 64'h300000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_83 = 64'hA600000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_84 = 64'h300000000757063; // @[BootROM.scala:50:22] wire [63:0] rom_85 = 64'hB200000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_87 = 64'hD100000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_89 = 64'hE400000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_74 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_76 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_88 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_90 = 64'h300000040000000; // @[BootROM.scala:50:22] wire [63:0] rom_91 = 64'hF100000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_78 = 64'h300000000800000; // @[BootROM.scala:50:22] wire [63:0] rom_92 = 64'h300000000800000; // @[BootROM.scala:50:22] wire [63:0] rom_93 = 64'hFE00000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_95 = 64'h901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_96 = 64'h300000020000000; // @[BootROM.scala:50:22] wire [63:0] rom_97 = 64'h140100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_98 = 64'h76732C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_99 = 64'h300000000003933; // @[BootROM.scala:50:22] wire [63:0] rom_100 = 64'h1D01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_102 = 64'h2E01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_104 = 64'h320100001F000000; // @[BootROM.scala:50:22] wire [63:0] rom_105 = 64'h66616D6934367672; // @[BootROM.scala:50:22] wire [63:0] rom_106 = 64'h5F727363697A6364; // @[BootROM.scala:50:22] wire [63:0] rom_107 = 64'h6965636E6566697A; // @[BootROM.scala:50:22] wire [63:0] rom_108 = 64'h6D7068697A5F; // @[BootROM.scala:50:22] wire [63:0] rom_110 = 64'h40000003C010000; // @[BootROM.scala:50:22] wire [63:0] rom_112 = 64'h800000051010000; // @[BootROM.scala:50:22] wire [63:0] rom_114 = 64'h79616B6F62010000; // @[BootROM.scala:50:22] wire [63:0] rom_116 = 64'h4000000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_117 = 64'h300000020A10700; // @[BootROM.scala:50:22] wire [63:0] rom_118 = 64'h6901000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_125 = 64'h1B0000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_126 = 64'h70632C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_127 = 64'h63746E692D75; // @[BootROM.scala:50:22] wire [63:0] rom_129 = 64'h300000084010000; // @[BootROM.scala:50:22] wire [63:0] rom_131 = 64'h200000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_133 = 64'h6669746801000000; // @[BootROM.scala:50:22] wire [63:0] rom_135 = 64'h1B0000000A000000; // @[BootROM.scala:50:22] wire [63:0] rom_136 = 64'h666974682C626375; // @[BootROM.scala:50:22] wire [63:0] rom_137 = 64'h200000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_144 = 64'h82E010000; // @[BootROM.scala:50:22] wire [63:0] rom_146 = 64'h6201000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_147 = 64'h64656C6261736964; // @[BootROM.scala:50:22] wire [63:0] rom_150 = 64'h200000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_138 = 64'h6F6D656D01000000; // @[BootROM.scala:50:22] wire [63:0] rom_151 = 64'h6F6D656D01000000; // @[BootROM.scala:50:22] wire [63:0] rom_139 = 64'h3030303038407972; // @[BootROM.scala:50:22] wire [63:0] rom_152 = 64'h3030303038407972; // @[BootROM.scala:50:22] wire [63:0] rom_153 = 64'h300000000303030; // @[BootROM.scala:50:22] wire [63:0] rom_141 = 64'hA600000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_154 = 64'hA600000007000000; // @[BootROM.scala:50:22] wire [63:0] rom_142 = 64'h79726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_155 = 64'h79726F6D656D; // @[BootROM.scala:50:22] wire [63:0] rom_157 = 64'h802E010000; // @[BootROM.scala:50:22] wire [63:0] rom_158 = 64'h300000000000010; // @[BootROM.scala:50:22] wire [63:0] rom_161 = 64'h636F7301000000; // @[BootROM.scala:50:22] wire [63:0] rom_33 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_44 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_60 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_163 = 64'h100000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_35 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_165 = 64'h10000000F000000; // @[BootROM.scala:50:22] wire [63:0] rom_166 = 64'h2000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_37 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_167 = 64'h2D6263751B000000; // @[BootROM.scala:50:22] wire [63:0] rom_38 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_168 = 64'h706968632C726162; // @[BootROM.scala:50:22] wire [63:0] rom_169 = 64'h636F732D64726179; // @[BootROM.scala:50:22] wire [63:0] rom_170 = 64'h2D656C706D697300; // @[BootROM.scala:50:22] wire [63:0] rom_171 = 64'h300000000737562; // @[BootROM.scala:50:22] wire [63:0] rom_172 = 64'hA101000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_173 = 64'h746F6F6201000000; // @[BootROM.scala:50:22] wire [63:0] rom_174 = 64'h737365726464612D; // @[BootROM.scala:50:22] wire [63:0] rom_175 = 64'h303031406765722D; // @[BootROM.scala:50:22] wire [63:0] rom_178 = 64'h10000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_182 = 64'h6863616301000000; // @[BootROM.scala:50:22] wire [63:0] rom_183 = 64'h6F72746E6F632D65; // @[BootROM.scala:50:22] wire [63:0] rom_184 = 64'h3130324072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_187 = 64'h4000000065000000; // @[BootROM.scala:50:22] wire [63:0] rom_189 = 64'h2000000B2010000; // @[BootROM.scala:50:22] wire [63:0] rom_191 = 64'h4000078000000; // @[BootROM.scala:50:22] wire [63:0] rom_193 = 64'h80085000000; // @[BootROM.scala:50:22] wire [63:0] rom_128 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_194 = 64'h3000000; // @[BootROM.scala:50:22] wire [63:0] rom_195 = 64'h3000000BE010000; // @[BootROM.scala:50:22] wire [63:0] rom_196 = 64'h1B0000001D000000; // @[BootROM.scala:50:22] wire [63:0] rom_197 = 64'h692C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_198 = 64'h65766973756C636E; // @[BootROM.scala:50:22] wire [63:0] rom_199 = 64'h6300306568636163; // @[BootROM.scala:50:22] wire [63:0] rom_200 = 64'h65686361; // @[BootROM.scala:50:22] wire [63:0] rom_202 = 64'h20000001D010000; // @[BootROM.scala:50:22] wire [63:0] rom_205 = 64'h10000000000102; // @[BootROM.scala:50:22] wire [63:0] rom_209 = 64'hCC01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_210 = 64'h30000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_212 = 64'h200000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_213 = 64'h7375626301000000; // @[BootROM.scala:50:22] wire [63:0] rom_220 = 64'h73756263EB010000; // @[BootROM.scala:50:22] wire [63:0] rom_226 = 64'h303240746E696C63; // @[BootROM.scala:50:22] wire [63:0] rom_227 = 64'h3030303030; // @[BootROM.scala:50:22] wire [63:0] rom_229 = 64'h637369721B000000; // @[BootROM.scala:50:22] wire [63:0] rom_230 = 64'h30746E696C632C76; // @[BootROM.scala:50:22] wire [63:0] rom_232 = 64'hFE01000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_233 = 64'h300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_234 = 64'h700000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_236 = 64'h22E010000; // @[BootROM.scala:50:22] wire [63:0] rom_241 = 64'h61672D6B636F6C63; // @[BootROM.scala:50:22] wire [63:0] rom_242 = 64'h3030303140726574; // @[BootROM.scala:50:22] wire [63:0] rom_140 = 64'h300000000003030; // @[BootROM.scala:50:22] wire [63:0] rom_243 = 64'h300000000003030; // @[BootROM.scala:50:22] wire [63:0] rom_245 = 64'h10000000001000; // @[BootROM.scala:50:22] wire [63:0] rom_249 = 64'h7562656401000000; // @[BootROM.scala:50:22] wire [63:0] rom_250 = 64'h6F72746E6F632D67; // @[BootROM.scala:50:22] wire [63:0] rom_251 = 64'h304072656C6C; // @[BootROM.scala:50:22] wire [63:0] rom_252 = 64'h2100000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_254 = 64'h67756265642C6576; // @[BootROM.scala:50:22] wire [63:0] rom_255 = 64'h736972003331302D; // @[BootROM.scala:50:22] wire [63:0] rom_256 = 64'h67756265642C7663; // @[BootROM.scala:50:22] wire [63:0] rom_257 = 64'h3331302D; // @[BootROM.scala:50:22] wire [63:0] rom_113 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_258 = 64'h500000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_259 = 64'h6761746A12020000; // @[BootROM.scala:50:22] wire [63:0] rom_261 = 64'hFE01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_262 = 64'hFFFF000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_264 = 64'h2E010000; // @[BootROM.scala:50:22] wire [63:0] rom_269 = 64'h65642D726F727265; // @[BootROM.scala:50:22] wire [63:0] rom_270 = 64'h3030334065636976; // @[BootROM.scala:50:22] wire [63:0] rom_66 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_176 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_271 = 64'h300000000000030; // @[BootROM.scala:50:22] wire [63:0] rom_272 = 64'h1B0000000E000000; // @[BootROM.scala:50:22] wire [63:0] rom_273 = 64'h652C657669666973; // @[BootROM.scala:50:22] wire [63:0] rom_274 = 64'h30726F7272; // @[BootROM.scala:50:22] wire [63:0] rom_276 = 64'h3000002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_277 = 64'h200000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_278 = 64'h7375626601000000; // @[BootROM.scala:50:22] wire [63:0] rom_285 = 64'h73756266EB010000; // @[BootROM.scala:50:22] wire [63:0] rom_291 = 64'h4063696E2D656369; // @[BootROM.scala:50:22] wire [63:0] rom_292 = 64'h3030303631303031; // @[BootROM.scala:50:22] wire [63:0] rom_294 = 64'h1B00000010000000; // @[BootROM.scala:50:22] wire [63:0] rom_42 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_70 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_295 = 64'h2C7261622D626375; // @[BootROM.scala:50:22] wire [63:0] rom_296 = 64'h63696E2D656369; // @[BootROM.scala:50:22] wire [63:0] rom_298 = 64'h50000001F020000; // @[BootROM.scala:50:22] wire [63:0] rom_300 = 64'h200000030020000; // @[BootROM.scala:50:22] wire [63:0] rom_303 = 64'h10000000600110; // @[BootROM.scala:50:22] wire [63:0] rom_119 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_307 = 64'h65746E6901000000; // @[BootROM.scala:50:22] wire [63:0] rom_310 = 64'h3030303030306340; // @[BootROM.scala:50:22] wire [63:0] rom_123 = 64'h7301000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_312 = 64'h7301000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_315 = 64'h6C702C7663736972; // @[BootROM.scala:50:22] wire [63:0] rom_316 = 64'h300000000306369; // @[BootROM.scala:50:22] wire [63:0] rom_317 = 64'h8401000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_318 = 64'h1000000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_319 = 64'h4000000FE010000; // @[BootROM.scala:50:22] wire [63:0] rom_320 = 64'h40000000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_321 = 64'h300000009000000; // @[BootROM.scala:50:22] wire [63:0] rom_323 = 64'h40000000C; // @[BootROM.scala:50:22] wire [63:0] rom_208 = 64'h3000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_326 = 64'h3000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_327 = 64'h3B02000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_329 = 64'h4E02000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_203 = 64'h300000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_301 = 64'h300000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_328 = 64'h300000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_330 = 64'h300000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_332 = 64'h200000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_333 = 64'h7375626D01000000; // @[BootROM.scala:50:22] wire [63:0] rom_340 = 64'h7375626DEB010000; // @[BootROM.scala:50:22] wire [63:0] rom_348 = 64'hDE01000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_67 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_350 = 64'h5300000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_351 = 64'h30000000065CD1D; // @[BootROM.scala:50:22] wire [63:0] rom_352 = 64'hEB0100000B000000; // @[BootROM.scala:50:22] wire [63:0] rom_346 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_353 = 64'h6F6C635F73756270; // @[BootROM.scala:50:22] wire [63:0] rom_347 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_354 = 64'h300000000006B63; // @[BootROM.scala:50:22] wire [63:0] rom_314 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_355 = 64'h1B0000000C000000; // @[BootROM.scala:50:22] wire [63:0] rom_356 = 64'h6C632D6465786966; // @[BootROM.scala:50:22] wire [63:0] rom_357 = 64'h3000000006B636F; // @[BootROM.scala:50:22] wire [63:0] rom_130 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_149 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_159 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_211 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_331 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_358 = 64'h9901000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_359 = 64'h200000006000000; // @[BootROM.scala:50:22] wire [63:0] rom_360 = 64'h406D6F7201000000; // @[BootROM.scala:50:22] wire [63:0] rom_361 = 64'h3030303031; // @[BootROM.scala:50:22] wire [63:0] rom_364 = 64'h306D6F722C6576; // @[BootROM.scala:50:22] wire [63:0] rom_366 = 64'h1002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_145 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_237 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_367 = 64'h300000000000100; // @[BootROM.scala:50:22] wire [63:0] rom_368 = 64'hA801000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_369 = 64'h2000000006D656D; // @[BootROM.scala:50:22] wire [63:0] rom_370 = 64'h7375627301000000; // @[BootROM.scala:50:22] wire [63:0] rom_216 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_281 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_336 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_373 = 64'hDE010000; // @[BootROM.scala:50:22] wire [63:0] rom_218 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_283 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_338 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_375 = 64'h65CD1D53000000; // @[BootROM.scala:50:22] wire [63:0] rom_219 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_284 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_339 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_376 = 64'hB00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_377 = 64'h73756273EB010000; // @[BootROM.scala:50:22] wire [63:0] rom_214 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_221 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_279 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_286 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_334 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_341 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_371 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_378 = 64'h6B636F6C635F; // @[BootROM.scala:50:22] wire [63:0] rom_222 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_287 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_342 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_362 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_379 = 64'hC00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_223 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_288 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_343 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_380 = 64'h657869661B000000; // @[BootROM.scala:50:22] wire [63:0] rom_224 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_289 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_344 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_381 = 64'h6B636F6C632D64; // @[BootROM.scala:50:22] wire [63:0] rom_57 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_225 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_240 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_268 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_290 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_345 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_382 = 64'h100000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_383 = 64'h31406C6169726573; // @[BootROM.scala:50:22] wire [63:0] rom_384 = 64'h30303030323030; // @[BootROM.scala:50:22] wire [63:0] rom_32 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_34 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_59 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_61 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_63 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_109 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_111 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_162 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_164 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_186 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_188 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_190 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_192 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_215 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_217 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_280 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_282 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_297 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_335 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_337 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_372 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_374 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_385 = 64'h400000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_386 = 64'h600000059020000; // @[BootROM.scala:50:22] wire [63:0] rom_228 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_387 = 64'hD00000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_253 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_363 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_388 = 64'h696669731B000000; // @[BootROM.scala:50:22] wire [63:0] rom_389 = 64'h30747261752C6576; // @[BootROM.scala:50:22] wire [63:0] rom_40 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_68 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_86 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_103 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_115 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_122 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_134 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_148 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_231 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_260 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_293 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_311 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_349 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_390 = 64'h300000000000000; // @[BootROM.scala:50:22] wire [63:0] rom_391 = 64'h1F02000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_392 = 64'h300000005000000; // @[BootROM.scala:50:22] wire [63:0] rom_393 = 64'h3002000004000000; // @[BootROM.scala:50:22] wire [63:0] rom_80 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_94 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_101 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_124 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_313 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_394 = 64'h300000001000000; // @[BootROM.scala:50:22] wire [63:0] rom_177 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_204 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_244 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_302 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_322 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_395 = 64'h2E01000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_396 = 64'h10000000000210; // @[BootROM.scala:50:22] wire [63:0] rom_180 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_207 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_247 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_305 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_325 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_398 = 64'h746E6F63A8010000; // @[BootROM.scala:50:22] wire [63:0] rom_181 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_248 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_306 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_399 = 64'h2000000006C6F72; // @[BootROM.scala:50:22] wire [63:0] rom_400 = 64'h656C697401000000; // @[BootROM.scala:50:22] wire [63:0] rom_401 = 64'h732D74657365722D; // @[BootROM.scala:50:22] wire [63:0] rom_402 = 64'h3131407265747465; // @[BootROM.scala:50:22] wire [63:0] rom_56 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_185 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_403 = 64'h30303030; // @[BootROM.scala:50:22] wire [63:0] rom_143 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_156 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_179 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_201 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_206 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_235 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_246 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_263 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_275 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_299 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_304 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_324 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_365 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_397 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_404 = 64'h800000003000000; // @[BootROM.scala:50:22] wire [63:0] rom_405 = 64'h11002E010000; // @[BootROM.scala:50:22] wire [63:0] rom_265 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_406 = 64'h300000000100000; // @[BootROM.scala:50:22] wire [63:0] rom_238 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_266 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_407 = 64'hA801000008000000; // @[BootROM.scala:50:22] wire [63:0] rom_239 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_267 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_408 = 64'h6C6F72746E6F63; // @[BootROM.scala:50:22] wire [63:0] rom_132 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_160 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_409 = 64'h200000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_410 = 64'h900000002000000; // @[BootROM.scala:50:22] wire [63:0] rom_411 = 64'h7373657264646123; // @[BootROM.scala:50:22] wire [63:0] rom_412 = 64'h2300736C6C65632D; // @[BootROM.scala:50:22] wire [63:0] rom_413 = 64'h6C65632D657A6973; // @[BootROM.scala:50:22] wire [63:0] rom_414 = 64'h61706D6F6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_415 = 64'h6F6D00656C626974; // @[BootROM.scala:50:22] wire [63:0] rom_416 = 64'h69726573006C6564; // @[BootROM.scala:50:22] wire [63:0] rom_417 = 64'h6F64747300306C61; // @[BootROM.scala:50:22] wire [63:0] rom_418 = 64'h687461702D7475; // @[BootROM.scala:50:22] wire [63:0] rom_419 = 64'h65736162656D6974; // @[BootROM.scala:50:22] wire [63:0] rom_421 = 64'h6B636F6C63007963; // @[BootROM.scala:50:22] wire [63:0] rom_420 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_422 = 64'h6E6575716572662D; // @[BootROM.scala:50:22] wire [63:0] rom_423 = 64'h6361632D64007963; // @[BootROM.scala:50:22] wire [63:0] rom_424 = 64'h6B636F6C622D6568; // @[BootROM.scala:50:22] wire [63:0] rom_425 = 64'h2D6400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_426 = 64'h65732D6568636163; // @[BootROM.scala:50:22] wire [63:0] rom_427 = 64'h6361632D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_428 = 64'h657A69732D6568; // @[BootROM.scala:50:22] wire [63:0] rom_429 = 64'h65732D626C742D64; // @[BootROM.scala:50:22] wire [63:0] rom_430 = 64'h626C742D64007374; // @[BootROM.scala:50:22] wire [63:0] rom_431 = 64'h656400657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_432 = 64'h7079745F65636976; // @[BootROM.scala:50:22] wire [63:0] rom_433 = 64'h6177647261680065; // @[BootROM.scala:50:22] wire [63:0] rom_434 = 64'h2D636578652D6572; // @[BootROM.scala:50:22] wire [63:0] rom_435 = 64'h696F706B61657262; // @[BootROM.scala:50:22] wire [63:0] rom_436 = 64'h746E756F632D746E; // @[BootROM.scala:50:22] wire [63:0] rom_438 = 64'h732D6B636F6C622D; // @[BootROM.scala:50:22] wire [63:0] rom_439 = 64'h61632D6900657A69; // @[BootROM.scala:50:22] wire [63:0] rom_440 = 64'h737465732D656863; // @[BootROM.scala:50:22] wire [63:0] rom_437 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_441 = 64'h65686361632D6900; // @[BootROM.scala:50:22] wire [63:0] rom_442 = 64'h2D6900657A69732D; // @[BootROM.scala:50:22] wire [63:0] rom_443 = 64'h737465732D626C74; // @[BootROM.scala:50:22] wire [63:0] rom_444 = 64'h732D626C742D6900; // @[BootROM.scala:50:22] wire [63:0] rom_445 = 64'h2D756D6D00657A69; // @[BootROM.scala:50:22] wire [63:0] rom_446 = 64'h78656E0065707974; // @[BootROM.scala:50:22] wire [63:0] rom_447 = 64'h2D6C6576656C2D74; // @[BootROM.scala:50:22] wire [63:0] rom_448 = 64'h6572006568636163; // @[BootROM.scala:50:22] wire [63:0] rom_449 = 64'h2C76637369720067; // @[BootROM.scala:50:22] wire [63:0] rom_450 = 64'h6373697200617369; // @[BootROM.scala:50:22] wire [63:0] rom_451 = 64'h617267706D702C76; // @[BootROM.scala:50:22] wire [63:0] rom_452 = 64'h79746972616C756E; // @[BootROM.scala:50:22] wire [63:0] rom_453 = 64'h702C766373697200; // @[BootROM.scala:50:22] wire [63:0] rom_454 = 64'h6E6F69676572706D; // @[BootROM.scala:50:22] wire [63:0] rom_455 = 64'h7375746174730073; // @[BootROM.scala:50:22] wire [63:0] rom_456 = 64'h6C70732D626C7400; // @[BootROM.scala:50:22] wire [63:0] rom_457 = 64'h65746E6923007469; // @[BootROM.scala:50:22] wire [63:0] rom_458 = 64'h65632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_459 = 64'h65746E6900736C6C; // @[BootROM.scala:50:22] wire [63:0] rom_120 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_308 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_460 = 64'h6F632D7470757272; // @[BootROM.scala:50:22] wire [63:0] rom_121 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_309 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_461 = 64'h72656C6C6F72746E; // @[BootROM.scala:50:22] wire [63:0] rom_462 = 64'h656C646E61687000; // @[BootROM.scala:50:22] wire [63:0] rom_463 = 64'h7365676E617200; // @[BootROM.scala:50:22] wire [63:0] rom_464 = 64'h656D616E2D676572; // @[BootROM.scala:50:22] wire [63:0] rom_465 = 64'h2D65686361630073; // @[BootROM.scala:50:22] wire [63:0] rom_466 = 64'h6163006C6576656C; // @[BootROM.scala:50:22] wire [63:0] rom_467 = 64'h66696E752D656863; // @[BootROM.scala:50:22] wire [63:0] rom_468 = 64'h6966697300646569; // @[BootROM.scala:50:22] wire [63:0] rom_469 = 64'h2D7268736D2C6576; // @[BootROM.scala:50:22] wire [63:0] rom_470 = 64'h632300746E756F63; // @[BootROM.scala:50:22] wire [63:0] rom_471 = 64'h6C65632D6B636F6C; // @[BootROM.scala:50:22] wire [63:0] rom_472 = 64'h6B636F6C6300736C; // @[BootROM.scala:50:22] wire [63:0] rom_473 = 64'h2D74757074756F2D; // @[BootROM.scala:50:22] wire [63:0] rom_474 = 64'h6E690073656D616E; // @[BootROM.scala:50:22] wire [63:0] rom_475 = 64'h7374707572726574; // @[BootROM.scala:50:22] wire [63:0] rom_476 = 64'h65646E657478652D; // @[BootROM.scala:50:22] wire [63:0] rom_477 = 64'h2D67756265640064; // @[BootROM.scala:50:22] wire [63:0] rom_478 = 64'h6900686361747461; // @[BootROM.scala:50:22] wire [63:0] rom_479 = 64'h747075727265746E; // @[BootROM.scala:50:22] wire [63:0] rom_480 = 64'h746E657261702D; // @[BootROM.scala:50:22] wire [63:0] rom_481 = 64'h7075727265746E69; // @[BootROM.scala:50:22] wire [63:0] rom_482 = 64'h7663736972007374; // @[BootROM.scala:50:22] wire [63:0] rom_483 = 64'h6972702D78616D2C; // @[BootROM.scala:50:22] wire [63:0] rom_484 = 64'h697200797469726F; // @[BootROM.scala:50:22] wire [63:0] rom_485 = 64'h7665646E2C766373; // @[BootROM.scala:50:22] wire [63:0] rom_486 = 64'h736B636F6C6300; // @[BootROM.scala:50:22] wire [63:0] rom_14 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_15 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_29 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_30 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_487 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_488 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_489 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_490 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_491 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_492 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_493 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_494 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_495 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_496 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_497 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_498 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_499 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_500 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_501 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_502 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_503 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_504 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_505 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_506 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_507 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_508 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_509 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_510 = 64'h0; // @[BootROM.scala:50:22] wire [63:0] rom_511 = 64'h0; // @[BootROM.scala:50:22] wire auto_in_d_bits_sink = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_denied = 1'h0; // @[BootROM.scala:41:9] wire auto_in_d_bits_corrupt = 1'h0; // @[BootROM.scala:41:9] wire nodeIn_d_bits_sink = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_d_sink = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_denied = 1'h0; // @[Edges.scala:810:17] wire nodeIn_d_bits_d_corrupt = 1'h0; // @[Edges.scala:810:17] wire [1:0] auto_in_d_bits_param = 2'h0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_d_bits_param = 2'h0; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_param = 2'h0; // @[Edges.scala:810:17] wire [2:0] auto_in_d_bits_opcode = 3'h1; // @[BootROM.scala:41:9] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode = 3'h1; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_d_opcode = 3'h1; // @[Edges.scala:810:17] wire nodeIn_a_valid = auto_in_a_valid_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[BootROM.scala:41:9] wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[BootROM.scala:41:9] wire [1:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[BootROM.scala:41:9] wire [11:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[BootROM.scala:41:9] wire [16:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[BootROM.scala:41:9] wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[BootROM.scala:41:9] wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[BootROM.scala:41:9] wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[BootROM.scala:41:9] wire nodeIn_d_ready = auto_in_d_ready_0; // @[BootROM.scala:41:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [11:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire auto_in_a_ready_0; // @[BootROM.scala:41:9] wire [1:0] auto_in_d_bits_size_0; // @[BootROM.scala:41:9] wire [11:0] auto_in_d_bits_source_0; // @[BootROM.scala:41:9] wire [63:0] auto_in_d_bits_data_0; // @[BootROM.scala:41:9] wire auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_a_ready_0 = nodeIn_a_ready; // @[BootROM.scala:41:9] assign nodeIn_d_valid = nodeIn_a_valid; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_d_size = nodeIn_a_bits_size; // @[Edges.scala:810:17] wire [11:0] nodeIn_d_bits_d_source = nodeIn_a_bits_source; // @[Edges.scala:810:17] assign nodeIn_a_ready = nodeIn_d_ready; // @[MixedNode.scala:551:17] assign auto_in_d_valid_0 = nodeIn_d_valid; // @[BootROM.scala:41:9] assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[BootROM.scala:41:9] assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[BootROM.scala:41:9] wire [63:0] nodeIn_d_bits_d_data; // @[Edges.scala:810:17] assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[BootROM.scala:41:9] wire [8:0] index = nodeIn_a_bits_address[11:3]; // @[BootROM.scala:55:34] wire [3:0] high = nodeIn_a_bits_address[15:12]; // @[BootROM.scala:56:64] wire _nodeIn_d_bits_T = |high; // @[BootROM.scala:56:64, :57:53] wire [63:0] _nodeIn_d_bits_T_1 = _nodeIn_d_bits_T ? 64'h0 : _GEN[index]; // @[BootROM.scala:55:34, :57:{47,53}] assign nodeIn_d_bits_d_data = _nodeIn_d_bits_T_1; // @[Edges.scala:810:17] assign nodeIn_d_bits_size = nodeIn_d_bits_d_size; // @[Edges.scala:810:17] assign nodeIn_d_bits_source = nodeIn_d_bits_d_source; // @[Edges.scala:810:17] assign nodeIn_d_bits_data = nodeIn_d_bits_d_data; // @[Edges.scala:810:17] TLMonitor_55 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] assign auto_in_a_ready = auto_in_a_ready_0; // @[BootROM.scala:41:9] assign auto_in_d_valid = auto_in_d_valid_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[BootROM.scala:41:9] assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[BootROM.scala:41:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPU_4 : input clock : Clock input reset : Reset output io : { flip hartid : UInt<3>, flip time : UInt<64>, flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip v_sew : UInt<3>, store_data : UInt<64>, toint_data : UInt<64>, flip ll_resp_val : UInt<1>, flip ll_resp_type : UInt<3>, flip ll_resp_tag : UInt<5>, flip ll_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip keep_clock_enabled : UInt<1>, flip cp_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} reg clock_en_reg : UInt<1>, clock node clock_en = or(clock_en_reg, io.cp_req.valid) inst fp_decoder of FPUDecoder_4 connect fp_decoder.clock, clock connect fp_decoder.reset, reset connect fp_decoder.io.inst, io.inst wire id_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} connect id_ctrl, fp_decoder.io.sigs regreset ex_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect ex_reg_valid, io.valid reg ex_reg_inst : UInt<32>, clock when io.valid : connect ex_reg_inst, io.inst reg ex_reg_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock when io.valid : connect ex_reg_ctrl, id_ctrl reg ex_ra_0 : UInt, clock reg ex_ra_1 : UInt, clock reg ex_ra_2 : UInt, clock reg load_wb : UInt<1>, clock connect load_wb, io.ll_resp_val node _load_wb_typeTag_T = bits(io.ll_resp_type, 1, 0) node _load_wb_typeTag_T_1 = sub(_load_wb_typeTag_T, UInt<1>(0h1)) node _load_wb_typeTag_T_2 = tail(_load_wb_typeTag_T_1, 1) reg load_wb_typeTag : UInt<2>, clock when io.ll_resp_val : connect load_wb_typeTag, _load_wb_typeTag_T_2 reg load_wb_data : UInt<64>, clock when io.ll_resp_val : connect load_wb_data, io.ll_resp_data reg load_wb_tag : UInt<5>, clock when io.ll_resp_val : connect load_wb_tag, io.ll_resp_tag node req_valid = or(ex_reg_valid, io.cp_req.valid) node ex_cp_valid = and(io.cp_req.ready, io.cp_req.valid) regreset mem_cp_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect mem_cp_valid, ex_cp_valid regreset wb_cp_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect wb_cp_valid, mem_cp_valid regreset mem_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) node _killm_T = or(io.killm, io.nack_mem) node _killm_T_1 = eq(mem_cp_valid, UInt<1>(0h0)) node killm = and(_killm_T, _killm_T_1) node _killx_T = and(mem_reg_valid, killm) node killx = or(io.killx, _killx_T) node _mem_reg_valid_T = eq(killx, UInt<1>(0h0)) node _mem_reg_valid_T_1 = and(ex_reg_valid, _mem_reg_valid_T) node _mem_reg_valid_T_2 = or(_mem_reg_valid_T_1, ex_cp_valid) connect mem_reg_valid, _mem_reg_valid_T_2 reg mem_reg_inst : UInt<32>, clock when ex_reg_valid : connect mem_reg_inst, ex_reg_inst node _wb_reg_valid_T = eq(killm, UInt<1>(0h0)) node _wb_reg_valid_T_1 = or(_wb_reg_valid_T, mem_cp_valid) node _wb_reg_valid_T_2 = and(mem_reg_valid, _wb_reg_valid_T_1) regreset wb_reg_valid : UInt<1>, clock, reset, UInt<1>(0h0) connect wb_reg_valid, _wb_reg_valid_T_2 wire cp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>} connect cp_ctrl.vec, io.cp_req.bits.vec connect cp_ctrl.wflags, io.cp_req.bits.wflags connect cp_ctrl.sqrt, io.cp_req.bits.sqrt connect cp_ctrl.div, io.cp_req.bits.div connect cp_ctrl.fma, io.cp_req.bits.fma connect cp_ctrl.fastpipe, io.cp_req.bits.fastpipe connect cp_ctrl.toint, io.cp_req.bits.toint connect cp_ctrl.fromint, io.cp_req.bits.fromint connect cp_ctrl.typeTagOut, io.cp_req.bits.typeTagOut connect cp_ctrl.typeTagIn, io.cp_req.bits.typeTagIn connect cp_ctrl.swap23, io.cp_req.bits.swap23 connect cp_ctrl.swap12, io.cp_req.bits.swap12 connect cp_ctrl.ren3, io.cp_req.bits.ren3 connect cp_ctrl.ren2, io.cp_req.bits.ren2 connect cp_ctrl.ren1, io.cp_req.bits.ren1 connect cp_ctrl.wen, io.cp_req.bits.wen connect cp_ctrl.ldst, io.cp_req.bits.ldst connect io.cp_resp.valid, UInt<1>(0h0) connect io.cp_resp.bits.data, UInt<1>(0h0) invalidate io.cp_resp.bits.exc node ex_ctrl = mux(ex_cp_valid, cp_ctrl, ex_reg_ctrl) reg mem_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock when req_valid : connect mem_ctrl, ex_ctrl reg wb_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, clock when mem_reg_valid : connect wb_ctrl, mem_ctrl wire frfWriteBundle_0 : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} invalidate frfWriteBundle_0.inst invalidate frfWriteBundle_0.rd1val invalidate frfWriteBundle_0.rd1src invalidate frfWriteBundle_0.rd0val invalidate frfWriteBundle_0.rd0src invalidate frfWriteBundle_0.wrenf invalidate frfWriteBundle_0.wrenx invalidate frfWriteBundle_0.wrdata invalidate frfWriteBundle_0.wrdst invalidate frfWriteBundle_0.pc invalidate frfWriteBundle_0.valid invalidate frfWriteBundle_0.timer invalidate frfWriteBundle_0.hartid invalidate frfWriteBundle_0.priv_mode invalidate frfWriteBundle_0.excpt invalidate frfWriteBundle_0.reset invalidate frfWriteBundle_0.clock wire frfWriteBundle_1 : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} invalidate frfWriteBundle_1.inst invalidate frfWriteBundle_1.rd1val invalidate frfWriteBundle_1.rd1src invalidate frfWriteBundle_1.rd0val invalidate frfWriteBundle_1.rd0src invalidate frfWriteBundle_1.wrenf invalidate frfWriteBundle_1.wrenx invalidate frfWriteBundle_1.wrdata invalidate frfWriteBundle_1.wrdst invalidate frfWriteBundle_1.pc invalidate frfWriteBundle_1.valid invalidate frfWriteBundle_1.timer invalidate frfWriteBundle_1.hartid invalidate frfWriteBundle_1.priv_mode invalidate frfWriteBundle_1.excpt invalidate frfWriteBundle_1.reset invalidate frfWriteBundle_1.clock connect frfWriteBundle_0.clock, clock connect frfWriteBundle_0.reset, reset connect frfWriteBundle_0.hartid, io.hartid node _frfWriteBundle_0_timer_T = bits(io.time, 31, 0) connect frfWriteBundle_0.timer, _frfWriteBundle_0_timer_T connect frfWriteBundle_0.valid, UInt<1>(0h0) connect frfWriteBundle_0.wrenx, UInt<1>(0h0) connect frfWriteBundle_0.wrenf, UInt<1>(0h0) connect frfWriteBundle_0.excpt, UInt<1>(0h0) connect frfWriteBundle_1.clock, clock connect frfWriteBundle_1.reset, reset connect frfWriteBundle_1.hartid, io.hartid node _frfWriteBundle_1_timer_T = bits(io.time, 31, 0) connect frfWriteBundle_1.timer, _frfWriteBundle_1_timer_T connect frfWriteBundle_1.valid, UInt<1>(0h0) connect frfWriteBundle_1.wrenx, UInt<1>(0h0) connect frfWriteBundle_1.wrenf, UInt<1>(0h0) connect frfWriteBundle_1.excpt, UInt<1>(0h0) cmem regfile : UInt<65> [32] when load_wb : node _wdata_T = eq(load_wb_typeTag, UInt<1>(0h1)) node _wdata_T_1 = mux(_wdata_T, UInt<64>(0hffffffff00000000), UInt<64>(0hffffffffffff0000)) node _wdata_T_2 = eq(load_wb_typeTag, UInt<2>(0h2)) node _wdata_T_3 = mux(_wdata_T_2, UInt<1>(0h0), _wdata_T_1) node _wdata_T_4 = eq(load_wb_typeTag, UInt<2>(0h3)) node _wdata_T_5 = mux(_wdata_T_4, UInt<1>(0h0), _wdata_T_3) node _wdata_T_6 = or(_wdata_T_5, load_wb_data) node wdata_rawIn_sign = bits(_wdata_T_6, 63, 63) node wdata_rawIn_expIn = bits(_wdata_T_6, 62, 52) node wdata_rawIn_fractIn = bits(_wdata_T_6, 51, 0) node wdata_rawIn_isZeroExpIn = eq(wdata_rawIn_expIn, UInt<1>(0h0)) node wdata_rawIn_isZeroFractIn = eq(wdata_rawIn_fractIn, UInt<1>(0h0)) node _wdata_rawIn_normDist_T = bits(wdata_rawIn_fractIn, 0, 0) node _wdata_rawIn_normDist_T_1 = bits(wdata_rawIn_fractIn, 1, 1) node _wdata_rawIn_normDist_T_2 = bits(wdata_rawIn_fractIn, 2, 2) node _wdata_rawIn_normDist_T_3 = bits(wdata_rawIn_fractIn, 3, 3) node _wdata_rawIn_normDist_T_4 = bits(wdata_rawIn_fractIn, 4, 4) node _wdata_rawIn_normDist_T_5 = bits(wdata_rawIn_fractIn, 5, 5) node _wdata_rawIn_normDist_T_6 = bits(wdata_rawIn_fractIn, 6, 6) node _wdata_rawIn_normDist_T_7 = bits(wdata_rawIn_fractIn, 7, 7) node _wdata_rawIn_normDist_T_8 = bits(wdata_rawIn_fractIn, 8, 8) node _wdata_rawIn_normDist_T_9 = bits(wdata_rawIn_fractIn, 9, 9) node _wdata_rawIn_normDist_T_10 = bits(wdata_rawIn_fractIn, 10, 10) node _wdata_rawIn_normDist_T_11 = bits(wdata_rawIn_fractIn, 11, 11) node _wdata_rawIn_normDist_T_12 = bits(wdata_rawIn_fractIn, 12, 12) node _wdata_rawIn_normDist_T_13 = bits(wdata_rawIn_fractIn, 13, 13) node _wdata_rawIn_normDist_T_14 = bits(wdata_rawIn_fractIn, 14, 14) node _wdata_rawIn_normDist_T_15 = bits(wdata_rawIn_fractIn, 15, 15) node _wdata_rawIn_normDist_T_16 = bits(wdata_rawIn_fractIn, 16, 16) node _wdata_rawIn_normDist_T_17 = bits(wdata_rawIn_fractIn, 17, 17) node _wdata_rawIn_normDist_T_18 = bits(wdata_rawIn_fractIn, 18, 18) node _wdata_rawIn_normDist_T_19 = bits(wdata_rawIn_fractIn, 19, 19) node _wdata_rawIn_normDist_T_20 = bits(wdata_rawIn_fractIn, 20, 20) node _wdata_rawIn_normDist_T_21 = bits(wdata_rawIn_fractIn, 21, 21) node _wdata_rawIn_normDist_T_22 = bits(wdata_rawIn_fractIn, 22, 22) node _wdata_rawIn_normDist_T_23 = bits(wdata_rawIn_fractIn, 23, 23) node _wdata_rawIn_normDist_T_24 = bits(wdata_rawIn_fractIn, 24, 24) node _wdata_rawIn_normDist_T_25 = bits(wdata_rawIn_fractIn, 25, 25) node _wdata_rawIn_normDist_T_26 = bits(wdata_rawIn_fractIn, 26, 26) node _wdata_rawIn_normDist_T_27 = bits(wdata_rawIn_fractIn, 27, 27) node _wdata_rawIn_normDist_T_28 = bits(wdata_rawIn_fractIn, 28, 28) node _wdata_rawIn_normDist_T_29 = bits(wdata_rawIn_fractIn, 29, 29) node _wdata_rawIn_normDist_T_30 = bits(wdata_rawIn_fractIn, 30, 30) node _wdata_rawIn_normDist_T_31 = bits(wdata_rawIn_fractIn, 31, 31) node _wdata_rawIn_normDist_T_32 = bits(wdata_rawIn_fractIn, 32, 32) node _wdata_rawIn_normDist_T_33 = bits(wdata_rawIn_fractIn, 33, 33) node _wdata_rawIn_normDist_T_34 = bits(wdata_rawIn_fractIn, 34, 34) node _wdata_rawIn_normDist_T_35 = bits(wdata_rawIn_fractIn, 35, 35) node _wdata_rawIn_normDist_T_36 = bits(wdata_rawIn_fractIn, 36, 36) node _wdata_rawIn_normDist_T_37 = bits(wdata_rawIn_fractIn, 37, 37) node _wdata_rawIn_normDist_T_38 = bits(wdata_rawIn_fractIn, 38, 38) node _wdata_rawIn_normDist_T_39 = bits(wdata_rawIn_fractIn, 39, 39) node _wdata_rawIn_normDist_T_40 = bits(wdata_rawIn_fractIn, 40, 40) node _wdata_rawIn_normDist_T_41 = bits(wdata_rawIn_fractIn, 41, 41) node _wdata_rawIn_normDist_T_42 = bits(wdata_rawIn_fractIn, 42, 42) node _wdata_rawIn_normDist_T_43 = bits(wdata_rawIn_fractIn, 43, 43) node _wdata_rawIn_normDist_T_44 = bits(wdata_rawIn_fractIn, 44, 44) node _wdata_rawIn_normDist_T_45 = bits(wdata_rawIn_fractIn, 45, 45) node _wdata_rawIn_normDist_T_46 = bits(wdata_rawIn_fractIn, 46, 46) node _wdata_rawIn_normDist_T_47 = bits(wdata_rawIn_fractIn, 47, 47) node _wdata_rawIn_normDist_T_48 = bits(wdata_rawIn_fractIn, 48, 48) node _wdata_rawIn_normDist_T_49 = bits(wdata_rawIn_fractIn, 49, 49) node _wdata_rawIn_normDist_T_50 = bits(wdata_rawIn_fractIn, 50, 50) node _wdata_rawIn_normDist_T_51 = bits(wdata_rawIn_fractIn, 51, 51) node _wdata_rawIn_normDist_T_52 = mux(_wdata_rawIn_normDist_T_1, UInt<6>(0h32), UInt<6>(0h33)) node _wdata_rawIn_normDist_T_53 = mux(_wdata_rawIn_normDist_T_2, UInt<6>(0h31), _wdata_rawIn_normDist_T_52) node _wdata_rawIn_normDist_T_54 = mux(_wdata_rawIn_normDist_T_3, UInt<6>(0h30), _wdata_rawIn_normDist_T_53) node _wdata_rawIn_normDist_T_55 = mux(_wdata_rawIn_normDist_T_4, UInt<6>(0h2f), _wdata_rawIn_normDist_T_54) node _wdata_rawIn_normDist_T_56 = mux(_wdata_rawIn_normDist_T_5, UInt<6>(0h2e), _wdata_rawIn_normDist_T_55) node _wdata_rawIn_normDist_T_57 = mux(_wdata_rawIn_normDist_T_6, UInt<6>(0h2d), _wdata_rawIn_normDist_T_56) node _wdata_rawIn_normDist_T_58 = mux(_wdata_rawIn_normDist_T_7, UInt<6>(0h2c), _wdata_rawIn_normDist_T_57) node _wdata_rawIn_normDist_T_59 = mux(_wdata_rawIn_normDist_T_8, UInt<6>(0h2b), _wdata_rawIn_normDist_T_58) node _wdata_rawIn_normDist_T_60 = mux(_wdata_rawIn_normDist_T_9, UInt<6>(0h2a), _wdata_rawIn_normDist_T_59) node _wdata_rawIn_normDist_T_61 = mux(_wdata_rawIn_normDist_T_10, UInt<6>(0h29), _wdata_rawIn_normDist_T_60) node _wdata_rawIn_normDist_T_62 = mux(_wdata_rawIn_normDist_T_11, UInt<6>(0h28), _wdata_rawIn_normDist_T_61) node _wdata_rawIn_normDist_T_63 = mux(_wdata_rawIn_normDist_T_12, UInt<6>(0h27), _wdata_rawIn_normDist_T_62) node _wdata_rawIn_normDist_T_64 = mux(_wdata_rawIn_normDist_T_13, UInt<6>(0h26), _wdata_rawIn_normDist_T_63) node _wdata_rawIn_normDist_T_65 = mux(_wdata_rawIn_normDist_T_14, UInt<6>(0h25), _wdata_rawIn_normDist_T_64) node _wdata_rawIn_normDist_T_66 = mux(_wdata_rawIn_normDist_T_15, UInt<6>(0h24), _wdata_rawIn_normDist_T_65) node _wdata_rawIn_normDist_T_67 = mux(_wdata_rawIn_normDist_T_16, UInt<6>(0h23), _wdata_rawIn_normDist_T_66) node _wdata_rawIn_normDist_T_68 = mux(_wdata_rawIn_normDist_T_17, UInt<6>(0h22), _wdata_rawIn_normDist_T_67) node _wdata_rawIn_normDist_T_69 = mux(_wdata_rawIn_normDist_T_18, UInt<6>(0h21), _wdata_rawIn_normDist_T_68) node _wdata_rawIn_normDist_T_70 = mux(_wdata_rawIn_normDist_T_19, UInt<6>(0h20), _wdata_rawIn_normDist_T_69) node _wdata_rawIn_normDist_T_71 = mux(_wdata_rawIn_normDist_T_20, UInt<5>(0h1f), _wdata_rawIn_normDist_T_70) node _wdata_rawIn_normDist_T_72 = mux(_wdata_rawIn_normDist_T_21, UInt<5>(0h1e), _wdata_rawIn_normDist_T_71) node _wdata_rawIn_normDist_T_73 = mux(_wdata_rawIn_normDist_T_22, UInt<5>(0h1d), _wdata_rawIn_normDist_T_72) node _wdata_rawIn_normDist_T_74 = mux(_wdata_rawIn_normDist_T_23, UInt<5>(0h1c), _wdata_rawIn_normDist_T_73) node _wdata_rawIn_normDist_T_75 = mux(_wdata_rawIn_normDist_T_24, UInt<5>(0h1b), _wdata_rawIn_normDist_T_74) node _wdata_rawIn_normDist_T_76 = mux(_wdata_rawIn_normDist_T_25, UInt<5>(0h1a), _wdata_rawIn_normDist_T_75) node _wdata_rawIn_normDist_T_77 = mux(_wdata_rawIn_normDist_T_26, UInt<5>(0h19), _wdata_rawIn_normDist_T_76) node _wdata_rawIn_normDist_T_78 = mux(_wdata_rawIn_normDist_T_27, UInt<5>(0h18), _wdata_rawIn_normDist_T_77) node _wdata_rawIn_normDist_T_79 = mux(_wdata_rawIn_normDist_T_28, UInt<5>(0h17), _wdata_rawIn_normDist_T_78) node _wdata_rawIn_normDist_T_80 = mux(_wdata_rawIn_normDist_T_29, UInt<5>(0h16), _wdata_rawIn_normDist_T_79) node _wdata_rawIn_normDist_T_81 = mux(_wdata_rawIn_normDist_T_30, UInt<5>(0h15), _wdata_rawIn_normDist_T_80) node _wdata_rawIn_normDist_T_82 = mux(_wdata_rawIn_normDist_T_31, UInt<5>(0h14), _wdata_rawIn_normDist_T_81) node _wdata_rawIn_normDist_T_83 = mux(_wdata_rawIn_normDist_T_32, UInt<5>(0h13), _wdata_rawIn_normDist_T_82) node _wdata_rawIn_normDist_T_84 = mux(_wdata_rawIn_normDist_T_33, UInt<5>(0h12), _wdata_rawIn_normDist_T_83) node _wdata_rawIn_normDist_T_85 = mux(_wdata_rawIn_normDist_T_34, UInt<5>(0h11), _wdata_rawIn_normDist_T_84) node _wdata_rawIn_normDist_T_86 = mux(_wdata_rawIn_normDist_T_35, UInt<5>(0h10), _wdata_rawIn_normDist_T_85) node _wdata_rawIn_normDist_T_87 = mux(_wdata_rawIn_normDist_T_36, UInt<4>(0hf), _wdata_rawIn_normDist_T_86) node _wdata_rawIn_normDist_T_88 = mux(_wdata_rawIn_normDist_T_37, UInt<4>(0he), _wdata_rawIn_normDist_T_87) node _wdata_rawIn_normDist_T_89 = mux(_wdata_rawIn_normDist_T_38, UInt<4>(0hd), _wdata_rawIn_normDist_T_88) node _wdata_rawIn_normDist_T_90 = mux(_wdata_rawIn_normDist_T_39, UInt<4>(0hc), _wdata_rawIn_normDist_T_89) node _wdata_rawIn_normDist_T_91 = mux(_wdata_rawIn_normDist_T_40, UInt<4>(0hb), _wdata_rawIn_normDist_T_90) node _wdata_rawIn_normDist_T_92 = mux(_wdata_rawIn_normDist_T_41, UInt<4>(0ha), _wdata_rawIn_normDist_T_91) node _wdata_rawIn_normDist_T_93 = mux(_wdata_rawIn_normDist_T_42, UInt<4>(0h9), _wdata_rawIn_normDist_T_92) node _wdata_rawIn_normDist_T_94 = mux(_wdata_rawIn_normDist_T_43, UInt<4>(0h8), _wdata_rawIn_normDist_T_93) node _wdata_rawIn_normDist_T_95 = mux(_wdata_rawIn_normDist_T_44, UInt<3>(0h7), _wdata_rawIn_normDist_T_94) node _wdata_rawIn_normDist_T_96 = mux(_wdata_rawIn_normDist_T_45, UInt<3>(0h6), _wdata_rawIn_normDist_T_95) node _wdata_rawIn_normDist_T_97 = mux(_wdata_rawIn_normDist_T_46, UInt<3>(0h5), _wdata_rawIn_normDist_T_96) node _wdata_rawIn_normDist_T_98 = mux(_wdata_rawIn_normDist_T_47, UInt<3>(0h4), _wdata_rawIn_normDist_T_97) node _wdata_rawIn_normDist_T_99 = mux(_wdata_rawIn_normDist_T_48, UInt<2>(0h3), _wdata_rawIn_normDist_T_98) node _wdata_rawIn_normDist_T_100 = mux(_wdata_rawIn_normDist_T_49, UInt<2>(0h2), _wdata_rawIn_normDist_T_99) node _wdata_rawIn_normDist_T_101 = mux(_wdata_rawIn_normDist_T_50, UInt<1>(0h1), _wdata_rawIn_normDist_T_100) node wdata_rawIn_normDist = mux(_wdata_rawIn_normDist_T_51, UInt<1>(0h0), _wdata_rawIn_normDist_T_101) node _wdata_rawIn_subnormFract_T = dshl(wdata_rawIn_fractIn, wdata_rawIn_normDist) node _wdata_rawIn_subnormFract_T_1 = bits(_wdata_rawIn_subnormFract_T, 50, 0) node wdata_rawIn_subnormFract = shl(_wdata_rawIn_subnormFract_T_1, 1) node _wdata_rawIn_adjustedExp_T = xor(wdata_rawIn_normDist, UInt<12>(0hfff)) node _wdata_rawIn_adjustedExp_T_1 = mux(wdata_rawIn_isZeroExpIn, _wdata_rawIn_adjustedExp_T, wdata_rawIn_expIn) node _wdata_rawIn_adjustedExp_T_2 = mux(wdata_rawIn_isZeroExpIn, UInt<2>(0h2), UInt<1>(0h1)) node _wdata_rawIn_adjustedExp_T_3 = or(UInt<11>(0h400), _wdata_rawIn_adjustedExp_T_2) node _wdata_rawIn_adjustedExp_T_4 = add(_wdata_rawIn_adjustedExp_T_1, _wdata_rawIn_adjustedExp_T_3) node wdata_rawIn_adjustedExp = tail(_wdata_rawIn_adjustedExp_T_4, 1) node wdata_rawIn_isZero = and(wdata_rawIn_isZeroExpIn, wdata_rawIn_isZeroFractIn) node _wdata_rawIn_isSpecial_T = bits(wdata_rawIn_adjustedExp, 11, 10) node wdata_rawIn_isSpecial = eq(_wdata_rawIn_isSpecial_T, UInt<2>(0h3)) wire wdata_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _wdata_rawIn_out_isNaN_T = eq(wdata_rawIn_isZeroFractIn, UInt<1>(0h0)) node _wdata_rawIn_out_isNaN_T_1 = and(wdata_rawIn_isSpecial, _wdata_rawIn_out_isNaN_T) connect wdata_rawIn.isNaN, _wdata_rawIn_out_isNaN_T_1 node _wdata_rawIn_out_isInf_T = and(wdata_rawIn_isSpecial, wdata_rawIn_isZeroFractIn) connect wdata_rawIn.isInf, _wdata_rawIn_out_isInf_T connect wdata_rawIn.isZero, wdata_rawIn_isZero connect wdata_rawIn.sign, wdata_rawIn_sign node _wdata_rawIn_out_sExp_T = bits(wdata_rawIn_adjustedExp, 11, 0) node _wdata_rawIn_out_sExp_T_1 = cvt(_wdata_rawIn_out_sExp_T) connect wdata_rawIn.sExp, _wdata_rawIn_out_sExp_T_1 node _wdata_rawIn_out_sig_T = eq(wdata_rawIn_isZero, UInt<1>(0h0)) node _wdata_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T) node _wdata_rawIn_out_sig_T_2 = mux(wdata_rawIn_isZeroExpIn, wdata_rawIn_subnormFract, wdata_rawIn_fractIn) node _wdata_rawIn_out_sig_T_3 = cat(_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2) connect wdata_rawIn.sig, _wdata_rawIn_out_sig_T_3 node _wdata_T_7 = bits(wdata_rawIn.sExp, 11, 9) node _wdata_T_8 = mux(wdata_rawIn.isZero, UInt<3>(0h0), _wdata_T_7) node _wdata_T_9 = mux(wdata_rawIn.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _wdata_T_10 = or(_wdata_T_8, _wdata_T_9) node _wdata_T_11 = cat(wdata_rawIn.sign, _wdata_T_10) node _wdata_T_12 = bits(wdata_rawIn.sExp, 8, 0) node _wdata_T_13 = cat(_wdata_T_11, _wdata_T_12) node _wdata_T_14 = bits(wdata_rawIn.sig, 51, 0) node _wdata_T_15 = cat(_wdata_T_13, _wdata_T_14) node wdata_rawIn_sign_1 = bits(_wdata_T_6, 31, 31) node wdata_rawIn_expIn_1 = bits(_wdata_T_6, 30, 23) node wdata_rawIn_fractIn_1 = bits(_wdata_T_6, 22, 0) node wdata_rawIn_isZeroExpIn_1 = eq(wdata_rawIn_expIn_1, UInt<1>(0h0)) node wdata_rawIn_isZeroFractIn_1 = eq(wdata_rawIn_fractIn_1, UInt<1>(0h0)) node _wdata_rawIn_normDist_T_102 = bits(wdata_rawIn_fractIn_1, 0, 0) node _wdata_rawIn_normDist_T_103 = bits(wdata_rawIn_fractIn_1, 1, 1) node _wdata_rawIn_normDist_T_104 = bits(wdata_rawIn_fractIn_1, 2, 2) node _wdata_rawIn_normDist_T_105 = bits(wdata_rawIn_fractIn_1, 3, 3) node _wdata_rawIn_normDist_T_106 = bits(wdata_rawIn_fractIn_1, 4, 4) node _wdata_rawIn_normDist_T_107 = bits(wdata_rawIn_fractIn_1, 5, 5) node _wdata_rawIn_normDist_T_108 = bits(wdata_rawIn_fractIn_1, 6, 6) node _wdata_rawIn_normDist_T_109 = bits(wdata_rawIn_fractIn_1, 7, 7) node _wdata_rawIn_normDist_T_110 = bits(wdata_rawIn_fractIn_1, 8, 8) node _wdata_rawIn_normDist_T_111 = bits(wdata_rawIn_fractIn_1, 9, 9) node _wdata_rawIn_normDist_T_112 = bits(wdata_rawIn_fractIn_1, 10, 10) node _wdata_rawIn_normDist_T_113 = bits(wdata_rawIn_fractIn_1, 11, 11) node _wdata_rawIn_normDist_T_114 = bits(wdata_rawIn_fractIn_1, 12, 12) node _wdata_rawIn_normDist_T_115 = bits(wdata_rawIn_fractIn_1, 13, 13) node _wdata_rawIn_normDist_T_116 = bits(wdata_rawIn_fractIn_1, 14, 14) node _wdata_rawIn_normDist_T_117 = bits(wdata_rawIn_fractIn_1, 15, 15) node _wdata_rawIn_normDist_T_118 = bits(wdata_rawIn_fractIn_1, 16, 16) node _wdata_rawIn_normDist_T_119 = bits(wdata_rawIn_fractIn_1, 17, 17) node _wdata_rawIn_normDist_T_120 = bits(wdata_rawIn_fractIn_1, 18, 18) node _wdata_rawIn_normDist_T_121 = bits(wdata_rawIn_fractIn_1, 19, 19) node _wdata_rawIn_normDist_T_122 = bits(wdata_rawIn_fractIn_1, 20, 20) node _wdata_rawIn_normDist_T_123 = bits(wdata_rawIn_fractIn_1, 21, 21) node _wdata_rawIn_normDist_T_124 = bits(wdata_rawIn_fractIn_1, 22, 22) node _wdata_rawIn_normDist_T_125 = mux(_wdata_rawIn_normDist_T_103, UInt<5>(0h15), UInt<5>(0h16)) node _wdata_rawIn_normDist_T_126 = mux(_wdata_rawIn_normDist_T_104, UInt<5>(0h14), _wdata_rawIn_normDist_T_125) node _wdata_rawIn_normDist_T_127 = mux(_wdata_rawIn_normDist_T_105, UInt<5>(0h13), _wdata_rawIn_normDist_T_126) node _wdata_rawIn_normDist_T_128 = mux(_wdata_rawIn_normDist_T_106, UInt<5>(0h12), _wdata_rawIn_normDist_T_127) node _wdata_rawIn_normDist_T_129 = mux(_wdata_rawIn_normDist_T_107, UInt<5>(0h11), _wdata_rawIn_normDist_T_128) node _wdata_rawIn_normDist_T_130 = mux(_wdata_rawIn_normDist_T_108, UInt<5>(0h10), _wdata_rawIn_normDist_T_129) node _wdata_rawIn_normDist_T_131 = mux(_wdata_rawIn_normDist_T_109, UInt<4>(0hf), _wdata_rawIn_normDist_T_130) node _wdata_rawIn_normDist_T_132 = mux(_wdata_rawIn_normDist_T_110, UInt<4>(0he), _wdata_rawIn_normDist_T_131) node _wdata_rawIn_normDist_T_133 = mux(_wdata_rawIn_normDist_T_111, UInt<4>(0hd), _wdata_rawIn_normDist_T_132) node _wdata_rawIn_normDist_T_134 = mux(_wdata_rawIn_normDist_T_112, UInt<4>(0hc), _wdata_rawIn_normDist_T_133) node _wdata_rawIn_normDist_T_135 = mux(_wdata_rawIn_normDist_T_113, UInt<4>(0hb), _wdata_rawIn_normDist_T_134) node _wdata_rawIn_normDist_T_136 = mux(_wdata_rawIn_normDist_T_114, UInt<4>(0ha), _wdata_rawIn_normDist_T_135) node _wdata_rawIn_normDist_T_137 = mux(_wdata_rawIn_normDist_T_115, UInt<4>(0h9), _wdata_rawIn_normDist_T_136) node _wdata_rawIn_normDist_T_138 = mux(_wdata_rawIn_normDist_T_116, UInt<4>(0h8), _wdata_rawIn_normDist_T_137) node _wdata_rawIn_normDist_T_139 = mux(_wdata_rawIn_normDist_T_117, UInt<3>(0h7), _wdata_rawIn_normDist_T_138) node _wdata_rawIn_normDist_T_140 = mux(_wdata_rawIn_normDist_T_118, UInt<3>(0h6), _wdata_rawIn_normDist_T_139) node _wdata_rawIn_normDist_T_141 = mux(_wdata_rawIn_normDist_T_119, UInt<3>(0h5), _wdata_rawIn_normDist_T_140) node _wdata_rawIn_normDist_T_142 = mux(_wdata_rawIn_normDist_T_120, UInt<3>(0h4), _wdata_rawIn_normDist_T_141) node _wdata_rawIn_normDist_T_143 = mux(_wdata_rawIn_normDist_T_121, UInt<2>(0h3), _wdata_rawIn_normDist_T_142) node _wdata_rawIn_normDist_T_144 = mux(_wdata_rawIn_normDist_T_122, UInt<2>(0h2), _wdata_rawIn_normDist_T_143) node _wdata_rawIn_normDist_T_145 = mux(_wdata_rawIn_normDist_T_123, UInt<1>(0h1), _wdata_rawIn_normDist_T_144) node wdata_rawIn_normDist_1 = mux(_wdata_rawIn_normDist_T_124, UInt<1>(0h0), _wdata_rawIn_normDist_T_145) node _wdata_rawIn_subnormFract_T_2 = dshl(wdata_rawIn_fractIn_1, wdata_rawIn_normDist_1) node _wdata_rawIn_subnormFract_T_3 = bits(_wdata_rawIn_subnormFract_T_2, 21, 0) node wdata_rawIn_subnormFract_1 = shl(_wdata_rawIn_subnormFract_T_3, 1) node _wdata_rawIn_adjustedExp_T_5 = xor(wdata_rawIn_normDist_1, UInt<9>(0h1ff)) node _wdata_rawIn_adjustedExp_T_6 = mux(wdata_rawIn_isZeroExpIn_1, _wdata_rawIn_adjustedExp_T_5, wdata_rawIn_expIn_1) node _wdata_rawIn_adjustedExp_T_7 = mux(wdata_rawIn_isZeroExpIn_1, UInt<2>(0h2), UInt<1>(0h1)) node _wdata_rawIn_adjustedExp_T_8 = or(UInt<8>(0h80), _wdata_rawIn_adjustedExp_T_7) node _wdata_rawIn_adjustedExp_T_9 = add(_wdata_rawIn_adjustedExp_T_6, _wdata_rawIn_adjustedExp_T_8) node wdata_rawIn_adjustedExp_1 = tail(_wdata_rawIn_adjustedExp_T_9, 1) node wdata_rawIn_isZero_1 = and(wdata_rawIn_isZeroExpIn_1, wdata_rawIn_isZeroFractIn_1) node _wdata_rawIn_isSpecial_T_1 = bits(wdata_rawIn_adjustedExp_1, 8, 7) node wdata_rawIn_isSpecial_1 = eq(_wdata_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire wdata_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _wdata_rawIn_out_isNaN_T_2 = eq(wdata_rawIn_isZeroFractIn_1, UInt<1>(0h0)) node _wdata_rawIn_out_isNaN_T_3 = and(wdata_rawIn_isSpecial_1, _wdata_rawIn_out_isNaN_T_2) connect wdata_rawIn_1.isNaN, _wdata_rawIn_out_isNaN_T_3 node _wdata_rawIn_out_isInf_T_1 = and(wdata_rawIn_isSpecial_1, wdata_rawIn_isZeroFractIn_1) connect wdata_rawIn_1.isInf, _wdata_rawIn_out_isInf_T_1 connect wdata_rawIn_1.isZero, wdata_rawIn_isZero_1 connect wdata_rawIn_1.sign, wdata_rawIn_sign_1 node _wdata_rawIn_out_sExp_T_2 = bits(wdata_rawIn_adjustedExp_1, 8, 0) node _wdata_rawIn_out_sExp_T_3 = cvt(_wdata_rawIn_out_sExp_T_2) connect wdata_rawIn_1.sExp, _wdata_rawIn_out_sExp_T_3 node _wdata_rawIn_out_sig_T_4 = eq(wdata_rawIn_isZero_1, UInt<1>(0h0)) node _wdata_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T_4) node _wdata_rawIn_out_sig_T_6 = mux(wdata_rawIn_isZeroExpIn_1, wdata_rawIn_subnormFract_1, wdata_rawIn_fractIn_1) node _wdata_rawIn_out_sig_T_7 = cat(_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6) connect wdata_rawIn_1.sig, _wdata_rawIn_out_sig_T_7 node _wdata_T_16 = bits(wdata_rawIn_1.sExp, 8, 6) node _wdata_T_17 = mux(wdata_rawIn_1.isZero, UInt<3>(0h0), _wdata_T_16) node _wdata_T_18 = mux(wdata_rawIn_1.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _wdata_T_19 = or(_wdata_T_17, _wdata_T_18) node _wdata_T_20 = cat(wdata_rawIn_1.sign, _wdata_T_19) node _wdata_T_21 = bits(wdata_rawIn_1.sExp, 5, 0) node _wdata_T_22 = cat(_wdata_T_20, _wdata_T_21) node _wdata_T_23 = bits(wdata_rawIn_1.sig, 22, 0) node _wdata_T_24 = cat(_wdata_T_22, _wdata_T_23) node wdata_rawIn_sign_2 = bits(_wdata_T_6, 15, 15) node wdata_rawIn_expIn_2 = bits(_wdata_T_6, 14, 10) node wdata_rawIn_fractIn_2 = bits(_wdata_T_6, 9, 0) node wdata_rawIn_isZeroExpIn_2 = eq(wdata_rawIn_expIn_2, UInt<1>(0h0)) node wdata_rawIn_isZeroFractIn_2 = eq(wdata_rawIn_fractIn_2, UInt<1>(0h0)) node _wdata_rawIn_normDist_T_146 = bits(wdata_rawIn_fractIn_2, 0, 0) node _wdata_rawIn_normDist_T_147 = bits(wdata_rawIn_fractIn_2, 1, 1) node _wdata_rawIn_normDist_T_148 = bits(wdata_rawIn_fractIn_2, 2, 2) node _wdata_rawIn_normDist_T_149 = bits(wdata_rawIn_fractIn_2, 3, 3) node _wdata_rawIn_normDist_T_150 = bits(wdata_rawIn_fractIn_2, 4, 4) node _wdata_rawIn_normDist_T_151 = bits(wdata_rawIn_fractIn_2, 5, 5) node _wdata_rawIn_normDist_T_152 = bits(wdata_rawIn_fractIn_2, 6, 6) node _wdata_rawIn_normDist_T_153 = bits(wdata_rawIn_fractIn_2, 7, 7) node _wdata_rawIn_normDist_T_154 = bits(wdata_rawIn_fractIn_2, 8, 8) node _wdata_rawIn_normDist_T_155 = bits(wdata_rawIn_fractIn_2, 9, 9) node _wdata_rawIn_normDist_T_156 = mux(_wdata_rawIn_normDist_T_147, UInt<4>(0h8), UInt<4>(0h9)) node _wdata_rawIn_normDist_T_157 = mux(_wdata_rawIn_normDist_T_148, UInt<3>(0h7), _wdata_rawIn_normDist_T_156) node _wdata_rawIn_normDist_T_158 = mux(_wdata_rawIn_normDist_T_149, UInt<3>(0h6), _wdata_rawIn_normDist_T_157) node _wdata_rawIn_normDist_T_159 = mux(_wdata_rawIn_normDist_T_150, UInt<3>(0h5), _wdata_rawIn_normDist_T_158) node _wdata_rawIn_normDist_T_160 = mux(_wdata_rawIn_normDist_T_151, UInt<3>(0h4), _wdata_rawIn_normDist_T_159) node _wdata_rawIn_normDist_T_161 = mux(_wdata_rawIn_normDist_T_152, UInt<2>(0h3), _wdata_rawIn_normDist_T_160) node _wdata_rawIn_normDist_T_162 = mux(_wdata_rawIn_normDist_T_153, UInt<2>(0h2), _wdata_rawIn_normDist_T_161) node _wdata_rawIn_normDist_T_163 = mux(_wdata_rawIn_normDist_T_154, UInt<1>(0h1), _wdata_rawIn_normDist_T_162) node wdata_rawIn_normDist_2 = mux(_wdata_rawIn_normDist_T_155, UInt<1>(0h0), _wdata_rawIn_normDist_T_163) node _wdata_rawIn_subnormFract_T_4 = dshl(wdata_rawIn_fractIn_2, wdata_rawIn_normDist_2) node _wdata_rawIn_subnormFract_T_5 = bits(_wdata_rawIn_subnormFract_T_4, 8, 0) node wdata_rawIn_subnormFract_2 = shl(_wdata_rawIn_subnormFract_T_5, 1) node _wdata_rawIn_adjustedExp_T_10 = xor(wdata_rawIn_normDist_2, UInt<6>(0h3f)) node _wdata_rawIn_adjustedExp_T_11 = mux(wdata_rawIn_isZeroExpIn_2, _wdata_rawIn_adjustedExp_T_10, wdata_rawIn_expIn_2) node _wdata_rawIn_adjustedExp_T_12 = mux(wdata_rawIn_isZeroExpIn_2, UInt<2>(0h2), UInt<1>(0h1)) node _wdata_rawIn_adjustedExp_T_13 = or(UInt<5>(0h10), _wdata_rawIn_adjustedExp_T_12) node _wdata_rawIn_adjustedExp_T_14 = add(_wdata_rawIn_adjustedExp_T_11, _wdata_rawIn_adjustedExp_T_13) node wdata_rawIn_adjustedExp_2 = tail(_wdata_rawIn_adjustedExp_T_14, 1) node wdata_rawIn_isZero_2 = and(wdata_rawIn_isZeroExpIn_2, wdata_rawIn_isZeroFractIn_2) node _wdata_rawIn_isSpecial_T_2 = bits(wdata_rawIn_adjustedExp_2, 5, 4) node wdata_rawIn_isSpecial_2 = eq(_wdata_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire wdata_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _wdata_rawIn_out_isNaN_T_4 = eq(wdata_rawIn_isZeroFractIn_2, UInt<1>(0h0)) node _wdata_rawIn_out_isNaN_T_5 = and(wdata_rawIn_isSpecial_2, _wdata_rawIn_out_isNaN_T_4) connect wdata_rawIn_2.isNaN, _wdata_rawIn_out_isNaN_T_5 node _wdata_rawIn_out_isInf_T_2 = and(wdata_rawIn_isSpecial_2, wdata_rawIn_isZeroFractIn_2) connect wdata_rawIn_2.isInf, _wdata_rawIn_out_isInf_T_2 connect wdata_rawIn_2.isZero, wdata_rawIn_isZero_2 connect wdata_rawIn_2.sign, wdata_rawIn_sign_2 node _wdata_rawIn_out_sExp_T_4 = bits(wdata_rawIn_adjustedExp_2, 5, 0) node _wdata_rawIn_out_sExp_T_5 = cvt(_wdata_rawIn_out_sExp_T_4) connect wdata_rawIn_2.sExp, _wdata_rawIn_out_sExp_T_5 node _wdata_rawIn_out_sig_T_8 = eq(wdata_rawIn_isZero_2, UInt<1>(0h0)) node _wdata_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _wdata_rawIn_out_sig_T_8) node _wdata_rawIn_out_sig_T_10 = mux(wdata_rawIn_isZeroExpIn_2, wdata_rawIn_subnormFract_2, wdata_rawIn_fractIn_2) node _wdata_rawIn_out_sig_T_11 = cat(_wdata_rawIn_out_sig_T_9, _wdata_rawIn_out_sig_T_10) connect wdata_rawIn_2.sig, _wdata_rawIn_out_sig_T_11 node _wdata_T_25 = bits(wdata_rawIn_2.sExp, 5, 3) node _wdata_T_26 = mux(wdata_rawIn_2.isZero, UInt<3>(0h0), _wdata_T_25) node _wdata_T_27 = mux(wdata_rawIn_2.isNaN, UInt<1>(0h1), UInt<1>(0h0)) node _wdata_T_28 = or(_wdata_T_26, _wdata_T_27) node _wdata_T_29 = cat(wdata_rawIn_2.sign, _wdata_T_28) node _wdata_T_30 = bits(wdata_rawIn_2.sExp, 2, 0) node _wdata_T_31 = cat(_wdata_T_29, _wdata_T_30) node _wdata_T_32 = bits(wdata_rawIn_2.sig, 9, 0) node _wdata_T_33 = cat(_wdata_T_31, _wdata_T_32) node _wdata_swizzledNaN_T = bits(_wdata_T_24, 32, 29) node _wdata_swizzledNaN_T_1 = bits(_wdata_T_24, 22, 16) node _wdata_swizzledNaN_T_2 = andr(_wdata_swizzledNaN_T_1) node _wdata_swizzledNaN_T_3 = bits(_wdata_T_24, 27, 24) node _wdata_swizzledNaN_T_4 = bits(_wdata_T_33, 15, 15) node _wdata_swizzledNaN_T_5 = bits(_wdata_T_24, 22, 16) node _wdata_swizzledNaN_T_6 = bits(_wdata_T_33, 16, 16) node _wdata_swizzledNaN_T_7 = bits(_wdata_T_33, 14, 0) node wdata_swizzledNaN_lo_hi = cat(_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6) node wdata_swizzledNaN_lo = cat(wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7) node wdata_swizzledNaN_hi_lo = cat(_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4) node wdata_swizzledNaN_hi_hi = cat(_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2) node wdata_swizzledNaN_hi = cat(wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo) node wdata_swizzledNaN = cat(wdata_swizzledNaN_hi, wdata_swizzledNaN_lo) node _wdata_T_34 = bits(_wdata_T_24, 31, 29) node _wdata_T_35 = andr(_wdata_T_34) node _wdata_T_36 = mux(_wdata_T_35, wdata_swizzledNaN, _wdata_T_24) node _wdata_swizzledNaN_T_8 = bits(_wdata_T_15, 64, 61) node _wdata_swizzledNaN_T_9 = bits(_wdata_T_15, 51, 32) node _wdata_swizzledNaN_T_10 = andr(_wdata_swizzledNaN_T_9) node _wdata_swizzledNaN_T_11 = bits(_wdata_T_15, 59, 53) node _wdata_swizzledNaN_T_12 = bits(_wdata_T_36, 31, 31) node _wdata_swizzledNaN_T_13 = bits(_wdata_T_15, 51, 32) node _wdata_swizzledNaN_T_14 = bits(_wdata_T_36, 32, 32) node _wdata_swizzledNaN_T_15 = bits(_wdata_T_36, 30, 0) node wdata_swizzledNaN_lo_hi_1 = cat(_wdata_swizzledNaN_T_13, _wdata_swizzledNaN_T_14) node wdata_swizzledNaN_lo_1 = cat(wdata_swizzledNaN_lo_hi_1, _wdata_swizzledNaN_T_15) node wdata_swizzledNaN_hi_lo_1 = cat(_wdata_swizzledNaN_T_11, _wdata_swizzledNaN_T_12) node wdata_swizzledNaN_hi_hi_1 = cat(_wdata_swizzledNaN_T_8, _wdata_swizzledNaN_T_10) node wdata_swizzledNaN_hi_1 = cat(wdata_swizzledNaN_hi_hi_1, wdata_swizzledNaN_hi_lo_1) node wdata_swizzledNaN_1 = cat(wdata_swizzledNaN_hi_1, wdata_swizzledNaN_lo_1) node _wdata_T_37 = bits(_wdata_T_15, 63, 61) node _wdata_T_38 = andr(_wdata_T_37) node wdata = mux(_wdata_T_38, wdata_swizzledNaN_1, _wdata_T_15) infer mport MPORT = regfile[load_wb_tag], clock connect MPORT, wdata node _unswizzled_T = bits(wdata, 31, 31) node _unswizzled_T_1 = bits(wdata, 52, 52) node _unswizzled_T_2 = bits(wdata, 30, 0) node unswizzled_hi = cat(_unswizzled_T, _unswizzled_T_1) node unswizzled = cat(unswizzled_hi, _unswizzled_T_2) node _prevOK_T = bits(wdata, 64, 60) node _prevOK_T_1 = andr(_prevOK_T) node _prevOK_T_2 = eq(_prevOK_T_1, UInt<1>(0h0)) node _prevOK_unswizzled_T = bits(unswizzled, 15, 15) node _prevOK_unswizzled_T_1 = bits(unswizzled, 23, 23) node _prevOK_unswizzled_T_2 = bits(unswizzled, 14, 0) node prevOK_unswizzled_hi = cat(_prevOK_unswizzled_T, _prevOK_unswizzled_T_1) node prevOK_unswizzled = cat(prevOK_unswizzled_hi, _prevOK_unswizzled_T_2) node _prevOK_prevOK_T = bits(unswizzled, 32, 28) node _prevOK_prevOK_T_1 = andr(_prevOK_prevOK_T) node _prevOK_prevOK_T_2 = eq(_prevOK_prevOK_T_1, UInt<1>(0h0)) node prevOK_prevOK = or(_prevOK_prevOK_T_2, UInt<1>(0h1)) node _prevOK_curOK_T = bits(unswizzled, 31, 29) node _prevOK_curOK_T_1 = andr(_prevOK_curOK_T) node _prevOK_curOK_T_2 = eq(_prevOK_curOK_T_1, UInt<1>(0h0)) node _prevOK_curOK_T_3 = bits(unswizzled, 28, 28) node _prevOK_curOK_T_4 = bits(unswizzled, 22, 16) node _prevOK_curOK_T_5 = andr(_prevOK_curOK_T_4) node _prevOK_curOK_T_6 = eq(_prevOK_curOK_T_3, _prevOK_curOK_T_5) node prevOK_curOK = or(_prevOK_curOK_T_2, _prevOK_curOK_T_6) node _prevOK_T_3 = and(prevOK_prevOK, prevOK_curOK) node prevOK = or(_prevOK_T_2, _prevOK_T_3) node _curOK_T = bits(wdata, 63, 61) node _curOK_T_1 = andr(_curOK_T) node _curOK_T_2 = eq(_curOK_T_1, UInt<1>(0h0)) node _curOK_T_3 = bits(wdata, 60, 60) node _curOK_T_4 = bits(wdata, 51, 32) node _curOK_T_5 = andr(_curOK_T_4) node _curOK_T_6 = eq(_curOK_T_3, _curOK_T_5) node curOK = or(_curOK_T_2, _curOK_T_6) node _T = and(prevOK, curOK) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at FPU.scala:822 assert(consistent(wdata))\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert connect frfWriteBundle_0.wrdst, load_wb_tag connect frfWriteBundle_0.wrenf, UInt<1>(0h1) node frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = bits(wdata, 63, 52) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 11, 9) node frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 11, 10) node frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_0_wrdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_0_wrdata_unrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = bits(wdata, 64, 64) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_unrecoded_rawIn_exp) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = bits(wdata, 51, 0) node _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_0_wrdata_unrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, 5, 0) node _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T) node frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, 1) node _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_unrecoded_denormFract_T, frfWriteBundle_0_wrdata_unrecoded_denormShiftDist) node frfWriteBundle_0_wrdata_unrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1, 51, 0) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sExp, 10, 0) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_unrecoded_expOut_T, UInt<11>(0h401)) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_1, 1) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_unrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf) node _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node frfWriteBundle_0_wrdata_unrecoded_expOut = or(_frfWriteBundle_0_wrdata_unrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5) node _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_unrecoded_rawIn.sig, 51, 0) node _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_unrecoded_fractOut_T) node frfWriteBundle_0_wrdata_unrecoded_fractOut = mux(frfWriteBundle_0_wrdata_unrecoded_isSubnormal, frfWriteBundle_0_wrdata_unrecoded_denormFract, _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1) node frfWriteBundle_0_wrdata_unrecoded_hi = cat(frfWriteBundle_0_wrdata_unrecoded_rawIn.sign, frfWriteBundle_0_wrdata_unrecoded_expOut) node frfWriteBundle_0_wrdata_unrecoded = cat(frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut) node _frfWriteBundle_0_wrdata_prevRecoded_T = bits(wdata, 31, 31) node _frfWriteBundle_0_wrdata_prevRecoded_T_1 = bits(wdata, 52, 52) node _frfWriteBundle_0_wrdata_prevRecoded_T_2 = bits(wdata, 30, 0) node frfWriteBundle_0_wrdata_prevRecoded_hi = cat(_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1) node frfWriteBundle_0_wrdata_prevRecoded = cat(frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp = bits(frfWriteBundle_0_wrdata_prevRecoded, 31, 23) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(frfWriteBundle_0_wrdata_prevRecoded, 32, 32) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_0_wrdata_prevRecoded, 22, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isInf) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut = or(_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut = mux(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi = cat(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn.sign, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut) node frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T = bits(frfWriteBundle_0_wrdata_prevRecoded, 15, 15) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1 = bits(frfWriteBundle_0_wrdata_prevRecoded, 23, 23) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2 = bits(frfWriteBundle_0_wrdata_prevRecoded, 14, 0) node frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1) node frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded, 15, 10) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isZero, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded, 16, 16) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded, 9, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = lt(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract = bits(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut = or(_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = bits(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut = mux(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi = cat(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut) node frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded = cat(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut) node _frfWriteBundle_0_wrdata_prevUnrecoded_T = shr(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded, 16) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_1 = bits(frfWriteBundle_0_wrdata_prevRecoded, 31, 29) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 = andr(_frfWriteBundle_0_wrdata_prevUnrecoded_T_1) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_3 = bits(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded, 15, 0) node _frfWriteBundle_0_wrdata_prevUnrecoded_T_4 = mux(_frfWriteBundle_0_wrdata_prevUnrecoded_T_2, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded, _frfWriteBundle_0_wrdata_prevUnrecoded_T_3) node frfWriteBundle_0_wrdata_prevUnrecoded = cat(_frfWriteBundle_0_wrdata_prevUnrecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_T_4) node _frfWriteBundle_0_wrdata_T = shr(frfWriteBundle_0_wrdata_unrecoded, 32) node _frfWriteBundle_0_wrdata_T_1 = bits(wdata, 63, 61) node _frfWriteBundle_0_wrdata_T_2 = andr(_frfWriteBundle_0_wrdata_T_1) node _frfWriteBundle_0_wrdata_T_3 = bits(frfWriteBundle_0_wrdata_unrecoded, 31, 0) node _frfWriteBundle_0_wrdata_T_4 = mux(_frfWriteBundle_0_wrdata_T_2, frfWriteBundle_0_wrdata_prevUnrecoded, _frfWriteBundle_0_wrdata_T_3) node _frfWriteBundle_0_wrdata_T_5 = cat(_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4) connect frfWriteBundle_0.wrdata, _frfWriteBundle_0_wrdata_T_5 node _ex_rs_T = or(ex_ra_0, UInt<5>(0h0)) node _ex_rs_T_1 = bits(_ex_rs_T, 4, 0) infer mport ex_rs_0 = regfile[_ex_rs_T_1], clock node _ex_rs_T_2 = or(ex_ra_1, UInt<5>(0h0)) node _ex_rs_T_3 = bits(_ex_rs_T_2, 4, 0) infer mport ex_rs_1 = regfile[_ex_rs_T_3], clock node _ex_rs_T_4 = or(ex_ra_2, UInt<5>(0h0)) node _ex_rs_T_5 = bits(_ex_rs_T_4, 4, 0) infer mport ex_rs_2 = regfile[_ex_rs_T_5], clock when io.valid : when id_ctrl.ren1 : node _T_4 = eq(id_ctrl.swap12, UInt<1>(0h0)) when _T_4 : node _ex_ra_0_T = bits(io.inst, 19, 15) connect ex_ra_0, _ex_ra_0_T when id_ctrl.swap12 : node _ex_ra_1_T = bits(io.inst, 19, 15) connect ex_ra_1, _ex_ra_1_T when id_ctrl.ren2 : when id_ctrl.swap12 : node _ex_ra_0_T_1 = bits(io.inst, 24, 20) connect ex_ra_0, _ex_ra_0_T_1 when id_ctrl.swap23 : node _ex_ra_2_T = bits(io.inst, 24, 20) connect ex_ra_2, _ex_ra_2_T node _T_5 = eq(id_ctrl.swap12, UInt<1>(0h0)) node _T_6 = eq(id_ctrl.swap23, UInt<1>(0h0)) node _T_7 = and(_T_5, _T_6) when _T_7 : node _ex_ra_1_T_1 = bits(io.inst, 24, 20) connect ex_ra_1, _ex_ra_1_T_1 when id_ctrl.ren3 : node _ex_ra_2_T_1 = bits(io.inst, 31, 27) connect ex_ra_2, _ex_ra_2_T_1 node _ex_rm_T = bits(ex_reg_inst, 14, 12) node _ex_rm_T_1 = eq(_ex_rm_T, UInt<3>(0h7)) node _ex_rm_T_2 = bits(ex_reg_inst, 14, 12) node ex_rm = mux(_ex_rm_T_1, io.fcsr_rm, _ex_rm_T_2) inst sfma of FPUFMAPipe_l3_f32_4 connect sfma.clock, clock connect sfma.reset, reset node _sfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) node _sfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) node _sfma_io_in_valid_T_2 = and(_sfma_io_in_valid_T, _sfma_io_in_valid_T_1) connect sfma.io.in.valid, _sfma_io_in_valid_T_2 wire sfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect sfma_io_in_bits_req.vec, ex_ctrl.vec connect sfma_io_in_bits_req.wflags, ex_ctrl.wflags connect sfma_io_in_bits_req.sqrt, ex_ctrl.sqrt connect sfma_io_in_bits_req.div, ex_ctrl.div connect sfma_io_in_bits_req.fma, ex_ctrl.fma connect sfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect sfma_io_in_bits_req.toint, ex_ctrl.toint connect sfma_io_in_bits_req.fromint, ex_ctrl.fromint connect sfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect sfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect sfma_io_in_bits_req.swap23, ex_ctrl.swap23 connect sfma_io_in_bits_req.swap12, ex_ctrl.swap12 connect sfma_io_in_bits_req.ren3, ex_ctrl.ren3 connect sfma_io_in_bits_req.ren2, ex_ctrl.ren2 connect sfma_io_in_bits_req.ren1, ex_ctrl.ren1 connect sfma_io_in_bits_req.wen, ex_ctrl.wen connect sfma_io_in_bits_req.ldst, ex_ctrl.ldst connect sfma_io_in_bits_req.rm, ex_rm node _sfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node sfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_floats_1 = cat(sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in1_floats_1, 15, 15) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in1_floats_1, 23, 23) node _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in1_floats_1, 14, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in1_floats_0 = cat(sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in1_floats_1, 32, 28) node sfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in1_prev_prev_0_1 = and(sfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node sfma_io_in_bits_req_in1_prev_isbox = andr(_sfma_io_in_bits_req_in1_prev_isbox_T) node sfma_io_in_bits_req_in1_oks_0 = and(sfma_io_in_bits_req_in1_prev_isbox, sfma_io_in_bits_req_in1_prev_prev_0_1) node sfma_io_in_bits_req_in1_oks_1 = and(sfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in1_sign = bits(ex_rs_0, 64, 64) node sfma_io_in_bits_req_in1_fractIn = bits(ex_rs_0, 51, 0) node sfma_io_in_bits_req_in1_expIn = bits(ex_rs_0, 63, 52) node _sfma_io_in_bits_req_in1_fractOut_T = shl(sfma_io_in_bits_req_in1_fractIn, 24) node sfma_io_in_bits_req_in1_fractOut = shr(_sfma_io_in_bits_req_in1_fractOut_T, 53) node sfma_io_in_bits_req_in1_expOut_expCode = bits(sfma_io_in_bits_req_in1_expIn, 11, 9) node _sfma_io_in_bits_req_in1_expOut_commonCase_T = add(sfma_io_in_bits_req_in1_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in1_expOut_commonCase = tail(_sfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in1_expOut_T = eq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in1_expOut_T_1 = geq(sfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in1_expOut_T_2 = or(_sfma_io_in_bits_req_in1_expOut_T, _sfma_io_in_bits_req_in1_expOut_T_1) node _sfma_io_in_bits_req_in1_expOut_T_3 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in1_expOut_T_4 = cat(sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3) node _sfma_io_in_bits_req_in1_expOut_T_5 = bits(sfma_io_in_bits_req_in1_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in1_expOut = mux(_sfma_io_in_bits_req_in1_expOut_T_2, _sfma_io_in_bits_req_in1_expOut_T_4, _sfma_io_in_bits_req_in1_expOut_T_5) node sfma_io_in_bits_req_in1_hi = cat(sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut) node sfma_io_in_bits_req_in1_floats_2 = cat(sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut) node _sfma_io_in_bits_req_in1_T = mux(sfma_io_in_bits_req_in1_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in1_T_1 = or(sfma_io_in_bits_req_in1_floats_1, _sfma_io_in_bits_req_in1_T) connect sfma_io_in_bits_req.in1, _sfma_io_in_bits_req_in1_T_1 node _sfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node sfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_floats_1 = cat(sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in2_floats_1, 15, 15) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in2_floats_1, 23, 23) node _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in2_floats_1, 14, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in2_floats_0 = cat(sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in2_floats_1, 32, 28) node sfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in2_prev_prev_0_1 = and(sfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node sfma_io_in_bits_req_in2_prev_isbox = andr(_sfma_io_in_bits_req_in2_prev_isbox_T) node sfma_io_in_bits_req_in2_oks_0 = and(sfma_io_in_bits_req_in2_prev_isbox, sfma_io_in_bits_req_in2_prev_prev_0_1) node sfma_io_in_bits_req_in2_oks_1 = and(sfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in2_sign = bits(ex_rs_1, 64, 64) node sfma_io_in_bits_req_in2_fractIn = bits(ex_rs_1, 51, 0) node sfma_io_in_bits_req_in2_expIn = bits(ex_rs_1, 63, 52) node _sfma_io_in_bits_req_in2_fractOut_T = shl(sfma_io_in_bits_req_in2_fractIn, 24) node sfma_io_in_bits_req_in2_fractOut = shr(_sfma_io_in_bits_req_in2_fractOut_T, 53) node sfma_io_in_bits_req_in2_expOut_expCode = bits(sfma_io_in_bits_req_in2_expIn, 11, 9) node _sfma_io_in_bits_req_in2_expOut_commonCase_T = add(sfma_io_in_bits_req_in2_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in2_expOut_commonCase = tail(_sfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in2_expOut_T = eq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in2_expOut_T_1 = geq(sfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in2_expOut_T_2 = or(_sfma_io_in_bits_req_in2_expOut_T, _sfma_io_in_bits_req_in2_expOut_T_1) node _sfma_io_in_bits_req_in2_expOut_T_3 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in2_expOut_T_4 = cat(sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3) node _sfma_io_in_bits_req_in2_expOut_T_5 = bits(sfma_io_in_bits_req_in2_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in2_expOut = mux(_sfma_io_in_bits_req_in2_expOut_T_2, _sfma_io_in_bits_req_in2_expOut_T_4, _sfma_io_in_bits_req_in2_expOut_T_5) node sfma_io_in_bits_req_in2_hi = cat(sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut) node sfma_io_in_bits_req_in2_floats_2 = cat(sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut) node _sfma_io_in_bits_req_in2_T = mux(sfma_io_in_bits_req_in2_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in2_T_1 = or(sfma_io_in_bits_req_in2_floats_1, _sfma_io_in_bits_req_in2_T) connect sfma_io_in_bits_req.in2, _sfma_io_in_bits_req_in2_T_1 node _sfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node sfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_floats_1 = cat(sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(sfma_io_in_bits_req_in3_floats_1, 15, 15) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(sfma_io_in_bits_req_in3_floats_1, 23, 23) node _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(sfma_io_in_bits_req_in3_floats_1, 14, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node sfma_io_in_bits_req_in3_floats_0 = cat(sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(sfma_io_in_bits_req_in3_floats_1, 32, 28) node sfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node sfma_io_in_bits_req_in3_prev_prev_0_1 = and(sfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node _sfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node sfma_io_in_bits_req_in3_prev_isbox = andr(_sfma_io_in_bits_req_in3_prev_isbox_T) node sfma_io_in_bits_req_in3_oks_0 = and(sfma_io_in_bits_req_in3_prev_isbox, sfma_io_in_bits_req_in3_prev_prev_0_1) node sfma_io_in_bits_req_in3_oks_1 = and(sfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node sfma_io_in_bits_req_in3_sign = bits(ex_rs_2, 64, 64) node sfma_io_in_bits_req_in3_fractIn = bits(ex_rs_2, 51, 0) node sfma_io_in_bits_req_in3_expIn = bits(ex_rs_2, 63, 52) node _sfma_io_in_bits_req_in3_fractOut_T = shl(sfma_io_in_bits_req_in3_fractIn, 24) node sfma_io_in_bits_req_in3_fractOut = shr(_sfma_io_in_bits_req_in3_fractOut_T, 53) node sfma_io_in_bits_req_in3_expOut_expCode = bits(sfma_io_in_bits_req_in3_expIn, 11, 9) node _sfma_io_in_bits_req_in3_expOut_commonCase_T = add(sfma_io_in_bits_req_in3_expIn, UInt<9>(0h100)) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_sfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node sfma_io_in_bits_req_in3_expOut_commonCase = tail(_sfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _sfma_io_in_bits_req_in3_expOut_T = eq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _sfma_io_in_bits_req_in3_expOut_T_1 = geq(sfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _sfma_io_in_bits_req_in3_expOut_T_2 = or(_sfma_io_in_bits_req_in3_expOut_T, _sfma_io_in_bits_req_in3_expOut_T_1) node _sfma_io_in_bits_req_in3_expOut_T_3 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node _sfma_io_in_bits_req_in3_expOut_T_4 = cat(sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3) node _sfma_io_in_bits_req_in3_expOut_T_5 = bits(sfma_io_in_bits_req_in3_expOut_commonCase, 8, 0) node sfma_io_in_bits_req_in3_expOut = mux(_sfma_io_in_bits_req_in3_expOut_T_2, _sfma_io_in_bits_req_in3_expOut_T_4, _sfma_io_in_bits_req_in3_expOut_T_5) node sfma_io_in_bits_req_in3_hi = cat(sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut) node sfma_io_in_bits_req_in3_floats_2 = cat(sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut) node _sfma_io_in_bits_req_in3_T = mux(sfma_io_in_bits_req_in3_oks_1, UInt<1>(0h0), UInt<33>(0he0400000)) node _sfma_io_in_bits_req_in3_T_1 = or(sfma_io_in_bits_req_in3_floats_1, _sfma_io_in_bits_req_in3_T) connect sfma_io_in_bits_req.in3, _sfma_io_in_bits_req_in3_T_1 node _sfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect sfma_io_in_bits_req.typ, _sfma_io_in_bits_req_typ_T node _sfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect sfma_io_in_bits_req.fmt, _sfma_io_in_bits_req_fmt_T node _sfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _sfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _sfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _sfma_io_in_bits_req_fmaCmd_T_3 = and(_sfma_io_in_bits_req_fmaCmd_T_1, _sfma_io_in_bits_req_fmaCmd_T_2) node _sfma_io_in_bits_req_fmaCmd_T_4 = or(_sfma_io_in_bits_req_fmaCmd_T, _sfma_io_in_bits_req_fmaCmd_T_3) connect sfma_io_in_bits_req.fmaCmd, _sfma_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect sfma_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect sfma_io_in_bits_req.in1, io.cp_req.bits.in2 connect sfma_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect sfma_io_in_bits_req.in2, io.cp_req.bits.in3 connect sfma_io_in_bits_req.in3, io.cp_req.bits.in2 connect sfma.io.in.bits.in3, sfma_io_in_bits_req.in3 connect sfma.io.in.bits.in2, sfma_io_in_bits_req.in2 connect sfma.io.in.bits.in1, sfma_io_in_bits_req.in1 connect sfma.io.in.bits.fmt, sfma_io_in_bits_req.fmt connect sfma.io.in.bits.typ, sfma_io_in_bits_req.typ connect sfma.io.in.bits.fmaCmd, sfma_io_in_bits_req.fmaCmd connect sfma.io.in.bits.rm, sfma_io_in_bits_req.rm connect sfma.io.in.bits.vec, sfma_io_in_bits_req.vec connect sfma.io.in.bits.wflags, sfma_io_in_bits_req.wflags connect sfma.io.in.bits.sqrt, sfma_io_in_bits_req.sqrt connect sfma.io.in.bits.div, sfma_io_in_bits_req.div connect sfma.io.in.bits.fma, sfma_io_in_bits_req.fma connect sfma.io.in.bits.fastpipe, sfma_io_in_bits_req.fastpipe connect sfma.io.in.bits.toint, sfma_io_in_bits_req.toint connect sfma.io.in.bits.fromint, sfma_io_in_bits_req.fromint connect sfma.io.in.bits.typeTagOut, sfma_io_in_bits_req.typeTagOut connect sfma.io.in.bits.typeTagIn, sfma_io_in_bits_req.typeTagIn connect sfma.io.in.bits.swap23, sfma_io_in_bits_req.swap23 connect sfma.io.in.bits.swap12, sfma_io_in_bits_req.swap12 connect sfma.io.in.bits.ren3, sfma_io_in_bits_req.ren3 connect sfma.io.in.bits.ren2, sfma_io_in_bits_req.ren2 connect sfma.io.in.bits.ren1, sfma_io_in_bits_req.ren1 connect sfma.io.in.bits.wen, sfma_io_in_bits_req.wen connect sfma.io.in.bits.ldst, sfma_io_in_bits_req.ldst inst fpiu of FPToInt_4 connect fpiu.clock, clock connect fpiu.reset, reset node _fpiu_io_in_valid_T = or(ex_ctrl.toint, ex_ctrl.div) node _fpiu_io_in_valid_T_1 = or(_fpiu_io_in_valid_T, ex_ctrl.sqrt) node _fpiu_io_in_valid_T_2 = and(ex_ctrl.fastpipe, ex_ctrl.wflags) node _fpiu_io_in_valid_T_3 = or(_fpiu_io_in_valid_T_1, _fpiu_io_in_valid_T_2) node _fpiu_io_in_valid_T_4 = and(req_valid, _fpiu_io_in_valid_T_3) connect fpiu.io.in.valid, _fpiu_io_in_valid_T_4 wire fpiu_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect fpiu_io_in_bits_req.vec, ex_ctrl.vec connect fpiu_io_in_bits_req.wflags, ex_ctrl.wflags connect fpiu_io_in_bits_req.sqrt, ex_ctrl.sqrt connect fpiu_io_in_bits_req.div, ex_ctrl.div connect fpiu_io_in_bits_req.fma, ex_ctrl.fma connect fpiu_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect fpiu_io_in_bits_req.toint, ex_ctrl.toint connect fpiu_io_in_bits_req.fromint, ex_ctrl.fromint connect fpiu_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect fpiu_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect fpiu_io_in_bits_req.swap23, ex_ctrl.swap23 connect fpiu_io_in_bits_req.swap12, ex_ctrl.swap12 connect fpiu_io_in_bits_req.ren3, ex_ctrl.ren3 connect fpiu_io_in_bits_req.ren2, ex_ctrl.ren2 connect fpiu_io_in_bits_req.ren1, ex_ctrl.ren1 connect fpiu_io_in_bits_req.wen, ex_ctrl.wen connect fpiu_io_in_bits_req.ldst, ex_ctrl.ldst connect fpiu_io_in_bits_req.rm, ex_rm node _fpiu_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node fpiu_io_in_bits_req_in1_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_0 = cat(fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in1_prev_prev_0_1 = and(fpiu_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in1_prev_prev_sign = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in1_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in1_prev_prev_expIn = bits(fpiu_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in1_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in1_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in1_prev_prev_hi = cat(fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut) node fpiu_io_in_bits_req_in1_floats_1 = cat(fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut) node _fpiu_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node fpiu_io_in_bits_req_in1_prev_isbox = andr(_fpiu_io_in_bits_req_in1_prev_isbox_T) node fpiu_io_in_bits_req_in1_oks_0 = and(fpiu_io_in_bits_req_in1_prev_isbox, fpiu_io_in_bits_req_in1_prev_prev_0_1) node fpiu_io_in_bits_req_in1_oks_1 = and(fpiu_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_1 = mux(_fpiu_io_in_bits_req_in1_T, fpiu_io_in_bits_req_in1_oks_1, fpiu_io_in_bits_req_in1_oks_0) node _fpiu_io_in_bits_req_in1_T_2 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in1_T_3 = mux(_fpiu_io_in_bits_req_in1_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in1_T_1) node _fpiu_io_in_bits_req_in1_T_4 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in1_T_5 = mux(_fpiu_io_in_bits_req_in1_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in1_T_3) node _fpiu_io_in_bits_req_in1_T_6 = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in1_T_7 = mux(_fpiu_io_in_bits_req_in1_T_6, fpiu_io_in_bits_req_in1_floats_1, fpiu_io_in_bits_req_in1_floats_0) node _fpiu_io_in_bits_req_in1_T_8 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in1_T_9 = mux(_fpiu_io_in_bits_req_in1_T_8, ex_rs_0, _fpiu_io_in_bits_req_in1_T_7) node _fpiu_io_in_bits_req_in1_T_10 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in1_T_11 = mux(_fpiu_io_in_bits_req_in1_T_10, ex_rs_0, _fpiu_io_in_bits_req_in1_T_9) node _fpiu_io_in_bits_req_in1_T_12 = mux(_fpiu_io_in_bits_req_in1_T_5, _fpiu_io_in_bits_req_in1_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in1, _fpiu_io_in_bits_req_in1_T_12 node _fpiu_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node fpiu_io_in_bits_req_in2_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_0 = cat(fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in2_prev_prev_0_1 = and(fpiu_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in2_prev_prev_sign = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in2_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in2_prev_prev_expIn = bits(fpiu_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in2_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in2_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in2_prev_prev_hi = cat(fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut) node fpiu_io_in_bits_req_in2_floats_1 = cat(fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut) node _fpiu_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node fpiu_io_in_bits_req_in2_prev_isbox = andr(_fpiu_io_in_bits_req_in2_prev_isbox_T) node fpiu_io_in_bits_req_in2_oks_0 = and(fpiu_io_in_bits_req_in2_prev_isbox, fpiu_io_in_bits_req_in2_prev_prev_0_1) node fpiu_io_in_bits_req_in2_oks_1 = and(fpiu_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_1 = mux(_fpiu_io_in_bits_req_in2_T, fpiu_io_in_bits_req_in2_oks_1, fpiu_io_in_bits_req_in2_oks_0) node _fpiu_io_in_bits_req_in2_T_2 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in2_T_3 = mux(_fpiu_io_in_bits_req_in2_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in2_T_1) node _fpiu_io_in_bits_req_in2_T_4 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in2_T_5 = mux(_fpiu_io_in_bits_req_in2_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in2_T_3) node _fpiu_io_in_bits_req_in2_T_6 = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in2_T_7 = mux(_fpiu_io_in_bits_req_in2_T_6, fpiu_io_in_bits_req_in2_floats_1, fpiu_io_in_bits_req_in2_floats_0) node _fpiu_io_in_bits_req_in2_T_8 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in2_T_9 = mux(_fpiu_io_in_bits_req_in2_T_8, ex_rs_1, _fpiu_io_in_bits_req_in2_T_7) node _fpiu_io_in_bits_req_in2_T_10 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in2_T_11 = mux(_fpiu_io_in_bits_req_in2_T_10, ex_rs_1, _fpiu_io_in_bits_req_in2_T_9) node _fpiu_io_in_bits_req_in2_T_12 = mux(_fpiu_io_in_bits_req_in2_T_5, _fpiu_io_in_bits_req_in2_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in2, _fpiu_io_in_bits_req_in2_T_12 node _fpiu_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node fpiu_io_in_bits_req_in3_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 14, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_0 = cat(fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 28) node fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T) node fpiu_io_in_bits_req_in3_prev_prev_0_1 = and(fpiu_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node fpiu_io_in_bits_req_in3_prev_prev_sign = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 32, 32) node fpiu_io_in_bits_req_in3_prev_prev_fractIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 22, 0) node fpiu_io_in_bits_req_in3_prev_prev_expIn = bits(fpiu_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = shl(fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53) node fpiu_io_in_bits_req_in3_prev_prev_fractOut = shr(_fpiu_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(fpiu_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(fpiu_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = eq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3) node _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node fpiu_io_in_bits_req_in3_prev_prev_expOut = mux(_fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5) node fpiu_io_in_bits_req_in3_prev_prev_hi = cat(fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut) node fpiu_io_in_bits_req_in3_floats_1 = cat(fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut) node _fpiu_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node fpiu_io_in_bits_req_in3_prev_isbox = andr(_fpiu_io_in_bits_req_in3_prev_isbox_T) node fpiu_io_in_bits_req_in3_oks_0 = and(fpiu_io_in_bits_req_in3_prev_isbox, fpiu_io_in_bits_req_in3_prev_prev_0_1) node fpiu_io_in_bits_req_in3_oks_1 = and(fpiu_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_1 = mux(_fpiu_io_in_bits_req_in3_T, fpiu_io_in_bits_req_in3_oks_1, fpiu_io_in_bits_req_in3_oks_0) node _fpiu_io_in_bits_req_in3_T_2 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in3_T_3 = mux(_fpiu_io_in_bits_req_in3_T_2, UInt<1>(0h1), _fpiu_io_in_bits_req_in3_T_1) node _fpiu_io_in_bits_req_in3_T_4 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in3_T_5 = mux(_fpiu_io_in_bits_req_in3_T_4, UInt<1>(0h1), _fpiu_io_in_bits_req_in3_T_3) node _fpiu_io_in_bits_req_in3_T_6 = eq(ex_ctrl.typeTagIn, UInt<1>(0h1)) node _fpiu_io_in_bits_req_in3_T_7 = mux(_fpiu_io_in_bits_req_in3_T_6, fpiu_io_in_bits_req_in3_floats_1, fpiu_io_in_bits_req_in3_floats_0) node _fpiu_io_in_bits_req_in3_T_8 = eq(ex_ctrl.typeTagIn, UInt<2>(0h2)) node _fpiu_io_in_bits_req_in3_T_9 = mux(_fpiu_io_in_bits_req_in3_T_8, ex_rs_2, _fpiu_io_in_bits_req_in3_T_7) node _fpiu_io_in_bits_req_in3_T_10 = eq(ex_ctrl.typeTagIn, UInt<2>(0h3)) node _fpiu_io_in_bits_req_in3_T_11 = mux(_fpiu_io_in_bits_req_in3_T_10, ex_rs_2, _fpiu_io_in_bits_req_in3_T_9) node _fpiu_io_in_bits_req_in3_T_12 = mux(_fpiu_io_in_bits_req_in3_T_5, _fpiu_io_in_bits_req_in3_T_11, UInt<65>(0he008000000000000)) connect fpiu_io_in_bits_req.in3, _fpiu_io_in_bits_req_in3_T_12 node _fpiu_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect fpiu_io_in_bits_req.typ, _fpiu_io_in_bits_req_typ_T node _fpiu_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect fpiu_io_in_bits_req.fmt, _fpiu_io_in_bits_req_fmt_T node _fpiu_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _fpiu_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _fpiu_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _fpiu_io_in_bits_req_fmaCmd_T_3 = and(_fpiu_io_in_bits_req_fmaCmd_T_1, _fpiu_io_in_bits_req_fmaCmd_T_2) node _fpiu_io_in_bits_req_fmaCmd_T_4 = or(_fpiu_io_in_bits_req_fmaCmd_T, _fpiu_io_in_bits_req_fmaCmd_T_3) connect fpiu_io_in_bits_req.fmaCmd, _fpiu_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect fpiu_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect fpiu_io_in_bits_req.in1, io.cp_req.bits.in2 connect fpiu_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect fpiu_io_in_bits_req.in2, io.cp_req.bits.in3 connect fpiu_io_in_bits_req.in3, io.cp_req.bits.in2 connect fpiu.io.in.bits.in3, fpiu_io_in_bits_req.in3 connect fpiu.io.in.bits.in2, fpiu_io_in_bits_req.in2 connect fpiu.io.in.bits.in1, fpiu_io_in_bits_req.in1 connect fpiu.io.in.bits.fmt, fpiu_io_in_bits_req.fmt connect fpiu.io.in.bits.typ, fpiu_io_in_bits_req.typ connect fpiu.io.in.bits.fmaCmd, fpiu_io_in_bits_req.fmaCmd connect fpiu.io.in.bits.rm, fpiu_io_in_bits_req.rm connect fpiu.io.in.bits.vec, fpiu_io_in_bits_req.vec connect fpiu.io.in.bits.wflags, fpiu_io_in_bits_req.wflags connect fpiu.io.in.bits.sqrt, fpiu_io_in_bits_req.sqrt connect fpiu.io.in.bits.div, fpiu_io_in_bits_req.div connect fpiu.io.in.bits.fma, fpiu_io_in_bits_req.fma connect fpiu.io.in.bits.fastpipe, fpiu_io_in_bits_req.fastpipe connect fpiu.io.in.bits.toint, fpiu_io_in_bits_req.toint connect fpiu.io.in.bits.fromint, fpiu_io_in_bits_req.fromint connect fpiu.io.in.bits.typeTagOut, fpiu_io_in_bits_req.typeTagOut connect fpiu.io.in.bits.typeTagIn, fpiu_io_in_bits_req.typeTagIn connect fpiu.io.in.bits.swap23, fpiu_io_in_bits_req.swap23 connect fpiu.io.in.bits.swap12, fpiu_io_in_bits_req.swap12 connect fpiu.io.in.bits.ren3, fpiu_io_in_bits_req.ren3 connect fpiu.io.in.bits.ren2, fpiu_io_in_bits_req.ren2 connect fpiu.io.in.bits.ren1, fpiu_io_in_bits_req.ren1 connect fpiu.io.in.bits.wen, fpiu_io_in_bits_req.wen connect fpiu.io.in.bits.ldst, fpiu_io_in_bits_req.ldst connect io.store_data, fpiu.io.out.bits.store connect io.toint_data, fpiu.io.out.bits.toint node _T_8 = and(fpiu.io.out.valid, mem_cp_valid) node _T_9 = and(_T_8, mem_ctrl.toint) when _T_9 : connect io.cp_resp.bits.data, fpiu.io.out.bits.toint connect io.cp_resp.valid, UInt<1>(0h1) inst ifpu of IntToFP_4 connect ifpu.clock, clock connect ifpu.reset, reset node _ifpu_io_in_valid_T = and(req_valid, ex_ctrl.fromint) connect ifpu.io.in.valid, _ifpu_io_in_valid_T connect ifpu.io.in.bits.in1, fpiu.io.in.bits.in1 connect ifpu.io.in.bits.typ, fpiu.io.in.bits.typ connect ifpu.io.in.bits.rm, fpiu.io.in.bits.rm connect ifpu.io.in.bits.vec, fpiu.io.in.bits.vec connect ifpu.io.in.bits.wflags, fpiu.io.in.bits.wflags connect ifpu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt connect ifpu.io.in.bits.div, fpiu.io.in.bits.div connect ifpu.io.in.bits.fma, fpiu.io.in.bits.fma connect ifpu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe connect ifpu.io.in.bits.toint, fpiu.io.in.bits.toint connect ifpu.io.in.bits.fromint, fpiu.io.in.bits.fromint connect ifpu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut connect ifpu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn connect ifpu.io.in.bits.swap23, fpiu.io.in.bits.swap23 connect ifpu.io.in.bits.swap12, fpiu.io.in.bits.swap12 connect ifpu.io.in.bits.ren3, fpiu.io.in.bits.ren3 connect ifpu.io.in.bits.ren2, fpiu.io.in.bits.ren2 connect ifpu.io.in.bits.ren1, fpiu.io.in.bits.ren1 connect ifpu.io.in.bits.wen, fpiu.io.in.bits.wen connect ifpu.io.in.bits.ldst, fpiu.io.in.bits.ldst node _ifpu_io_in_bits_in1_T = mux(ex_cp_valid, io.cp_req.bits.in1, io.fromint_data) connect ifpu.io.in.bits.in1, _ifpu_io_in_bits_in1_T inst fpmu of FPToFP_4 connect fpmu.clock, clock connect fpmu.reset, reset node _fpmu_io_in_valid_T = and(req_valid, ex_ctrl.fastpipe) connect fpmu.io.in.valid, _fpmu_io_in_valid_T connect fpmu.io.in.bits.in3, fpiu.io.in.bits.in3 connect fpmu.io.in.bits.in2, fpiu.io.in.bits.in2 connect fpmu.io.in.bits.in1, fpiu.io.in.bits.in1 connect fpmu.io.in.bits.fmt, fpiu.io.in.bits.fmt connect fpmu.io.in.bits.typ, fpiu.io.in.bits.typ connect fpmu.io.in.bits.fmaCmd, fpiu.io.in.bits.fmaCmd connect fpmu.io.in.bits.rm, fpiu.io.in.bits.rm connect fpmu.io.in.bits.vec, fpiu.io.in.bits.vec connect fpmu.io.in.bits.wflags, fpiu.io.in.bits.wflags connect fpmu.io.in.bits.sqrt, fpiu.io.in.bits.sqrt connect fpmu.io.in.bits.div, fpiu.io.in.bits.div connect fpmu.io.in.bits.fma, fpiu.io.in.bits.fma connect fpmu.io.in.bits.fastpipe, fpiu.io.in.bits.fastpipe connect fpmu.io.in.bits.toint, fpiu.io.in.bits.toint connect fpmu.io.in.bits.fromint, fpiu.io.in.bits.fromint connect fpmu.io.in.bits.typeTagOut, fpiu.io.in.bits.typeTagOut connect fpmu.io.in.bits.typeTagIn, fpiu.io.in.bits.typeTagIn connect fpmu.io.in.bits.swap23, fpiu.io.in.bits.swap23 connect fpmu.io.in.bits.swap12, fpiu.io.in.bits.swap12 connect fpmu.io.in.bits.ren3, fpiu.io.in.bits.ren3 connect fpmu.io.in.bits.ren2, fpiu.io.in.bits.ren2 connect fpmu.io.in.bits.ren1, fpiu.io.in.bits.ren1 connect fpmu.io.in.bits.wen, fpiu.io.in.bits.wen connect fpmu.io.in.bits.ldst, fpiu.io.in.bits.ldst connect fpmu.io.lt, fpiu.io.out.bits.lt wire divSqrt_wen : UInt<1> connect divSqrt_wen, UInt<1>(0h0) wire divSqrt_inFlight : UInt<1> connect divSqrt_inFlight, UInt<1>(0h0) reg divSqrt_waddr : UInt<5>, clock reg divSqrt_cp : UInt<1>, clock wire divSqrt_typeTag : UInt<2> wire divSqrt_wdata : UInt<65> wire divSqrt_flags : UInt<5> invalidate divSqrt_typeTag invalidate divSqrt_wdata invalidate divSqrt_flags inst dfma of FPUFMAPipe_l4_f64_4 connect dfma.clock, clock connect dfma.reset, reset node _dfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) node _dfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<2>(0h2)) node _dfma_io_in_valid_T_2 = and(_dfma_io_in_valid_T, _dfma_io_in_valid_T_1) connect dfma.io.in.valid, _dfma_io_in_valid_T_2 wire dfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect dfma_io_in_bits_req.vec, ex_ctrl.vec connect dfma_io_in_bits_req.wflags, ex_ctrl.wflags connect dfma_io_in_bits_req.sqrt, ex_ctrl.sqrt connect dfma_io_in_bits_req.div, ex_ctrl.div connect dfma_io_in_bits_req.fma, ex_ctrl.fma connect dfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect dfma_io_in_bits_req.toint, ex_ctrl.toint connect dfma_io_in_bits_req.fromint, ex_ctrl.fromint connect dfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect dfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect dfma_io_in_bits_req.swap23, ex_ctrl.swap23 connect dfma_io_in_bits_req.swap12, ex_ctrl.swap12 connect dfma_io_in_bits_req.ren3, ex_ctrl.ren3 connect dfma_io_in_bits_req.ren2, ex_ctrl.ren2 connect dfma_io_in_bits_req.ren1, ex_ctrl.ren1 connect dfma_io_in_bits_req.wen, ex_ctrl.wen connect dfma_io_in_bits_req.ldst, ex_ctrl.ldst connect dfma_io_in_bits_req.rm, ex_rm node _dfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node dfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_0 = cat(dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in1_prev_prev_0_1 = and(dfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in1_prev_prev_sign = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in1_prev_prev_fractIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in1_prev_prev_expIn = bits(dfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in1_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in1_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in1_prev_prev_expOut_T, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in1_prev_prev_expOut = mux(_dfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in1_prev_prev_hi = cat(dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut) node dfma_io_in_bits_req_in1_floats_1 = cat(dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut) node _dfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node dfma_io_in_bits_req_in1_prev_isbox = andr(_dfma_io_in_bits_req_in1_prev_isbox_T) node dfma_io_in_bits_req_in1_oks_0 = and(dfma_io_in_bits_req_in1_prev_isbox, dfma_io_in_bits_req_in1_prev_prev_0_1) node dfma_io_in_bits_req_in1_oks_1 = and(dfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in1_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in1_T_1 = or(ex_rs_0, _dfma_io_in_bits_req_in1_T) connect dfma_io_in_bits_req.in1, _dfma_io_in_bits_req_in1_T_1 node _dfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node dfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_0 = cat(dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in2_prev_prev_0_1 = and(dfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in2_prev_prev_sign = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in2_prev_prev_fractIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in2_prev_prev_expIn = bits(dfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in2_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in2_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in2_prev_prev_expOut_T, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in2_prev_prev_expOut = mux(_dfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in2_prev_prev_hi = cat(dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut) node dfma_io_in_bits_req_in2_floats_1 = cat(dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut) node _dfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node dfma_io_in_bits_req_in2_prev_isbox = andr(_dfma_io_in_bits_req_in2_prev_isbox_T) node dfma_io_in_bits_req_in2_oks_0 = and(dfma_io_in_bits_req_in2_prev_isbox, dfma_io_in_bits_req_in2_prev_prev_0_1) node dfma_io_in_bits_req_in2_oks_1 = and(dfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in2_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in2_T_1 = or(ex_rs_1, _dfma_io_in_bits_req_in2_T) connect dfma_io_in_bits_req.in2, _dfma_io_in_bits_req_in2_T_1 node _dfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node dfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 14, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = cat(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 16, 16) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 9, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled, 15, 10) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T, 11) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, 5, 3) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1, UInt<6>(0h20)) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_0 = cat(dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 28) node dfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node dfma_io_in_bits_req_in3_prev_prev_0_1 = and(dfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node dfma_io_in_bits_req_in3_prev_prev_sign = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node dfma_io_in_bits_req_in3_prev_prev_fractIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node dfma_io_in_bits_req_in3_prev_prev_expIn = bits(dfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(dfma_io_in_bits_req_in3_prev_prev_fractIn, 53) node dfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_dfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(dfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(dfma_io_in_bits_req_in3_prev_prev_expIn, UInt<12>(0h800)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_dfma_io_in_bits_req_in3_prev_prev_expOut_T, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 8, 0) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 11, 0) node dfma_io_in_bits_req_in3_prev_prev_expOut = mux(_dfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node dfma_io_in_bits_req_in3_prev_prev_hi = cat(dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut) node dfma_io_in_bits_req_in3_floats_1 = cat(dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut) node _dfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node dfma_io_in_bits_req_in3_prev_isbox = andr(_dfma_io_in_bits_req_in3_prev_isbox_T) node dfma_io_in_bits_req_in3_oks_0 = and(dfma_io_in_bits_req_in3_prev_isbox, dfma_io_in_bits_req_in3_prev_prev_0_1) node dfma_io_in_bits_req_in3_oks_1 = and(dfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node _dfma_io_in_bits_req_in3_T = mux(UInt<1>(0h1), UInt<1>(0h0), UInt<65>(0he008000000000000)) node _dfma_io_in_bits_req_in3_T_1 = or(ex_rs_2, _dfma_io_in_bits_req_in3_T) connect dfma_io_in_bits_req.in3, _dfma_io_in_bits_req_in3_T_1 node _dfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect dfma_io_in_bits_req.typ, _dfma_io_in_bits_req_typ_T node _dfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect dfma_io_in_bits_req.fmt, _dfma_io_in_bits_req_fmt_T node _dfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _dfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _dfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _dfma_io_in_bits_req_fmaCmd_T_3 = and(_dfma_io_in_bits_req_fmaCmd_T_1, _dfma_io_in_bits_req_fmaCmd_T_2) node _dfma_io_in_bits_req_fmaCmd_T_4 = or(_dfma_io_in_bits_req_fmaCmd_T, _dfma_io_in_bits_req_fmaCmd_T_3) connect dfma_io_in_bits_req.fmaCmd, _dfma_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect dfma_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect dfma_io_in_bits_req.in1, io.cp_req.bits.in2 connect dfma_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect dfma_io_in_bits_req.in2, io.cp_req.bits.in3 connect dfma_io_in_bits_req.in3, io.cp_req.bits.in2 connect dfma.io.in.bits.in3, dfma_io_in_bits_req.in3 connect dfma.io.in.bits.in2, dfma_io_in_bits_req.in2 connect dfma.io.in.bits.in1, dfma_io_in_bits_req.in1 connect dfma.io.in.bits.fmt, dfma_io_in_bits_req.fmt connect dfma.io.in.bits.typ, dfma_io_in_bits_req.typ connect dfma.io.in.bits.fmaCmd, dfma_io_in_bits_req.fmaCmd connect dfma.io.in.bits.rm, dfma_io_in_bits_req.rm connect dfma.io.in.bits.vec, dfma_io_in_bits_req.vec connect dfma.io.in.bits.wflags, dfma_io_in_bits_req.wflags connect dfma.io.in.bits.sqrt, dfma_io_in_bits_req.sqrt connect dfma.io.in.bits.div, dfma_io_in_bits_req.div connect dfma.io.in.bits.fma, dfma_io_in_bits_req.fma connect dfma.io.in.bits.fastpipe, dfma_io_in_bits_req.fastpipe connect dfma.io.in.bits.toint, dfma_io_in_bits_req.toint connect dfma.io.in.bits.fromint, dfma_io_in_bits_req.fromint connect dfma.io.in.bits.typeTagOut, dfma_io_in_bits_req.typeTagOut connect dfma.io.in.bits.typeTagIn, dfma_io_in_bits_req.typeTagIn connect dfma.io.in.bits.swap23, dfma_io_in_bits_req.swap23 connect dfma.io.in.bits.swap12, dfma_io_in_bits_req.swap12 connect dfma.io.in.bits.ren3, dfma_io_in_bits_req.ren3 connect dfma.io.in.bits.ren2, dfma_io_in_bits_req.ren2 connect dfma.io.in.bits.ren1, dfma_io_in_bits_req.ren1 connect dfma.io.in.bits.wen, dfma_io_in_bits_req.wen connect dfma.io.in.bits.ldst, dfma_io_in_bits_req.ldst inst hfma of FPUFMAPipe_l3_f16_4 connect hfma.clock, clock connect hfma.reset, reset node _hfma_io_in_valid_T = and(req_valid, ex_ctrl.fma) node _hfma_io_in_valid_T_1 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) node _hfma_io_in_valid_T_2 = and(_hfma_io_in_valid_T, _hfma_io_in_valid_T_1) connect hfma.io.in.valid, _hfma_io_in_valid_T_2 wire hfma_io_in_bits_req : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} connect hfma_io_in_bits_req.vec, ex_ctrl.vec connect hfma_io_in_bits_req.wflags, ex_ctrl.wflags connect hfma_io_in_bits_req.sqrt, ex_ctrl.sqrt connect hfma_io_in_bits_req.div, ex_ctrl.div connect hfma_io_in_bits_req.fma, ex_ctrl.fma connect hfma_io_in_bits_req.fastpipe, ex_ctrl.fastpipe connect hfma_io_in_bits_req.toint, ex_ctrl.toint connect hfma_io_in_bits_req.fromint, ex_ctrl.fromint connect hfma_io_in_bits_req.typeTagOut, ex_ctrl.typeTagOut connect hfma_io_in_bits_req.typeTagIn, ex_ctrl.typeTagIn connect hfma_io_in_bits_req.swap23, ex_ctrl.swap23 connect hfma_io_in_bits_req.swap12, ex_ctrl.swap12 connect hfma_io_in_bits_req.ren3, ex_ctrl.ren3 connect hfma_io_in_bits_req.ren2, ex_ctrl.ren2 connect hfma_io_in_bits_req.ren1, ex_ctrl.ren1 connect hfma_io_in_bits_req.wen, ex_ctrl.wen connect hfma_io_in_bits_req.ldst, ex_ctrl.ldst connect hfma_io_in_bits_req.rm, ex_rm node _hfma_io_in_bits_req_in1_prev_unswizzled_T = bits(ex_rs_0, 31, 31) node _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = bits(ex_rs_0, 52, 52) node _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = bits(ex_rs_0, 30, 0) node hfma_io_in_bits_req_in1_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1) node hfma_io_in_bits_req_in1_prev_unswizzled = cat(hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in1_floats_0 = cat(hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in1_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in1_prev_prev_0_1 = and(hfma_io_in_bits_req_in1_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in1_prev_prev_sign = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in1_prev_prev_fractIn = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in1_prev_prev_expIn = bits(hfma_io_in_bits_req_in1_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in1_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in1_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in1_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in1_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in1_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in1_prev_prev_expOut_T, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in1_prev_prev_expOut = mux(_hfma_io_in_bits_req_in1_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in1_prev_prev_hi = cat(hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut) node hfma_io_in_bits_req_in1_floats_1 = cat(hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut) node _hfma_io_in_bits_req_in1_prev_isbox_T = bits(ex_rs_0, 64, 60) node hfma_io_in_bits_req_in1_prev_isbox = andr(_hfma_io_in_bits_req_in1_prev_isbox_T) node hfma_io_in_bits_req_in1_oks_0 = and(hfma_io_in_bits_req_in1_prev_isbox, hfma_io_in_bits_req_in1_prev_prev_0_1) node hfma_io_in_bits_req_in1_oks_1 = and(hfma_io_in_bits_req_in1_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in1_sign = bits(ex_rs_0, 64, 64) node hfma_io_in_bits_req_in1_fractIn = bits(ex_rs_0, 51, 0) node hfma_io_in_bits_req_in1_expIn = bits(ex_rs_0, 63, 52) node _hfma_io_in_bits_req_in1_fractOut_T = shl(hfma_io_in_bits_req_in1_fractIn, 11) node hfma_io_in_bits_req_in1_fractOut = shr(_hfma_io_in_bits_req_in1_fractOut_T, 53) node hfma_io_in_bits_req_in1_expOut_expCode = bits(hfma_io_in_bits_req_in1_expIn, 11, 9) node _hfma_io_in_bits_req_in1_expOut_commonCase_T = add(hfma_io_in_bits_req_in1_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in1_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in1_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in1_expOut_commonCase = tail(_hfma_io_in_bits_req_in1_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in1_expOut_T = eq(hfma_io_in_bits_req_in1_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in1_expOut_T_1 = geq(hfma_io_in_bits_req_in1_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in1_expOut_T_2 = or(_hfma_io_in_bits_req_in1_expOut_T, _hfma_io_in_bits_req_in1_expOut_T_1) node _hfma_io_in_bits_req_in1_expOut_T_3 = bits(hfma_io_in_bits_req_in1_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in1_expOut_T_4 = cat(hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3) node _hfma_io_in_bits_req_in1_expOut_T_5 = bits(hfma_io_in_bits_req_in1_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in1_expOut = mux(_hfma_io_in_bits_req_in1_expOut_T_2, _hfma_io_in_bits_req_in1_expOut_T_4, _hfma_io_in_bits_req_in1_expOut_T_5) node hfma_io_in_bits_req_in1_hi = cat(hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut) node hfma_io_in_bits_req_in1_floats_2 = cat(hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut) node _hfma_io_in_bits_req_in1_T = mux(hfma_io_in_bits_req_in1_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in1_T_1 = or(hfma_io_in_bits_req_in1_floats_0, _hfma_io_in_bits_req_in1_T) connect hfma_io_in_bits_req.in1, _hfma_io_in_bits_req_in1_T_1 node _hfma_io_in_bits_req_in2_prev_unswizzled_T = bits(ex_rs_1, 31, 31) node _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = bits(ex_rs_1, 52, 52) node _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = bits(ex_rs_1, 30, 0) node hfma_io_in_bits_req_in2_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1) node hfma_io_in_bits_req_in2_prev_unswizzled = cat(hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in2_floats_0 = cat(hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in2_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in2_prev_prev_0_1 = and(hfma_io_in_bits_req_in2_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in2_prev_prev_sign = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in2_prev_prev_fractIn = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in2_prev_prev_expIn = bits(hfma_io_in_bits_req_in2_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in2_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in2_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in2_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in2_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in2_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in2_prev_prev_expOut_T, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in2_prev_prev_expOut = mux(_hfma_io_in_bits_req_in2_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in2_prev_prev_hi = cat(hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut) node hfma_io_in_bits_req_in2_floats_1 = cat(hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut) node _hfma_io_in_bits_req_in2_prev_isbox_T = bits(ex_rs_1, 64, 60) node hfma_io_in_bits_req_in2_prev_isbox = andr(_hfma_io_in_bits_req_in2_prev_isbox_T) node hfma_io_in_bits_req_in2_oks_0 = and(hfma_io_in_bits_req_in2_prev_isbox, hfma_io_in_bits_req_in2_prev_prev_0_1) node hfma_io_in_bits_req_in2_oks_1 = and(hfma_io_in_bits_req_in2_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in2_sign = bits(ex_rs_1, 64, 64) node hfma_io_in_bits_req_in2_fractIn = bits(ex_rs_1, 51, 0) node hfma_io_in_bits_req_in2_expIn = bits(ex_rs_1, 63, 52) node _hfma_io_in_bits_req_in2_fractOut_T = shl(hfma_io_in_bits_req_in2_fractIn, 11) node hfma_io_in_bits_req_in2_fractOut = shr(_hfma_io_in_bits_req_in2_fractOut_T, 53) node hfma_io_in_bits_req_in2_expOut_expCode = bits(hfma_io_in_bits_req_in2_expIn, 11, 9) node _hfma_io_in_bits_req_in2_expOut_commonCase_T = add(hfma_io_in_bits_req_in2_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in2_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in2_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in2_expOut_commonCase = tail(_hfma_io_in_bits_req_in2_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in2_expOut_T = eq(hfma_io_in_bits_req_in2_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in2_expOut_T_1 = geq(hfma_io_in_bits_req_in2_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in2_expOut_T_2 = or(_hfma_io_in_bits_req_in2_expOut_T, _hfma_io_in_bits_req_in2_expOut_T_1) node _hfma_io_in_bits_req_in2_expOut_T_3 = bits(hfma_io_in_bits_req_in2_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in2_expOut_T_4 = cat(hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3) node _hfma_io_in_bits_req_in2_expOut_T_5 = bits(hfma_io_in_bits_req_in2_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in2_expOut = mux(_hfma_io_in_bits_req_in2_expOut_T_2, _hfma_io_in_bits_req_in2_expOut_T_4, _hfma_io_in_bits_req_in2_expOut_T_5) node hfma_io_in_bits_req_in2_hi = cat(hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut) node hfma_io_in_bits_req_in2_floats_2 = cat(hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut) node _hfma_io_in_bits_req_in2_T = mux(hfma_io_in_bits_req_in2_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in2_T_1 = or(hfma_io_in_bits_req_in2_floats_0, _hfma_io_in_bits_req_in2_T) connect hfma_io_in_bits_req.in2, _hfma_io_in_bits_req_in2_T_1 node _hfma_io_in_bits_req_in3_prev_unswizzled_T = bits(ex_rs_2, 31, 31) node _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = bits(ex_rs_2, 52, 52) node _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = bits(ex_rs_2, 30, 0) node hfma_io_in_bits_req_in3_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1) node hfma_io_in_bits_req_in3_prev_unswizzled = cat(hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 15, 15) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 23, 23) node _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 14, 0) node hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = cat(_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1) node hfma_io_in_bits_req_in3_floats_0 = cat(hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2) node _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 32, 28) node hfma_io_in_bits_req_in3_prev_prev_prev_isbox = andr(_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T) node hfma_io_in_bits_req_in3_prev_prev_0_1 = and(hfma_io_in_bits_req_in3_prev_prev_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in3_prev_prev_sign = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 32, 32) node hfma_io_in_bits_req_in3_prev_prev_fractIn = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 22, 0) node hfma_io_in_bits_req_in3_prev_prev_expIn = bits(hfma_io_in_bits_req_in3_prev_unswizzled, 31, 23) node _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = shl(hfma_io_in_bits_req_in3_prev_prev_fractIn, 11) node hfma_io_in_bits_req_in3_prev_prev_fractOut = shr(_hfma_io_in_bits_req_in3_prev_prev_fractOut_T, 24) node hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = bits(hfma_io_in_bits_req_in3_prev_prev_expIn, 8, 6) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = add(hfma_io_in_bits_req_in3_prev_prev_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1, UInt<9>(0h100)) node hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = tail(_hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T = eq(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = geq(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = or(_hfma_io_in_bits_req_in3_prev_prev_expOut_T, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = bits(hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = cat(hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3) node _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = bits(hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in3_prev_prev_expOut = mux(_hfma_io_in_bits_req_in3_prev_prev_expOut_T_2, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5) node hfma_io_in_bits_req_in3_prev_prev_hi = cat(hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut) node hfma_io_in_bits_req_in3_floats_1 = cat(hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut) node _hfma_io_in_bits_req_in3_prev_isbox_T = bits(ex_rs_2, 64, 60) node hfma_io_in_bits_req_in3_prev_isbox = andr(_hfma_io_in_bits_req_in3_prev_isbox_T) node hfma_io_in_bits_req_in3_oks_0 = and(hfma_io_in_bits_req_in3_prev_isbox, hfma_io_in_bits_req_in3_prev_prev_0_1) node hfma_io_in_bits_req_in3_oks_1 = and(hfma_io_in_bits_req_in3_prev_isbox, UInt<1>(0h1)) node hfma_io_in_bits_req_in3_sign = bits(ex_rs_2, 64, 64) node hfma_io_in_bits_req_in3_fractIn = bits(ex_rs_2, 51, 0) node hfma_io_in_bits_req_in3_expIn = bits(ex_rs_2, 63, 52) node _hfma_io_in_bits_req_in3_fractOut_T = shl(hfma_io_in_bits_req_in3_fractIn, 11) node hfma_io_in_bits_req_in3_fractOut = shr(_hfma_io_in_bits_req_in3_fractOut_T, 53) node hfma_io_in_bits_req_in3_expOut_expCode = bits(hfma_io_in_bits_req_in3_expIn, 11, 9) node _hfma_io_in_bits_req_in3_expOut_commonCase_T = add(hfma_io_in_bits_req_in3_expIn, UInt<6>(0h20)) node _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = tail(_hfma_io_in_bits_req_in3_expOut_commonCase_T, 1) node _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = sub(_hfma_io_in_bits_req_in3_expOut_commonCase_T_1, UInt<12>(0h800)) node hfma_io_in_bits_req_in3_expOut_commonCase = tail(_hfma_io_in_bits_req_in3_expOut_commonCase_T_2, 1) node _hfma_io_in_bits_req_in3_expOut_T = eq(hfma_io_in_bits_req_in3_expOut_expCode, UInt<1>(0h0)) node _hfma_io_in_bits_req_in3_expOut_T_1 = geq(hfma_io_in_bits_req_in3_expOut_expCode, UInt<3>(0h6)) node _hfma_io_in_bits_req_in3_expOut_T_2 = or(_hfma_io_in_bits_req_in3_expOut_T, _hfma_io_in_bits_req_in3_expOut_T_1) node _hfma_io_in_bits_req_in3_expOut_T_3 = bits(hfma_io_in_bits_req_in3_expOut_commonCase, 2, 0) node _hfma_io_in_bits_req_in3_expOut_T_4 = cat(hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3) node _hfma_io_in_bits_req_in3_expOut_T_5 = bits(hfma_io_in_bits_req_in3_expOut_commonCase, 5, 0) node hfma_io_in_bits_req_in3_expOut = mux(_hfma_io_in_bits_req_in3_expOut_T_2, _hfma_io_in_bits_req_in3_expOut_T_4, _hfma_io_in_bits_req_in3_expOut_T_5) node hfma_io_in_bits_req_in3_hi = cat(hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut) node hfma_io_in_bits_req_in3_floats_2 = cat(hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut) node _hfma_io_in_bits_req_in3_T = mux(hfma_io_in_bits_req_in3_oks_0, UInt<1>(0h0), UInt<17>(0he200)) node _hfma_io_in_bits_req_in3_T_1 = or(hfma_io_in_bits_req_in3_floats_0, _hfma_io_in_bits_req_in3_T) connect hfma_io_in_bits_req.in3, _hfma_io_in_bits_req_in3_T_1 node _hfma_io_in_bits_req_typ_T = bits(ex_reg_inst, 21, 20) connect hfma_io_in_bits_req.typ, _hfma_io_in_bits_req_typ_T node _hfma_io_in_bits_req_fmt_T = bits(ex_reg_inst, 26, 25) connect hfma_io_in_bits_req.fmt, _hfma_io_in_bits_req_fmt_T node _hfma_io_in_bits_req_fmaCmd_T = bits(ex_reg_inst, 3, 2) node _hfma_io_in_bits_req_fmaCmd_T_1 = eq(ex_ctrl.ren3, UInt<1>(0h0)) node _hfma_io_in_bits_req_fmaCmd_T_2 = bits(ex_reg_inst, 27, 27) node _hfma_io_in_bits_req_fmaCmd_T_3 = and(_hfma_io_in_bits_req_fmaCmd_T_1, _hfma_io_in_bits_req_fmaCmd_T_2) node _hfma_io_in_bits_req_fmaCmd_T_4 = or(_hfma_io_in_bits_req_fmaCmd_T, _hfma_io_in_bits_req_fmaCmd_T_3) connect hfma_io_in_bits_req.fmaCmd, _hfma_io_in_bits_req_fmaCmd_T_4 when ex_cp_valid : connect hfma_io_in_bits_req, io.cp_req.bits when io.cp_req.bits.swap12 : connect hfma_io_in_bits_req.in1, io.cp_req.bits.in2 connect hfma_io_in_bits_req.in2, io.cp_req.bits.in1 when io.cp_req.bits.swap23 : connect hfma_io_in_bits_req.in2, io.cp_req.bits.in3 connect hfma_io_in_bits_req.in3, io.cp_req.bits.in2 connect hfma.io.in.bits.in3, hfma_io_in_bits_req.in3 connect hfma.io.in.bits.in2, hfma_io_in_bits_req.in2 connect hfma.io.in.bits.in1, hfma_io_in_bits_req.in1 connect hfma.io.in.bits.fmt, hfma_io_in_bits_req.fmt connect hfma.io.in.bits.typ, hfma_io_in_bits_req.typ connect hfma.io.in.bits.fmaCmd, hfma_io_in_bits_req.fmaCmd connect hfma.io.in.bits.rm, hfma_io_in_bits_req.rm connect hfma.io.in.bits.vec, hfma_io_in_bits_req.vec connect hfma.io.in.bits.wflags, hfma_io_in_bits_req.wflags connect hfma.io.in.bits.sqrt, hfma_io_in_bits_req.sqrt connect hfma.io.in.bits.div, hfma_io_in_bits_req.div connect hfma.io.in.bits.fma, hfma_io_in_bits_req.fma connect hfma.io.in.bits.fastpipe, hfma_io_in_bits_req.fastpipe connect hfma.io.in.bits.toint, hfma_io_in_bits_req.toint connect hfma.io.in.bits.fromint, hfma_io_in_bits_req.fromint connect hfma.io.in.bits.typeTagOut, hfma_io_in_bits_req.typeTagOut connect hfma.io.in.bits.typeTagIn, hfma_io_in_bits_req.typeTagIn connect hfma.io.in.bits.swap23, hfma_io_in_bits_req.swap23 connect hfma.io.in.bits.swap12, hfma_io_in_bits_req.swap12 connect hfma.io.in.bits.ren3, hfma_io_in_bits_req.ren3 connect hfma.io.in.bits.ren2, hfma_io_in_bits_req.ren2 connect hfma.io.in.bits.ren1, hfma_io_in_bits_req.ren1 connect hfma.io.in.bits.wen, hfma_io_in_bits_req.wen connect hfma.io.in.bits.ldst, hfma_io_in_bits_req.ldst node _memLatencyMask_T = mux(mem_ctrl.fastpipe, UInt<1>(0h1), UInt<1>(0h0)) node _memLatencyMask_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _memLatencyMask_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _memLatencyMask_T_3 = and(mem_ctrl.fma, _memLatencyMask_T_2) node _memLatencyMask_T_4 = mux(_memLatencyMask_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _memLatencyMask_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _memLatencyMask_T_6 = and(mem_ctrl.fma, _memLatencyMask_T_5) node _memLatencyMask_T_7 = mux(_memLatencyMask_T_6, UInt<3>(0h4), UInt<1>(0h0)) node _memLatencyMask_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _memLatencyMask_T_9 = and(mem_ctrl.fma, _memLatencyMask_T_8) node _memLatencyMask_T_10 = mux(_memLatencyMask_T_9, UInt<2>(0h2), UInt<1>(0h0)) node _memLatencyMask_T_11 = or(_memLatencyMask_T, _memLatencyMask_T_1) node _memLatencyMask_T_12 = or(_memLatencyMask_T_11, _memLatencyMask_T_4) node _memLatencyMask_T_13 = or(_memLatencyMask_T_12, _memLatencyMask_T_7) node memLatencyMask = or(_memLatencyMask_T_13, _memLatencyMask_T_10) regreset wen : UInt<3>, clock, reset, UInt<3>(0h0) reg wbInfo : { rd : UInt<5>, typeTag : UInt<2>, cp : UInt<1>, pipeid : UInt<3>}[3], clock node _mem_wen_T = or(mem_ctrl.fma, mem_ctrl.fastpipe) node _mem_wen_T_1 = or(_mem_wen_T, mem_ctrl.fromint) node mem_wen = and(mem_reg_valid, _mem_wen_T_1) node _write_port_busy_T = mux(ex_ctrl.fastpipe, UInt<2>(0h2), UInt<1>(0h0)) node _write_port_busy_T_1 = mux(ex_ctrl.fromint, UInt<2>(0h2), UInt<1>(0h0)) node _write_port_busy_T_2 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) node _write_port_busy_T_3 = and(ex_ctrl.fma, _write_port_busy_T_2) node _write_port_busy_T_4 = mux(_write_port_busy_T_3, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_5 = eq(ex_ctrl.typeTagOut, UInt<2>(0h2)) node _write_port_busy_T_6 = and(ex_ctrl.fma, _write_port_busy_T_5) node _write_port_busy_T_7 = mux(_write_port_busy_T_6, UInt<4>(0h8), UInt<1>(0h0)) node _write_port_busy_T_8 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) node _write_port_busy_T_9 = and(ex_ctrl.fma, _write_port_busy_T_8) node _write_port_busy_T_10 = mux(_write_port_busy_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_11 = or(_write_port_busy_T, _write_port_busy_T_1) node _write_port_busy_T_12 = or(_write_port_busy_T_11, _write_port_busy_T_4) node _write_port_busy_T_13 = or(_write_port_busy_T_12, _write_port_busy_T_7) node _write_port_busy_T_14 = or(_write_port_busy_T_13, _write_port_busy_T_10) node _write_port_busy_T_15 = and(memLatencyMask, _write_port_busy_T_14) node _write_port_busy_T_16 = orr(_write_port_busy_T_15) node _write_port_busy_T_17 = and(mem_wen, _write_port_busy_T_16) node _write_port_busy_T_18 = mux(ex_ctrl.fastpipe, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_19 = mux(ex_ctrl.fromint, UInt<3>(0h4), UInt<1>(0h0)) node _write_port_busy_T_20 = eq(ex_ctrl.typeTagOut, UInt<1>(0h1)) node _write_port_busy_T_21 = and(ex_ctrl.fma, _write_port_busy_T_20) node _write_port_busy_T_22 = mux(_write_port_busy_T_21, UInt<4>(0h8), UInt<1>(0h0)) node _write_port_busy_T_23 = eq(ex_ctrl.typeTagOut, UInt<2>(0h2)) node _write_port_busy_T_24 = and(ex_ctrl.fma, _write_port_busy_T_23) node _write_port_busy_T_25 = mux(_write_port_busy_T_24, UInt<5>(0h10), UInt<1>(0h0)) node _write_port_busy_T_26 = eq(ex_ctrl.typeTagOut, UInt<1>(0h0)) node _write_port_busy_T_27 = and(ex_ctrl.fma, _write_port_busy_T_26) node _write_port_busy_T_28 = mux(_write_port_busy_T_27, UInt<4>(0h8), UInt<1>(0h0)) node _write_port_busy_T_29 = or(_write_port_busy_T_18, _write_port_busy_T_19) node _write_port_busy_T_30 = or(_write_port_busy_T_29, _write_port_busy_T_22) node _write_port_busy_T_31 = or(_write_port_busy_T_30, _write_port_busy_T_25) node _write_port_busy_T_32 = or(_write_port_busy_T_31, _write_port_busy_T_28) node _write_port_busy_T_33 = and(wen, _write_port_busy_T_32) node _write_port_busy_T_34 = orr(_write_port_busy_T_33) node _write_port_busy_T_35 = or(_write_port_busy_T_17, _write_port_busy_T_34) reg write_port_busy : UInt<1>, clock when req_valid : connect write_port_busy, _write_port_busy_T_35 node _T_10 = and(mem_reg_valid, write_port_busy) node _T_11 = bits(wen, 1, 1) when _T_11 : connect wbInfo[0], wbInfo[1] node _T_12 = bits(wen, 2, 2) when _T_12 : connect wbInfo[1], wbInfo[2] node _wen_T = shr(wen, 1) connect wen, _wen_T when mem_wen : node _T_13 = eq(killm, UInt<1>(0h0)) when _T_13 : node _wen_T_1 = shr(wen, 1) node _wen_T_2 = or(_wen_T_1, memLatencyMask) connect wen, _wen_T_2 node _T_14 = eq(write_port_busy, UInt<1>(0h0)) node _T_15 = bits(memLatencyMask, 0, 0) node _T_16 = and(_T_14, _T_15) when _T_16 : connect wbInfo[0].cp, mem_cp_valid connect wbInfo[0].typeTag, mem_ctrl.typeTagOut node _wbInfo_0_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _wbInfo_0_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_2) node _wbInfo_0_pipeid_T_4 = mux(_wbInfo_0_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _wbInfo_0_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_5) node _wbInfo_0_pipeid_T_7 = mux(_wbInfo_0_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _wbInfo_0_pipeid_T_9 = and(mem_ctrl.fma, _wbInfo_0_pipeid_T_8) node _wbInfo_0_pipeid_T_10 = mux(_wbInfo_0_pipeid_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _wbInfo_0_pipeid_T_11 = or(_wbInfo_0_pipeid_T, _wbInfo_0_pipeid_T_1) node _wbInfo_0_pipeid_T_12 = or(_wbInfo_0_pipeid_T_11, _wbInfo_0_pipeid_T_4) node _wbInfo_0_pipeid_T_13 = or(_wbInfo_0_pipeid_T_12, _wbInfo_0_pipeid_T_7) node _wbInfo_0_pipeid_T_14 = or(_wbInfo_0_pipeid_T_13, _wbInfo_0_pipeid_T_10) connect wbInfo[0].pipeid, _wbInfo_0_pipeid_T_14 node _wbInfo_0_rd_T = bits(mem_reg_inst, 11, 7) connect wbInfo[0].rd, _wbInfo_0_rd_T node _T_17 = eq(write_port_busy, UInt<1>(0h0)) node _T_18 = bits(memLatencyMask, 1, 1) node _T_19 = and(_T_17, _T_18) when _T_19 : connect wbInfo[1].cp, mem_cp_valid connect wbInfo[1].typeTag, mem_ctrl.typeTagOut node _wbInfo_1_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _wbInfo_1_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_2) node _wbInfo_1_pipeid_T_4 = mux(_wbInfo_1_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _wbInfo_1_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_5) node _wbInfo_1_pipeid_T_7 = mux(_wbInfo_1_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _wbInfo_1_pipeid_T_9 = and(mem_ctrl.fma, _wbInfo_1_pipeid_T_8) node _wbInfo_1_pipeid_T_10 = mux(_wbInfo_1_pipeid_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _wbInfo_1_pipeid_T_11 = or(_wbInfo_1_pipeid_T, _wbInfo_1_pipeid_T_1) node _wbInfo_1_pipeid_T_12 = or(_wbInfo_1_pipeid_T_11, _wbInfo_1_pipeid_T_4) node _wbInfo_1_pipeid_T_13 = or(_wbInfo_1_pipeid_T_12, _wbInfo_1_pipeid_T_7) node _wbInfo_1_pipeid_T_14 = or(_wbInfo_1_pipeid_T_13, _wbInfo_1_pipeid_T_10) connect wbInfo[1].pipeid, _wbInfo_1_pipeid_T_14 node _wbInfo_1_rd_T = bits(mem_reg_inst, 11, 7) connect wbInfo[1].rd, _wbInfo_1_rd_T node _T_20 = eq(write_port_busy, UInt<1>(0h0)) node _T_21 = bits(memLatencyMask, 2, 2) node _T_22 = and(_T_20, _T_21) when _T_22 : connect wbInfo[2].cp, mem_cp_valid connect wbInfo[2].typeTag, mem_ctrl.typeTagOut node _wbInfo_2_pipeid_T = mux(mem_ctrl.fastpipe, UInt<1>(0h0), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_1 = mux(mem_ctrl.fromint, UInt<1>(0h1), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _wbInfo_2_pipeid_T_3 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_2) node _wbInfo_2_pipeid_T_4 = mux(_wbInfo_2_pipeid_T_3, UInt<2>(0h2), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_5 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _wbInfo_2_pipeid_T_6 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_5) node _wbInfo_2_pipeid_T_7 = mux(_wbInfo_2_pipeid_T_6, UInt<2>(0h3), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_8 = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _wbInfo_2_pipeid_T_9 = and(mem_ctrl.fma, _wbInfo_2_pipeid_T_8) node _wbInfo_2_pipeid_T_10 = mux(_wbInfo_2_pipeid_T_9, UInt<3>(0h4), UInt<1>(0h0)) node _wbInfo_2_pipeid_T_11 = or(_wbInfo_2_pipeid_T, _wbInfo_2_pipeid_T_1) node _wbInfo_2_pipeid_T_12 = or(_wbInfo_2_pipeid_T_11, _wbInfo_2_pipeid_T_4) node _wbInfo_2_pipeid_T_13 = or(_wbInfo_2_pipeid_T_12, _wbInfo_2_pipeid_T_7) node _wbInfo_2_pipeid_T_14 = or(_wbInfo_2_pipeid_T_13, _wbInfo_2_pipeid_T_10) connect wbInfo[2].pipeid, _wbInfo_2_pipeid_T_14 node _wbInfo_2_rd_T = bits(mem_reg_inst, 11, 7) connect wbInfo[2].rd, _wbInfo_2_rd_T node waddr = mux(divSqrt_wen, divSqrt_waddr, wbInfo[0].rd) node wb_cp = mux(divSqrt_wen, divSqrt_cp, wbInfo[0].cp) node wtypeTag = mux(divSqrt_wen, divSqrt_typeTag, wbInfo[0].typeTag) node _wdata_T_39 = eq(wbInfo[0].pipeid, UInt<1>(0h1)) node _wdata_T_40 = mux(_wdata_T_39, ifpu.io.out.bits.data, fpmu.io.out.bits.data) node _wdata_T_41 = eq(wbInfo[0].pipeid, UInt<2>(0h2)) node _wdata_T_42 = mux(_wdata_T_41, sfma.io.out.bits.data, _wdata_T_40) node _wdata_T_43 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) node _wdata_T_44 = mux(_wdata_T_43, dfma.io.out.bits.data, _wdata_T_42) node _wdata_T_45 = eq(wbInfo[0].pipeid, UInt<3>(0h4)) node _wdata_T_46 = mux(_wdata_T_45, hfma.io.out.bits.data, _wdata_T_44) node _wdata_T_47 = eq(wbInfo[0].pipeid, UInt<3>(0h5)) node _wdata_T_48 = mux(_wdata_T_47, hfma.io.out.bits.data, _wdata_T_46) node _wdata_T_49 = eq(wbInfo[0].pipeid, UInt<3>(0h6)) node _wdata_T_50 = mux(_wdata_T_49, hfma.io.out.bits.data, _wdata_T_48) node _wdata_T_51 = eq(wbInfo[0].pipeid, UInt<3>(0h7)) node _wdata_T_52 = mux(_wdata_T_51, hfma.io.out.bits.data, _wdata_T_50) node _wdata_T_53 = mux(divSqrt_wen, divSqrt_wdata, _wdata_T_52) node _wdata_opts_bigger_swizzledNaN_T = andr(UInt<7>(0h7f)) node _wdata_opts_bigger_swizzledNaN_T_1 = bits(_wdata_T_53, 15, 15) node _wdata_opts_bigger_swizzledNaN_T_2 = bits(_wdata_T_53, 16, 16) node _wdata_opts_bigger_swizzledNaN_T_3 = bits(_wdata_T_53, 14, 0) node wdata_opts_bigger_swizzledNaN_lo_hi = cat(UInt<7>(0h7f), _wdata_opts_bigger_swizzledNaN_T_2) node wdata_opts_bigger_swizzledNaN_lo = cat(wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3) node wdata_opts_bigger_swizzledNaN_hi_lo = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T_1) node wdata_opts_bigger_swizzledNaN_hi_hi = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T) node wdata_opts_bigger_swizzledNaN_hi = cat(wdata_opts_bigger_swizzledNaN_hi_hi, wdata_opts_bigger_swizzledNaN_hi_lo) node wdata_opts_bigger_swizzledNaN = cat(wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo) node _wdata_opts_bigger_T = andr(UInt<3>(0h7)) node wdata_opts_bigger = mux(_wdata_opts_bigger_T, wdata_opts_bigger_swizzledNaN, UInt<33>(0h1ffffffff)) node wdata_opts_0 = or(wdata_opts_bigger, UInt<65>(0h1fffffffe00000000)) node _wdata_opts_bigger_swizzledNaN_T_4 = andr(UInt<20>(0hfffff)) node _wdata_opts_bigger_swizzledNaN_T_5 = bits(_wdata_T_53, 31, 31) node _wdata_opts_bigger_swizzledNaN_T_6 = bits(_wdata_T_53, 32, 32) node _wdata_opts_bigger_swizzledNaN_T_7 = bits(_wdata_T_53, 30, 0) node wdata_opts_bigger_swizzledNaN_lo_hi_1 = cat(UInt<20>(0hfffff), _wdata_opts_bigger_swizzledNaN_T_6) node wdata_opts_bigger_swizzledNaN_lo_1 = cat(wdata_opts_bigger_swizzledNaN_lo_hi_1, _wdata_opts_bigger_swizzledNaN_T_7) node wdata_opts_bigger_swizzledNaN_hi_lo_1 = cat(UInt<7>(0h7f), _wdata_opts_bigger_swizzledNaN_T_5) node wdata_opts_bigger_swizzledNaN_hi_hi_1 = cat(UInt<4>(0hf), _wdata_opts_bigger_swizzledNaN_T_4) node wdata_opts_bigger_swizzledNaN_hi_1 = cat(wdata_opts_bigger_swizzledNaN_hi_hi_1, wdata_opts_bigger_swizzledNaN_hi_lo_1) node wdata_opts_bigger_swizzledNaN_1 = cat(wdata_opts_bigger_swizzledNaN_hi_1, wdata_opts_bigger_swizzledNaN_lo_1) node _wdata_opts_bigger_T_1 = andr(UInt<3>(0h7)) node wdata_opts_bigger_1 = mux(_wdata_opts_bigger_T_1, wdata_opts_bigger_swizzledNaN_1, UInt<65>(0h1ffffffffffffffff)) node wdata_opts_1 = or(wdata_opts_bigger_1, UInt<1>(0h0)) node _wdata_T_54 = eq(wtypeTag, UInt<1>(0h1)) node _wdata_T_55 = mux(_wdata_T_54, wdata_opts_1, wdata_opts_0) node _wdata_T_56 = eq(wtypeTag, UInt<2>(0h2)) node _wdata_T_57 = mux(_wdata_T_56, _wdata_T_53, _wdata_T_55) node _wdata_T_58 = eq(wtypeTag, UInt<2>(0h3)) node wdata_1 = mux(_wdata_T_58, _wdata_T_53, _wdata_T_57) node _wexc_T = eq(wbInfo[0].pipeid, UInt<1>(0h1)) node _wexc_T_1 = mux(_wexc_T, ifpu.io.out.bits.exc, fpmu.io.out.bits.exc) node _wexc_T_2 = eq(wbInfo[0].pipeid, UInt<2>(0h2)) node _wexc_T_3 = mux(_wexc_T_2, sfma.io.out.bits.exc, _wexc_T_1) node _wexc_T_4 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) node _wexc_T_5 = mux(_wexc_T_4, dfma.io.out.bits.exc, _wexc_T_3) node _wexc_T_6 = eq(wbInfo[0].pipeid, UInt<3>(0h4)) node _wexc_T_7 = mux(_wexc_T_6, hfma.io.out.bits.exc, _wexc_T_5) node _wexc_T_8 = eq(wbInfo[0].pipeid, UInt<3>(0h5)) node _wexc_T_9 = mux(_wexc_T_8, hfma.io.out.bits.exc, _wexc_T_7) node _wexc_T_10 = eq(wbInfo[0].pipeid, UInt<3>(0h6)) node _wexc_T_11 = mux(_wexc_T_10, hfma.io.out.bits.exc, _wexc_T_9) node _wexc_T_12 = eq(wbInfo[0].pipeid, UInt<3>(0h7)) node wexc = mux(_wexc_T_12, hfma.io.out.bits.exc, _wexc_T_11) node _T_23 = eq(wbInfo[0].cp, UInt<1>(0h0)) node _T_24 = bits(wen, 0, 0) node _T_25 = and(_T_23, _T_24) node _T_26 = or(_T_25, divSqrt_wen) when _T_26 : node _unswizzled_T_3 = bits(wdata_1, 31, 31) node _unswizzled_T_4 = bits(wdata_1, 52, 52) node _unswizzled_T_5 = bits(wdata_1, 30, 0) node unswizzled_hi_1 = cat(_unswizzled_T_3, _unswizzled_T_4) node unswizzled_1 = cat(unswizzled_hi_1, _unswizzled_T_5) node _prevOK_T_4 = bits(wdata_1, 64, 60) node _prevOK_T_5 = andr(_prevOK_T_4) node _prevOK_T_6 = eq(_prevOK_T_5, UInt<1>(0h0)) node _prevOK_unswizzled_T_3 = bits(unswizzled_1, 15, 15) node _prevOK_unswizzled_T_4 = bits(unswizzled_1, 23, 23) node _prevOK_unswizzled_T_5 = bits(unswizzled_1, 14, 0) node prevOK_unswizzled_hi_1 = cat(_prevOK_unswizzled_T_3, _prevOK_unswizzled_T_4) node prevOK_unswizzled_1 = cat(prevOK_unswizzled_hi_1, _prevOK_unswizzled_T_5) node _prevOK_prevOK_T_3 = bits(unswizzled_1, 32, 28) node _prevOK_prevOK_T_4 = andr(_prevOK_prevOK_T_3) node _prevOK_prevOK_T_5 = eq(_prevOK_prevOK_T_4, UInt<1>(0h0)) node prevOK_prevOK_1 = or(_prevOK_prevOK_T_5, UInt<1>(0h1)) node _prevOK_curOK_T_7 = bits(unswizzled_1, 31, 29) node _prevOK_curOK_T_8 = andr(_prevOK_curOK_T_7) node _prevOK_curOK_T_9 = eq(_prevOK_curOK_T_8, UInt<1>(0h0)) node _prevOK_curOK_T_10 = bits(unswizzled_1, 28, 28) node _prevOK_curOK_T_11 = bits(unswizzled_1, 22, 16) node _prevOK_curOK_T_12 = andr(_prevOK_curOK_T_11) node _prevOK_curOK_T_13 = eq(_prevOK_curOK_T_10, _prevOK_curOK_T_12) node prevOK_curOK_1 = or(_prevOK_curOK_T_9, _prevOK_curOK_T_13) node _prevOK_T_7 = and(prevOK_prevOK_1, prevOK_curOK_1) node prevOK_1 = or(_prevOK_T_6, _prevOK_T_7) node _curOK_T_7 = bits(wdata_1, 63, 61) node _curOK_T_8 = andr(_curOK_T_7) node _curOK_T_9 = eq(_curOK_T_8, UInt<1>(0h0)) node _curOK_T_10 = bits(wdata_1, 60, 60) node _curOK_T_11 = bits(wdata_1, 51, 32) node _curOK_T_12 = andr(_curOK_T_11) node _curOK_T_13 = eq(_curOK_T_10, _curOK_T_12) node curOK_1 = or(_curOK_T_9, _curOK_T_13) node _T_27 = and(prevOK_1, curOK_1) node _T_28 = asUInt(reset) node _T_29 = eq(_T_28, UInt<1>(0h0)) when _T_29 : node _T_30 = eq(_T_27, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "Assertion failed\n at FPU.scala:969 assert(consistent(wdata))\n") : printf_1 assert(clock, _T_27, UInt<1>(0h1), "") : assert_1 infer mport MPORT_1 = regfile[waddr], clock connect MPORT_1, wdata_1 connect frfWriteBundle_1.wrdst, waddr connect frfWriteBundle_1.wrenf, UInt<1>(0h1) node frfWriteBundle_1_wrdata_unrecoded_rawIn_exp = bits(wdata_1, 63, 52) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 11, 9) node frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 11, 10) node frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_1_wrdata_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp, 9, 9) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_1_wrdata_unrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sign_T = bits(wdata_1, 64, 64) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sign_T node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_unrecoded_rawIn_exp) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_2 = bits(wdata_1, 51, 0) node _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_1_wrdata_unrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, 5, 0) node _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T) node frfWriteBundle_1_wrdata_unrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_1_wrdata_unrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, 1) node _frfWriteBundle_1_wrdata_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_unrecoded_denormFract_T, frfWriteBundle_1_wrdata_unrecoded_denormShiftDist) node frfWriteBundle_1_wrdata_unrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_unrecoded_denormFract_T_1, 51, 0) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sExp, 10, 0) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_unrecoded_expOut_T, UInt<11>(0h401)) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_1, 1) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_expOut_T_2) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_unrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf) node _frfWriteBundle_1_wrdata_unrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node frfWriteBundle_1_wrdata_unrecoded_expOut = or(_frfWriteBundle_1_wrdata_unrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_unrecoded_expOut_T_5) node _frfWriteBundle_1_wrdata_unrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_unrecoded_rawIn.sig, 51, 0) node _frfWriteBundle_1_wrdata_unrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_unrecoded_fractOut_T) node frfWriteBundle_1_wrdata_unrecoded_fractOut = mux(frfWriteBundle_1_wrdata_unrecoded_isSubnormal, frfWriteBundle_1_wrdata_unrecoded_denormFract, _frfWriteBundle_1_wrdata_unrecoded_fractOut_T_1) node frfWriteBundle_1_wrdata_unrecoded_hi = cat(frfWriteBundle_1_wrdata_unrecoded_rawIn.sign, frfWriteBundle_1_wrdata_unrecoded_expOut) node frfWriteBundle_1_wrdata_unrecoded = cat(frfWriteBundle_1_wrdata_unrecoded_hi, frfWriteBundle_1_wrdata_unrecoded_fractOut) node _frfWriteBundle_1_wrdata_prevRecoded_T = bits(wdata_1, 31, 31) node _frfWriteBundle_1_wrdata_prevRecoded_T_1 = bits(wdata_1, 52, 52) node _frfWriteBundle_1_wrdata_prevRecoded_T_2 = bits(wdata_1, 30, 0) node frfWriteBundle_1_wrdata_prevRecoded_hi = cat(_frfWriteBundle_1_wrdata_prevRecoded_T, _frfWriteBundle_1_wrdata_prevRecoded_T_1) node frfWriteBundle_1_wrdata_prevRecoded = cat(frfWriteBundle_1_wrdata_prevRecoded_hi, _frfWriteBundle_1_wrdata_prevRecoded_T_2) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp = bits(frfWriteBundle_1_wrdata_prevRecoded, 31, 23) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(frfWriteBundle_1_wrdata_prevRecoded, 32, 32) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_exp) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_1_wrdata_prevRecoded, 22, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormShiftDist) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_2) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isInf) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut = or(_frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut_T_5) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut = mux(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_isSubnormal, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_denormFract, _frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut_T_1) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_hi = cat(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_rawIn.sign, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_expOut) node frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded_fractOut) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T = bits(frfWriteBundle_1_wrdata_prevRecoded, 15, 15) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_1 = bits(frfWriteBundle_1_wrdata_prevRecoded, 23, 23) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_2 = bits(frfWriteBundle_1_wrdata_prevRecoded, 14, 0) node frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_hi = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_1) node frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded_T_2) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded, 15, 10) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isZero, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded, 16, 16) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevRecoded, 9, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = lt(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract = bits(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isNaN, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut = or(_frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = bits(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut = mux(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_denormFract, _frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_hi = cat(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_rawIn.sign, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_expOut) node frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded = cat(frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded_fractOut) node _frfWriteBundle_1_wrdata_prevUnrecoded_T = shr(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded, 16) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_1 = bits(frfWriteBundle_1_wrdata_prevRecoded, 31, 29) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_2 = andr(_frfWriteBundle_1_wrdata_prevUnrecoded_T_1) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_3 = bits(frfWriteBundle_1_wrdata_prevUnrecoded_unrecoded, 15, 0) node _frfWriteBundle_1_wrdata_prevUnrecoded_T_4 = mux(_frfWriteBundle_1_wrdata_prevUnrecoded_T_2, frfWriteBundle_1_wrdata_prevUnrecoded_prevUnrecoded, _frfWriteBundle_1_wrdata_prevUnrecoded_T_3) node frfWriteBundle_1_wrdata_prevUnrecoded = cat(_frfWriteBundle_1_wrdata_prevUnrecoded_T, _frfWriteBundle_1_wrdata_prevUnrecoded_T_4) node _frfWriteBundle_1_wrdata_T = shr(frfWriteBundle_1_wrdata_unrecoded, 32) node _frfWriteBundle_1_wrdata_T_1 = bits(wdata_1, 63, 61) node _frfWriteBundle_1_wrdata_T_2 = andr(_frfWriteBundle_1_wrdata_T_1) node _frfWriteBundle_1_wrdata_T_3 = bits(frfWriteBundle_1_wrdata_unrecoded, 31, 0) node _frfWriteBundle_1_wrdata_T_4 = mux(_frfWriteBundle_1_wrdata_T_2, frfWriteBundle_1_wrdata_prevUnrecoded, _frfWriteBundle_1_wrdata_T_3) node _frfWriteBundle_1_wrdata_T_5 = cat(_frfWriteBundle_1_wrdata_T, _frfWriteBundle_1_wrdata_T_4) connect frfWriteBundle_1.wrdata, _frfWriteBundle_1_wrdata_T_5 node _T_31 = bits(wen, 0, 0) node _T_32 = or(_T_31, divSqrt_wen) node _T_33 = and(wb_cp, _T_32) when _T_33 : connect io.cp_resp.bits.data, wdata_1 connect io.cp_resp.valid, UInt<1>(0h1) node _T_34 = eq(io.cp_req.valid, UInt<1>(0h0)) node _T_35 = or(_T_34, UInt<1>(0h0)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed: FPU only supports coprocessor if FMA pipes have uniform latency List(2, 2, 3, 4, 3)\n at FPU.scala:987 assert(!io.cp_req.valid || pipes.forall(_.lat == pipes.head.lat).B,\n") : printf_2 assert(clock, _T_35, UInt<1>(0h1), "") : assert_2 node _io_cp_req_ready_T = eq(ex_reg_valid, UInt<1>(0h0)) node _io_cp_req_ready_T_1 = neq(wen, UInt<1>(0h0)) node _io_cp_req_ready_T_2 = and(cp_ctrl.toint, _io_cp_req_ready_T_1) node _io_cp_req_ready_T_3 = eq(_io_cp_req_ready_T_2, UInt<1>(0h0)) node _io_cp_req_ready_T_4 = and(_io_cp_req_ready_T, _io_cp_req_ready_T_3) node _io_cp_req_ready_T_5 = eq(divSqrt_inFlight, UInt<1>(0h0)) node _io_cp_req_ready_T_6 = and(_io_cp_req_ready_T_4, _io_cp_req_ready_T_5) connect io.cp_req.ready, _io_cp_req_ready_T_6 node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) reg wb_toint_exc : UInt<5>, clock when mem_ctrl.toint : connect wb_toint_exc, fpiu.io.out.bits.exc node _io_fcsr_flags_valid_T = or(wb_toint_valid, divSqrt_wen) node _io_fcsr_flags_valid_T_1 = bits(wen, 0, 0) node _io_fcsr_flags_valid_T_2 = or(_io_fcsr_flags_valid_T, _io_fcsr_flags_valid_T_1) connect io.fcsr_flags.valid, _io_fcsr_flags_valid_T_2 node _io_fcsr_flags_bits_T = mux(wb_toint_valid, wb_toint_exc, UInt<1>(0h0)) node _io_fcsr_flags_bits_T_1 = mux(divSqrt_wen, divSqrt_flags, UInt<1>(0h0)) node _io_fcsr_flags_bits_T_2 = or(_io_fcsr_flags_bits_T, _io_fcsr_flags_bits_T_1) node _io_fcsr_flags_bits_T_3 = bits(wen, 0, 0) node _io_fcsr_flags_bits_T_4 = mux(_io_fcsr_flags_bits_T_3, wexc, UInt<1>(0h0)) node _io_fcsr_flags_bits_T_5 = or(_io_fcsr_flags_bits_T_2, _io_fcsr_flags_bits_T_4) connect io.fcsr_flags.bits, _io_fcsr_flags_bits_T_5 node _divSqrt_write_port_busy_T = or(mem_ctrl.div, mem_ctrl.sqrt) node _divSqrt_write_port_busy_T_1 = orr(wen) node divSqrt_write_port_busy = and(_divSqrt_write_port_busy_T, _divSqrt_write_port_busy_T_1) node _io_fcsr_rdy_T = and(ex_reg_valid, ex_ctrl.wflags) node _io_fcsr_rdy_T_1 = and(mem_reg_valid, mem_ctrl.wflags) node _io_fcsr_rdy_T_2 = or(_io_fcsr_rdy_T, _io_fcsr_rdy_T_1) node _io_fcsr_rdy_T_3 = and(wb_reg_valid, wb_ctrl.toint) node _io_fcsr_rdy_T_4 = or(_io_fcsr_rdy_T_2, _io_fcsr_rdy_T_3) node _io_fcsr_rdy_T_5 = orr(wen) node _io_fcsr_rdy_T_6 = or(_io_fcsr_rdy_T_4, _io_fcsr_rdy_T_5) node _io_fcsr_rdy_T_7 = or(_io_fcsr_rdy_T_6, divSqrt_inFlight) node _io_fcsr_rdy_T_8 = eq(_io_fcsr_rdy_T_7, UInt<1>(0h0)) connect io.fcsr_rdy, _io_fcsr_rdy_T_8 node _io_nack_mem_T = or(write_port_busy, divSqrt_write_port_busy) node _io_nack_mem_T_1 = or(_io_nack_mem_T, divSqrt_inFlight) node _io_nack_mem_T_2 = eq(mem_cp_valid, UInt<1>(0h0)) node _io_nack_mem_T_3 = and(_io_nack_mem_T_1, _io_nack_mem_T_2) connect io.nack_mem, _io_nack_mem_T_3 connect io.dec, id_ctrl node _io_sboard_set_T = eq(wb_cp_valid, UInt<1>(0h0)) node _io_sboard_set_T_1 = and(wb_reg_valid, _io_sboard_set_T) node _io_sboard_set_T_2 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _io_sboard_set_T_3 = and(mem_ctrl.fma, _io_sboard_set_T_2) node _io_sboard_set_T_4 = or(UInt<1>(0h0), _io_sboard_set_T_3) node _io_sboard_set_T_5 = or(_io_sboard_set_T_4, mem_ctrl.div) node _io_sboard_set_T_6 = or(_io_sboard_set_T_5, mem_ctrl.sqrt) node _io_sboard_set_T_7 = or(_io_sboard_set_T_6, mem_ctrl.vec) reg io_sboard_set_REG : UInt<1>, clock connect io_sboard_set_REG, _io_sboard_set_T_7 node _io_sboard_set_T_8 = and(_io_sboard_set_T_1, io_sboard_set_REG) connect io.sboard_set, _io_sboard_set_T_8 node _io_sboard_clr_T = eq(wb_cp_valid, UInt<1>(0h0)) node _io_sboard_clr_T_1 = bits(wen, 0, 0) node _io_sboard_clr_T_2 = eq(wbInfo[0].pipeid, UInt<2>(0h3)) node _io_sboard_clr_T_3 = or(UInt<1>(0h0), _io_sboard_clr_T_2) node _io_sboard_clr_T_4 = and(_io_sboard_clr_T_1, _io_sboard_clr_T_3) node _io_sboard_clr_T_5 = or(divSqrt_wen, _io_sboard_clr_T_4) node _io_sboard_clr_T_6 = and(_io_sboard_clr_T, _io_sboard_clr_T_5) connect io.sboard_clr, _io_sboard_clr_T_6 connect io.sboard_clra, waddr node _T_39 = and(io.sboard_clr, load_wb) node _io_illegal_rm_T = bits(io.inst, 14, 12) node _io_illegal_rm_T_1 = eq(_io_illegal_rm_T, UInt<3>(0h5)) node _io_illegal_rm_T_2 = eq(_io_illegal_rm_T, UInt<3>(0h6)) node _io_illegal_rm_T_3 = or(_io_illegal_rm_T_1, _io_illegal_rm_T_2) node _io_illegal_rm_T_4 = bits(io.inst, 14, 12) node _io_illegal_rm_T_5 = eq(_io_illegal_rm_T_4, UInt<3>(0h7)) node _io_illegal_rm_T_6 = geq(io.fcsr_rm, UInt<3>(0h5)) node _io_illegal_rm_T_7 = and(_io_illegal_rm_T_5, _io_illegal_rm_T_6) node _io_illegal_rm_T_8 = or(_io_illegal_rm_T_3, _io_illegal_rm_T_7) connect io.illegal_rm, _io_illegal_rm_T_8 node _divSqrt_inValid_T = or(mem_ctrl.div, mem_ctrl.sqrt) node _divSqrt_inValid_T_1 = and(mem_reg_valid, _divSqrt_inValid_T) node _divSqrt_inValid_T_2 = eq(divSqrt_inFlight, UInt<1>(0h0)) node divSqrt_inValid = and(_divSqrt_inValid_T_1, _divSqrt_inValid_T_2) node _divSqrt_killed_T = and(divSqrt_inValid, killm) regreset divSqrt_killed : UInt<1>, clock, reset, UInt<1>(0h1) connect divSqrt_killed, _divSqrt_killed_T when divSqrt_inValid : node _divSqrt_waddr_T = bits(mem_reg_inst, 11, 7) connect divSqrt_waddr, _divSqrt_waddr_T connect divSqrt_cp, mem_cp_valid node _T_40 = and(divSqrt_inFlight, divSqrt_killed) node _T_41 = and(divSqrt_inFlight, mem_reg_valid) node _T_42 = or(mem_ctrl.div, mem_ctrl.sqrt) node _T_43 = and(_T_41, _T_42) node _T_44 = and(mem_reg_valid, divSqrt_write_port_busy) inst divSqrt of DivSqrtRecFM_small_e5_s11_4 connect divSqrt.clock, clock connect divSqrt.reset, divSqrt_killed node _divSqrt_io_inValid_T = eq(mem_ctrl.typeTagOut, UInt<1>(0h0)) node _divSqrt_io_inValid_T_1 = and(divSqrt_inValid, _divSqrt_io_inValid_T) connect divSqrt.io.inValid, _divSqrt_io_inValid_T_1 connect divSqrt.io.sqrtOp, mem_ctrl.sqrt node divSqrt_io_a_sign = bits(fpiu.io.out.bits.in.in1, 64, 64) node divSqrt_io_a_fractIn = bits(fpiu.io.out.bits.in.in1, 51, 0) node divSqrt_io_a_expIn = bits(fpiu.io.out.bits.in.in1, 63, 52) node _divSqrt_io_a_fractOut_T = shl(divSqrt_io_a_fractIn, 11) node divSqrt_io_a_fractOut = shr(_divSqrt_io_a_fractOut_T, 53) node divSqrt_io_a_expOut_expCode = bits(divSqrt_io_a_expIn, 11, 9) node _divSqrt_io_a_expOut_commonCase_T = add(divSqrt_io_a_expIn, UInt<6>(0h20)) node _divSqrt_io_a_expOut_commonCase_T_1 = tail(_divSqrt_io_a_expOut_commonCase_T, 1) node _divSqrt_io_a_expOut_commonCase_T_2 = sub(_divSqrt_io_a_expOut_commonCase_T_1, UInt<12>(0h800)) node divSqrt_io_a_expOut_commonCase = tail(_divSqrt_io_a_expOut_commonCase_T_2, 1) node _divSqrt_io_a_expOut_T = eq(divSqrt_io_a_expOut_expCode, UInt<1>(0h0)) node _divSqrt_io_a_expOut_T_1 = geq(divSqrt_io_a_expOut_expCode, UInt<3>(0h6)) node _divSqrt_io_a_expOut_T_2 = or(_divSqrt_io_a_expOut_T, _divSqrt_io_a_expOut_T_1) node _divSqrt_io_a_expOut_T_3 = bits(divSqrt_io_a_expOut_commonCase, 2, 0) node _divSqrt_io_a_expOut_T_4 = cat(divSqrt_io_a_expOut_expCode, _divSqrt_io_a_expOut_T_3) node _divSqrt_io_a_expOut_T_5 = bits(divSqrt_io_a_expOut_commonCase, 5, 0) node divSqrt_io_a_expOut = mux(_divSqrt_io_a_expOut_T_2, _divSqrt_io_a_expOut_T_4, _divSqrt_io_a_expOut_T_5) node divSqrt_io_a_hi = cat(divSqrt_io_a_sign, divSqrt_io_a_expOut) node _divSqrt_io_a_T = cat(divSqrt_io_a_hi, divSqrt_io_a_fractOut) connect divSqrt.io.a, _divSqrt_io_a_T node divSqrt_io_b_sign = bits(fpiu.io.out.bits.in.in2, 64, 64) node divSqrt_io_b_fractIn = bits(fpiu.io.out.bits.in.in2, 51, 0) node divSqrt_io_b_expIn = bits(fpiu.io.out.bits.in.in2, 63, 52) node _divSqrt_io_b_fractOut_T = shl(divSqrt_io_b_fractIn, 11) node divSqrt_io_b_fractOut = shr(_divSqrt_io_b_fractOut_T, 53) node divSqrt_io_b_expOut_expCode = bits(divSqrt_io_b_expIn, 11, 9) node _divSqrt_io_b_expOut_commonCase_T = add(divSqrt_io_b_expIn, UInt<6>(0h20)) node _divSqrt_io_b_expOut_commonCase_T_1 = tail(_divSqrt_io_b_expOut_commonCase_T, 1) node _divSqrt_io_b_expOut_commonCase_T_2 = sub(_divSqrt_io_b_expOut_commonCase_T_1, UInt<12>(0h800)) node divSqrt_io_b_expOut_commonCase = tail(_divSqrt_io_b_expOut_commonCase_T_2, 1) node _divSqrt_io_b_expOut_T = eq(divSqrt_io_b_expOut_expCode, UInt<1>(0h0)) node _divSqrt_io_b_expOut_T_1 = geq(divSqrt_io_b_expOut_expCode, UInt<3>(0h6)) node _divSqrt_io_b_expOut_T_2 = or(_divSqrt_io_b_expOut_T, _divSqrt_io_b_expOut_T_1) node _divSqrt_io_b_expOut_T_3 = bits(divSqrt_io_b_expOut_commonCase, 2, 0) node _divSqrt_io_b_expOut_T_4 = cat(divSqrt_io_b_expOut_expCode, _divSqrt_io_b_expOut_T_3) node _divSqrt_io_b_expOut_T_5 = bits(divSqrt_io_b_expOut_commonCase, 5, 0) node divSqrt_io_b_expOut = mux(_divSqrt_io_b_expOut_T_2, _divSqrt_io_b_expOut_T_4, _divSqrt_io_b_expOut_T_5) node divSqrt_io_b_hi = cat(divSqrt_io_b_sign, divSqrt_io_b_expOut) node _divSqrt_io_b_T = cat(divSqrt_io_b_hi, divSqrt_io_b_fractOut) connect divSqrt.io.b, _divSqrt_io_b_T connect divSqrt.io.roundingMode, fpiu.io.out.bits.in.rm connect divSqrt.io.detectTininess, UInt<1>(0h1) node _T_45 = eq(divSqrt.io.inReady, UInt<1>(0h0)) when _T_45 : connect divSqrt_inFlight, UInt<1>(0h1) node _T_46 = or(divSqrt.io.outValid_div, divSqrt.io.outValid_sqrt) when _T_46 : node _divSqrt_wen_T = eq(divSqrt_killed, UInt<1>(0h0)) connect divSqrt_wen, _divSqrt_wen_T connect divSqrt_wdata, divSqrt.io.out connect divSqrt_flags, divSqrt.io.exceptionFlags connect divSqrt_typeTag, UInt<1>(0h0) inst divSqrt_1 of DivSqrtRecFM_small_e8_s24_4 connect divSqrt_1.clock, clock connect divSqrt_1.reset, divSqrt_killed node _divSqrt_io_inValid_T_2 = eq(mem_ctrl.typeTagOut, UInt<1>(0h1)) node _divSqrt_io_inValid_T_3 = and(divSqrt_inValid, _divSqrt_io_inValid_T_2) connect divSqrt_1.io.inValid, _divSqrt_io_inValid_T_3 connect divSqrt_1.io.sqrtOp, mem_ctrl.sqrt node divSqrt_io_a_sign_1 = bits(fpiu.io.out.bits.in.in1, 64, 64) node divSqrt_io_a_fractIn_1 = bits(fpiu.io.out.bits.in.in1, 51, 0) node divSqrt_io_a_expIn_1 = bits(fpiu.io.out.bits.in.in1, 63, 52) node _divSqrt_io_a_fractOut_T_1 = shl(divSqrt_io_a_fractIn_1, 24) node divSqrt_io_a_fractOut_1 = shr(_divSqrt_io_a_fractOut_T_1, 53) node divSqrt_io_a_expOut_expCode_1 = bits(divSqrt_io_a_expIn_1, 11, 9) node _divSqrt_io_a_expOut_commonCase_T_3 = add(divSqrt_io_a_expIn_1, UInt<9>(0h100)) node _divSqrt_io_a_expOut_commonCase_T_4 = tail(_divSqrt_io_a_expOut_commonCase_T_3, 1) node _divSqrt_io_a_expOut_commonCase_T_5 = sub(_divSqrt_io_a_expOut_commonCase_T_4, UInt<12>(0h800)) node divSqrt_io_a_expOut_commonCase_1 = tail(_divSqrt_io_a_expOut_commonCase_T_5, 1) node _divSqrt_io_a_expOut_T_6 = eq(divSqrt_io_a_expOut_expCode_1, UInt<1>(0h0)) node _divSqrt_io_a_expOut_T_7 = geq(divSqrt_io_a_expOut_expCode_1, UInt<3>(0h6)) node _divSqrt_io_a_expOut_T_8 = or(_divSqrt_io_a_expOut_T_6, _divSqrt_io_a_expOut_T_7) node _divSqrt_io_a_expOut_T_9 = bits(divSqrt_io_a_expOut_commonCase_1, 5, 0) node _divSqrt_io_a_expOut_T_10 = cat(divSqrt_io_a_expOut_expCode_1, _divSqrt_io_a_expOut_T_9) node _divSqrt_io_a_expOut_T_11 = bits(divSqrt_io_a_expOut_commonCase_1, 8, 0) node divSqrt_io_a_expOut_1 = mux(_divSqrt_io_a_expOut_T_8, _divSqrt_io_a_expOut_T_10, _divSqrt_io_a_expOut_T_11) node divSqrt_io_a_hi_1 = cat(divSqrt_io_a_sign_1, divSqrt_io_a_expOut_1) node _divSqrt_io_a_T_1 = cat(divSqrt_io_a_hi_1, divSqrt_io_a_fractOut_1) connect divSqrt_1.io.a, _divSqrt_io_a_T_1 node divSqrt_io_b_sign_1 = bits(fpiu.io.out.bits.in.in2, 64, 64) node divSqrt_io_b_fractIn_1 = bits(fpiu.io.out.bits.in.in2, 51, 0) node divSqrt_io_b_expIn_1 = bits(fpiu.io.out.bits.in.in2, 63, 52) node _divSqrt_io_b_fractOut_T_1 = shl(divSqrt_io_b_fractIn_1, 24) node divSqrt_io_b_fractOut_1 = shr(_divSqrt_io_b_fractOut_T_1, 53) node divSqrt_io_b_expOut_expCode_1 = bits(divSqrt_io_b_expIn_1, 11, 9) node _divSqrt_io_b_expOut_commonCase_T_3 = add(divSqrt_io_b_expIn_1, UInt<9>(0h100)) node _divSqrt_io_b_expOut_commonCase_T_4 = tail(_divSqrt_io_b_expOut_commonCase_T_3, 1) node _divSqrt_io_b_expOut_commonCase_T_5 = sub(_divSqrt_io_b_expOut_commonCase_T_4, UInt<12>(0h800)) node divSqrt_io_b_expOut_commonCase_1 = tail(_divSqrt_io_b_expOut_commonCase_T_5, 1) node _divSqrt_io_b_expOut_T_6 = eq(divSqrt_io_b_expOut_expCode_1, UInt<1>(0h0)) node _divSqrt_io_b_expOut_T_7 = geq(divSqrt_io_b_expOut_expCode_1, UInt<3>(0h6)) node _divSqrt_io_b_expOut_T_8 = or(_divSqrt_io_b_expOut_T_6, _divSqrt_io_b_expOut_T_7) node _divSqrt_io_b_expOut_T_9 = bits(divSqrt_io_b_expOut_commonCase_1, 5, 0) node _divSqrt_io_b_expOut_T_10 = cat(divSqrt_io_b_expOut_expCode_1, _divSqrt_io_b_expOut_T_9) node _divSqrt_io_b_expOut_T_11 = bits(divSqrt_io_b_expOut_commonCase_1, 8, 0) node divSqrt_io_b_expOut_1 = mux(_divSqrt_io_b_expOut_T_8, _divSqrt_io_b_expOut_T_10, _divSqrt_io_b_expOut_T_11) node divSqrt_io_b_hi_1 = cat(divSqrt_io_b_sign_1, divSqrt_io_b_expOut_1) node _divSqrt_io_b_T_1 = cat(divSqrt_io_b_hi_1, divSqrt_io_b_fractOut_1) connect divSqrt_1.io.b, _divSqrt_io_b_T_1 connect divSqrt_1.io.roundingMode, fpiu.io.out.bits.in.rm connect divSqrt_1.io.detectTininess, UInt<1>(0h1) node _T_47 = eq(divSqrt_1.io.inReady, UInt<1>(0h0)) when _T_47 : connect divSqrt_inFlight, UInt<1>(0h1) node _T_48 = or(divSqrt_1.io.outValid_div, divSqrt_1.io.outValid_sqrt) when _T_48 : node _divSqrt_wen_T_1 = eq(divSqrt_killed, UInt<1>(0h0)) connect divSqrt_wen, _divSqrt_wen_T_1 node _divSqrt_wdata_maskedNaN_T = not(UInt<33>(0h10800000)) node divSqrt_wdata_maskedNaN = and(divSqrt_1.io.out, _divSqrt_wdata_maskedNaN_T) node _divSqrt_wdata_T = bits(divSqrt_1.io.out, 31, 29) node _divSqrt_wdata_T_1 = andr(_divSqrt_wdata_T) node _divSqrt_wdata_T_2 = mux(_divSqrt_wdata_T_1, divSqrt_wdata_maskedNaN, divSqrt_1.io.out) connect divSqrt_wdata, _divSqrt_wdata_T_2 connect divSqrt_flags, divSqrt_1.io.exceptionFlags connect divSqrt_typeTag, UInt<1>(0h1) inst divSqrt_2 of DivSqrtRecFM_small_e11_s53_4 connect divSqrt_2.clock, clock connect divSqrt_2.reset, divSqrt_killed node _divSqrt_io_inValid_T_4 = eq(mem_ctrl.typeTagOut, UInt<2>(0h2)) node _divSqrt_io_inValid_T_5 = and(divSqrt_inValid, _divSqrt_io_inValid_T_4) connect divSqrt_2.io.inValid, _divSqrt_io_inValid_T_5 connect divSqrt_2.io.sqrtOp, mem_ctrl.sqrt connect divSqrt_2.io.a, fpiu.io.out.bits.in.in1 connect divSqrt_2.io.b, fpiu.io.out.bits.in.in2 connect divSqrt_2.io.roundingMode, fpiu.io.out.bits.in.rm connect divSqrt_2.io.detectTininess, UInt<1>(0h1) node _T_49 = eq(divSqrt_2.io.inReady, UInt<1>(0h0)) when _T_49 : connect divSqrt_inFlight, UInt<1>(0h1) node _T_50 = or(divSqrt_2.io.outValid_div, divSqrt_2.io.outValid_sqrt) when _T_50 : node _divSqrt_wen_T_2 = eq(divSqrt_killed, UInt<1>(0h0)) connect divSqrt_wen, _divSqrt_wen_T_2 node _divSqrt_wdata_maskedNaN_T_1 = not(UInt<65>(0h1010000000000000)) node divSqrt_wdata_maskedNaN_1 = and(divSqrt_2.io.out, _divSqrt_wdata_maskedNaN_T_1) node _divSqrt_wdata_T_3 = bits(divSqrt_2.io.out, 63, 61) node _divSqrt_wdata_T_4 = andr(_divSqrt_wdata_T_3) node _divSqrt_wdata_T_5 = mux(_divSqrt_wdata_T_4, divSqrt_wdata_maskedNaN_1, divSqrt_2.io.out) connect divSqrt_wdata, _divSqrt_wdata_T_5 connect divSqrt_flags, divSqrt_2.io.exceptionFlags connect divSqrt_typeTag, UInt<2>(0h2) when divSqrt_killed : connect divSqrt_inFlight, UInt<1>(0h0) node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0)) node _clock_en_reg_T_1 = or(_clock_en_reg_T, io.keep_clock_enabled) node _clock_en_reg_T_2 = or(_clock_en_reg_T_1, io.valid) node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, req_valid) node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, mem_reg_valid) node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, mem_cp_valid) node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, wb_reg_valid) node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, wb_cp_valid) node _clock_en_reg_T_8 = orr(wen) node _clock_en_reg_T_9 = or(_clock_en_reg_T_7, _clock_en_reg_T_8) node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, divSqrt_inFlight) node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, io.ll_resp_val) connect clock_en_reg, _clock_en_reg_T_11
module FPU_4( // @[FPU.scala:735:7] input clock, // @[FPU.scala:735:7] input reset, // @[FPU.scala:735:7] input [2:0] io_hartid, // @[FPU.scala:736:14] input [63:0] io_time, // @[FPU.scala:736:14] input [31:0] io_inst, // @[FPU.scala:736:14] input [63:0] io_fromint_data, // @[FPU.scala:736:14] input [2:0] io_fcsr_rm, // @[FPU.scala:736:14] output io_fcsr_flags_valid, // @[FPU.scala:736:14] output [4:0] io_fcsr_flags_bits, // @[FPU.scala:736:14] output [63:0] io_store_data, // @[FPU.scala:736:14] output [63:0] io_toint_data, // @[FPU.scala:736:14] input io_ll_resp_val, // @[FPU.scala:736:14] input [2:0] io_ll_resp_type, // @[FPU.scala:736:14] input [4:0] io_ll_resp_tag, // @[FPU.scala:736:14] input [63:0] io_ll_resp_data, // @[FPU.scala:736:14] input io_valid, // @[FPU.scala:736:14] output io_fcsr_rdy, // @[FPU.scala:736:14] output io_nack_mem, // @[FPU.scala:736:14] output io_illegal_rm, // @[FPU.scala:736:14] input io_killx, // @[FPU.scala:736:14] input io_killm, // @[FPU.scala:736:14] output io_dec_ldst, // @[FPU.scala:736:14] output io_dec_wen, // @[FPU.scala:736:14] output io_dec_ren1, // @[FPU.scala:736:14] output io_dec_ren2, // @[FPU.scala:736:14] output io_dec_ren3, // @[FPU.scala:736:14] output io_dec_swap12, // @[FPU.scala:736:14] output io_dec_swap23, // @[FPU.scala:736:14] output [1:0] io_dec_typeTagIn, // @[FPU.scala:736:14] output [1:0] io_dec_typeTagOut, // @[FPU.scala:736:14] output io_dec_fromint, // @[FPU.scala:736:14] output io_dec_toint, // @[FPU.scala:736:14] output io_dec_fastpipe, // @[FPU.scala:736:14] output io_dec_fma, // @[FPU.scala:736:14] output io_dec_div, // @[FPU.scala:736:14] output io_dec_sqrt, // @[FPU.scala:736:14] output io_dec_wflags, // @[FPU.scala:736:14] output io_dec_vec, // @[FPU.scala:736:14] output io_sboard_set, // @[FPU.scala:736:14] output io_sboard_clr, // @[FPU.scala:736:14] output [4:0] io_sboard_clra, // @[FPU.scala:736:14] input io_keep_clock_enabled // @[FPU.scala:736:14] ); wire wdata_rawIn_2_isNaN; // @[rawFloatFromFN.scala:63:19] wire wdata_rawIn_1_isNaN; // @[rawFloatFromFN.scala:63:19] wire wdata_rawIn_isNaN; // @[rawFloatFromFN.scala:63:19] wire _divSqrt_2_io_inReady; // @[FPU.scala:1027:55] wire _divSqrt_2_io_outValid_div; // @[FPU.scala:1027:55] wire _divSqrt_2_io_outValid_sqrt; // @[FPU.scala:1027:55] wire [64:0] _divSqrt_2_io_out; // @[FPU.scala:1027:55] wire [4:0] _divSqrt_2_io_exceptionFlags; // @[FPU.scala:1027:55] wire _divSqrt_1_io_inReady; // @[FPU.scala:1027:55] wire _divSqrt_1_io_outValid_div; // @[FPU.scala:1027:55] wire _divSqrt_1_io_outValid_sqrt; // @[FPU.scala:1027:55] wire [32:0] _divSqrt_1_io_out; // @[FPU.scala:1027:55] wire [4:0] _divSqrt_1_io_exceptionFlags; // @[FPU.scala:1027:55] wire _divSqrt_io_inReady; // @[FPU.scala:1027:55] wire _divSqrt_io_outValid_div; // @[FPU.scala:1027:55] wire _divSqrt_io_outValid_sqrt; // @[FPU.scala:1027:55] wire [16:0] _divSqrt_io_out; // @[FPU.scala:1027:55] wire [4:0] _divSqrt_io_exceptionFlags; // @[FPU.scala:1027:55] wire [64:0] _hfma_io_out_bits_data; // @[FPU.scala:919:28] wire [4:0] _hfma_io_out_bits_exc; // @[FPU.scala:919:28] wire [64:0] _dfma_io_out_bits_data; // @[FPU.scala:913:28] wire [4:0] _dfma_io_out_bits_exc; // @[FPU.scala:913:28] wire [64:0] _fpmu_io_out_bits_data; // @[FPU.scala:891:20] wire [4:0] _fpmu_io_out_bits_exc; // @[FPU.scala:891:20] wire [64:0] _ifpu_io_out_bits_data; // @[FPU.scala:886:20] wire [4:0] _ifpu_io_out_bits_exc; // @[FPU.scala:886:20] wire [2:0] _fpiu_io_out_bits_in_rm; // @[FPU.scala:876:20] wire [64:0] _fpiu_io_out_bits_in_in1; // @[FPU.scala:876:20] wire [64:0] _fpiu_io_out_bits_in_in2; // @[FPU.scala:876:20] wire _fpiu_io_out_bits_lt; // @[FPU.scala:876:20] wire [4:0] _fpiu_io_out_bits_exc; // @[FPU.scala:876:20] wire [64:0] _sfma_io_out_bits_data; // @[FPU.scala:872:20] wire [4:0] _sfma_io_out_bits_exc; // @[FPU.scala:872:20] wire [64:0] _regfile_ext_R0_data; // @[FPU.scala:818:20] wire [64:0] _regfile_ext_R1_data; // @[FPU.scala:818:20] wire [64:0] _regfile_ext_R2_data; // @[FPU.scala:818:20] wire [2:0] io_hartid_0 = io_hartid; // @[FPU.scala:735:7] wire [63:0] io_time_0 = io_time; // @[FPU.scala:735:7] wire [31:0] io_inst_0 = io_inst; // @[FPU.scala:735:7] wire [63:0] io_fromint_data_0 = io_fromint_data; // @[FPU.scala:735:7] wire [2:0] io_fcsr_rm_0 = io_fcsr_rm; // @[FPU.scala:735:7] wire io_ll_resp_val_0 = io_ll_resp_val; // @[FPU.scala:735:7] wire [2:0] io_ll_resp_type_0 = io_ll_resp_type; // @[FPU.scala:735:7] wire [4:0] io_ll_resp_tag_0 = io_ll_resp_tag; // @[FPU.scala:735:7] wire [63:0] io_ll_resp_data_0 = io_ll_resp_data; // @[FPU.scala:735:7] wire io_valid_0 = io_valid; // @[FPU.scala:735:7] wire io_killx_0 = io_killx; // @[FPU.scala:735:7] wire io_killm_0 = io_killm; // @[FPU.scala:735:7] wire io_keep_clock_enabled_0 = io_keep_clock_enabled; // @[FPU.scala:735:7] wire frfWriteBundle_0_clock = clock; // @[FPU.scala:805:44] wire frfWriteBundle_0_reset = reset; // @[FPU.scala:805:44] wire frfWriteBundle_1_clock = clock; // @[FPU.scala:805:44] wire frfWriteBundle_1_reset = reset; // @[FPU.scala:805:44] wire clock_en = 1'h1; // @[FPU.scala:735:7, :745:31] wire _killm_T_1 = 1'h1; // @[FPU.scala:735:7, :785:44] wire prevOK_prevOK = 1'h1; // @[FPU.scala:384:33, :735:7] wire _wdata_opts_bigger_swizzledNaN_T = 1'h1; // @[FPU.scala:338:42, :735:7] wire _wdata_opts_bigger_T = 1'h1; // @[FPU.scala:249:56, :735:7] wire _wdata_opts_bigger_swizzledNaN_T_4 = 1'h1; // @[FPU.scala:338:42, :735:7] wire _wdata_opts_bigger_T_1 = 1'h1; // @[FPU.scala:249:56, :735:7] wire prevOK_prevOK_1 = 1'h1; // @[FPU.scala:384:33, :735:7] wire _io_cp_req_ready_T_3 = 1'h1; // @[FPU.scala:735:7, :991:39] wire _io_nack_mem_T_2 = 1'h1; // @[FPU.scala:735:7, :1003:86] wire _io_sboard_set_T = 1'h1; // @[FPU.scala:735:7, :1006:36] wire _io_sboard_clr_T = 1'h1; // @[FPU.scala:735:7, :1007:20] wire _clock_en_reg_T = 1'h1; // @[FPU.scala:735:7, :1051:19] wire _clock_en_reg_T_1 = 1'h1; // @[FPU.scala:735:7, :1051:37] wire _clock_en_reg_T_2 = 1'h1; // @[FPU.scala:735:7, :1052:27] wire _clock_en_reg_T_3 = 1'h1; // @[FPU.scala:735:7, :1053:14] wire _clock_en_reg_T_4 = 1'h1; // @[FPU.scala:735:7, :1054:15] wire _clock_en_reg_T_5 = 1'h1; // @[FPU.scala:735:7, :1055:19] wire _clock_en_reg_T_6 = 1'h1; // @[FPU.scala:735:7, :1055:35] wire _clock_en_reg_T_7 = 1'h1; // @[FPU.scala:735:7, :1056:18] wire _clock_en_reg_T_9 = 1'h1; // @[FPU.scala:735:7, :1056:33] wire _clock_en_reg_T_10 = 1'h1; // @[FPU.scala:735:7, :1057:13] wire _clock_en_reg_T_11 = 1'h1; // @[FPU.scala:735:7, :1057:33] wire io_cp_req_valid = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ldst = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_wen = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ren1 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ren2 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_ren3 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_swap12 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_swap23 = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_fromint = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_toint = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_fastpipe = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_fma = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_div = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_sqrt = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_wflags = 1'h0; // @[FPU.scala:735:7] wire io_cp_req_bits_vec = 1'h0; // @[FPU.scala:735:7] wire io_cp_resp_ready = 1'h0; // @[FPU.scala:735:7] wire ex_cp_valid = 1'h0; // @[Decoupled.scala:51:35] wire cp_ctrl_ldst = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_wen = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_ren1 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_ren2 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_ren3 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_swap12 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_swap23 = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_fromint = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_toint = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_fastpipe = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_fma = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_div = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_sqrt = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_wflags = 1'h0; // @[FPU.scala:794:21] wire cp_ctrl_vec = 1'h0; // @[FPU.scala:794:21] wire frfWriteBundle_0_excpt = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_0_valid = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_0_wrenx = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_1_excpt = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_1_valid = 1'h0; // @[FPU.scala:805:44] wire frfWriteBundle_1_wrenx = 1'h0; // @[FPU.scala:805:44] wire _wbInfo_0_pipeid_T = 1'h0; // @[FPU.scala:928:63] wire _wbInfo_1_pipeid_T = 1'h0; // @[FPU.scala:928:63] wire _wbInfo_2_pipeid_T = 1'h0; // @[FPU.scala:928:63] wire _io_cp_req_ready_T_2 = 1'h0; // @[FPU.scala:991:55] wire [64:0] io_cp_req_bits_in1 = 65'h0; // @[FPU.scala:735:7] wire [64:0] io_cp_req_bits_in2 = 65'h0; // @[FPU.scala:735:7] wire [64:0] io_cp_req_bits_in3 = 65'h0; // @[FPU.scala:735:7] wire [64:0] _dfma_io_in_bits_req_in1_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in2_T = 65'h0; // @[FPU.scala:372:31] wire [64:0] _dfma_io_in_bits_req_in3_T = 65'h0; // @[FPU.scala:372:31] wire [2:0] io_v_sew = 3'h0; // @[FPU.scala:735:7] wire [2:0] io_cp_req_bits_rm = 3'h0; // @[FPU.scala:735:7] wire [2:0] frfWriteBundle_0_priv_mode = 3'h0; // @[FPU.scala:805:44] wire [2:0] frfWriteBundle_1_priv_mode = 3'h0; // @[FPU.scala:805:44] wire [1:0] io_cp_req_bits_typeTagIn = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_typeTagOut = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_fmaCmd = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_typ = 2'h0; // @[FPU.scala:735:7] wire [1:0] io_cp_req_bits_fmt = 2'h0; // @[FPU.scala:735:7] wire [1:0] cp_ctrl_typeTagIn = 2'h0; // @[FPU.scala:794:21] wire [1:0] cp_ctrl_typeTagOut = 2'h0; // @[FPU.scala:794:21] wire [4:0] io_cp_resp_bits_exc = 5'h0; // @[FPU.scala:735:7] wire [4:0] frfWriteBundle_0_rd0src = 5'h0; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_0_rd1src = 5'h0; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_1_rd0src = 5'h0; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_1_rd1src = 5'h0; // @[FPU.scala:805:44] wire [64:0] _divSqrt_wdata_maskedNaN_T_1 = 65'h1EFEFFFFFFFFFFFFF; // @[FPU.scala:413:27] wire [32:0] _divSqrt_wdata_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi = 5'h1F; // @[FPU.scala:336:26] wire [4:0] wdata_opts_bigger_swizzledNaN_hi_hi_1 = 5'h1F; // @[FPU.scala:336:26] wire [31:0] frfWriteBundle_0_inst = 32'h0; // @[FPU.scala:805:44] wire [31:0] frfWriteBundle_1_inst = 32'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_pc = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_rd0val = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_rd1val = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_pc = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_rd0val = 64'h0; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_rd1val = 64'h0; // @[FPU.scala:805:44] wire _io_fcsr_flags_valid_T_2; // @[FPU.scala:995:56] wire [4:0] _io_fcsr_flags_bits_T_5; // @[FPU.scala:998:42] wire _io_fcsr_rdy_T_8; // @[FPU.scala:1002:18] wire _io_nack_mem_T_3; // @[FPU.scala:1003:83] wire _io_illegal_rm_T_8; // @[FPU.scala:1011:53] wire id_ctrl_ldst; // @[FPU.scala:752:25] wire id_ctrl_wen; // @[FPU.scala:752:25] wire id_ctrl_ren1; // @[FPU.scala:752:25] wire id_ctrl_ren2; // @[FPU.scala:752:25] wire id_ctrl_ren3; // @[FPU.scala:752:25] wire id_ctrl_swap12; // @[FPU.scala:752:25] wire id_ctrl_swap23; // @[FPU.scala:752:25] wire [1:0] id_ctrl_typeTagIn; // @[FPU.scala:752:25] wire [1:0] id_ctrl_typeTagOut; // @[FPU.scala:752:25] wire id_ctrl_fromint; // @[FPU.scala:752:25] wire id_ctrl_toint; // @[FPU.scala:752:25] wire id_ctrl_fastpipe; // @[FPU.scala:752:25] wire id_ctrl_fma; // @[FPU.scala:752:25] wire id_ctrl_div; // @[FPU.scala:752:25] wire id_ctrl_sqrt; // @[FPU.scala:752:25] wire id_ctrl_wflags; // @[FPU.scala:752:25] wire id_ctrl_vec; // @[FPU.scala:752:25] wire _io_sboard_set_T_8; // @[FPU.scala:1006:49] wire _io_sboard_clr_T_6; // @[FPU.scala:1007:33] wire [4:0] waddr; // @[FPU.scala:963:18] wire _io_cp_req_ready_T_6; // @[FPU.scala:991:71] wire io_fcsr_flags_valid_0; // @[FPU.scala:735:7] wire [4:0] io_fcsr_flags_bits_0; // @[FPU.scala:735:7] wire io_dec_ldst_0; // @[FPU.scala:735:7] wire io_dec_wen_0; // @[FPU.scala:735:7] wire io_dec_ren1_0; // @[FPU.scala:735:7] wire io_dec_ren2_0; // @[FPU.scala:735:7] wire io_dec_ren3_0; // @[FPU.scala:735:7] wire io_dec_swap12_0; // @[FPU.scala:735:7] wire io_dec_swap23_0; // @[FPU.scala:735:7] wire [1:0] io_dec_typeTagIn_0; // @[FPU.scala:735:7] wire [1:0] io_dec_typeTagOut_0; // @[FPU.scala:735:7] wire io_dec_fromint_0; // @[FPU.scala:735:7] wire io_dec_toint_0; // @[FPU.scala:735:7] wire io_dec_fastpipe_0; // @[FPU.scala:735:7] wire io_dec_fma_0; // @[FPU.scala:735:7] wire io_dec_div_0; // @[FPU.scala:735:7] wire io_dec_sqrt_0; // @[FPU.scala:735:7] wire io_dec_wflags_0; // @[FPU.scala:735:7] wire io_dec_vec_0; // @[FPU.scala:735:7] wire io_cp_req_ready; // @[FPU.scala:735:7] wire [64:0] io_cp_resp_bits_data; // @[FPU.scala:735:7] wire io_cp_resp_valid; // @[FPU.scala:735:7] wire [63:0] io_store_data_0; // @[FPU.scala:735:7] wire [63:0] io_toint_data_0; // @[FPU.scala:735:7] wire io_fcsr_rdy_0; // @[FPU.scala:735:7] wire io_nack_mem_0; // @[FPU.scala:735:7] wire io_illegal_rm_0; // @[FPU.scala:735:7] wire io_sboard_set_0; // @[FPU.scala:735:7] wire io_sboard_clr_0; // @[FPU.scala:735:7] wire [4:0] io_sboard_clra_0; // @[FPU.scala:735:7] assign io_dec_ldst_0 = id_ctrl_ldst; // @[FPU.scala:735:7, :752:25] assign io_dec_wen_0 = id_ctrl_wen; // @[FPU.scala:735:7, :752:25] assign io_dec_ren1_0 = id_ctrl_ren1; // @[FPU.scala:735:7, :752:25] assign io_dec_ren2_0 = id_ctrl_ren2; // @[FPU.scala:735:7, :752:25] assign io_dec_ren3_0 = id_ctrl_ren3; // @[FPU.scala:735:7, :752:25] assign io_dec_swap12_0 = id_ctrl_swap12; // @[FPU.scala:735:7, :752:25] assign io_dec_swap23_0 = id_ctrl_swap23; // @[FPU.scala:735:7, :752:25] assign io_dec_typeTagIn_0 = id_ctrl_typeTagIn; // @[FPU.scala:735:7, :752:25] assign io_dec_typeTagOut_0 = id_ctrl_typeTagOut; // @[FPU.scala:735:7, :752:25] assign io_dec_fromint_0 = id_ctrl_fromint; // @[FPU.scala:735:7, :752:25] assign io_dec_toint_0 = id_ctrl_toint; // @[FPU.scala:735:7, :752:25] assign io_dec_fastpipe_0 = id_ctrl_fastpipe; // @[FPU.scala:735:7, :752:25] assign io_dec_fma_0 = id_ctrl_fma; // @[FPU.scala:735:7, :752:25] assign io_dec_div_0 = id_ctrl_div; // @[FPU.scala:735:7, :752:25] assign io_dec_sqrt_0 = id_ctrl_sqrt; // @[FPU.scala:735:7, :752:25] assign io_dec_wflags_0 = id_ctrl_wflags; // @[FPU.scala:735:7, :752:25] assign io_dec_vec_0 = id_ctrl_vec; // @[FPU.scala:735:7, :752:25] reg ex_reg_valid; // @[FPU.scala:767:29] wire req_valid = ex_reg_valid; // @[FPU.scala:767:29, :780:32] reg [31:0] ex_reg_inst; // @[FPU.scala:768:30] reg ex_reg_ctrl_ldst; // @[FPU.scala:769:30] wire ex_ctrl_ldst = ex_reg_ctrl_ldst; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_wen; // @[FPU.scala:769:30] wire ex_ctrl_wen = ex_reg_ctrl_wen; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_ren1; // @[FPU.scala:769:30] wire ex_ctrl_ren1 = ex_reg_ctrl_ren1; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_ren2; // @[FPU.scala:769:30] wire ex_ctrl_ren2 = ex_reg_ctrl_ren2; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_ren3; // @[FPU.scala:769:30] wire ex_ctrl_ren3 = ex_reg_ctrl_ren3; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_swap12; // @[FPU.scala:769:30] wire ex_ctrl_swap12 = ex_reg_ctrl_swap12; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_swap23; // @[FPU.scala:769:30] wire ex_ctrl_swap23 = ex_reg_ctrl_swap23; // @[FPU.scala:769:30, :800:20] reg [1:0] ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30] wire [1:0] ex_ctrl_typeTagIn = ex_reg_ctrl_typeTagIn; // @[FPU.scala:769:30, :800:20] reg [1:0] ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30] wire [1:0] ex_ctrl_typeTagOut = ex_reg_ctrl_typeTagOut; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_fromint; // @[FPU.scala:769:30] wire ex_ctrl_fromint = ex_reg_ctrl_fromint; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_toint; // @[FPU.scala:769:30] wire ex_ctrl_toint = ex_reg_ctrl_toint; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30] wire ex_ctrl_fastpipe = ex_reg_ctrl_fastpipe; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_fma; // @[FPU.scala:769:30] wire ex_ctrl_fma = ex_reg_ctrl_fma; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_div; // @[FPU.scala:769:30] wire ex_ctrl_div = ex_reg_ctrl_div; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_sqrt; // @[FPU.scala:769:30] wire ex_ctrl_sqrt = ex_reg_ctrl_sqrt; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_wflags; // @[FPU.scala:769:30] wire ex_ctrl_wflags = ex_reg_ctrl_wflags; // @[FPU.scala:769:30, :800:20] reg ex_reg_ctrl_vec; // @[FPU.scala:769:30] wire ex_ctrl_vec = ex_reg_ctrl_vec; // @[FPU.scala:769:30, :800:20] reg [4:0] ex_ra_0; // @[FPU.scala:770:31] wire [4:0] _ex_rs_T = ex_ra_0; // @[FPU.scala:770:31, :832:37] reg [4:0] ex_ra_1; // @[FPU.scala:770:31] wire [4:0] _ex_rs_T_2 = ex_ra_1; // @[FPU.scala:770:31, :832:37] reg [4:0] ex_ra_2; // @[FPU.scala:770:31] wire [4:0] _ex_rs_T_4 = ex_ra_2; // @[FPU.scala:770:31, :832:37] reg load_wb; // @[FPU.scala:773:24] wire frfWriteBundle_0_wrenf = load_wb; // @[FPU.scala:773:24, :805:44] wire [1:0] _load_wb_typeTag_T = io_ll_resp_type_0[1:0]; // @[FPU.scala:735:7, :774:50] wire [2:0] _load_wb_typeTag_T_1 = {1'h0, _load_wb_typeTag_T} - 3'h1; // @[FPU.scala:774:{50,56}] wire [1:0] _load_wb_typeTag_T_2 = _load_wb_typeTag_T_1[1:0]; // @[FPU.scala:774:56] reg [1:0] load_wb_typeTag; // @[FPU.scala:774:34] reg [63:0] load_wb_data; // @[FPU.scala:775:31] reg [4:0] load_wb_tag; // @[FPU.scala:776:30] wire [4:0] frfWriteBundle_0_wrdst = load_wb_tag; // @[FPU.scala:776:30, :805:44] reg mem_reg_valid; // @[FPU.scala:784:30] wire _killm_T = io_killm_0 | io_nack_mem_0; // @[FPU.scala:735:7, :785:25] wire killm = _killm_T; // @[FPU.scala:785:{25,41}] wire _killx_T = mem_reg_valid & killm; // @[FPU.scala:784:30, :785:41, :789:41] wire killx = io_killx_0 | _killx_T; // @[FPU.scala:735:7, :789:{24,41}] wire _mem_reg_valid_T = ~killx; // @[FPU.scala:789:24, :790:36] wire _mem_reg_valid_T_1 = ex_reg_valid & _mem_reg_valid_T; // @[FPU.scala:767:29, :790:{33,36}] wire _mem_reg_valid_T_2 = _mem_reg_valid_T_1; // @[FPU.scala:790:{33,43}] reg [31:0] mem_reg_inst; // @[FPU.scala:791:31] wire _wb_reg_valid_T = ~killm; // @[FPU.scala:785:41, :792:48] wire _wb_reg_valid_T_1 = _wb_reg_valid_T; // @[FPU.scala:792:{48,55}] wire _wb_reg_valid_T_2 = mem_reg_valid & _wb_reg_valid_T_1; // @[FPU.scala:784:30, :792:{44,55}] reg wb_reg_valid; // @[FPU.scala:792:29] wire _io_sboard_set_T_1 = wb_reg_valid; // @[FPU.scala:792:29, :1006:33] wire sfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ldst = ex_ctrl_ldst; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_wen = ex_ctrl_wen; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ren1 = ex_ctrl_ren1; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ren2 = ex_ctrl_ren2; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_ren3 = ex_ctrl_ren3; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_swap12 = ex_ctrl_swap12; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_swap23 = ex_ctrl_swap23; // @[FPU.scala:800:20, :848:19] wire [1:0] sfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] fpiu_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] dfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] hfma_io_in_bits_req_typeTagIn = ex_ctrl_typeTagIn; // @[FPU.scala:800:20, :848:19] wire [1:0] sfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire [1:0] fpiu_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire [1:0] dfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire [1:0] hfma_io_in_bits_req_typeTagOut = ex_ctrl_typeTagOut; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_fromint = ex_ctrl_fromint; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_toint = ex_ctrl_toint; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_fastpipe = ex_ctrl_fastpipe; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_fma = ex_ctrl_fma; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_div = ex_ctrl_div; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_sqrt = ex_ctrl_sqrt; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_wflags = ex_ctrl_wflags; // @[FPU.scala:800:20, :848:19] wire sfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] wire fpiu_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] wire dfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] wire hfma_io_in_bits_req_vec = ex_ctrl_vec; // @[FPU.scala:800:20, :848:19] reg mem_ctrl_ldst; // @[FPU.scala:801:27] reg mem_ctrl_wen; // @[FPU.scala:801:27] reg mem_ctrl_ren1; // @[FPU.scala:801:27] reg mem_ctrl_ren2; // @[FPU.scala:801:27] reg mem_ctrl_ren3; // @[FPU.scala:801:27] reg mem_ctrl_swap12; // @[FPU.scala:801:27] reg mem_ctrl_swap23; // @[FPU.scala:801:27] reg [1:0] mem_ctrl_typeTagIn; // @[FPU.scala:801:27] reg [1:0] mem_ctrl_typeTagOut; // @[FPU.scala:801:27] reg mem_ctrl_fromint; // @[FPU.scala:801:27] wire _memLatencyMask_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :926:23] wire _wbInfo_0_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63] wire _wbInfo_1_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63] wire _wbInfo_2_pipeid_T_1 = mem_ctrl_fromint; // @[FPU.scala:801:27, :928:63] reg mem_ctrl_toint; // @[FPU.scala:801:27] reg mem_ctrl_fastpipe; // @[FPU.scala:801:27] wire _memLatencyMask_T = mem_ctrl_fastpipe; // @[FPU.scala:801:27, :926:23] reg mem_ctrl_fma; // @[FPU.scala:801:27] reg mem_ctrl_div; // @[FPU.scala:801:27] reg mem_ctrl_sqrt; // @[FPU.scala:801:27] reg mem_ctrl_wflags; // @[FPU.scala:801:27] reg mem_ctrl_vec; // @[FPU.scala:801:27] reg wb_ctrl_ldst; // @[FPU.scala:802:26] reg wb_ctrl_wen; // @[FPU.scala:802:26] reg wb_ctrl_ren1; // @[FPU.scala:802:26] reg wb_ctrl_ren2; // @[FPU.scala:802:26] reg wb_ctrl_ren3; // @[FPU.scala:802:26] reg wb_ctrl_swap12; // @[FPU.scala:802:26] reg wb_ctrl_swap23; // @[FPU.scala:802:26] reg [1:0] wb_ctrl_typeTagIn; // @[FPU.scala:802:26] reg [1:0] wb_ctrl_typeTagOut; // @[FPU.scala:802:26] reg wb_ctrl_fromint; // @[FPU.scala:802:26] reg wb_ctrl_toint; // @[FPU.scala:802:26] reg wb_ctrl_fastpipe; // @[FPU.scala:802:26] reg wb_ctrl_fma; // @[FPU.scala:802:26] reg wb_ctrl_div; // @[FPU.scala:802:26] reg wb_ctrl_sqrt; // @[FPU.scala:802:26] reg wb_ctrl_wflags; // @[FPU.scala:802:26] reg wb_ctrl_vec; // @[FPU.scala:802:26] wire [31:0] _frfWriteBundle_0_timer_T; // @[FPU.scala:810:23] wire [63:0] _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10] wire [63:0] frfWriteBundle_0_hartid; // @[FPU.scala:805:44] wire [31:0] frfWriteBundle_0_timer; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_0_wrdata; // @[FPU.scala:805:44] wire [31:0] _frfWriteBundle_1_timer_T; // @[FPU.scala:810:23] wire [63:0] _frfWriteBundle_1_wrdata_T_5; // @[FPU.scala:446:10] wire [63:0] frfWriteBundle_1_hartid; // @[FPU.scala:805:44] wire [31:0] frfWriteBundle_1_timer; // @[FPU.scala:805:44] wire [4:0] frfWriteBundle_1_wrdst; // @[FPU.scala:805:44] wire [63:0] frfWriteBundle_1_wrdata; // @[FPU.scala:805:44] wire frfWriteBundle_1_wrenf; // @[FPU.scala:805:44] wire [63:0] _GEN = {61'h0, io_hartid_0}; // @[FPU.scala:735:7, :809:14] assign frfWriteBundle_0_hartid = _GEN; // @[FPU.scala:805:44, :809:14] assign frfWriteBundle_1_hartid = _GEN; // @[FPU.scala:805:44, :809:14] assign _frfWriteBundle_0_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23] assign _frfWriteBundle_1_timer_T = io_time_0[31:0]; // @[FPU.scala:735:7, :810:23] assign frfWriteBundle_0_timer = _frfWriteBundle_0_timer_T; // @[FPU.scala:805:44, :810:23] assign frfWriteBundle_1_timer = _frfWriteBundle_1_timer_T; // @[FPU.scala:805:44, :810:23] wire _wdata_T = load_wb_typeTag == 2'h1; // @[package.scala:39:86] wire [63:0] _wdata_T_1 = _wdata_T ? 64'hFFFFFFFF00000000 : 64'hFFFFFFFFFFFF0000; // @[package.scala:39:{76,86}] wire _wdata_T_2 = load_wb_typeTag == 2'h2; // @[package.scala:39:86] wire [63:0] _wdata_T_3 = _wdata_T_2 ? 64'h0 : _wdata_T_1; // @[package.scala:39:{76,86}] wire _wdata_T_4 = &load_wb_typeTag; // @[package.scala:39:86] wire [63:0] _wdata_T_5 = _wdata_T_4 ? 64'h0 : _wdata_T_3; // @[package.scala:39:{76,86}] wire [63:0] _wdata_T_6 = _wdata_T_5 | load_wb_data; // @[package.scala:39:76] wire wdata_rawIn_sign = _wdata_T_6[63]; // @[FPU.scala:431:23] wire wdata_rawIn_sign_0 = wdata_rawIn_sign; // @[rawFloatFromFN.scala:44:18, :63:19] wire [10:0] wdata_rawIn_expIn = _wdata_T_6[62:52]; // @[FPU.scala:431:23] wire [51:0] wdata_rawIn_fractIn = _wdata_T_6[51:0]; // @[FPU.scala:431:23] wire wdata_rawIn_isZeroExpIn = wdata_rawIn_expIn == 11'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire wdata_rawIn_isZeroFractIn = wdata_rawIn_fractIn == 52'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _wdata_rawIn_normDist_T = wdata_rawIn_fractIn[0]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_1 = wdata_rawIn_fractIn[1]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_2 = wdata_rawIn_fractIn[2]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_3 = wdata_rawIn_fractIn[3]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_4 = wdata_rawIn_fractIn[4]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_5 = wdata_rawIn_fractIn[5]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_6 = wdata_rawIn_fractIn[6]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_7 = wdata_rawIn_fractIn[7]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_8 = wdata_rawIn_fractIn[8]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_9 = wdata_rawIn_fractIn[9]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_10 = wdata_rawIn_fractIn[10]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_11 = wdata_rawIn_fractIn[11]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_12 = wdata_rawIn_fractIn[12]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_13 = wdata_rawIn_fractIn[13]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_14 = wdata_rawIn_fractIn[14]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_15 = wdata_rawIn_fractIn[15]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_16 = wdata_rawIn_fractIn[16]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_17 = wdata_rawIn_fractIn[17]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_18 = wdata_rawIn_fractIn[18]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_19 = wdata_rawIn_fractIn[19]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_20 = wdata_rawIn_fractIn[20]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_21 = wdata_rawIn_fractIn[21]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_22 = wdata_rawIn_fractIn[22]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_23 = wdata_rawIn_fractIn[23]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_24 = wdata_rawIn_fractIn[24]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_25 = wdata_rawIn_fractIn[25]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_26 = wdata_rawIn_fractIn[26]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_27 = wdata_rawIn_fractIn[27]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_28 = wdata_rawIn_fractIn[28]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_29 = wdata_rawIn_fractIn[29]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_30 = wdata_rawIn_fractIn[30]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_31 = wdata_rawIn_fractIn[31]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_32 = wdata_rawIn_fractIn[32]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_33 = wdata_rawIn_fractIn[33]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_34 = wdata_rawIn_fractIn[34]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_35 = wdata_rawIn_fractIn[35]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_36 = wdata_rawIn_fractIn[36]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_37 = wdata_rawIn_fractIn[37]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_38 = wdata_rawIn_fractIn[38]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_39 = wdata_rawIn_fractIn[39]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_40 = wdata_rawIn_fractIn[40]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_41 = wdata_rawIn_fractIn[41]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_42 = wdata_rawIn_fractIn[42]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_43 = wdata_rawIn_fractIn[43]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_44 = wdata_rawIn_fractIn[44]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_45 = wdata_rawIn_fractIn[45]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_46 = wdata_rawIn_fractIn[46]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_47 = wdata_rawIn_fractIn[47]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_48 = wdata_rawIn_fractIn[48]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_49 = wdata_rawIn_fractIn[49]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_50 = wdata_rawIn_fractIn[50]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_51 = wdata_rawIn_fractIn[51]; // @[rawFloatFromFN.scala:46:21] wire [5:0] _wdata_rawIn_normDist_T_52 = {5'h19, ~_wdata_rawIn_normDist_T_1}; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_53 = _wdata_rawIn_normDist_T_2 ? 6'h31 : _wdata_rawIn_normDist_T_52; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_54 = _wdata_rawIn_normDist_T_3 ? 6'h30 : _wdata_rawIn_normDist_T_53; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_55 = _wdata_rawIn_normDist_T_4 ? 6'h2F : _wdata_rawIn_normDist_T_54; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_56 = _wdata_rawIn_normDist_T_5 ? 6'h2E : _wdata_rawIn_normDist_T_55; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_57 = _wdata_rawIn_normDist_T_6 ? 6'h2D : _wdata_rawIn_normDist_T_56; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_58 = _wdata_rawIn_normDist_T_7 ? 6'h2C : _wdata_rawIn_normDist_T_57; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_59 = _wdata_rawIn_normDist_T_8 ? 6'h2B : _wdata_rawIn_normDist_T_58; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_60 = _wdata_rawIn_normDist_T_9 ? 6'h2A : _wdata_rawIn_normDist_T_59; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_61 = _wdata_rawIn_normDist_T_10 ? 6'h29 : _wdata_rawIn_normDist_T_60; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_62 = _wdata_rawIn_normDist_T_11 ? 6'h28 : _wdata_rawIn_normDist_T_61; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_63 = _wdata_rawIn_normDist_T_12 ? 6'h27 : _wdata_rawIn_normDist_T_62; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_64 = _wdata_rawIn_normDist_T_13 ? 6'h26 : _wdata_rawIn_normDist_T_63; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_65 = _wdata_rawIn_normDist_T_14 ? 6'h25 : _wdata_rawIn_normDist_T_64; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_66 = _wdata_rawIn_normDist_T_15 ? 6'h24 : _wdata_rawIn_normDist_T_65; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_67 = _wdata_rawIn_normDist_T_16 ? 6'h23 : _wdata_rawIn_normDist_T_66; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_68 = _wdata_rawIn_normDist_T_17 ? 6'h22 : _wdata_rawIn_normDist_T_67; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_69 = _wdata_rawIn_normDist_T_18 ? 6'h21 : _wdata_rawIn_normDist_T_68; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_70 = _wdata_rawIn_normDist_T_19 ? 6'h20 : _wdata_rawIn_normDist_T_69; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_71 = _wdata_rawIn_normDist_T_20 ? 6'h1F : _wdata_rawIn_normDist_T_70; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_72 = _wdata_rawIn_normDist_T_21 ? 6'h1E : _wdata_rawIn_normDist_T_71; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_73 = _wdata_rawIn_normDist_T_22 ? 6'h1D : _wdata_rawIn_normDist_T_72; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_74 = _wdata_rawIn_normDist_T_23 ? 6'h1C : _wdata_rawIn_normDist_T_73; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_75 = _wdata_rawIn_normDist_T_24 ? 6'h1B : _wdata_rawIn_normDist_T_74; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_76 = _wdata_rawIn_normDist_T_25 ? 6'h1A : _wdata_rawIn_normDist_T_75; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_77 = _wdata_rawIn_normDist_T_26 ? 6'h19 : _wdata_rawIn_normDist_T_76; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_78 = _wdata_rawIn_normDist_T_27 ? 6'h18 : _wdata_rawIn_normDist_T_77; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_79 = _wdata_rawIn_normDist_T_28 ? 6'h17 : _wdata_rawIn_normDist_T_78; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_80 = _wdata_rawIn_normDist_T_29 ? 6'h16 : _wdata_rawIn_normDist_T_79; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_81 = _wdata_rawIn_normDist_T_30 ? 6'h15 : _wdata_rawIn_normDist_T_80; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_82 = _wdata_rawIn_normDist_T_31 ? 6'h14 : _wdata_rawIn_normDist_T_81; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_83 = _wdata_rawIn_normDist_T_32 ? 6'h13 : _wdata_rawIn_normDist_T_82; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_84 = _wdata_rawIn_normDist_T_33 ? 6'h12 : _wdata_rawIn_normDist_T_83; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_85 = _wdata_rawIn_normDist_T_34 ? 6'h11 : _wdata_rawIn_normDist_T_84; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_86 = _wdata_rawIn_normDist_T_35 ? 6'h10 : _wdata_rawIn_normDist_T_85; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_87 = _wdata_rawIn_normDist_T_36 ? 6'hF : _wdata_rawIn_normDist_T_86; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_88 = _wdata_rawIn_normDist_T_37 ? 6'hE : _wdata_rawIn_normDist_T_87; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_89 = _wdata_rawIn_normDist_T_38 ? 6'hD : _wdata_rawIn_normDist_T_88; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_90 = _wdata_rawIn_normDist_T_39 ? 6'hC : _wdata_rawIn_normDist_T_89; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_91 = _wdata_rawIn_normDist_T_40 ? 6'hB : _wdata_rawIn_normDist_T_90; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_92 = _wdata_rawIn_normDist_T_41 ? 6'hA : _wdata_rawIn_normDist_T_91; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_93 = _wdata_rawIn_normDist_T_42 ? 6'h9 : _wdata_rawIn_normDist_T_92; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_94 = _wdata_rawIn_normDist_T_43 ? 6'h8 : _wdata_rawIn_normDist_T_93; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_95 = _wdata_rawIn_normDist_T_44 ? 6'h7 : _wdata_rawIn_normDist_T_94; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_96 = _wdata_rawIn_normDist_T_45 ? 6'h6 : _wdata_rawIn_normDist_T_95; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_97 = _wdata_rawIn_normDist_T_46 ? 6'h5 : _wdata_rawIn_normDist_T_96; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_98 = _wdata_rawIn_normDist_T_47 ? 6'h4 : _wdata_rawIn_normDist_T_97; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_99 = _wdata_rawIn_normDist_T_48 ? 6'h3 : _wdata_rawIn_normDist_T_98; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_100 = _wdata_rawIn_normDist_T_49 ? 6'h2 : _wdata_rawIn_normDist_T_99; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_normDist_T_101 = _wdata_rawIn_normDist_T_50 ? 6'h1 : _wdata_rawIn_normDist_T_100; // @[Mux.scala:50:70] wire [5:0] wdata_rawIn_normDist = _wdata_rawIn_normDist_T_51 ? 6'h0 : _wdata_rawIn_normDist_T_101; // @[Mux.scala:50:70] wire [114:0] _wdata_rawIn_subnormFract_T = {63'h0, wdata_rawIn_fractIn} << wdata_rawIn_normDist; // @[Mux.scala:50:70] wire [50:0] _wdata_rawIn_subnormFract_T_1 = _wdata_rawIn_subnormFract_T[50:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [51:0] wdata_rawIn_subnormFract = {_wdata_rawIn_subnormFract_T_1, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [11:0] _wdata_rawIn_adjustedExp_T = {6'h3F, ~wdata_rawIn_normDist}; // @[Mux.scala:50:70] wire [11:0] _wdata_rawIn_adjustedExp_T_1 = wdata_rawIn_isZeroExpIn ? _wdata_rawIn_adjustedExp_T : {1'h0, wdata_rawIn_expIn}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _wdata_rawIn_adjustedExp_T_2 = wdata_rawIn_isZeroExpIn ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [10:0] _wdata_rawIn_adjustedExp_T_3 = {9'h100, _wdata_rawIn_adjustedExp_T_2}; // @[rawFloatFromFN.scala:58:{9,14}] wire [12:0] _wdata_rawIn_adjustedExp_T_4 = {1'h0, _wdata_rawIn_adjustedExp_T_1} + {2'h0, _wdata_rawIn_adjustedExp_T_3}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [11:0] wdata_rawIn_adjustedExp = _wdata_rawIn_adjustedExp_T_4[11:0]; // @[rawFloatFromFN.scala:57:9] wire [11:0] _wdata_rawIn_out_sExp_T = wdata_rawIn_adjustedExp; // @[rawFloatFromFN.scala:57:9, :68:28] wire wdata_rawIn_isZero = wdata_rawIn_isZeroExpIn & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire wdata_rawIn_isZero_0 = wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _wdata_rawIn_isSpecial_T = wdata_rawIn_adjustedExp[11:10]; // @[rawFloatFromFN.scala:57:9, :61:32] wire wdata_rawIn_isSpecial = &_wdata_rawIn_isSpecial_T; // @[rawFloatFromFN.scala:61:{32,57}] wire _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:64:28] wire _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:65:28] wire _wdata_T_9 = wdata_rawIn_isNaN; // @[recFNFromFN.scala:49:20] wire [12:0] _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:68:42] wire [53:0] _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:70:27] wire wdata_rawIn_isInf; // @[rawFloatFromFN.scala:63:19] wire [12:0] wdata_rawIn_sExp; // @[rawFloatFromFN.scala:63:19] wire [53:0] wdata_rawIn_sig; // @[rawFloatFromFN.scala:63:19] wire _wdata_rawIn_out_isNaN_T = ~wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :64:31] assign _wdata_rawIn_out_isNaN_T_1 = wdata_rawIn_isSpecial & _wdata_rawIn_out_isNaN_T; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign wdata_rawIn_isNaN = _wdata_rawIn_out_isNaN_T_1; // @[rawFloatFromFN.scala:63:19, :64:28] assign _wdata_rawIn_out_isInf_T = wdata_rawIn_isSpecial & wdata_rawIn_isZeroFractIn; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign wdata_rawIn_isInf = _wdata_rawIn_out_isInf_T; // @[rawFloatFromFN.scala:63:19, :65:28] assign _wdata_rawIn_out_sExp_T_1 = {1'h0, _wdata_rawIn_out_sExp_T}; // @[rawFloatFromFN.scala:68:{28,42}] assign wdata_rawIn_sExp = _wdata_rawIn_out_sExp_T_1; // @[rawFloatFromFN.scala:63:19, :68:42] wire _wdata_rawIn_out_sig_T = ~wdata_rawIn_isZero; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _wdata_rawIn_out_sig_T_1 = {1'h0, _wdata_rawIn_out_sig_T}; // @[rawFloatFromFN.scala:70:{16,19}] wire [51:0] _wdata_rawIn_out_sig_T_2 = wdata_rawIn_isZeroExpIn ? wdata_rawIn_subnormFract : wdata_rawIn_fractIn; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _wdata_rawIn_out_sig_T_3 = {_wdata_rawIn_out_sig_T_1, _wdata_rawIn_out_sig_T_2}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign wdata_rawIn_sig = _wdata_rawIn_out_sig_T_3; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _wdata_T_7 = wdata_rawIn_sExp[11:9]; // @[recFNFromFN.scala:48:50] wire [2:0] _wdata_T_8 = wdata_rawIn_isZero_0 ? 3'h0 : _wdata_T_7; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _wdata_T_10 = {_wdata_T_8[2:1], _wdata_T_8[0] | _wdata_T_9}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _wdata_T_11 = {wdata_rawIn_sign_0, _wdata_T_10}; // @[recFNFromFN.scala:47:20, :48:76] wire [8:0] _wdata_T_12 = wdata_rawIn_sExp[8:0]; // @[recFNFromFN.scala:50:23] wire [12:0] _wdata_T_13 = {_wdata_T_11, _wdata_T_12}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [51:0] _wdata_T_14 = wdata_rawIn_sig[51:0]; // @[recFNFromFN.scala:51:22] wire [64:0] _wdata_T_15 = {_wdata_T_13, _wdata_T_14}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire wdata_rawIn_sign_1 = _wdata_T_6[31]; // @[FPU.scala:431:23] wire wdata_rawIn_1_sign = wdata_rawIn_sign_1; // @[rawFloatFromFN.scala:44:18, :63:19] wire [7:0] wdata_rawIn_expIn_1 = _wdata_T_6[30:23]; // @[FPU.scala:431:23] wire [22:0] wdata_rawIn_fractIn_1 = _wdata_T_6[22:0]; // @[FPU.scala:431:23] wire wdata_rawIn_isZeroExpIn_1 = wdata_rawIn_expIn_1 == 8'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire wdata_rawIn_isZeroFractIn_1 = wdata_rawIn_fractIn_1 == 23'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _wdata_rawIn_normDist_T_102 = wdata_rawIn_fractIn_1[0]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_103 = wdata_rawIn_fractIn_1[1]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_104 = wdata_rawIn_fractIn_1[2]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_105 = wdata_rawIn_fractIn_1[3]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_106 = wdata_rawIn_fractIn_1[4]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_107 = wdata_rawIn_fractIn_1[5]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_108 = wdata_rawIn_fractIn_1[6]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_109 = wdata_rawIn_fractIn_1[7]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_110 = wdata_rawIn_fractIn_1[8]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_111 = wdata_rawIn_fractIn_1[9]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_112 = wdata_rawIn_fractIn_1[10]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_113 = wdata_rawIn_fractIn_1[11]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_114 = wdata_rawIn_fractIn_1[12]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_115 = wdata_rawIn_fractIn_1[13]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_116 = wdata_rawIn_fractIn_1[14]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_117 = wdata_rawIn_fractIn_1[15]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_118 = wdata_rawIn_fractIn_1[16]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_119 = wdata_rawIn_fractIn_1[17]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_120 = wdata_rawIn_fractIn_1[18]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_121 = wdata_rawIn_fractIn_1[19]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_122 = wdata_rawIn_fractIn_1[20]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_123 = wdata_rawIn_fractIn_1[21]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_124 = wdata_rawIn_fractIn_1[22]; // @[rawFloatFromFN.scala:46:21] wire [4:0] _wdata_rawIn_normDist_T_125 = _wdata_rawIn_normDist_T_103 ? 5'h15 : 5'h16; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_126 = _wdata_rawIn_normDist_T_104 ? 5'h14 : _wdata_rawIn_normDist_T_125; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_127 = _wdata_rawIn_normDist_T_105 ? 5'h13 : _wdata_rawIn_normDist_T_126; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_128 = _wdata_rawIn_normDist_T_106 ? 5'h12 : _wdata_rawIn_normDist_T_127; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_129 = _wdata_rawIn_normDist_T_107 ? 5'h11 : _wdata_rawIn_normDist_T_128; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_130 = _wdata_rawIn_normDist_T_108 ? 5'h10 : _wdata_rawIn_normDist_T_129; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_131 = _wdata_rawIn_normDist_T_109 ? 5'hF : _wdata_rawIn_normDist_T_130; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_132 = _wdata_rawIn_normDist_T_110 ? 5'hE : _wdata_rawIn_normDist_T_131; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_133 = _wdata_rawIn_normDist_T_111 ? 5'hD : _wdata_rawIn_normDist_T_132; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_134 = _wdata_rawIn_normDist_T_112 ? 5'hC : _wdata_rawIn_normDist_T_133; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_135 = _wdata_rawIn_normDist_T_113 ? 5'hB : _wdata_rawIn_normDist_T_134; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_136 = _wdata_rawIn_normDist_T_114 ? 5'hA : _wdata_rawIn_normDist_T_135; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_137 = _wdata_rawIn_normDist_T_115 ? 5'h9 : _wdata_rawIn_normDist_T_136; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_138 = _wdata_rawIn_normDist_T_116 ? 5'h8 : _wdata_rawIn_normDist_T_137; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_139 = _wdata_rawIn_normDist_T_117 ? 5'h7 : _wdata_rawIn_normDist_T_138; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_140 = _wdata_rawIn_normDist_T_118 ? 5'h6 : _wdata_rawIn_normDist_T_139; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_141 = _wdata_rawIn_normDist_T_119 ? 5'h5 : _wdata_rawIn_normDist_T_140; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_142 = _wdata_rawIn_normDist_T_120 ? 5'h4 : _wdata_rawIn_normDist_T_141; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_143 = _wdata_rawIn_normDist_T_121 ? 5'h3 : _wdata_rawIn_normDist_T_142; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_144 = _wdata_rawIn_normDist_T_122 ? 5'h2 : _wdata_rawIn_normDist_T_143; // @[Mux.scala:50:70] wire [4:0] _wdata_rawIn_normDist_T_145 = _wdata_rawIn_normDist_T_123 ? 5'h1 : _wdata_rawIn_normDist_T_144; // @[Mux.scala:50:70] wire [4:0] wdata_rawIn_normDist_1 = _wdata_rawIn_normDist_T_124 ? 5'h0 : _wdata_rawIn_normDist_T_145; // @[Mux.scala:50:70] wire [53:0] _wdata_rawIn_subnormFract_T_2 = {31'h0, wdata_rawIn_fractIn_1} << wdata_rawIn_normDist_1; // @[Mux.scala:50:70] wire [21:0] _wdata_rawIn_subnormFract_T_3 = _wdata_rawIn_subnormFract_T_2[21:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [22:0] wdata_rawIn_subnormFract_1 = {_wdata_rawIn_subnormFract_T_3, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [8:0] _wdata_rawIn_adjustedExp_T_5 = {4'hF, ~wdata_rawIn_normDist_1}; // @[Mux.scala:50:70] wire [8:0] _wdata_rawIn_adjustedExp_T_6 = wdata_rawIn_isZeroExpIn_1 ? _wdata_rawIn_adjustedExp_T_5 : {1'h0, wdata_rawIn_expIn_1}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _wdata_rawIn_adjustedExp_T_7 = wdata_rawIn_isZeroExpIn_1 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [7:0] _wdata_rawIn_adjustedExp_T_8 = {6'h20, _wdata_rawIn_adjustedExp_T_7}; // @[rawFloatFromFN.scala:58:{9,14}] wire [9:0] _wdata_rawIn_adjustedExp_T_9 = {1'h0, _wdata_rawIn_adjustedExp_T_6} + {2'h0, _wdata_rawIn_adjustedExp_T_8}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [8:0] wdata_rawIn_adjustedExp_1 = _wdata_rawIn_adjustedExp_T_9[8:0]; // @[rawFloatFromFN.scala:57:9] wire [8:0] _wdata_rawIn_out_sExp_T_2 = wdata_rawIn_adjustedExp_1; // @[rawFloatFromFN.scala:57:9, :68:28] wire wdata_rawIn_isZero_1 = wdata_rawIn_isZeroExpIn_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire wdata_rawIn_1_isZero = wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _wdata_rawIn_isSpecial_T_1 = wdata_rawIn_adjustedExp_1[8:7]; // @[rawFloatFromFN.scala:57:9, :61:32] wire wdata_rawIn_isSpecial_1 = &_wdata_rawIn_isSpecial_T_1; // @[rawFloatFromFN.scala:61:{32,57}] wire _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:64:28] wire _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:65:28] wire _wdata_T_18 = wdata_rawIn_1_isNaN; // @[recFNFromFN.scala:49:20] wire [9:0] _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:68:42] wire [24:0] _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:70:27] wire wdata_rawIn_1_isInf; // @[rawFloatFromFN.scala:63:19] wire [9:0] wdata_rawIn_1_sExp; // @[rawFloatFromFN.scala:63:19] wire [24:0] wdata_rawIn_1_sig; // @[rawFloatFromFN.scala:63:19] wire _wdata_rawIn_out_isNaN_T_2 = ~wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :64:31] assign _wdata_rawIn_out_isNaN_T_3 = wdata_rawIn_isSpecial_1 & _wdata_rawIn_out_isNaN_T_2; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign wdata_rawIn_1_isNaN = _wdata_rawIn_out_isNaN_T_3; // @[rawFloatFromFN.scala:63:19, :64:28] assign _wdata_rawIn_out_isInf_T_1 = wdata_rawIn_isSpecial_1 & wdata_rawIn_isZeroFractIn_1; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign wdata_rawIn_1_isInf = _wdata_rawIn_out_isInf_T_1; // @[rawFloatFromFN.scala:63:19, :65:28] assign _wdata_rawIn_out_sExp_T_3 = {1'h0, _wdata_rawIn_out_sExp_T_2}; // @[rawFloatFromFN.scala:68:{28,42}] assign wdata_rawIn_1_sExp = _wdata_rawIn_out_sExp_T_3; // @[rawFloatFromFN.scala:63:19, :68:42] wire _wdata_rawIn_out_sig_T_4 = ~wdata_rawIn_isZero_1; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _wdata_rawIn_out_sig_T_5 = {1'h0, _wdata_rawIn_out_sig_T_4}; // @[rawFloatFromFN.scala:70:{16,19}] wire [22:0] _wdata_rawIn_out_sig_T_6 = wdata_rawIn_isZeroExpIn_1 ? wdata_rawIn_subnormFract_1 : wdata_rawIn_fractIn_1; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _wdata_rawIn_out_sig_T_7 = {_wdata_rawIn_out_sig_T_5, _wdata_rawIn_out_sig_T_6}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign wdata_rawIn_1_sig = _wdata_rawIn_out_sig_T_7; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _wdata_T_16 = wdata_rawIn_1_sExp[8:6]; // @[recFNFromFN.scala:48:50] wire [2:0] _wdata_T_17 = wdata_rawIn_1_isZero ? 3'h0 : _wdata_T_16; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _wdata_T_19 = {_wdata_T_17[2:1], _wdata_T_17[0] | _wdata_T_18}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _wdata_T_20 = {wdata_rawIn_1_sign, _wdata_T_19}; // @[recFNFromFN.scala:47:20, :48:76] wire [5:0] _wdata_T_21 = wdata_rawIn_1_sExp[5:0]; // @[recFNFromFN.scala:50:23] wire [9:0] _wdata_T_22 = {_wdata_T_20, _wdata_T_21}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [22:0] _wdata_T_23 = wdata_rawIn_1_sig[22:0]; // @[recFNFromFN.scala:51:22] wire [32:0] _wdata_T_24 = {_wdata_T_22, _wdata_T_23}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire wdata_rawIn_sign_2 = _wdata_T_6[15]; // @[FPU.scala:431:23] wire wdata_rawIn_2_sign = wdata_rawIn_sign_2; // @[rawFloatFromFN.scala:44:18, :63:19] wire [4:0] wdata_rawIn_expIn_2 = _wdata_T_6[14:10]; // @[FPU.scala:431:23] wire [9:0] wdata_rawIn_fractIn_2 = _wdata_T_6[9:0]; // @[FPU.scala:431:23] wire wdata_rawIn_isZeroExpIn_2 = wdata_rawIn_expIn_2 == 5'h0; // @[rawFloatFromFN.scala:45:19, :48:30] wire wdata_rawIn_isZeroFractIn_2 = wdata_rawIn_fractIn_2 == 10'h0; // @[rawFloatFromFN.scala:46:21, :49:34] wire _wdata_rawIn_normDist_T_146 = wdata_rawIn_fractIn_2[0]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_147 = wdata_rawIn_fractIn_2[1]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_148 = wdata_rawIn_fractIn_2[2]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_149 = wdata_rawIn_fractIn_2[3]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_150 = wdata_rawIn_fractIn_2[4]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_151 = wdata_rawIn_fractIn_2[5]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_152 = wdata_rawIn_fractIn_2[6]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_153 = wdata_rawIn_fractIn_2[7]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_154 = wdata_rawIn_fractIn_2[8]; // @[rawFloatFromFN.scala:46:21] wire _wdata_rawIn_normDist_T_155 = wdata_rawIn_fractIn_2[9]; // @[rawFloatFromFN.scala:46:21] wire [3:0] _wdata_rawIn_normDist_T_156 = {3'h4, ~_wdata_rawIn_normDist_T_147}; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_157 = _wdata_rawIn_normDist_T_148 ? 4'h7 : _wdata_rawIn_normDist_T_156; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_158 = _wdata_rawIn_normDist_T_149 ? 4'h6 : _wdata_rawIn_normDist_T_157; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_159 = _wdata_rawIn_normDist_T_150 ? 4'h5 : _wdata_rawIn_normDist_T_158; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_160 = _wdata_rawIn_normDist_T_151 ? 4'h4 : _wdata_rawIn_normDist_T_159; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_161 = _wdata_rawIn_normDist_T_152 ? 4'h3 : _wdata_rawIn_normDist_T_160; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_162 = _wdata_rawIn_normDist_T_153 ? 4'h2 : _wdata_rawIn_normDist_T_161; // @[Mux.scala:50:70] wire [3:0] _wdata_rawIn_normDist_T_163 = _wdata_rawIn_normDist_T_154 ? 4'h1 : _wdata_rawIn_normDist_T_162; // @[Mux.scala:50:70] wire [3:0] wdata_rawIn_normDist_2 = _wdata_rawIn_normDist_T_155 ? 4'h0 : _wdata_rawIn_normDist_T_163; // @[Mux.scala:50:70] wire [24:0] _wdata_rawIn_subnormFract_T_4 = {15'h0, wdata_rawIn_fractIn_2} << wdata_rawIn_normDist_2; // @[Mux.scala:50:70] wire [8:0] _wdata_rawIn_subnormFract_T_5 = _wdata_rawIn_subnormFract_T_4[8:0]; // @[rawFloatFromFN.scala:52:{33,46}] wire [9:0] wdata_rawIn_subnormFract_2 = {_wdata_rawIn_subnormFract_T_5, 1'h0}; // @[rawFloatFromFN.scala:52:{46,64}] wire [5:0] _wdata_rawIn_adjustedExp_T_10 = {2'h3, ~wdata_rawIn_normDist_2}; // @[Mux.scala:50:70] wire [5:0] _wdata_rawIn_adjustedExp_T_11 = wdata_rawIn_isZeroExpIn_2 ? _wdata_rawIn_adjustedExp_T_10 : {1'h0, wdata_rawIn_expIn_2}; // @[rawFloatFromFN.scala:45:19, :48:30, :54:10, :55:18] wire [1:0] _wdata_rawIn_adjustedExp_T_12 = wdata_rawIn_isZeroExpIn_2 ? 2'h2 : 2'h1; // @[rawFloatFromFN.scala:48:30, :58:14] wire [4:0] _wdata_rawIn_adjustedExp_T_13 = {3'h4, _wdata_rawIn_adjustedExp_T_12}; // @[rawFloatFromFN.scala:58:{9,14}] wire [6:0] _wdata_rawIn_adjustedExp_T_14 = {1'h0, _wdata_rawIn_adjustedExp_T_11} + {2'h0, _wdata_rawIn_adjustedExp_T_13}; // @[rawFloatFromFN.scala:54:10, :57:9, :58:9] wire [5:0] wdata_rawIn_adjustedExp_2 = _wdata_rawIn_adjustedExp_T_14[5:0]; // @[rawFloatFromFN.scala:57:9] wire [5:0] _wdata_rawIn_out_sExp_T_4 = wdata_rawIn_adjustedExp_2; // @[rawFloatFromFN.scala:57:9, :68:28] wire wdata_rawIn_isZero_2 = wdata_rawIn_isZeroExpIn_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:48:30, :49:34, :60:30] wire wdata_rawIn_2_isZero = wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :63:19] wire [1:0] _wdata_rawIn_isSpecial_T_2 = wdata_rawIn_adjustedExp_2[5:4]; // @[rawFloatFromFN.scala:57:9, :61:32] wire wdata_rawIn_isSpecial_2 = &_wdata_rawIn_isSpecial_T_2; // @[rawFloatFromFN.scala:61:{32,57}] wire _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:64:28] wire _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:65:28] wire _wdata_T_27 = wdata_rawIn_2_isNaN; // @[recFNFromFN.scala:49:20] wire [6:0] _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:68:42] wire [11:0] _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:70:27] wire wdata_rawIn_2_isInf; // @[rawFloatFromFN.scala:63:19] wire [6:0] wdata_rawIn_2_sExp; // @[rawFloatFromFN.scala:63:19] wire [11:0] wdata_rawIn_2_sig; // @[rawFloatFromFN.scala:63:19] wire _wdata_rawIn_out_isNaN_T_4 = ~wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :64:31] assign _wdata_rawIn_out_isNaN_T_5 = wdata_rawIn_isSpecial_2 & _wdata_rawIn_out_isNaN_T_4; // @[rawFloatFromFN.scala:61:57, :64:{28,31}] assign wdata_rawIn_2_isNaN = _wdata_rawIn_out_isNaN_T_5; // @[rawFloatFromFN.scala:63:19, :64:28] assign _wdata_rawIn_out_isInf_T_2 = wdata_rawIn_isSpecial_2 & wdata_rawIn_isZeroFractIn_2; // @[rawFloatFromFN.scala:49:34, :61:57, :65:28] assign wdata_rawIn_2_isInf = _wdata_rawIn_out_isInf_T_2; // @[rawFloatFromFN.scala:63:19, :65:28] assign _wdata_rawIn_out_sExp_T_5 = {1'h0, _wdata_rawIn_out_sExp_T_4}; // @[rawFloatFromFN.scala:68:{28,42}] assign wdata_rawIn_2_sExp = _wdata_rawIn_out_sExp_T_5; // @[rawFloatFromFN.scala:63:19, :68:42] wire _wdata_rawIn_out_sig_T_8 = ~wdata_rawIn_isZero_2; // @[rawFloatFromFN.scala:60:30, :70:19] wire [1:0] _wdata_rawIn_out_sig_T_9 = {1'h0, _wdata_rawIn_out_sig_T_8}; // @[rawFloatFromFN.scala:70:{16,19}] wire [9:0] _wdata_rawIn_out_sig_T_10 = wdata_rawIn_isZeroExpIn_2 ? wdata_rawIn_subnormFract_2 : wdata_rawIn_fractIn_2; // @[rawFloatFromFN.scala:46:21, :48:30, :52:64, :70:33] assign _wdata_rawIn_out_sig_T_11 = {_wdata_rawIn_out_sig_T_9, _wdata_rawIn_out_sig_T_10}; // @[rawFloatFromFN.scala:70:{16,27,33}] assign wdata_rawIn_2_sig = _wdata_rawIn_out_sig_T_11; // @[rawFloatFromFN.scala:63:19, :70:27] wire [2:0] _wdata_T_25 = wdata_rawIn_2_sExp[5:3]; // @[recFNFromFN.scala:48:50] wire [2:0] _wdata_T_26 = wdata_rawIn_2_isZero ? 3'h0 : _wdata_T_25; // @[recFNFromFN.scala:48:{15,50}] wire [2:0] _wdata_T_28 = {_wdata_T_26[2:1], _wdata_T_26[0] | _wdata_T_27}; // @[recFNFromFN.scala:48:{15,76}, :49:20] wire [3:0] _wdata_T_29 = {wdata_rawIn_2_sign, _wdata_T_28}; // @[recFNFromFN.scala:47:20, :48:76] wire [2:0] _wdata_T_30 = wdata_rawIn_2_sExp[2:0]; // @[recFNFromFN.scala:50:23] wire [6:0] _wdata_T_31 = {_wdata_T_29, _wdata_T_30}; // @[recFNFromFN.scala:47:20, :49:45, :50:23] wire [9:0] _wdata_T_32 = wdata_rawIn_2_sig[9:0]; // @[recFNFromFN.scala:51:22] wire [16:0] _wdata_T_33 = {_wdata_T_31, _wdata_T_32}; // @[recFNFromFN.scala:49:45, :50:41, :51:22] wire [3:0] _wdata_swizzledNaN_T = _wdata_T_24[32:29]; // @[FPU.scala:337:8] wire [6:0] _wdata_swizzledNaN_T_1 = _wdata_T_24[22:16]; // @[FPU.scala:338:8] wire [6:0] _wdata_swizzledNaN_T_5 = _wdata_T_24[22:16]; // @[FPU.scala:338:8, :341:8] wire _wdata_swizzledNaN_T_2 = &_wdata_swizzledNaN_T_1; // @[FPU.scala:338:{8,42}] wire [3:0] _wdata_swizzledNaN_T_3 = _wdata_T_24[27:24]; // @[FPU.scala:339:8] wire _wdata_swizzledNaN_T_4 = _wdata_T_33[15]; // @[FPU.scala:340:8] wire _wdata_swizzledNaN_T_6 = _wdata_T_33[16]; // @[FPU.scala:342:8] wire [14:0] _wdata_swizzledNaN_T_7 = _wdata_T_33[14:0]; // @[FPU.scala:343:8] wire [7:0] wdata_swizzledNaN_lo_hi = {_wdata_swizzledNaN_T_5, _wdata_swizzledNaN_T_6}; // @[FPU.scala:336:26, :341:8, :342:8] wire [22:0] wdata_swizzledNaN_lo = {wdata_swizzledNaN_lo_hi, _wdata_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [4:0] wdata_swizzledNaN_hi_lo = {_wdata_swizzledNaN_T_3, _wdata_swizzledNaN_T_4}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] wdata_swizzledNaN_hi_hi = {_wdata_swizzledNaN_T, _wdata_swizzledNaN_T_2}; // @[FPU.scala:336:26, :337:8, :338:42] wire [9:0] wdata_swizzledNaN_hi = {wdata_swizzledNaN_hi_hi, wdata_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] wdata_swizzledNaN = {wdata_swizzledNaN_hi, wdata_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [2:0] _wdata_T_34 = _wdata_T_24[31:29]; // @[FPU.scala:249:25] wire _wdata_T_35 = &_wdata_T_34; // @[FPU.scala:249:{25,56}] wire [32:0] _wdata_T_36 = _wdata_T_35 ? wdata_swizzledNaN : _wdata_T_24; // @[FPU.scala:249:56, :336:26, :344:8] wire [3:0] _wdata_swizzledNaN_T_8 = _wdata_T_15[64:61]; // @[FPU.scala:337:8] wire [19:0] _wdata_swizzledNaN_T_9 = _wdata_T_15[51:32]; // @[FPU.scala:338:8] wire [19:0] _wdata_swizzledNaN_T_13 = _wdata_T_15[51:32]; // @[FPU.scala:338:8, :341:8] wire _wdata_swizzledNaN_T_10 = &_wdata_swizzledNaN_T_9; // @[FPU.scala:338:{8,42}] wire [6:0] _wdata_swizzledNaN_T_11 = _wdata_T_15[59:53]; // @[FPU.scala:339:8] wire _wdata_swizzledNaN_T_12 = _wdata_T_36[31]; // @[FPU.scala:340:8, :344:8] wire _wdata_swizzledNaN_T_14 = _wdata_T_36[32]; // @[FPU.scala:342:8, :344:8] wire [30:0] _wdata_swizzledNaN_T_15 = _wdata_T_36[30:0]; // @[FPU.scala:343:8, :344:8] wire [20:0] wdata_swizzledNaN_lo_hi_1 = {_wdata_swizzledNaN_T_13, _wdata_swizzledNaN_T_14}; // @[FPU.scala:336:26, :341:8, :342:8] wire [51:0] wdata_swizzledNaN_lo_1 = {wdata_swizzledNaN_lo_hi_1, _wdata_swizzledNaN_T_15}; // @[FPU.scala:336:26, :343:8] wire [7:0] wdata_swizzledNaN_hi_lo_1 = {_wdata_swizzledNaN_T_11, _wdata_swizzledNaN_T_12}; // @[FPU.scala:336:26, :339:8, :340:8] wire [4:0] wdata_swizzledNaN_hi_hi_1 = {_wdata_swizzledNaN_T_8, _wdata_swizzledNaN_T_10}; // @[FPU.scala:336:26, :337:8, :338:42] wire [12:0] wdata_swizzledNaN_hi_1 = {wdata_swizzledNaN_hi_hi_1, wdata_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] wdata_swizzledNaN_1 = {wdata_swizzledNaN_hi_1, wdata_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [2:0] _wdata_T_37 = _wdata_T_15[63:61]; // @[FPU.scala:249:25] wire _wdata_T_38 = &_wdata_T_37; // @[FPU.scala:249:{25,56}] wire [64:0] wdata = _wdata_T_38 ? wdata_swizzledNaN_1 : _wdata_T_15; // @[FPU.scala:249:56, :336:26, :344:8] wire _unswizzled_T = wdata[31]; // @[FPU.scala:344:8, :381:10] wire _frfWriteBundle_0_wrdata_prevRecoded_T = wdata[31]; // @[FPU.scala:344:8, :381:10, :442:10] wire _unswizzled_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10] wire _frfWriteBundle_0_wrdata_prevRecoded_T_1 = wdata[52]; // @[FPU.scala:344:8, :382:10, :443:10] wire [30:0] _unswizzled_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10] wire [30:0] _frfWriteBundle_0_wrdata_prevRecoded_T_2 = wdata[30:0]; // @[FPU.scala:344:8, :383:10, :444:10] wire [1:0] unswizzled_hi = {_unswizzled_T, _unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10] wire [32:0] unswizzled = {unswizzled_hi, _unswizzled_T_2}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_T = wdata[64:60]; // @[FPU.scala:332:49, :344:8] wire _prevOK_T_1 = &_prevOK_T; // @[FPU.scala:332:{49,84}] wire _prevOK_T_2 = ~_prevOK_T_1; // @[FPU.scala:332:84, :384:20] wire _prevOK_unswizzled_T = unswizzled[15]; // @[FPU.scala:380:27, :381:10] wire _prevOK_unswizzled_T_1 = unswizzled[23]; // @[FPU.scala:380:27, :382:10] wire [14:0] _prevOK_unswizzled_T_2 = unswizzled[14:0]; // @[FPU.scala:380:27, :383:10] wire [1:0] prevOK_unswizzled_hi = {_prevOK_unswizzled_T, _prevOK_unswizzled_T_1}; // @[FPU.scala:380:27, :381:10, :382:10] wire [16:0] prevOK_unswizzled = {prevOK_unswizzled_hi, _prevOK_unswizzled_T_2}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_prevOK_T = unswizzled[32:28]; // @[FPU.scala:332:49, :380:27] wire _prevOK_prevOK_T_1 = &_prevOK_prevOK_T; // @[FPU.scala:332:{49,84}] wire _prevOK_prevOK_T_2 = ~_prevOK_prevOK_T_1; // @[FPU.scala:332:84, :384:20] wire [2:0] _prevOK_curOK_T = unswizzled[31:29]; // @[FPU.scala:249:25, :380:27] wire _prevOK_curOK_T_1 = &_prevOK_curOK_T; // @[FPU.scala:249:{25,56}] wire _prevOK_curOK_T_2 = ~_prevOK_curOK_T_1; // @[FPU.scala:249:56, :385:19] wire _prevOK_curOK_T_3 = unswizzled[28]; // @[FPU.scala:380:27, :385:35] wire [6:0] _prevOK_curOK_T_4 = unswizzled[22:16]; // @[FPU.scala:380:27, :385:60] wire _prevOK_curOK_T_5 = &_prevOK_curOK_T_4; // @[FPU.scala:385:{60,96}] wire _prevOK_curOK_T_6 = _prevOK_curOK_T_3 == _prevOK_curOK_T_5; // @[FPU.scala:385:{35,55,96}] wire prevOK_curOK = _prevOK_curOK_T_2 | _prevOK_curOK_T_6; // @[FPU.scala:385:{19,31,55}] wire _prevOK_T_3 = prevOK_curOK; // @[FPU.scala:385:31, :386:14] wire prevOK = _prevOK_T_2 | _prevOK_T_3; // @[FPU.scala:384:{20,33}, :386:14] wire [2:0] _curOK_T = wdata[63:61]; // @[FPU.scala:249:25, :344:8] wire [2:0] _frfWriteBundle_0_wrdata_T_1 = wdata[63:61]; // @[FPU.scala:249:25, :344:8] wire _curOK_T_1 = &_curOK_T; // @[FPU.scala:249:{25,56}] wire _curOK_T_2 = ~_curOK_T_1; // @[FPU.scala:249:56, :385:19] wire _curOK_T_3 = wdata[60]; // @[FPU.scala:344:8, :385:35] wire [19:0] _curOK_T_4 = wdata[51:32]; // @[FPU.scala:344:8, :385:60] wire _curOK_T_5 = &_curOK_T_4; // @[FPU.scala:385:{60,96}] wire _curOK_T_6 = _curOK_T_3 == _curOK_T_5; // @[FPU.scala:385:{35,55,96}] wire curOK = _curOK_T_2 | _curOK_T_6; // @[FPU.scala:385:{19,31,55}] wire [11:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_exp = wdata[63:52]; // @[FPU.scala:344:8] wire [2:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] frfWriteBundle_0_wrdata_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T = wdata[64]; // @[FPU.scala:344:8] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2 = wdata[51:0]; // @[FPU.scala:344:8] assign _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign frfWriteBundle_0_wrdata_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire frfWriteBundle_0_wrdata_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] frfWriteBundle_0_wrdata_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] frfWriteBundle_0_wrdata_unrecoded_denormFract = _frfWriteBundle_0_wrdata_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? 11'h0 : _frfWriteBundle_0_wrdata_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _frfWriteBundle_0_wrdata_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5 = {11{_frfWriteBundle_0_wrdata_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] frfWriteBundle_0_wrdata_unrecoded_expOut = _frfWriteBundle_0_wrdata_unrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_unrecoded_rawIn_isInf ? 52'h0 : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] frfWriteBundle_0_wrdata_unrecoded_fractOut = frfWriteBundle_0_wrdata_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_unrecoded_denormFract : _frfWriteBundle_0_wrdata_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] frfWriteBundle_0_wrdata_unrecoded_hi = {frfWriteBundle_0_wrdata_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] frfWriteBundle_0_wrdata_unrecoded = {frfWriteBundle_0_wrdata_unrecoded_hi, frfWriteBundle_0_wrdata_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] frfWriteBundle_0_wrdata_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevRecoded_T, _frfWriteBundle_0_wrdata_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] frfWriteBundle_0_wrdata_prevRecoded = {frfWriteBundle_0_wrdata_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevRecoded[32]; // @[FPU.scala:441:28] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5 = {8{_frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T = frfWriteBundle_0_wrdata_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2 = frfWriteBundle_0_wrdata_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_hi, _frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = frfWriteBundle_0_wrdata_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T >> frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2 = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isNaN | frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut = _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_3 | _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1 = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut = frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_isSubnormal ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_denormFract : _frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_rawIn_sign, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded = {frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_hi, frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_1 = frfWriteBundle_0_wrdata_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 = &_frfWriteBundle_0_wrdata_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_3 = frfWriteBundle_0_wrdata_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _frfWriteBundle_0_wrdata_prevUnrecoded_T_4 = _frfWriteBundle_0_wrdata_prevUnrecoded_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded_prevUnrecoded : _frfWriteBundle_0_wrdata_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] frfWriteBundle_0_wrdata_prevUnrecoded = {_frfWriteBundle_0_wrdata_prevUnrecoded_T, _frfWriteBundle_0_wrdata_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _frfWriteBundle_0_wrdata_T = frfWriteBundle_0_wrdata_unrecoded[63:32]; // @[FPU.scala:446:21] wire _frfWriteBundle_0_wrdata_T_2 = &_frfWriteBundle_0_wrdata_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _frfWriteBundle_0_wrdata_T_3 = frfWriteBundle_0_wrdata_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _frfWriteBundle_0_wrdata_T_4 = _frfWriteBundle_0_wrdata_T_2 ? frfWriteBundle_0_wrdata_prevUnrecoded : _frfWriteBundle_0_wrdata_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] assign _frfWriteBundle_0_wrdata_T_5 = {_frfWriteBundle_0_wrdata_T, _frfWriteBundle_0_wrdata_T_4}; // @[FPU.scala:446:{10,21,44}] assign frfWriteBundle_0_wrdata = _frfWriteBundle_0_wrdata_T_5; // @[FPU.scala:446:10, :805:44] wire [4:0] _ex_rs_T_1 = _ex_rs_T; // @[FPU.scala:832:37] wire [4:0] _ex_rs_T_3 = _ex_rs_T_2; // @[FPU.scala:832:37] wire [4:0] _ex_rs_T_5 = _ex_rs_T_4; // @[FPU.scala:832:37] wire [4:0] _ex_ra_0_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51] wire [4:0] _ex_ra_1_T = io_inst_0[19:15]; // @[FPU.scala:735:7, :835:51, :836:50] wire [4:0] _ex_ra_0_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50] wire [4:0] _ex_ra_2_T = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :840:50] wire [4:0] _ex_ra_1_T_1 = io_inst_0[24:20]; // @[FPU.scala:735:7, :839:50, :841:70] wire [4:0] _ex_ra_2_T_1 = io_inst_0[31:27]; // @[FPU.scala:735:7, :843:46] wire [2:0] _ex_rm_T = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:30] wire [2:0] _ex_rm_T_2 = ex_reg_inst[14:12]; // @[FPU.scala:768:30, :845:{30,70}] wire _ex_rm_T_1 = &_ex_rm_T; // @[FPU.scala:845:{30,38}] wire [2:0] ex_rm = _ex_rm_T_1 ? io_fcsr_rm_0 : _ex_rm_T_2; // @[FPU.scala:735:7, :845:{18,38,70}] wire [2:0] sfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire [2:0] fpiu_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire [2:0] dfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire [2:0] hfma_io_in_bits_req_rm = ex_rm; // @[FPU.scala:845:18, :848:19] wire _GEN_0 = req_valid & ex_ctrl_fma; // @[FPU.scala:780:32, :800:20, :873:33] wire _sfma_io_in_valid_T; // @[FPU.scala:873:33] assign _sfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33] wire _dfma_io_in_valid_T; // @[FPU.scala:914:41] assign _dfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :914:41] wire _hfma_io_in_valid_T; // @[FPU.scala:920:41] assign _hfma_io_in_valid_T = _GEN_0; // @[FPU.scala:873:33, :920:41] wire _GEN_1 = ex_ctrl_typeTagOut == 2'h1; // @[FPU.scala:800:20, :873:70] wire _sfma_io_in_valid_T_1; // @[FPU.scala:873:70] assign _sfma_io_in_valid_T_1 = _GEN_1; // @[FPU.scala:873:70] wire _write_port_busy_T_2; // @[FPU.scala:911:72] assign _write_port_busy_T_2 = _GEN_1; // @[FPU.scala:873:70, :911:72] wire _write_port_busy_T_20; // @[FPU.scala:911:72] assign _write_port_busy_T_20 = _GEN_1; // @[FPU.scala:873:70, :911:72] wire _sfma_io_in_valid_T_2 = _sfma_io_in_valid_T & _sfma_io_in_valid_T_1; // @[FPU.scala:873:{33,48,70}] wire [1:0] _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [1:0] _sfma_io_in_bits_req_typ_T; // @[FPU.scala:855:27] wire [1:0] _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:856:27] wire [1:0] sfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] sfma_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] sfma_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] sfma_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] sfma_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] sfma_io_in_bits_req_in3; // @[FPU.scala:848:19] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _hfma_io_in_bits_req_in1_prev_unswizzled_T = _regfile_ext_R2_data[31]; // @[FPU.scala:357:14, :818:20] wire _sfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire _dfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire _hfma_io_in_bits_req_in1_prev_unswizzled_T_1 = _regfile_ext_R2_data[52]; // @[FPU.scala:358:14, :818:20] wire [30:0] _sfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _dfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _hfma_io_in_bits_req_in1_prev_unswizzled_T_2 = _regfile_ext_R2_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [1:0] sfma_io_in_bits_req_in1_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in1_floats_1 = {sfma_io_in_bits_req_in1_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in1_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in1_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in1_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_0 = {sfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in1_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_prev_prev_0_1 = sfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [4:0] _sfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _fpiu_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _dfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _hfma_io_in_bits_req_in1_prev_isbox_T = _regfile_ext_R2_data[64:60]; // @[FPU.scala:332:49, :818:20] wire sfma_io_in_bits_req_in1_prev_isbox = &_sfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in1_oks_1 = sfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_oks_0 = sfma_io_in_bits_req_in1_prev_isbox & sfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20] wire hfma_io_in_bits_req_in1_sign = _regfile_ext_R2_data[64]; // @[FPU.scala:274:17, :818:20] wire [51:0] sfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [51:0] hfma_io_in_bits_req_in1_fractIn = _regfile_ext_R2_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [11:0] sfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [11:0] hfma_io_in_bits_req_in1_expIn = _regfile_ext_R2_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [75:0] _sfma_io_in_bits_req_in1_fractOut_T = {sfma_io_in_bits_req_in1_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in1_fractOut = _sfma_io_in_bits_req_in1_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in1_expOut_expCode = sfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in1_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in1_expOut_commonCase = _sfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in1_expOut_T = sfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in1_expOut_T_1 = sfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in1_expOut_T_2 = _sfma_io_in_bits_req_in1_expOut_T | _sfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in1_expOut_T_3 = sfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_4 = {sfma_io_in_bits_req_in1_expOut_expCode, _sfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in1_expOut_T_5 = sfma_io_in_bits_req_in1_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in1_expOut = _sfma_io_in_bits_req_in1_expOut_T_2 ? _sfma_io_in_bits_req_in1_expOut_T_4 : _sfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in1_hi = {sfma_io_in_bits_req_in1_sign, sfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in1_floats_2 = {sfma_io_in_bits_req_in1_hi, sfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in1_T = sfma_io_in_bits_req_in1_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in1_T_1 = sfma_io_in_bits_req_in1_floats_1 | _sfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in1 = {32'h0, _sfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _hfma_io_in_bits_req_in2_prev_unswizzled_T = _regfile_ext_R1_data[31]; // @[FPU.scala:357:14, :818:20] wire _sfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire _dfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire _hfma_io_in_bits_req_in2_prev_unswizzled_T_1 = _regfile_ext_R1_data[52]; // @[FPU.scala:358:14, :818:20] wire [30:0] _sfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _dfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _hfma_io_in_bits_req_in2_prev_unswizzled_T_2 = _regfile_ext_R1_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [1:0] sfma_io_in_bits_req_in2_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in2_floats_1 = {sfma_io_in_bits_req_in2_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in2_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in2_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in2_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_0 = {sfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in2_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_prev_prev_0_1 = sfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [4:0] _sfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _fpiu_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _dfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _hfma_io_in_bits_req_in2_prev_isbox_T = _regfile_ext_R1_data[64:60]; // @[FPU.scala:332:49, :818:20] wire sfma_io_in_bits_req_in2_prev_isbox = &_sfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in2_oks_1 = sfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_oks_0 = sfma_io_in_bits_req_in2_prev_isbox & sfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20] wire hfma_io_in_bits_req_in2_sign = _regfile_ext_R1_data[64]; // @[FPU.scala:274:17, :818:20] wire [51:0] sfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [51:0] hfma_io_in_bits_req_in2_fractIn = _regfile_ext_R1_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [11:0] sfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [11:0] hfma_io_in_bits_req_in2_expIn = _regfile_ext_R1_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [75:0] _sfma_io_in_bits_req_in2_fractOut_T = {sfma_io_in_bits_req_in2_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in2_fractOut = _sfma_io_in_bits_req_in2_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in2_expOut_expCode = sfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in2_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in2_expOut_commonCase = _sfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in2_expOut_T = sfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in2_expOut_T_1 = sfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in2_expOut_T_2 = _sfma_io_in_bits_req_in2_expOut_T | _sfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in2_expOut_T_3 = sfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_4 = {sfma_io_in_bits_req_in2_expOut_expCode, _sfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in2_expOut_T_5 = sfma_io_in_bits_req_in2_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in2_expOut = _sfma_io_in_bits_req_in2_expOut_T_2 ? _sfma_io_in_bits_req_in2_expOut_T_4 : _sfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in2_hi = {sfma_io_in_bits_req_in2_sign, sfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in2_floats_2 = {sfma_io_in_bits_req_in2_hi, sfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in2_T = sfma_io_in_bits_req_in2_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in2_T_1 = sfma_io_in_bits_req_in2_floats_1 | _sfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in2 = {32'h0, _sfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :853:13] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _hfma_io_in_bits_req_in3_prev_unswizzled_T = _regfile_ext_R0_data[31]; // @[FPU.scala:357:14, :818:20] wire _sfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire _dfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire _hfma_io_in_bits_req_in3_prev_unswizzled_T_1 = _regfile_ext_R0_data[52]; // @[FPU.scala:358:14, :818:20] wire [30:0] _sfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _dfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [30:0] _hfma_io_in_bits_req_in3_prev_unswizzled_T_2 = _regfile_ext_R0_data[30:0]; // @[FPU.scala:359:14, :818:20] wire [1:0] sfma_io_in_bits_req_in3_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] sfma_io_in_bits_req_in3_floats_1 = {sfma_io_in_bits_req_in3_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = sfma_io_in_bits_req_in3_floats_1[15]; // @[FPU.scala:356:31, :357:14] wire _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = sfma_io_in_bits_req_in3_floats_1[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = sfma_io_in_bits_req_in3_floats_1[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = sfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [33:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[33:11]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {4'h0, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 10'h100; // @[FPU.scala:276:18, :280:31] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 10'h20; // @[FPU.scala:280:{31,50}] wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, sfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_0 = {sfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, sfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = sfma_io_in_bits_req_in3_floats_1[32:28]; // @[FPU.scala:332:49, :356:31] wire sfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_sfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_prev_prev_0_1 = sfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire [4:0] _sfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _fpiu_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _dfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire [4:0] _hfma_io_in_bits_req_in3_prev_isbox_T = _regfile_ext_R0_data[64:60]; // @[FPU.scala:332:49, :818:20] wire sfma_io_in_bits_req_in3_prev_isbox = &_sfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire sfma_io_in_bits_req_in3_oks_1 = sfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_oks_0 = sfma_io_in_bits_req_in3_prev_isbox & sfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire sfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20] wire hfma_io_in_bits_req_in3_sign = _regfile_ext_R0_data[64]; // @[FPU.scala:274:17, :818:20] wire [51:0] sfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [51:0] hfma_io_in_bits_req_in3_fractIn = _regfile_ext_R0_data[51:0]; // @[FPU.scala:275:20, :818:20] wire [11:0] sfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [11:0] hfma_io_in_bits_req_in3_expIn = _regfile_ext_R0_data[63:52]; // @[FPU.scala:276:18, :818:20] wire [75:0] _sfma_io_in_bits_req_in3_fractOut_T = {sfma_io_in_bits_req_in3_fractIn, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] sfma_io_in_bits_req_in3_fractOut = _sfma_io_in_bits_req_in3_fractOut_T[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] sfma_io_in_bits_req_in3_expOut_expCode = sfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, sfma_io_in_bits_req_in3_expIn} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _sfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _sfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _sfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] sfma_io_in_bits_req_in3_expOut_commonCase = _sfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _sfma_io_in_bits_req_in3_expOut_T = sfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _sfma_io_in_bits_req_in3_expOut_T_1 = sfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _sfma_io_in_bits_req_in3_expOut_T_2 = _sfma_io_in_bits_req_in3_expOut_T | _sfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [5:0] _sfma_io_in_bits_req_in3_expOut_T_3 = sfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_4 = {sfma_io_in_bits_req_in3_expOut_expCode, _sfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _sfma_io_in_bits_req_in3_expOut_T_5 = sfma_io_in_bits_req_in3_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] sfma_io_in_bits_req_in3_expOut = _sfma_io_in_bits_req_in3_expOut_T_2 ? _sfma_io_in_bits_req_in3_expOut_T_4 : _sfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] sfma_io_in_bits_req_in3_hi = {sfma_io_in_bits_req_in3_sign, sfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] sfma_io_in_bits_req_in3_floats_2 = {sfma_io_in_bits_req_in3_hi, sfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [32:0] _sfma_io_in_bits_req_in3_T = sfma_io_in_bits_req_in3_oks_1 ? 33'h0 : 33'hE0400000; // @[FPU.scala:362:32, :372:31] wire [32:0] _sfma_io_in_bits_req_in3_T_1 = sfma_io_in_bits_req_in3_floats_1 | _sfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign sfma_io_in_bits_req_in3 = {32'h0, _sfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :854:13] assign _sfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] wire [1:0] _fpiu_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] wire [1:0] _dfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] wire [1:0] _hfma_io_in_bits_req_typ_T = ex_reg_inst[21:20]; // @[FPU.scala:768:30, :855:27] assign sfma_io_in_bits_req_typ = _sfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign _sfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] wire [1:0] _fpiu_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] wire [1:0] _dfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] wire [1:0] _hfma_io_in_bits_req_fmt_T = ex_reg_inst[26:25]; // @[FPU.scala:768:30, :856:27] assign sfma_io_in_bits_req_fmt = _sfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire [1:0] _sfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire [1:0] _dfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire [1:0] _hfma_io_in_bits_req_fmaCmd_T = ex_reg_inst[3:2]; // @[FPU.scala:768:30, :857:30] wire _sfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _sfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _fpiu_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _dfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _hfma_io_in_bits_req_fmaCmd_T_2 = ex_reg_inst[27]; // @[FPU.scala:768:30, :857:67] wire _sfma_io_in_bits_req_fmaCmd_T_3 = _sfma_io_in_bits_req_fmaCmd_T_1 & _sfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _sfma_io_in_bits_req_fmaCmd_T_4 = {_sfma_io_in_bits_req_fmaCmd_T[1], _sfma_io_in_bits_req_fmaCmd_T[0] | _sfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign sfma_io_in_bits_req_fmaCmd = _sfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _fpiu_io_in_valid_T = ex_ctrl_toint | ex_ctrl_div; // @[FPU.scala:800:20, :877:51] wire _fpiu_io_in_valid_T_1 = _fpiu_io_in_valid_T | ex_ctrl_sqrt; // @[FPU.scala:800:20, :877:{51,66}] wire _fpiu_io_in_valid_T_2 = ex_ctrl_fastpipe & ex_ctrl_wflags; // @[FPU.scala:800:20, :877:103] wire _fpiu_io_in_valid_T_3 = _fpiu_io_in_valid_T_1 | _fpiu_io_in_valid_T_2; // @[FPU.scala:877:{66,82,103}] wire _fpiu_io_in_valid_T_4 = req_valid & _fpiu_io_in_valid_T_3; // @[FPU.scala:780:32, :877:{33,82}] wire [1:0] _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [64:0] _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10] wire [64:0] _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10] wire [1:0] fpiu_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] fpiu_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] fpiu_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] fpiu_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] fpiu_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] fpiu_io_in_bits_req_in3; // @[FPU.scala:848:19] wire [1:0] fpiu_io_in_bits_req_in1_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in1_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_0 = {fpiu_io_in_bits_req_in1_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in1_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_prev_prev_0_1 = fpiu_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_prev_prev_sign = fpiu_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in1_prev_prev_fractIn = fpiu_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in1_prev_prev_expIn = fpiu_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in1_prev_prev_fractOut = _fpiu_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T | _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in1_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in1_prev_prev_expOut = _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in1_prev_prev_hi = {fpiu_io_in_bits_req_in1_prev_prev_sign, fpiu_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in1_floats_1 = {fpiu_io_in_bits_req_in1_prev_prev_hi, fpiu_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in1_prev_isbox = &_fpiu_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in1_oks_1 = fpiu_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in1_oks_0 = fpiu_io_in_bits_req_in1_prev_isbox & fpiu_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _GEN_2 = ex_ctrl_typeTagIn == 2'h1; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_6 = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_6 = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_6; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_6 = _GEN_2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_1 = _fpiu_io_in_bits_req_in1_T ? fpiu_io_in_bits_req_in1_oks_1 : fpiu_io_in_bits_req_in1_oks_0; // @[package.scala:39:{76,86}] wire _GEN_3 = ex_ctrl_typeTagIn == 2'h2; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_2 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in1_T_8 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_2 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in2_T_8 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_2; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_2 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_8; // @[package.scala:39:86] assign _fpiu_io_in_bits_req_in3_T_8 = _GEN_3; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_3 = _fpiu_io_in_bits_req_in1_T_2 | _fpiu_io_in_bits_req_in1_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in1_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in1_T_5 = _fpiu_io_in_bits_req_in1_T_4 | _fpiu_io_in_bits_req_in1_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in1_T_7 = _fpiu_io_in_bits_req_in1_T_6 ? fpiu_io_in_bits_req_in1_floats_1 : fpiu_io_in_bits_req_in1_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in1_T_9 = _fpiu_io_in_bits_req_in1_T_8 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_7; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in1_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire [64:0] _fpiu_io_in_bits_req_in1_T_11 = _fpiu_io_in_bits_req_in1_T_10 ? _regfile_ext_R2_data : _fpiu_io_in_bits_req_in1_T_9; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in1_T_12 = _fpiu_io_in_bits_req_in1_T_5 ? _fpiu_io_in_bits_req_in1_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in1 = _fpiu_io_in_bits_req_in1_T_12; // @[FPU.scala:369:10, :848:19] wire [1:0] fpiu_io_in_bits_req_in2_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in2_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_0 = {fpiu_io_in_bits_req_in2_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in2_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_prev_prev_0_1 = fpiu_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_prev_prev_sign = fpiu_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in2_prev_prev_fractIn = fpiu_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in2_prev_prev_expIn = fpiu_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in2_prev_prev_fractOut = _fpiu_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T | _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in2_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in2_prev_prev_expOut = _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in2_prev_prev_hi = {fpiu_io_in_bits_req_in2_prev_prev_sign, fpiu_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in2_floats_1 = {fpiu_io_in_bits_req_in2_prev_prev_hi, fpiu_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in2_prev_isbox = &_fpiu_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in2_oks_1 = fpiu_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in2_oks_0 = fpiu_io_in_bits_req_in2_prev_isbox & fpiu_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpiu_io_in_bits_req_in2_T_1 = _fpiu_io_in_bits_req_in2_T ? fpiu_io_in_bits_req_in2_oks_1 : fpiu_io_in_bits_req_in2_oks_0; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_3 = _fpiu_io_in_bits_req_in2_T_2 | _fpiu_io_in_bits_req_in2_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in2_T_5 = _fpiu_io_in_bits_req_in2_T_4 | _fpiu_io_in_bits_req_in2_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in2_T_7 = _fpiu_io_in_bits_req_in2_T_6 ? fpiu_io_in_bits_req_in2_floats_1 : fpiu_io_in_bits_req_in2_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in2_T_9 = _fpiu_io_in_bits_req_in2_T_8 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_7; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in2_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire [64:0] _fpiu_io_in_bits_req_in2_T_11 = _fpiu_io_in_bits_req_in2_T_10 ? _regfile_ext_R1_data : _fpiu_io_in_bits_req_in2_T_9; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in2_T_12 = _fpiu_io_in_bits_req_in2_T_5 ? _fpiu_io_in_bits_req_in2_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in2 = _fpiu_io_in_bits_req_in2_T_12; // @[FPU.scala:369:10, :848:19] wire [1:0] fpiu_io_in_bits_req_in3_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] fpiu_io_in_bits_req_in3_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = fpiu_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = fpiu_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = fpiu_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled = {fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_0 = {fpiu_io_in_bits_req_in3_prev_prev_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T = fpiu_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire fpiu_io_in_bits_req_in3_prev_prev_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_prev_prev_0_1 = fpiu_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_prev_prev_sign = fpiu_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] fpiu_io_in_bits_req_in3_prev_prev_fractIn = fpiu_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] fpiu_io_in_bits_req_in3_prev_prev_expIn = fpiu_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T = {fpiu_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] fpiu_io_in_bits_req_in3_prev_prev_fractOut = _fpiu_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode = fpiu_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, fpiu_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase = _fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1 = fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T | _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3 = fpiu_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 = {fpiu_io_in_bits_req_in3_prev_prev_expOut_expCode, _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] fpiu_io_in_bits_req_in3_prev_prev_expOut = _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_4 : _fpiu_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] fpiu_io_in_bits_req_in3_prev_prev_hi = {fpiu_io_in_bits_req_in3_prev_prev_sign, fpiu_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] fpiu_io_in_bits_req_in3_floats_1 = {fpiu_io_in_bits_req_in3_prev_prev_hi, fpiu_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire fpiu_io_in_bits_req_in3_prev_isbox = &_fpiu_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire fpiu_io_in_bits_req_in3_oks_1 = fpiu_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire fpiu_io_in_bits_req_in3_oks_0 = fpiu_io_in_bits_req_in3_prev_isbox & fpiu_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire _fpiu_io_in_bits_req_in3_T_1 = _fpiu_io_in_bits_req_in3_T ? fpiu_io_in_bits_req_in3_oks_1 : fpiu_io_in_bits_req_in3_oks_0; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_3 = _fpiu_io_in_bits_req_in3_T_2 | _fpiu_io_in_bits_req_in3_T_1; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_4 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire _fpiu_io_in_bits_req_in3_T_5 = _fpiu_io_in_bits_req_in3_T_4 | _fpiu_io_in_bits_req_in3_T_3; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_7 = _fpiu_io_in_bits_req_in3_T_6 ? fpiu_io_in_bits_req_in3_floats_1 : fpiu_io_in_bits_req_in3_floats_0; // @[package.scala:39:{76,86}] wire [64:0] _fpiu_io_in_bits_req_in3_T_9 = _fpiu_io_in_bits_req_in3_T_8 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_7; // @[package.scala:39:{76,86}] wire _fpiu_io_in_bits_req_in3_T_10 = &ex_ctrl_typeTagIn; // @[package.scala:39:86] wire [64:0] _fpiu_io_in_bits_req_in3_T_11 = _fpiu_io_in_bits_req_in3_T_10 ? _regfile_ext_R0_data : _fpiu_io_in_bits_req_in3_T_9; // @[package.scala:39:{76,86}] assign _fpiu_io_in_bits_req_in3_T_12 = _fpiu_io_in_bits_req_in3_T_5 ? _fpiu_io_in_bits_req_in3_T_11 : 65'hE008000000000000; // @[package.scala:39:76] assign fpiu_io_in_bits_req_in3 = _fpiu_io_in_bits_req_in3_T_12; // @[FPU.scala:369:10, :848:19] assign fpiu_io_in_bits_req_typ = _fpiu_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign fpiu_io_in_bits_req_fmt = _fpiu_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire _fpiu_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _fpiu_io_in_bits_req_fmaCmd_T_3 = _fpiu_io_in_bits_req_fmaCmd_T_1 & _fpiu_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _fpiu_io_in_bits_req_fmaCmd_T_4 = {_fpiu_io_in_bits_req_fmaCmd_T[1], _fpiu_io_in_bits_req_fmaCmd_T[0] | _fpiu_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign fpiu_io_in_bits_req_fmaCmd = _fpiu_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _ifpu_io_in_valid_T = req_valid & ex_ctrl_fromint; // @[FPU.scala:780:32, :800:20, :887:33] wire [64:0] _ifpu_io_in_bits_in1_T = {1'h0, io_fromint_data_0}; // @[FPU.scala:735:7, :889:29] wire _fpmu_io_in_valid_T = req_valid & ex_ctrl_fastpipe; // @[FPU.scala:780:32, :800:20, :892:33] wire divSqrt_wen; // @[FPU.scala:896:32] wire divSqrt_inFlight; // @[FPU.scala:897:37] reg [4:0] divSqrt_waddr; // @[FPU.scala:898:26] reg divSqrt_cp; // @[FPU.scala:899:23] wire [1:0] divSqrt_typeTag; // @[FPU.scala:900:29] wire [64:0] divSqrt_wdata; // @[FPU.scala:901:27] wire [4:0] divSqrt_flags; // @[FPU.scala:902:27] wire _GEN_4 = ex_ctrl_typeTagOut == 2'h2; // @[FPU.scala:800:20, :914:78] wire _dfma_io_in_valid_T_1; // @[FPU.scala:914:78] assign _dfma_io_in_valid_T_1 = _GEN_4; // @[FPU.scala:914:78] wire _write_port_busy_T_5; // @[FPU.scala:916:78] assign _write_port_busy_T_5 = _GEN_4; // @[FPU.scala:914:78, :916:78] wire _write_port_busy_T_23; // @[FPU.scala:916:78] assign _write_port_busy_T_23 = _GEN_4; // @[FPU.scala:914:78, :916:78] wire _dfma_io_in_valid_T_2 = _dfma_io_in_valid_T & _dfma_io_in_valid_T_1; // @[FPU.scala:914:{41,56,78}] wire [1:0] _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [64:0] _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26] wire [64:0] _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26] wire [1:0] dfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] dfma_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] dfma_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] dfma_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] dfma_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] dfma_io_in_bits_req_in3; // @[FPU.scala:848:19] wire [1:0] dfma_io_in_bits_req_in1_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in1_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_0 = {dfma_io_in_bits_req_in1_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_prev_prev_0_1 = dfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in1_prev_prev_sign = dfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in1_prev_prev_fractIn = dfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in1_prev_prev_expIn = dfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in1_prev_prev_fractOut_T = {dfma_io_in_bits_req_in1_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in1_prev_prev_fractOut = _dfma_io_in_bits_req_in1_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in1_prev_prev_expOut_expCode = dfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in1_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in1_prev_prev_expOut_T | _dfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in1_prev_prev_expOut = _dfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in1_prev_prev_hi = {dfma_io_in_bits_req_in1_prev_prev_sign, dfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in1_floats_1 = {dfma_io_in_bits_req_in1_prev_prev_hi, dfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in1_prev_isbox = &_dfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in1_oks_1 = dfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in1_oks_0 = dfma_io_in_bits_req_in1_prev_isbox & dfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in1 = _dfma_io_in_bits_req_in1_T_1; // @[FPU.scala:372:26, :848:19] wire [1:0] dfma_io_in_bits_req_in2_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in2_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_0 = {dfma_io_in_bits_req_in2_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_prev_prev_0_1 = dfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in2_prev_prev_sign = dfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in2_prev_prev_fractIn = dfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in2_prev_prev_expIn = dfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in2_prev_prev_fractOut_T = {dfma_io_in_bits_req_in2_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in2_prev_prev_fractOut = _dfma_io_in_bits_req_in2_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in2_prev_prev_expOut_expCode = dfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in2_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in2_prev_prev_expOut_T | _dfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in2_prev_prev_expOut = _dfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in2_prev_prev_hi = {dfma_io_in_bits_req_in2_prev_prev_sign, dfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in2_floats_1 = {dfma_io_in_bits_req_in2_prev_prev_hi, dfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in2_prev_isbox = &_dfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in2_oks_1 = dfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in2_oks_0 = dfma_io_in_bits_req_in2_prev_isbox & dfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in2 = _dfma_io_in_bits_req_in2_T_1; // @[FPU.scala:372:26, :848:19] wire [1:0] dfma_io_in_bits_req_in3_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] dfma_io_in_bits_req_in3_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = dfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = dfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = dfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled = {dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[16]; // @[FPU.scala:274:17, :356:31] wire [9:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[9:0]; // @[FPU.scala:275:20, :356:31] wire [5:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_prev_prev_unswizzled[15:10]; // @[FPU.scala:276:18, :356:31] wire [62:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut_T[62:11]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn[5:3]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T = {7'h0, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_1} - 13'h20; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_0 = {dfma_io_in_bits_req_in3_prev_prev_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire [4:0] _dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = dfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire dfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_dfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_prev_prev_0_1 = dfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in3_prev_prev_sign = dfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] dfma_io_in_bits_req_in3_prev_prev_fractIn = dfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] dfma_io_in_bits_req_in3_prev_prev_expIn = dfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [75:0] _dfma_io_in_bits_req_in3_prev_prev_fractOut_T = {dfma_io_in_bits_req_in3_prev_prev_fractIn, 53'h0}; // @[FPU.scala:275:20, :277:28] wire [51:0] dfma_io_in_bits_req_in3_prev_prev_fractOut = _dfma_io_in_bits_req_in3_prev_prev_fractOut_T[75:24]; // @[FPU.scala:277:{28,38}] wire [2:0] dfma_io_in_bits_req_in3_prev_prev_expOut_expCode = dfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {4'h0, dfma_io_in_bits_req_in3_prev_prev_expIn} + 13'h800; // @[FPU.scala:276:18, :280:31] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 13'h100; // @[FPU.scala:280:{31,50}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase; // @[FPU.scala:280:50, :281:97] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = dfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _dfma_io_in_bits_req_in3_prev_prev_expOut_T | _dfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [8:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = dfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[8:0]; // @[FPU.scala:280:50, :281:69] wire [11:0] _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {dfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _dfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [11:0] dfma_io_in_bits_req_in3_prev_prev_expOut = _dfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _dfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _dfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [12:0] dfma_io_in_bits_req_in3_prev_prev_hi = {dfma_io_in_bits_req_in3_prev_prev_sign, dfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [64:0] dfma_io_in_bits_req_in3_floats_1 = {dfma_io_in_bits_req_in3_prev_prev_hi, dfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire dfma_io_in_bits_req_in3_prev_isbox = &_dfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire dfma_io_in_bits_req_in3_oks_1 = dfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire dfma_io_in_bits_req_in3_oks_0 = dfma_io_in_bits_req_in3_prev_isbox & dfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] assign dfma_io_in_bits_req_in3 = _dfma_io_in_bits_req_in3_T_1; // @[FPU.scala:372:26, :848:19] assign dfma_io_in_bits_req_typ = _dfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign dfma_io_in_bits_req_fmt = _dfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire _dfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _dfma_io_in_bits_req_fmaCmd_T_3 = _dfma_io_in_bits_req_fmaCmd_T_1 & _dfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _dfma_io_in_bits_req_fmaCmd_T_4 = {_dfma_io_in_bits_req_fmaCmd_T[1], _dfma_io_in_bits_req_fmaCmd_T[0] | _dfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign dfma_io_in_bits_req_fmaCmd = _dfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _GEN_5 = ex_ctrl_typeTagOut == 2'h0; // @[FPU.scala:800:20, :920:78] wire _hfma_io_in_valid_T_1; // @[FPU.scala:920:78] assign _hfma_io_in_valid_T_1 = _GEN_5; // @[FPU.scala:920:78] wire _write_port_busy_T_8; // @[FPU.scala:922:78] assign _write_port_busy_T_8 = _GEN_5; // @[FPU.scala:920:78, :922:78] wire _write_port_busy_T_26; // @[FPU.scala:922:78] assign _write_port_busy_T_26 = _GEN_5; // @[FPU.scala:920:78, :922:78] wire _hfma_io_in_valid_T_2 = _hfma_io_in_valid_T & _hfma_io_in_valid_T_1; // @[FPU.scala:920:{41,56,78}] wire [1:0] _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:857:36] wire [1:0] hfma_io_in_bits_req_fmaCmd; // @[FPU.scala:848:19] wire [1:0] hfma_io_in_bits_req_typ; // @[FPU.scala:848:19] wire [1:0] hfma_io_in_bits_req_fmt; // @[FPU.scala:848:19] wire [64:0] hfma_io_in_bits_req_in1; // @[FPU.scala:848:19] wire [64:0] hfma_io_in_bits_req_in2; // @[FPU.scala:848:19] wire [64:0] hfma_io_in_bits_req_in3; // @[FPU.scala:848:19] wire [1:0] hfma_io_in_bits_req_in1_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in1_prev_unswizzled = {hfma_io_in_bits_req_in1_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in1_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in1_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in1_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in1_floats_0 = {hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in1_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in1_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in1_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in1_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in1_prev_prev_0_1 = hfma_io_in_bits_req_in1_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in1_prev_prev_sign = hfma_io_in_bits_req_in1_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in1_prev_prev_fractIn = hfma_io_in_bits_req_in1_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expIn = hfma_io_in_bits_req_in1_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in1_prev_prev_fractOut_T = {hfma_io_in_bits_req_in1_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in1_prev_prev_fractOut = _hfma_io_in_bits_req_in1_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in1_prev_prev_expOut_expCode = hfma_io_in_bits_req_in1_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in1_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in1_prev_prev_expOut_T | _hfma_io_in_bits_req_in1_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in1_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in1_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in1_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in1_prev_prev_expOut = _hfma_io_in_bits_req_in1_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in1_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in1_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in1_prev_prev_hi = {hfma_io_in_bits_req_in1_prev_prev_sign, hfma_io_in_bits_req_in1_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in1_floats_1 = {hfma_io_in_bits_req_in1_prev_prev_hi, hfma_io_in_bits_req_in1_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in1_prev_isbox = &_hfma_io_in_bits_req_in1_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in1_oks_1 = hfma_io_in_bits_req_in1_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in1_oks_0 = hfma_io_in_bits_req_in1_prev_isbox & hfma_io_in_bits_req_in1_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in1_fractOut_T = {hfma_io_in_bits_req_in1_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in1_fractOut = _hfma_io_in_bits_req_in1_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in1_expOut_expCode = hfma_io_in_bits_req_in1_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in1_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in1_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in1_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in1_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in1_expOut_commonCase = _hfma_io_in_bits_req_in1_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in1_expOut_T = hfma_io_in_bits_req_in1_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in1_expOut_T_1 = hfma_io_in_bits_req_in1_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in1_expOut_T_2 = _hfma_io_in_bits_req_in1_expOut_T | _hfma_io_in_bits_req_in1_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in1_expOut_T_3 = hfma_io_in_bits_req_in1_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_4 = {hfma_io_in_bits_req_in1_expOut_expCode, _hfma_io_in_bits_req_in1_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in1_expOut_T_5 = hfma_io_in_bits_req_in1_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in1_expOut = _hfma_io_in_bits_req_in1_expOut_T_2 ? _hfma_io_in_bits_req_in1_expOut_T_4 : _hfma_io_in_bits_req_in1_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in1_hi = {hfma_io_in_bits_req_in1_sign, hfma_io_in_bits_req_in1_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in1_floats_2 = {hfma_io_in_bits_req_in1_hi, hfma_io_in_bits_req_in1_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in1_T = hfma_io_in_bits_req_in1_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in1_T_1 = hfma_io_in_bits_req_in1_floats_0 | _hfma_io_in_bits_req_in1_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in1 = {48'h0, _hfma_io_in_bits_req_in1_T_1}; // @[FPU.scala:372:26, :848:19, :852:13] wire [1:0] hfma_io_in_bits_req_in2_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in2_prev_unswizzled = {hfma_io_in_bits_req_in2_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in2_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in2_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in2_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in2_floats_0 = {hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in2_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in2_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in2_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in2_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in2_prev_prev_0_1 = hfma_io_in_bits_req_in2_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in2_prev_prev_sign = hfma_io_in_bits_req_in2_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in2_prev_prev_fractIn = hfma_io_in_bits_req_in2_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expIn = hfma_io_in_bits_req_in2_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in2_prev_prev_fractOut_T = {hfma_io_in_bits_req_in2_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in2_prev_prev_fractOut = _hfma_io_in_bits_req_in2_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in2_prev_prev_expOut_expCode = hfma_io_in_bits_req_in2_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in2_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in2_prev_prev_expOut_T | _hfma_io_in_bits_req_in2_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in2_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in2_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in2_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in2_prev_prev_expOut = _hfma_io_in_bits_req_in2_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in2_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in2_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in2_prev_prev_hi = {hfma_io_in_bits_req_in2_prev_prev_sign, hfma_io_in_bits_req_in2_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in2_floats_1 = {hfma_io_in_bits_req_in2_prev_prev_hi, hfma_io_in_bits_req_in2_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in2_prev_isbox = &_hfma_io_in_bits_req_in2_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in2_oks_1 = hfma_io_in_bits_req_in2_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in2_oks_0 = hfma_io_in_bits_req_in2_prev_isbox & hfma_io_in_bits_req_in2_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in2_fractOut_T = {hfma_io_in_bits_req_in2_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in2_fractOut = _hfma_io_in_bits_req_in2_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in2_expOut_expCode = hfma_io_in_bits_req_in2_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in2_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in2_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in2_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in2_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in2_expOut_commonCase = _hfma_io_in_bits_req_in2_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in2_expOut_T = hfma_io_in_bits_req_in2_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in2_expOut_T_1 = hfma_io_in_bits_req_in2_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in2_expOut_T_2 = _hfma_io_in_bits_req_in2_expOut_T | _hfma_io_in_bits_req_in2_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in2_expOut_T_3 = hfma_io_in_bits_req_in2_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_4 = {hfma_io_in_bits_req_in2_expOut_expCode, _hfma_io_in_bits_req_in2_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in2_expOut_T_5 = hfma_io_in_bits_req_in2_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in2_expOut = _hfma_io_in_bits_req_in2_expOut_T_2 ? _hfma_io_in_bits_req_in2_expOut_T_4 : _hfma_io_in_bits_req_in2_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in2_hi = {hfma_io_in_bits_req_in2_sign, hfma_io_in_bits_req_in2_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in2_floats_2 = {hfma_io_in_bits_req_in2_hi, hfma_io_in_bits_req_in2_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in2_T = hfma_io_in_bits_req_in2_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in2_T_1 = hfma_io_in_bits_req_in2_floats_0 | _hfma_io_in_bits_req_in2_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in2 = {48'h0, _hfma_io_in_bits_req_in2_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :853:13] wire [1:0] hfma_io_in_bits_req_in3_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [32:0] hfma_io_in_bits_req_in3_prev_unswizzled = {hfma_io_in_bits_req_in3_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T = hfma_io_in_bits_req_in3_prev_unswizzled[15]; // @[FPU.scala:356:31, :357:14] wire _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1 = hfma_io_in_bits_req_in3_prev_unswizzled[23]; // @[FPU.scala:356:31, :358:14] wire [14:0] _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2 = hfma_io_in_bits_req_in3_prev_unswizzled[14:0]; // @[FPU.scala:356:31, :359:14] wire [1:0] hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi = {_hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_1}; // @[FPU.scala:356:31, :357:14, :358:14] wire [16:0] hfma_io_in_bits_req_in3_floats_0 = {hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_hi, _hfma_io_in_bits_req_in3_prev_prev_prev_unswizzled_T_2}; // @[FPU.scala:356:31, :359:14] wire [4:0] _hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T = hfma_io_in_bits_req_in3_prev_unswizzled[32:28]; // @[FPU.scala:332:49, :356:31] wire hfma_io_in_bits_req_in3_prev_prev_prev_isbox = &_hfma_io_in_bits_req_in3_prev_prev_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in3_prev_prev_0_1 = hfma_io_in_bits_req_in3_prev_prev_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in3_prev_prev_sign = hfma_io_in_bits_req_in3_prev_unswizzled[32]; // @[FPU.scala:274:17, :356:31] wire [22:0] hfma_io_in_bits_req_in3_prev_prev_fractIn = hfma_io_in_bits_req_in3_prev_unswizzled[22:0]; // @[FPU.scala:275:20, :356:31] wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expIn = hfma_io_in_bits_req_in3_prev_unswizzled[31:23]; // @[FPU.scala:276:18, :356:31] wire [33:0] _hfma_io_in_bits_req_in3_prev_prev_fractOut_T = {hfma_io_in_bits_req_in3_prev_prev_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in3_prev_prev_fractOut = _hfma_io_in_bits_req_in3_prev_prev_fractOut_T[33:24]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in3_prev_prev_expOut_expCode = hfma_io_in_bits_req_in3_prev_prev_expIn[8:6]; // @[FPU.scala:276:18, :279:26] wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_prev_prev_expIn} + 10'h20; // @[FPU.scala:276:18, :280:31] wire [8:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T[8:0]; // @[FPU.scala:280:31] wire [9:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_1} - 10'h100; // @[FPU.scala:280:{31,50}] wire [8:0] hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase = _hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase_T_2[8:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1 = hfma_io_in_bits_req_in3_prev_prev_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 = _hfma_io_in_bits_req_in3_prev_prev_expOut_T | _hfma_io_in_bits_req_in3_prev_prev_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 = {hfma_io_in_bits_req_in3_prev_prev_expOut_expCode, _hfma_io_in_bits_req_in3_prev_prev_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5 = hfma_io_in_bits_req_in3_prev_prev_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in3_prev_prev_expOut = _hfma_io_in_bits_req_in3_prev_prev_expOut_T_2 ? _hfma_io_in_bits_req_in3_prev_prev_expOut_T_4 : _hfma_io_in_bits_req_in3_prev_prev_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in3_prev_prev_hi = {hfma_io_in_bits_req_in3_prev_prev_sign, hfma_io_in_bits_req_in3_prev_prev_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in3_floats_1 = {hfma_io_in_bits_req_in3_prev_prev_hi, hfma_io_in_bits_req_in3_prev_prev_fractOut}; // @[FPU.scala:277:38, :283:8] wire hfma_io_in_bits_req_in3_prev_isbox = &_hfma_io_in_bits_req_in3_prev_isbox_T; // @[FPU.scala:332:{49,84}] wire hfma_io_in_bits_req_in3_oks_1 = hfma_io_in_bits_req_in3_prev_isbox; // @[FPU.scala:332:84, :362:32] wire hfma_io_in_bits_req_in3_oks_0 = hfma_io_in_bits_req_in3_prev_isbox & hfma_io_in_bits_req_in3_prev_prev_0_1; // @[FPU.scala:332:84, :362:32] wire [62:0] _hfma_io_in_bits_req_in3_fractOut_T = {hfma_io_in_bits_req_in3_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] hfma_io_in_bits_req_in3_fractOut = _hfma_io_in_bits_req_in3_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] hfma_io_in_bits_req_in3_expOut_expCode = hfma_io_in_bits_req_in3_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T = {1'h0, hfma_io_in_bits_req_in3_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_1 = _hfma_io_in_bits_req_in3_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _hfma_io_in_bits_req_in3_expOut_commonCase_T_2 = {1'h0, _hfma_io_in_bits_req_in3_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] hfma_io_in_bits_req_in3_expOut_commonCase = _hfma_io_in_bits_req_in3_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _hfma_io_in_bits_req_in3_expOut_T = hfma_io_in_bits_req_in3_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _hfma_io_in_bits_req_in3_expOut_T_1 = hfma_io_in_bits_req_in3_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _hfma_io_in_bits_req_in3_expOut_T_2 = _hfma_io_in_bits_req_in3_expOut_T | _hfma_io_in_bits_req_in3_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _hfma_io_in_bits_req_in3_expOut_T_3 = hfma_io_in_bits_req_in3_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_4 = {hfma_io_in_bits_req_in3_expOut_expCode, _hfma_io_in_bits_req_in3_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _hfma_io_in_bits_req_in3_expOut_T_5 = hfma_io_in_bits_req_in3_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] hfma_io_in_bits_req_in3_expOut = _hfma_io_in_bits_req_in3_expOut_T_2 ? _hfma_io_in_bits_req_in3_expOut_T_4 : _hfma_io_in_bits_req_in3_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] hfma_io_in_bits_req_in3_hi = {hfma_io_in_bits_req_in3_sign, hfma_io_in_bits_req_in3_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] hfma_io_in_bits_req_in3_floats_2 = {hfma_io_in_bits_req_in3_hi, hfma_io_in_bits_req_in3_fractOut}; // @[FPU.scala:277:38, :283:8] wire [16:0] _hfma_io_in_bits_req_in3_T = hfma_io_in_bits_req_in3_oks_0 ? 17'h0 : 17'hE200; // @[FPU.scala:362:32, :372:31] wire [16:0] _hfma_io_in_bits_req_in3_T_1 = hfma_io_in_bits_req_in3_floats_0 | _hfma_io_in_bits_req_in3_T; // @[FPU.scala:356:31, :372:{26,31}] assign hfma_io_in_bits_req_in3 = {48'h0, _hfma_io_in_bits_req_in3_T_1}; // @[FPU.scala:372:26, :848:19, :852:13, :854:13] assign hfma_io_in_bits_req_typ = _hfma_io_in_bits_req_typ_T; // @[FPU.scala:848:19, :855:27] assign hfma_io_in_bits_req_fmt = _hfma_io_in_bits_req_fmt_T; // @[FPU.scala:848:19, :856:27] wire _hfma_io_in_bits_req_fmaCmd_T_1 = ~ex_ctrl_ren3; // @[FPU.scala:800:20, :857:39] wire _hfma_io_in_bits_req_fmaCmd_T_3 = _hfma_io_in_bits_req_fmaCmd_T_1 & _hfma_io_in_bits_req_fmaCmd_T_2; // @[FPU.scala:857:{39,53,67}] assign _hfma_io_in_bits_req_fmaCmd_T_4 = {_hfma_io_in_bits_req_fmaCmd_T[1], _hfma_io_in_bits_req_fmaCmd_T[0] | _hfma_io_in_bits_req_fmaCmd_T_3}; // @[FPU.scala:857:{30,36,53}] assign hfma_io_in_bits_req_fmaCmd = _hfma_io_in_bits_req_fmaCmd_T_4; // @[FPU.scala:848:19, :857:36] wire _GEN_6 = mem_ctrl_typeTagOut == 2'h1; // @[FPU.scala:801:27, :911:72] wire _memLatencyMask_T_2; // @[FPU.scala:911:72] assign _memLatencyMask_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _wbInfo_0_pipeid_T_2; // @[FPU.scala:911:72] assign _wbInfo_0_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _wbInfo_1_pipeid_T_2; // @[FPU.scala:911:72] assign _wbInfo_1_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _wbInfo_2_pipeid_T_2; // @[FPU.scala:911:72] assign _wbInfo_2_pipeid_T_2 = _GEN_6; // @[FPU.scala:911:72] wire _divSqrt_io_inValid_T_2; // @[FPU.scala:1028:52] assign _divSqrt_io_inValid_T_2 = _GEN_6; // @[FPU.scala:911:72, :1028:52] wire _memLatencyMask_T_3 = mem_ctrl_fma & _memLatencyMask_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _memLatencyMask_T_4 = {_memLatencyMask_T_3, 1'h0}; // @[FPU.scala:911:56, :926:23] wire _GEN_7 = mem_ctrl_typeTagOut == 2'h2; // @[FPU.scala:801:27, :916:78] wire _memLatencyMask_T_5; // @[FPU.scala:916:78] assign _memLatencyMask_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _wbInfo_0_pipeid_T_5; // @[FPU.scala:916:78] assign _wbInfo_0_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _wbInfo_1_pipeid_T_5; // @[FPU.scala:916:78] assign _wbInfo_1_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _wbInfo_2_pipeid_T_5; // @[FPU.scala:916:78] assign _wbInfo_2_pipeid_T_5 = _GEN_7; // @[FPU.scala:916:78] wire _io_sboard_set_T_2; // @[FPU.scala:916:78] assign _io_sboard_set_T_2 = _GEN_7; // @[FPU.scala:916:78] wire _divSqrt_io_inValid_T_4; // @[FPU.scala:1028:52] assign _divSqrt_io_inValid_T_4 = _GEN_7; // @[FPU.scala:916:78, :1028:52] wire _memLatencyMask_T_6 = mem_ctrl_fma & _memLatencyMask_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [2:0] _memLatencyMask_T_7 = {_memLatencyMask_T_6, 2'h0}; // @[FPU.scala:916:62, :926:23] wire _GEN_8 = mem_ctrl_typeTagOut == 2'h0; // @[FPU.scala:801:27, :922:78] wire _memLatencyMask_T_8; // @[FPU.scala:922:78] assign _memLatencyMask_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _wbInfo_0_pipeid_T_8; // @[FPU.scala:922:78] assign _wbInfo_0_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _wbInfo_1_pipeid_T_8; // @[FPU.scala:922:78] assign _wbInfo_1_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _wbInfo_2_pipeid_T_8; // @[FPU.scala:922:78] assign _wbInfo_2_pipeid_T_8 = _GEN_8; // @[FPU.scala:922:78] wire _divSqrt_io_inValid_T; // @[FPU.scala:1028:52] assign _divSqrt_io_inValid_T = _GEN_8; // @[FPU.scala:922:78, :1028:52] wire _memLatencyMask_T_9 = mem_ctrl_fma & _memLatencyMask_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [1:0] _memLatencyMask_T_10 = {_memLatencyMask_T_9, 1'h0}; // @[FPU.scala:922:62, :926:23] wire _memLatencyMask_T_11 = _memLatencyMask_T | _memLatencyMask_T_1; // @[FPU.scala:926:{23,72}] wire [1:0] _memLatencyMask_T_12 = {1'h0, _memLatencyMask_T_11} | _memLatencyMask_T_4; // @[FPU.scala:926:{23,72}] wire [2:0] _memLatencyMask_T_13 = {1'h0, _memLatencyMask_T_12} | _memLatencyMask_T_7; // @[FPU.scala:926:{23,72}] wire [2:0] memLatencyMask = {_memLatencyMask_T_13[2], _memLatencyMask_T_13[1:0] | _memLatencyMask_T_10}; // @[FPU.scala:926:{23,72}] reg [2:0] wen; // @[FPU.scala:939:20] reg [4:0] wbInfo_0_rd; // @[FPU.scala:940:19] reg [1:0] wbInfo_0_typeTag; // @[FPU.scala:940:19] reg wbInfo_0_cp; // @[FPU.scala:940:19] reg [2:0] wbInfo_0_pipeid; // @[FPU.scala:940:19] reg [4:0] wbInfo_1_rd; // @[FPU.scala:940:19] reg [1:0] wbInfo_1_typeTag; // @[FPU.scala:940:19] reg wbInfo_1_cp; // @[FPU.scala:940:19] reg [2:0] wbInfo_1_pipeid; // @[FPU.scala:940:19] reg [4:0] wbInfo_2_rd; // @[FPU.scala:940:19] reg [1:0] wbInfo_2_typeTag; // @[FPU.scala:940:19] reg wbInfo_2_cp; // @[FPU.scala:940:19] reg [2:0] wbInfo_2_pipeid; // @[FPU.scala:940:19] wire _mem_wen_T = mem_ctrl_fma | mem_ctrl_fastpipe; // @[FPU.scala:801:27, :941:48] wire _mem_wen_T_1 = _mem_wen_T | mem_ctrl_fromint; // @[FPU.scala:801:27, :941:{48,69}] wire mem_wen = mem_reg_valid & _mem_wen_T_1; // @[FPU.scala:784:30, :941:{31,69}] wire [1:0] _write_port_busy_T = {ex_ctrl_fastpipe, 1'h0}; // @[FPU.scala:800:20, :926:23] wire [1:0] _write_port_busy_T_1 = {ex_ctrl_fromint, 1'h0}; // @[FPU.scala:800:20, :926:23] wire _write_port_busy_T_3 = ex_ctrl_fma & _write_port_busy_T_2; // @[FPU.scala:800:20, :911:{56,72}] wire [2:0] _write_port_busy_T_4 = {_write_port_busy_T_3, 2'h0}; // @[FPU.scala:911:56, :926:23] wire _write_port_busy_T_6 = ex_ctrl_fma & _write_port_busy_T_5; // @[FPU.scala:800:20, :916:{62,78}] wire [3:0] _write_port_busy_T_7 = {_write_port_busy_T_6, 3'h0}; // @[FPU.scala:916:62, :926:23] wire _write_port_busy_T_9 = ex_ctrl_fma & _write_port_busy_T_8; // @[FPU.scala:800:20, :922:{62,78}] wire [2:0] _write_port_busy_T_10 = {_write_port_busy_T_9, 2'h0}; // @[FPU.scala:922:62, :926:23] wire [1:0] _write_port_busy_T_11 = _write_port_busy_T | _write_port_busy_T_1; // @[FPU.scala:926:{23,72}] wire [2:0] _write_port_busy_T_12 = {1'h0, _write_port_busy_T_11} | _write_port_busy_T_4; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_13 = {1'h0, _write_port_busy_T_12} | _write_port_busy_T_7; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_14 = {_write_port_busy_T_13[3], _write_port_busy_T_13[2:0] | _write_port_busy_T_10}; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_15 = {1'h0, _write_port_busy_T_14[2:0] & memLatencyMask}; // @[FPU.scala:926:72, :942:62] wire _write_port_busy_T_16 = |_write_port_busy_T_15; // @[FPU.scala:942:{62,89}] wire _write_port_busy_T_17 = mem_wen & _write_port_busy_T_16; // @[FPU.scala:941:31, :942:{43,89}] wire [2:0] _write_port_busy_T_18 = {ex_ctrl_fastpipe, 2'h0}; // @[FPU.scala:800:20, :926:23] wire [2:0] _write_port_busy_T_19 = {ex_ctrl_fromint, 2'h0}; // @[FPU.scala:800:20, :926:23] wire _write_port_busy_T_21 = ex_ctrl_fma & _write_port_busy_T_20; // @[FPU.scala:800:20, :911:{56,72}] wire [3:0] _write_port_busy_T_22 = {_write_port_busy_T_21, 3'h0}; // @[FPU.scala:911:56, :926:23] wire _write_port_busy_T_24 = ex_ctrl_fma & _write_port_busy_T_23; // @[FPU.scala:800:20, :916:{62,78}] wire [4:0] _write_port_busy_T_25 = {_write_port_busy_T_24, 4'h0}; // @[FPU.scala:916:62, :926:23] wire _write_port_busy_T_27 = ex_ctrl_fma & _write_port_busy_T_26; // @[FPU.scala:800:20, :922:{62,78}] wire [3:0] _write_port_busy_T_28 = {_write_port_busy_T_27, 3'h0}; // @[FPU.scala:922:62, :926:23] wire [2:0] _write_port_busy_T_29 = _write_port_busy_T_18 | _write_port_busy_T_19; // @[FPU.scala:926:{23,72}] wire [3:0] _write_port_busy_T_30 = {1'h0, _write_port_busy_T_29} | _write_port_busy_T_22; // @[FPU.scala:926:{23,72}] wire [4:0] _write_port_busy_T_31 = {1'h0, _write_port_busy_T_30} | _write_port_busy_T_25; // @[FPU.scala:926:{23,72}] wire [4:0] _write_port_busy_T_32 = {_write_port_busy_T_31[4], _write_port_busy_T_31[3:0] | _write_port_busy_T_28}; // @[FPU.scala:926:{23,72}] wire [4:0] _write_port_busy_T_33 = {2'h0, _write_port_busy_T_32[2:0] & wen}; // @[FPU.scala:926:72, :939:20, :942:101] wire _write_port_busy_T_34 = |_write_port_busy_T_33; // @[FPU.scala:942:{101,128}] wire _write_port_busy_T_35 = _write_port_busy_T_17 | _write_port_busy_T_34; // @[FPU.scala:942:{43,93,128}] reg write_port_busy; // @[FPU.scala:942:34] wire [1:0] _wen_T = wen[2:1]; // @[FPU.scala:939:20, :948:14] wire [1:0] _wen_T_1 = wen[2:1]; // @[FPU.scala:939:20, :948:14, :951:18] wire [2:0] _wen_T_2 = {1'h0, _wen_T_1} | memLatencyMask; // @[FPU.scala:926:72, :951:{18,23}] wire _wbInfo_0_pipeid_T_11 = _wbInfo_0_pipeid_T_1; // @[FPU.scala:928:{63,100}] wire _wbInfo_0_pipeid_T_3 = mem_ctrl_fma & _wbInfo_0_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _wbInfo_0_pipeid_T_4 = {_wbInfo_0_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63] wire _wbInfo_0_pipeid_T_6 = mem_ctrl_fma & _wbInfo_0_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [1:0] _wbInfo_0_pipeid_T_7 = {2{_wbInfo_0_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63] wire _wbInfo_0_pipeid_T_9 = mem_ctrl_fma & _wbInfo_0_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [2:0] _wbInfo_0_pipeid_T_10 = {_wbInfo_0_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63] wire [1:0] _wbInfo_0_pipeid_T_12 = {1'h0, _wbInfo_0_pipeid_T_11} | _wbInfo_0_pipeid_T_4; // @[FPU.scala:928:{63,100}] wire [1:0] _wbInfo_0_pipeid_T_13 = _wbInfo_0_pipeid_T_12 | _wbInfo_0_pipeid_T_7; // @[FPU.scala:928:{63,100}] wire [2:0] _wbInfo_0_pipeid_T_14 = {1'h0, _wbInfo_0_pipeid_T_13} | _wbInfo_0_pipeid_T_10; // @[FPU.scala:928:{63,100}] wire [4:0] _wbInfo_0_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37] wire [4:0] _wbInfo_1_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37] wire [4:0] _wbInfo_2_rd_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37] wire [4:0] _divSqrt_waddr_T = mem_reg_inst[11:7]; // @[FPU.scala:791:31, :958:37, :1017:36] wire _wbInfo_1_pipeid_T_11 = _wbInfo_1_pipeid_T_1; // @[FPU.scala:928:{63,100}] wire _wbInfo_1_pipeid_T_3 = mem_ctrl_fma & _wbInfo_1_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _wbInfo_1_pipeid_T_4 = {_wbInfo_1_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63] wire _wbInfo_1_pipeid_T_6 = mem_ctrl_fma & _wbInfo_1_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [1:0] _wbInfo_1_pipeid_T_7 = {2{_wbInfo_1_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63] wire _wbInfo_1_pipeid_T_9 = mem_ctrl_fma & _wbInfo_1_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [2:0] _wbInfo_1_pipeid_T_10 = {_wbInfo_1_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63] wire [1:0] _wbInfo_1_pipeid_T_12 = {1'h0, _wbInfo_1_pipeid_T_11} | _wbInfo_1_pipeid_T_4; // @[FPU.scala:928:{63,100}] wire [1:0] _wbInfo_1_pipeid_T_13 = _wbInfo_1_pipeid_T_12 | _wbInfo_1_pipeid_T_7; // @[FPU.scala:928:{63,100}] wire [2:0] _wbInfo_1_pipeid_T_14 = {1'h0, _wbInfo_1_pipeid_T_13} | _wbInfo_1_pipeid_T_10; // @[FPU.scala:928:{63,100}] wire _wbInfo_2_pipeid_T_11 = _wbInfo_2_pipeid_T_1; // @[FPU.scala:928:{63,100}] wire _wbInfo_2_pipeid_T_3 = mem_ctrl_fma & _wbInfo_2_pipeid_T_2; // @[FPU.scala:801:27, :911:{56,72}] wire [1:0] _wbInfo_2_pipeid_T_4 = {_wbInfo_2_pipeid_T_3, 1'h0}; // @[FPU.scala:911:56, :928:63] wire _wbInfo_2_pipeid_T_6 = mem_ctrl_fma & _wbInfo_2_pipeid_T_5; // @[FPU.scala:801:27, :916:{62,78}] wire [1:0] _wbInfo_2_pipeid_T_7 = {2{_wbInfo_2_pipeid_T_6}}; // @[FPU.scala:916:62, :928:63] wire _wbInfo_2_pipeid_T_9 = mem_ctrl_fma & _wbInfo_2_pipeid_T_8; // @[FPU.scala:801:27, :922:{62,78}] wire [2:0] _wbInfo_2_pipeid_T_10 = {_wbInfo_2_pipeid_T_9, 2'h0}; // @[FPU.scala:922:62, :928:63] wire [1:0] _wbInfo_2_pipeid_T_12 = {1'h0, _wbInfo_2_pipeid_T_11} | _wbInfo_2_pipeid_T_4; // @[FPU.scala:928:{63,100}] wire [1:0] _wbInfo_2_pipeid_T_13 = _wbInfo_2_pipeid_T_12 | _wbInfo_2_pipeid_T_7; // @[FPU.scala:928:{63,100}] wire [2:0] _wbInfo_2_pipeid_T_14 = {1'h0, _wbInfo_2_pipeid_T_13} | _wbInfo_2_pipeid_T_10; // @[FPU.scala:928:{63,100}] assign waddr = divSqrt_wen ? divSqrt_waddr : wbInfo_0_rd; // @[FPU.scala:896:32, :898:26, :940:19, :963:18] assign io_sboard_clra_0 = waddr; // @[FPU.scala:735:7, :963:18] assign frfWriteBundle_1_wrdst = waddr; // @[FPU.scala:805:44, :963:18] wire wb_cp = divSqrt_wen ? divSqrt_cp : wbInfo_0_cp; // @[FPU.scala:896:32, :899:23, :940:19, :964:18] wire [1:0] wtypeTag = divSqrt_wen ? divSqrt_typeTag : wbInfo_0_typeTag; // @[FPU.scala:896:32, :900:29, :940:19, :965:21] wire _GEN_9 = wbInfo_0_pipeid == 3'h1; // @[package.scala:39:86] wire _wdata_T_39; // @[package.scala:39:86] assign _wdata_T_39 = _GEN_9; // @[package.scala:39:86] wire _wexc_T; // @[package.scala:39:86] assign _wexc_T = _GEN_9; // @[package.scala:39:86] wire [64:0] _wdata_T_40 = _wdata_T_39 ? _ifpu_io_out_bits_data : _fpmu_io_out_bits_data; // @[package.scala:39:{76,86}] wire _GEN_10 = wbInfo_0_pipeid == 3'h2; // @[package.scala:39:86] wire _wdata_T_41; // @[package.scala:39:86] assign _wdata_T_41 = _GEN_10; // @[package.scala:39:86] wire _wexc_T_2; // @[package.scala:39:86] assign _wexc_T_2 = _GEN_10; // @[package.scala:39:86] wire [64:0] _wdata_T_42 = _wdata_T_41 ? _sfma_io_out_bits_data : _wdata_T_40; // @[package.scala:39:{76,86}] wire _GEN_11 = wbInfo_0_pipeid == 3'h3; // @[package.scala:39:86] wire _wdata_T_43; // @[package.scala:39:86] assign _wdata_T_43 = _GEN_11; // @[package.scala:39:86] wire _wexc_T_4; // @[package.scala:39:86] assign _wexc_T_4 = _GEN_11; // @[package.scala:39:86] wire _io_sboard_clr_T_2; // @[FPU.scala:1007:99] assign _io_sboard_clr_T_2 = _GEN_11; // @[package.scala:39:86] wire [64:0] _wdata_T_44 = _wdata_T_43 ? _dfma_io_out_bits_data : _wdata_T_42; // @[package.scala:39:{76,86}] wire _GEN_12 = wbInfo_0_pipeid == 3'h4; // @[package.scala:39:86] wire _wdata_T_45; // @[package.scala:39:86] assign _wdata_T_45 = _GEN_12; // @[package.scala:39:86] wire _wexc_T_6; // @[package.scala:39:86] assign _wexc_T_6 = _GEN_12; // @[package.scala:39:86] wire [64:0] _wdata_T_46 = _wdata_T_45 ? _hfma_io_out_bits_data : _wdata_T_44; // @[package.scala:39:{76,86}] wire _GEN_13 = wbInfo_0_pipeid == 3'h5; // @[package.scala:39:86] wire _wdata_T_47; // @[package.scala:39:86] assign _wdata_T_47 = _GEN_13; // @[package.scala:39:86] wire _wexc_T_8; // @[package.scala:39:86] assign _wexc_T_8 = _GEN_13; // @[package.scala:39:86] wire [64:0] _wdata_T_48 = _wdata_T_47 ? _hfma_io_out_bits_data : _wdata_T_46; // @[package.scala:39:{76,86}] wire _GEN_14 = wbInfo_0_pipeid == 3'h6; // @[package.scala:39:86] wire _wdata_T_49; // @[package.scala:39:86] assign _wdata_T_49 = _GEN_14; // @[package.scala:39:86] wire _wexc_T_10; // @[package.scala:39:86] assign _wexc_T_10 = _GEN_14; // @[package.scala:39:86] wire [64:0] _wdata_T_50 = _wdata_T_49 ? _hfma_io_out_bits_data : _wdata_T_48; // @[package.scala:39:{76,86}] wire _wdata_T_51 = &wbInfo_0_pipeid; // @[package.scala:39:86] wire [64:0] _wdata_T_52 = _wdata_T_51 ? _hfma_io_out_bits_data : _wdata_T_50; // @[package.scala:39:{76,86}] wire [64:0] _wdata_T_53 = divSqrt_wen ? divSqrt_wdata : _wdata_T_52; // @[package.scala:39:76] wire _wdata_opts_bigger_swizzledNaN_T_1 = _wdata_T_53[15]; // @[FPU.scala:340:8, :966:22] wire _wdata_opts_bigger_swizzledNaN_T_2 = _wdata_T_53[16]; // @[FPU.scala:342:8, :966:22] wire [14:0] _wdata_opts_bigger_swizzledNaN_T_3 = _wdata_T_53[14:0]; // @[FPU.scala:343:8, :966:22] wire [7:0] wdata_opts_bigger_swizzledNaN_lo_hi = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_2}; // @[FPU.scala:336:26, :342:8] wire [22:0] wdata_opts_bigger_swizzledNaN_lo = {wdata_opts_bigger_swizzledNaN_lo_hi, _wdata_opts_bigger_swizzledNaN_T_3}; // @[FPU.scala:336:26, :343:8] wire [4:0] wdata_opts_bigger_swizzledNaN_hi_lo = {4'hF, _wdata_opts_bigger_swizzledNaN_T_1}; // @[FPU.scala:336:26, :340:8] wire [9:0] wdata_opts_bigger_swizzledNaN_hi = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo}; // @[FPU.scala:336:26] wire [32:0] wdata_opts_bigger_swizzledNaN = {wdata_opts_bigger_swizzledNaN_hi, wdata_opts_bigger_swizzledNaN_lo}; // @[FPU.scala:336:26] wire [32:0] wdata_opts_bigger = wdata_opts_bigger_swizzledNaN; // @[FPU.scala:336:26, :344:8] wire [64:0] wdata_opts_0 = {32'hFFFFFFFF, wdata_opts_bigger}; // @[FPU.scala:344:8, :398:14] wire _wdata_opts_bigger_swizzledNaN_T_5 = _wdata_T_53[31]; // @[FPU.scala:340:8, :966:22] wire _wdata_opts_bigger_swizzledNaN_T_6 = _wdata_T_53[32]; // @[FPU.scala:342:8, :966:22] wire [30:0] _wdata_opts_bigger_swizzledNaN_T_7 = _wdata_T_53[30:0]; // @[FPU.scala:343:8, :966:22] wire [20:0] wdata_opts_bigger_swizzledNaN_lo_hi_1 = {20'hFFFFF, _wdata_opts_bigger_swizzledNaN_T_6}; // @[FPU.scala:336:26, :342:8] wire [51:0] wdata_opts_bigger_swizzledNaN_lo_1 = {wdata_opts_bigger_swizzledNaN_lo_hi_1, _wdata_opts_bigger_swizzledNaN_T_7}; // @[FPU.scala:336:26, :343:8] wire [7:0] wdata_opts_bigger_swizzledNaN_hi_lo_1 = {7'h7F, _wdata_opts_bigger_swizzledNaN_T_5}; // @[FPU.scala:336:26, :340:8] wire [12:0] wdata_opts_bigger_swizzledNaN_hi_1 = {5'h1F, wdata_opts_bigger_swizzledNaN_hi_lo_1}; // @[FPU.scala:336:26] wire [64:0] wdata_opts_bigger_swizzledNaN_1 = {wdata_opts_bigger_swizzledNaN_hi_1, wdata_opts_bigger_swizzledNaN_lo_1}; // @[FPU.scala:336:26] wire [64:0] wdata_opts_bigger_1 = wdata_opts_bigger_swizzledNaN_1; // @[FPU.scala:336:26, :344:8] wire [64:0] wdata_opts_1 = wdata_opts_bigger_1; // @[FPU.scala:344:8, :398:14] wire _wdata_T_54 = wtypeTag == 2'h1; // @[package.scala:39:86] wire [64:0] _wdata_T_55 = _wdata_T_54 ? wdata_opts_1 : wdata_opts_0; // @[package.scala:39:{76,86}] wire _wdata_T_56 = wtypeTag == 2'h2; // @[package.scala:39:86] wire [64:0] _wdata_T_57 = _wdata_T_56 ? _wdata_T_53 : _wdata_T_55; // @[package.scala:39:{76,86}] wire _wdata_T_58 = &wtypeTag; // @[package.scala:39:86] wire [64:0] wdata_1 = _wdata_T_58 ? _wdata_T_53 : _wdata_T_57; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_1 = _wexc_T ? _ifpu_io_out_bits_exc : _fpmu_io_out_bits_exc; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_3 = _wexc_T_2 ? _sfma_io_out_bits_exc : _wexc_T_1; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_5 = _wexc_T_4 ? _dfma_io_out_bits_exc : _wexc_T_3; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_7 = _wexc_T_6 ? _hfma_io_out_bits_exc : _wexc_T_5; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_9 = _wexc_T_8 ? _hfma_io_out_bits_exc : _wexc_T_7; // @[package.scala:39:{76,86}] wire [4:0] _wexc_T_11 = _wexc_T_10 ? _hfma_io_out_bits_exc : _wexc_T_9; // @[package.scala:39:{76,86}] wire _wexc_T_12 = &wbInfo_0_pipeid; // @[package.scala:39:86] wire [4:0] wexc = _wexc_T_12 ? _hfma_io_out_bits_exc : _wexc_T_11; // @[package.scala:39:{76,86}] wire _io_fcsr_flags_valid_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :995:62] wire _io_fcsr_flags_bits_T_3 = wen[0]; // @[FPU.scala:939:20, :968:30, :999:12] wire _io_sboard_clr_T_1 = wen[0]; // @[FPU.scala:939:20, :968:30, :1007:56] assign frfWriteBundle_1_wrenf = ~wbInfo_0_cp & wen[0] | divSqrt_wen; // @[FPU.scala:805:44, :896:32, :939:20, :940:19, :968:{10,24,30,35}] wire _unswizzled_T_3 = wdata_1[31]; // @[package.scala:39:76] wire _frfWriteBundle_1_wrdata_prevRecoded_T = wdata_1[31]; // @[package.scala:39:76] wire _unswizzled_T_4 = wdata_1[52]; // @[package.scala:39:76] wire _frfWriteBundle_1_wrdata_prevRecoded_T_1 = wdata_1[52]; // @[package.scala:39:76] wire [30:0] _unswizzled_T_5 = wdata_1[30:0]; // @[package.scala:39:76] wire [30:0] _frfWriteBundle_1_wrdata_prevRecoded_T_2 = wdata_1[30:0]; // @[package.scala:39:76] wire [1:0] unswizzled_hi_1 = {_unswizzled_T_3, _unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10] wire [32:0] unswizzled_1 = {unswizzled_hi_1, _unswizzled_T_5}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_T_4 = wdata_1[64:60]; // @[package.scala:39:76] wire _prevOK_T_5 = &_prevOK_T_4; // @[FPU.scala:332:{49,84}] wire _prevOK_T_6 = ~_prevOK_T_5; // @[FPU.scala:332:84, :384:20] wire _prevOK_unswizzled_T_3 = unswizzled_1[15]; // @[FPU.scala:380:27, :381:10] wire _prevOK_unswizzled_T_4 = unswizzled_1[23]; // @[FPU.scala:380:27, :382:10] wire [14:0] _prevOK_unswizzled_T_5 = unswizzled_1[14:0]; // @[FPU.scala:380:27, :383:10] wire [1:0] prevOK_unswizzled_hi_1 = {_prevOK_unswizzled_T_3, _prevOK_unswizzled_T_4}; // @[FPU.scala:380:27, :381:10, :382:10] wire [16:0] prevOK_unswizzled_1 = {prevOK_unswizzled_hi_1, _prevOK_unswizzled_T_5}; // @[FPU.scala:380:27, :383:10] wire [4:0] _prevOK_prevOK_T_3 = unswizzled_1[32:28]; // @[FPU.scala:332:49, :380:27] wire _prevOK_prevOK_T_4 = &_prevOK_prevOK_T_3; // @[FPU.scala:332:{49,84}] wire _prevOK_prevOK_T_5 = ~_prevOK_prevOK_T_4; // @[FPU.scala:332:84, :384:20] wire [2:0] _prevOK_curOK_T_7 = unswizzled_1[31:29]; // @[FPU.scala:249:25, :380:27] wire _prevOK_curOK_T_8 = &_prevOK_curOK_T_7; // @[FPU.scala:249:{25,56}] wire _prevOK_curOK_T_9 = ~_prevOK_curOK_T_8; // @[FPU.scala:249:56, :385:19] wire _prevOK_curOK_T_10 = unswizzled_1[28]; // @[FPU.scala:380:27, :385:35] wire [6:0] _prevOK_curOK_T_11 = unswizzled_1[22:16]; // @[FPU.scala:380:27, :385:60] wire _prevOK_curOK_T_12 = &_prevOK_curOK_T_11; // @[FPU.scala:385:{60,96}] wire _prevOK_curOK_T_13 = _prevOK_curOK_T_10 == _prevOK_curOK_T_12; // @[FPU.scala:385:{35,55,96}] wire prevOK_curOK_1 = _prevOK_curOK_T_9 | _prevOK_curOK_T_13; // @[FPU.scala:385:{19,31,55}] wire _prevOK_T_7 = prevOK_curOK_1; // @[FPU.scala:385:31, :386:14] wire prevOK_1 = _prevOK_T_6 | _prevOK_T_7; // @[FPU.scala:384:{20,33}, :386:14] wire [2:0] _curOK_T_7 = wdata_1[63:61]; // @[package.scala:39:76] wire [2:0] _frfWriteBundle_1_wrdata_T_1 = wdata_1[63:61]; // @[package.scala:39:76] wire _curOK_T_8 = &_curOK_T_7; // @[FPU.scala:249:{25,56}] wire _curOK_T_9 = ~_curOK_T_8; // @[FPU.scala:249:56, :385:19] wire _curOK_T_10 = wdata_1[60]; // @[package.scala:39:76] wire [19:0] _curOK_T_11 = wdata_1[51:32]; // @[package.scala:39:76] wire _curOK_T_12 = &_curOK_T_11; // @[FPU.scala:385:{60,96}] wire _curOK_T_13 = _curOK_T_10 == _curOK_T_12; // @[FPU.scala:385:{35,55,96}] wire curOK_1 = _curOK_T_9 | _curOK_T_13; // @[FPU.scala:385:{19,31,55}]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_92 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<13>(0h1000))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<17>(0h10000))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<18>(0h2f000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<27>(0h4000000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_27, _T_32) node _T_64 = or(_T_63, _T_37) node _T_65 = or(_T_64, _T_42) node _T_66 = or(_T_65, _T_47) node _T_67 = or(_T_66, _T_52) node _T_68 = or(_T_67, _T_57) node _T_69 = or(_T_68, _T_62) node _T_70 = and(_T_22, _T_69) node _T_71 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_72 = or(UInt<1>(0h0), _T_71) node _T_73 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_74 = cvt(_T_73) node _T_75 = and(_T_74, asSInt(UInt<17>(0h10000))) node _T_76 = asSInt(_T_75) node _T_77 = eq(_T_76, asSInt(UInt<1>(0h0))) node _T_78 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_79 = cvt(_T_78) node _T_80 = and(_T_79, asSInt(UInt<29>(0h10000000))) node _T_81 = asSInt(_T_80) node _T_82 = eq(_T_81, asSInt(UInt<1>(0h0))) node _T_83 = or(_T_77, _T_82) node _T_84 = and(_T_72, _T_83) node _T_85 = or(UInt<1>(0h0), _T_70) node _T_86 = or(_T_85, _T_84) node _T_87 = and(_T_21, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_87, UInt<1>(0h1), "") : assert_2 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<14>(0h2000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<13>(0h1000))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_106 = cvt(_T_105) node _T_107 = and(_T_106, asSInt(UInt<17>(0h10000))) node _T_108 = asSInt(_T_107) node _T_109 = eq(_T_108, asSInt(UInt<1>(0h0))) node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_111 = cvt(_T_110) node _T_112 = and(_T_111, asSInt(UInt<18>(0h2f000))) node _T_113 = asSInt(_T_112) node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0))) node _T_115 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_116 = cvt(_T_115) node _T_117 = and(_T_116, asSInt(UInt<17>(0h10000))) node _T_118 = asSInt(_T_117) node _T_119 = eq(_T_118, asSInt(UInt<1>(0h0))) node _T_120 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_121 = cvt(_T_120) node _T_122 = and(_T_121, asSInt(UInt<13>(0h1000))) node _T_123 = asSInt(_T_122) node _T_124 = eq(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_126 = cvt(_T_125) node _T_127 = and(_T_126, asSInt(UInt<17>(0h10000))) node _T_128 = asSInt(_T_127) node _T_129 = eq(_T_128, asSInt(UInt<1>(0h0))) node _T_130 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<27>(0h4000000))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_136 = cvt(_T_135) node _T_137 = and(_T_136, asSInt(UInt<13>(0h1000))) node _T_138 = asSInt(_T_137) node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0))) node _T_140 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_141 = cvt(_T_140) node _T_142 = and(_T_141, asSInt(UInt<29>(0h10000000))) node _T_143 = asSInt(_T_142) node _T_144 = eq(_T_143, asSInt(UInt<1>(0h0))) node _T_145 = or(_T_99, _T_104) node _T_146 = or(_T_145, _T_109) node _T_147 = or(_T_146, _T_114) node _T_148 = or(_T_147, _T_119) node _T_149 = or(_T_148, _T_124) node _T_150 = or(_T_149, _T_129) node _T_151 = or(_T_150, _T_134) node _T_152 = or(_T_151, _T_139) node _T_153 = or(_T_152, _T_144) node _T_154 = and(_T_94, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = and(UInt<1>(0h0), _T_155) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_156, UInt<1>(0h1), "") : assert_3 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_163 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_163, UInt<1>(0h1), "") : assert_5 node _T_167 = asUInt(reset) node _T_168 = eq(_T_167, UInt<1>(0h0)) when _T_168 : node _T_169 = eq(is_aligned, UInt<1>(0h0)) when _T_169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_170 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_171 = asUInt(reset) node _T_172 = eq(_T_171, UInt<1>(0h0)) when _T_172 : node _T_173 = eq(_T_170, UInt<1>(0h0)) when _T_173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_170, UInt<1>(0h1), "") : assert_7 node _T_174 = not(io.in.a.bits.mask) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_175, UInt<1>(0h1), "") : assert_8 node _T_179 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_179, UInt<1>(0h1), "") : assert_9 node _T_183 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_183 : node _T_184 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_185 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_186 = and(_T_184, _T_185) node _T_187 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_188 = and(_T_186, _T_187) node _T_189 = or(UInt<1>(0h0), _T_188) node _T_190 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_191 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_192 = cvt(_T_191) node _T_193 = and(_T_192, asSInt(UInt<14>(0h2000))) node _T_194 = asSInt(_T_193) node _T_195 = eq(_T_194, asSInt(UInt<1>(0h0))) node _T_196 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_197 = cvt(_T_196) node _T_198 = and(_T_197, asSInt(UInt<13>(0h1000))) node _T_199 = asSInt(_T_198) node _T_200 = eq(_T_199, asSInt(UInt<1>(0h0))) node _T_201 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_202 = cvt(_T_201) node _T_203 = and(_T_202, asSInt(UInt<17>(0h10000))) node _T_204 = asSInt(_T_203) node _T_205 = eq(_T_204, asSInt(UInt<1>(0h0))) node _T_206 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<18>(0h2f000))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<17>(0h10000))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_217 = cvt(_T_216) node _T_218 = and(_T_217, asSInt(UInt<13>(0h1000))) node _T_219 = asSInt(_T_218) node _T_220 = eq(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_222 = cvt(_T_221) node _T_223 = and(_T_222, asSInt(UInt<27>(0h4000000))) node _T_224 = asSInt(_T_223) node _T_225 = eq(_T_224, asSInt(UInt<1>(0h0))) node _T_226 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<13>(0h1000))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_195, _T_200) node _T_232 = or(_T_231, _T_205) node _T_233 = or(_T_232, _T_210) node _T_234 = or(_T_233, _T_215) node _T_235 = or(_T_234, _T_220) node _T_236 = or(_T_235, _T_225) node _T_237 = or(_T_236, _T_230) node _T_238 = and(_T_190, _T_237) node _T_239 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_242 = cvt(_T_241) node _T_243 = and(_T_242, asSInt(UInt<17>(0h10000))) node _T_244 = asSInt(_T_243) node _T_245 = eq(_T_244, asSInt(UInt<1>(0h0))) node _T_246 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_247 = cvt(_T_246) node _T_248 = and(_T_247, asSInt(UInt<29>(0h10000000))) node _T_249 = asSInt(_T_248) node _T_250 = eq(_T_249, asSInt(UInt<1>(0h0))) node _T_251 = or(_T_245, _T_250) node _T_252 = and(_T_240, _T_251) node _T_253 = or(UInt<1>(0h0), _T_238) node _T_254 = or(_T_253, _T_252) node _T_255 = and(_T_189, _T_254) node _T_256 = asUInt(reset) node _T_257 = eq(_T_256, UInt<1>(0h0)) when _T_257 : node _T_258 = eq(_T_255, UInt<1>(0h0)) when _T_258 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_255, UInt<1>(0h1), "") : assert_10 node _T_259 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_260 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_261 = and(_T_259, _T_260) node _T_262 = or(UInt<1>(0h0), _T_261) node _T_263 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_264 = cvt(_T_263) node _T_265 = and(_T_264, asSInt(UInt<14>(0h2000))) node _T_266 = asSInt(_T_265) node _T_267 = eq(_T_266, asSInt(UInt<1>(0h0))) node _T_268 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_269 = cvt(_T_268) node _T_270 = and(_T_269, asSInt(UInt<13>(0h1000))) node _T_271 = asSInt(_T_270) node _T_272 = eq(_T_271, asSInt(UInt<1>(0h0))) node _T_273 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_274 = cvt(_T_273) node _T_275 = and(_T_274, asSInt(UInt<17>(0h10000))) node _T_276 = asSInt(_T_275) node _T_277 = eq(_T_276, asSInt(UInt<1>(0h0))) node _T_278 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_279 = cvt(_T_278) node _T_280 = and(_T_279, asSInt(UInt<18>(0h2f000))) node _T_281 = asSInt(_T_280) node _T_282 = eq(_T_281, asSInt(UInt<1>(0h0))) node _T_283 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<17>(0h10000))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<13>(0h1000))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_294 = cvt(_T_293) node _T_295 = and(_T_294, asSInt(UInt<17>(0h10000))) node _T_296 = asSInt(_T_295) node _T_297 = eq(_T_296, asSInt(UInt<1>(0h0))) node _T_298 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_299 = cvt(_T_298) node _T_300 = and(_T_299, asSInt(UInt<27>(0h4000000))) node _T_301 = asSInt(_T_300) node _T_302 = eq(_T_301, asSInt(UInt<1>(0h0))) node _T_303 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_304 = cvt(_T_303) node _T_305 = and(_T_304, asSInt(UInt<13>(0h1000))) node _T_306 = asSInt(_T_305) node _T_307 = eq(_T_306, asSInt(UInt<1>(0h0))) node _T_308 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_309 = cvt(_T_308) node _T_310 = and(_T_309, asSInt(UInt<29>(0h10000000))) node _T_311 = asSInt(_T_310) node _T_312 = eq(_T_311, asSInt(UInt<1>(0h0))) node _T_313 = or(_T_267, _T_272) node _T_314 = or(_T_313, _T_277) node _T_315 = or(_T_314, _T_282) node _T_316 = or(_T_315, _T_287) node _T_317 = or(_T_316, _T_292) node _T_318 = or(_T_317, _T_297) node _T_319 = or(_T_318, _T_302) node _T_320 = or(_T_319, _T_307) node _T_321 = or(_T_320, _T_312) node _T_322 = and(_T_262, _T_321) node _T_323 = or(UInt<1>(0h0), _T_322) node _T_324 = and(UInt<1>(0h0), _T_323) node _T_325 = asUInt(reset) node _T_326 = eq(_T_325, UInt<1>(0h0)) when _T_326 : node _T_327 = eq(_T_324, UInt<1>(0h0)) when _T_327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_324, UInt<1>(0h1), "") : assert_11 node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_331 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_331, UInt<1>(0h1), "") : assert_13 node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(is_aligned, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_338 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_338, UInt<1>(0h1), "") : assert_15 node _T_342 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_342, UInt<1>(0h1), "") : assert_16 node _T_346 = not(io.in.a.bits.mask) node _T_347 = eq(_T_346, UInt<1>(0h0)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_347, UInt<1>(0h1), "") : assert_17 node _T_351 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_351, UInt<1>(0h1), "") : assert_18 node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_355 : node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(_T_361, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_361, UInt<1>(0h1), "") : assert_19 node _T_365 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_366 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_367 = and(_T_365, _T_366) node _T_368 = or(UInt<1>(0h0), _T_367) node _T_369 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_370 = cvt(_T_369) node _T_371 = and(_T_370, asSInt(UInt<13>(0h1000))) node _T_372 = asSInt(_T_371) node _T_373 = eq(_T_372, asSInt(UInt<1>(0h0))) node _T_374 = and(_T_368, _T_373) node _T_375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_376 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_377 = and(_T_375, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_380 = cvt(_T_379) node _T_381 = and(_T_380, asSInt(UInt<14>(0h2000))) node _T_382 = asSInt(_T_381) node _T_383 = eq(_T_382, asSInt(UInt<1>(0h0))) node _T_384 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_385 = cvt(_T_384) node _T_386 = and(_T_385, asSInt(UInt<17>(0h10000))) node _T_387 = asSInt(_T_386) node _T_388 = eq(_T_387, asSInt(UInt<1>(0h0))) node _T_389 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_390 = cvt(_T_389) node _T_391 = and(_T_390, asSInt(UInt<18>(0h2f000))) node _T_392 = asSInt(_T_391) node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0))) node _T_394 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_395 = cvt(_T_394) node _T_396 = and(_T_395, asSInt(UInt<17>(0h10000))) node _T_397 = asSInt(_T_396) node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0))) node _T_399 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_400 = cvt(_T_399) node _T_401 = and(_T_400, asSInt(UInt<13>(0h1000))) node _T_402 = asSInt(_T_401) node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0))) node _T_404 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_405 = cvt(_T_404) node _T_406 = and(_T_405, asSInt(UInt<17>(0h10000))) node _T_407 = asSInt(_T_406) node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0))) node _T_409 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_410 = cvt(_T_409) node _T_411 = and(_T_410, asSInt(UInt<27>(0h4000000))) node _T_412 = asSInt(_T_411) node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0))) node _T_414 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_415 = cvt(_T_414) node _T_416 = and(_T_415, asSInt(UInt<13>(0h1000))) node _T_417 = asSInt(_T_416) node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0))) node _T_419 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_420 = cvt(_T_419) node _T_421 = and(_T_420, asSInt(UInt<29>(0h10000000))) node _T_422 = asSInt(_T_421) node _T_423 = eq(_T_422, asSInt(UInt<1>(0h0))) node _T_424 = or(_T_383, _T_388) node _T_425 = or(_T_424, _T_393) node _T_426 = or(_T_425, _T_398) node _T_427 = or(_T_426, _T_403) node _T_428 = or(_T_427, _T_408) node _T_429 = or(_T_428, _T_413) node _T_430 = or(_T_429, _T_418) node _T_431 = or(_T_430, _T_423) node _T_432 = and(_T_378, _T_431) node _T_433 = or(UInt<1>(0h0), _T_374) node _T_434 = or(_T_433, _T_432) node _T_435 = asUInt(reset) node _T_436 = eq(_T_435, UInt<1>(0h0)) when _T_436 : node _T_437 = eq(_T_434, UInt<1>(0h0)) when _T_437 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_434, UInt<1>(0h1), "") : assert_20 node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_441 = asUInt(reset) node _T_442 = eq(_T_441, UInt<1>(0h0)) when _T_442 : node _T_443 = eq(is_aligned, UInt<1>(0h0)) when _T_443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_444 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_445 = asUInt(reset) node _T_446 = eq(_T_445, UInt<1>(0h0)) when _T_446 : node _T_447 = eq(_T_444, UInt<1>(0h0)) when _T_447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_444, UInt<1>(0h1), "") : assert_23 node _T_448 = eq(io.in.a.bits.mask, mask) node _T_449 = asUInt(reset) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(_T_448, UInt<1>(0h0)) when _T_451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_448, UInt<1>(0h1), "") : assert_24 node _T_452 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_452, UInt<1>(0h1), "") : assert_25 node _T_456 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_456 : node _T_457 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_458 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_459 = and(_T_457, _T_458) node _T_460 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_461 = and(_T_459, _T_460) node _T_462 = or(UInt<1>(0h0), _T_461) node _T_463 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_464 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_465 = and(_T_463, _T_464) node _T_466 = or(UInt<1>(0h0), _T_465) node _T_467 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<13>(0h1000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = and(_T_466, _T_471) node _T_473 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_474 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_475 = and(_T_473, _T_474) node _T_476 = or(UInt<1>(0h0), _T_475) node _T_477 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<14>(0h2000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<18>(0h2f000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_488 = cvt(_T_487) node _T_489 = and(_T_488, asSInt(UInt<17>(0h10000))) node _T_490 = asSInt(_T_489) node _T_491 = eq(_T_490, asSInt(UInt<1>(0h0))) node _T_492 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_498 = cvt(_T_497) node _T_499 = and(_T_498, asSInt(UInt<17>(0h10000))) node _T_500 = asSInt(_T_499) node _T_501 = eq(_T_500, asSInt(UInt<1>(0h0))) node _T_502 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_503 = cvt(_T_502) node _T_504 = and(_T_503, asSInt(UInt<27>(0h4000000))) node _T_505 = asSInt(_T_504) node _T_506 = eq(_T_505, asSInt(UInt<1>(0h0))) node _T_507 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_508 = cvt(_T_507) node _T_509 = and(_T_508, asSInt(UInt<13>(0h1000))) node _T_510 = asSInt(_T_509) node _T_511 = eq(_T_510, asSInt(UInt<1>(0h0))) node _T_512 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_513 = cvt(_T_512) node _T_514 = and(_T_513, asSInt(UInt<29>(0h10000000))) node _T_515 = asSInt(_T_514) node _T_516 = eq(_T_515, asSInt(UInt<1>(0h0))) node _T_517 = or(_T_481, _T_486) node _T_518 = or(_T_517, _T_491) node _T_519 = or(_T_518, _T_496) node _T_520 = or(_T_519, _T_501) node _T_521 = or(_T_520, _T_506) node _T_522 = or(_T_521, _T_511) node _T_523 = or(_T_522, _T_516) node _T_524 = and(_T_476, _T_523) node _T_525 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_526 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_527 = cvt(_T_526) node _T_528 = and(_T_527, asSInt(UInt<17>(0h10000))) node _T_529 = asSInt(_T_528) node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0))) node _T_531 = and(_T_525, _T_530) node _T_532 = or(UInt<1>(0h0), _T_472) node _T_533 = or(_T_532, _T_524) node _T_534 = or(_T_533, _T_531) node _T_535 = and(_T_462, _T_534) node _T_536 = asUInt(reset) node _T_537 = eq(_T_536, UInt<1>(0h0)) when _T_537 : node _T_538 = eq(_T_535, UInt<1>(0h0)) when _T_538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_535, UInt<1>(0h1), "") : assert_26 node _T_539 = asUInt(reset) node _T_540 = eq(_T_539, UInt<1>(0h0)) when _T_540 : node _T_541 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(is_aligned, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_545 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_545, UInt<1>(0h1), "") : assert_29 node _T_549 = eq(io.in.a.bits.mask, mask) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_549, UInt<1>(0h1), "") : assert_30 node _T_553 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_553 : node _T_554 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_555 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_556 = and(_T_554, _T_555) node _T_557 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_558 = and(_T_556, _T_557) node _T_559 = or(UInt<1>(0h0), _T_558) node _T_560 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_561 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_562 = and(_T_560, _T_561) node _T_563 = or(UInt<1>(0h0), _T_562) node _T_564 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<13>(0h1000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = and(_T_563, _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<14>(0h2000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<18>(0h2f000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_585 = cvt(_T_584) node _T_586 = and(_T_585, asSInt(UInt<17>(0h10000))) node _T_587 = asSInt(_T_586) node _T_588 = eq(_T_587, asSInt(UInt<1>(0h0))) node _T_589 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_590 = cvt(_T_589) node _T_591 = and(_T_590, asSInt(UInt<13>(0h1000))) node _T_592 = asSInt(_T_591) node _T_593 = eq(_T_592, asSInt(UInt<1>(0h0))) node _T_594 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_595 = cvt(_T_594) node _T_596 = and(_T_595, asSInt(UInt<17>(0h10000))) node _T_597 = asSInt(_T_596) node _T_598 = eq(_T_597, asSInt(UInt<1>(0h0))) node _T_599 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_600 = cvt(_T_599) node _T_601 = and(_T_600, asSInt(UInt<27>(0h4000000))) node _T_602 = asSInt(_T_601) node _T_603 = eq(_T_602, asSInt(UInt<1>(0h0))) node _T_604 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_605 = cvt(_T_604) node _T_606 = and(_T_605, asSInt(UInt<13>(0h1000))) node _T_607 = asSInt(_T_606) node _T_608 = eq(_T_607, asSInt(UInt<1>(0h0))) node _T_609 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<29>(0h10000000))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_578, _T_583) node _T_615 = or(_T_614, _T_588) node _T_616 = or(_T_615, _T_593) node _T_617 = or(_T_616, _T_598) node _T_618 = or(_T_617, _T_603) node _T_619 = or(_T_618, _T_608) node _T_620 = or(_T_619, _T_613) node _T_621 = and(_T_573, _T_620) node _T_622 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_623 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_624 = cvt(_T_623) node _T_625 = and(_T_624, asSInt(UInt<17>(0h10000))) node _T_626 = asSInt(_T_625) node _T_627 = eq(_T_626, asSInt(UInt<1>(0h0))) node _T_628 = and(_T_622, _T_627) node _T_629 = or(UInt<1>(0h0), _T_569) node _T_630 = or(_T_629, _T_621) node _T_631 = or(_T_630, _T_628) node _T_632 = and(_T_559, _T_631) node _T_633 = asUInt(reset) node _T_634 = eq(_T_633, UInt<1>(0h0)) when _T_634 : node _T_635 = eq(_T_632, UInt<1>(0h0)) when _T_635 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_632, UInt<1>(0h1), "") : assert_31 node _T_636 = asUInt(reset) node _T_637 = eq(_T_636, UInt<1>(0h0)) when _T_637 : node _T_638 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_639 = asUInt(reset) node _T_640 = eq(_T_639, UInt<1>(0h0)) when _T_640 : node _T_641 = eq(is_aligned, UInt<1>(0h0)) when _T_641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_642 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_643 = asUInt(reset) node _T_644 = eq(_T_643, UInt<1>(0h0)) when _T_644 : node _T_645 = eq(_T_642, UInt<1>(0h0)) when _T_645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_642, UInt<1>(0h1), "") : assert_34 node _T_646 = not(mask) node _T_647 = and(io.in.a.bits.mask, _T_646) node _T_648 = eq(_T_647, UInt<1>(0h0)) node _T_649 = asUInt(reset) node _T_650 = eq(_T_649, UInt<1>(0h0)) when _T_650 : node _T_651 = eq(_T_648, UInt<1>(0h0)) when _T_651 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_648, UInt<1>(0h1), "") : assert_35 node _T_652 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_652 : node _T_653 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_654 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_655 = and(_T_653, _T_654) node _T_656 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_657 = and(_T_655, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_660 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_661 = and(_T_659, _T_660) node _T_662 = or(UInt<1>(0h0), _T_661) node _T_663 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<14>(0h2000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<18>(0h2f000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<17>(0h10000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<17>(0h10000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_694 = cvt(_T_693) node _T_695 = and(_T_694, asSInt(UInt<27>(0h4000000))) node _T_696 = asSInt(_T_695) node _T_697 = eq(_T_696, asSInt(UInt<1>(0h0))) node _T_698 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_699 = cvt(_T_698) node _T_700 = and(_T_699, asSInt(UInt<13>(0h1000))) node _T_701 = asSInt(_T_700) node _T_702 = eq(_T_701, asSInt(UInt<1>(0h0))) node _T_703 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_704 = cvt(_T_703) node _T_705 = and(_T_704, asSInt(UInt<29>(0h10000000))) node _T_706 = asSInt(_T_705) node _T_707 = eq(_T_706, asSInt(UInt<1>(0h0))) node _T_708 = or(_T_667, _T_672) node _T_709 = or(_T_708, _T_677) node _T_710 = or(_T_709, _T_682) node _T_711 = or(_T_710, _T_687) node _T_712 = or(_T_711, _T_692) node _T_713 = or(_T_712, _T_697) node _T_714 = or(_T_713, _T_702) node _T_715 = or(_T_714, _T_707) node _T_716 = and(_T_662, _T_715) node _T_717 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_718 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_719 = cvt(_T_718) node _T_720 = and(_T_719, asSInt(UInt<17>(0h10000))) node _T_721 = asSInt(_T_720) node _T_722 = eq(_T_721, asSInt(UInt<1>(0h0))) node _T_723 = and(_T_717, _T_722) node _T_724 = or(UInt<1>(0h0), _T_716) node _T_725 = or(_T_724, _T_723) node _T_726 = and(_T_658, _T_725) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_726, UInt<1>(0h1), "") : assert_36 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_736 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_736, UInt<1>(0h1), "") : assert_39 node _T_740 = eq(io.in.a.bits.mask, mask) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_740, UInt<1>(0h1), "") : assert_40 node _T_744 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_746 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_752 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_753 = and(_T_751, _T_752) node _T_754 = or(UInt<1>(0h0), _T_753) node _T_755 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_756 = cvt(_T_755) node _T_757 = and(_T_756, asSInt(UInt<14>(0h2000))) node _T_758 = asSInt(_T_757) node _T_759 = eq(_T_758, asSInt(UInt<1>(0h0))) node _T_760 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_761 = cvt(_T_760) node _T_762 = and(_T_761, asSInt(UInt<13>(0h1000))) node _T_763 = asSInt(_T_762) node _T_764 = eq(_T_763, asSInt(UInt<1>(0h0))) node _T_765 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_766 = cvt(_T_765) node _T_767 = and(_T_766, asSInt(UInt<18>(0h2f000))) node _T_768 = asSInt(_T_767) node _T_769 = eq(_T_768, asSInt(UInt<1>(0h0))) node _T_770 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_771 = cvt(_T_770) node _T_772 = and(_T_771, asSInt(UInt<17>(0h10000))) node _T_773 = asSInt(_T_772) node _T_774 = eq(_T_773, asSInt(UInt<1>(0h0))) node _T_775 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_776 = cvt(_T_775) node _T_777 = and(_T_776, asSInt(UInt<13>(0h1000))) node _T_778 = asSInt(_T_777) node _T_779 = eq(_T_778, asSInt(UInt<1>(0h0))) node _T_780 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_781 = cvt(_T_780) node _T_782 = and(_T_781, asSInt(UInt<17>(0h10000))) node _T_783 = asSInt(_T_782) node _T_784 = eq(_T_783, asSInt(UInt<1>(0h0))) node _T_785 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_786 = cvt(_T_785) node _T_787 = and(_T_786, asSInt(UInt<27>(0h4000000))) node _T_788 = asSInt(_T_787) node _T_789 = eq(_T_788, asSInt(UInt<1>(0h0))) node _T_790 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<13>(0h1000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_759, _T_764) node _T_801 = or(_T_800, _T_769) node _T_802 = or(_T_801, _T_774) node _T_803 = or(_T_802, _T_779) node _T_804 = or(_T_803, _T_784) node _T_805 = or(_T_804, _T_789) node _T_806 = or(_T_805, _T_794) node _T_807 = or(_T_806, _T_799) node _T_808 = and(_T_754, _T_807) node _T_809 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_810 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_811 = cvt(_T_810) node _T_812 = and(_T_811, asSInt(UInt<17>(0h10000))) node _T_813 = asSInt(_T_812) node _T_814 = eq(_T_813, asSInt(UInt<1>(0h0))) node _T_815 = and(_T_809, _T_814) node _T_816 = or(UInt<1>(0h0), _T_808) node _T_817 = or(_T_816, _T_815) node _T_818 = and(_T_750, _T_817) node _T_819 = asUInt(reset) node _T_820 = eq(_T_819, UInt<1>(0h0)) when _T_820 : node _T_821 = eq(_T_818, UInt<1>(0h0)) when _T_821 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_818, UInt<1>(0h1), "") : assert_41 node _T_822 = asUInt(reset) node _T_823 = eq(_T_822, UInt<1>(0h0)) when _T_823 : node _T_824 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_824 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(is_aligned, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_828 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_828, UInt<1>(0h1), "") : assert_44 node _T_832 = eq(io.in.a.bits.mask, mask) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_832, UInt<1>(0h1), "") : assert_45 node _T_836 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_836 : node _T_837 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_838 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_839 = and(_T_837, _T_838) node _T_840 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_841 = and(_T_839, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_854 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_855 = cvt(_T_854) node _T_856 = and(_T_855, asSInt(UInt<14>(0h2000))) node _T_857 = asSInt(_T_856) node _T_858 = eq(_T_857, asSInt(UInt<1>(0h0))) node _T_859 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_860 = cvt(_T_859) node _T_861 = and(_T_860, asSInt(UInt<17>(0h10000))) node _T_862 = asSInt(_T_861) node _T_863 = eq(_T_862, asSInt(UInt<1>(0h0))) node _T_864 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_865 = cvt(_T_864) node _T_866 = and(_T_865, asSInt(UInt<18>(0h2f000))) node _T_867 = asSInt(_T_866) node _T_868 = eq(_T_867, asSInt(UInt<1>(0h0))) node _T_869 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_870 = cvt(_T_869) node _T_871 = and(_T_870, asSInt(UInt<17>(0h10000))) node _T_872 = asSInt(_T_871) node _T_873 = eq(_T_872, asSInt(UInt<1>(0h0))) node _T_874 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_875 = cvt(_T_874) node _T_876 = and(_T_875, asSInt(UInt<13>(0h1000))) node _T_877 = asSInt(_T_876) node _T_878 = eq(_T_877, asSInt(UInt<1>(0h0))) node _T_879 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_880 = cvt(_T_879) node _T_881 = and(_T_880, asSInt(UInt<27>(0h4000000))) node _T_882 = asSInt(_T_881) node _T_883 = eq(_T_882, asSInt(UInt<1>(0h0))) node _T_884 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_885 = cvt(_T_884) node _T_886 = and(_T_885, asSInt(UInt<13>(0h1000))) node _T_887 = asSInt(_T_886) node _T_888 = eq(_T_887, asSInt(UInt<1>(0h0))) node _T_889 = or(_T_858, _T_863) node _T_890 = or(_T_889, _T_868) node _T_891 = or(_T_890, _T_873) node _T_892 = or(_T_891, _T_878) node _T_893 = or(_T_892, _T_883) node _T_894 = or(_T_893, _T_888) node _T_895 = and(_T_853, _T_894) node _T_896 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_897 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_898 = and(_T_896, _T_897) node _T_899 = or(UInt<1>(0h0), _T_898) node _T_900 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_901 = cvt(_T_900) node _T_902 = and(_T_901, asSInt(UInt<17>(0h10000))) node _T_903 = asSInt(_T_902) node _T_904 = eq(_T_903, asSInt(UInt<1>(0h0))) node _T_905 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_906 = cvt(_T_905) node _T_907 = and(_T_906, asSInt(UInt<29>(0h10000000))) node _T_908 = asSInt(_T_907) node _T_909 = eq(_T_908, asSInt(UInt<1>(0h0))) node _T_910 = or(_T_904, _T_909) node _T_911 = and(_T_899, _T_910) node _T_912 = or(UInt<1>(0h0), _T_852) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_911) node _T_915 = and(_T_842, _T_914) node _T_916 = asUInt(reset) node _T_917 = eq(_T_916, UInt<1>(0h0)) when _T_917 : node _T_918 = eq(_T_915, UInt<1>(0h0)) when _T_918 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_915, UInt<1>(0h1), "") : assert_46 node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_922 = asUInt(reset) node _T_923 = eq(_T_922, UInt<1>(0h0)) when _T_923 : node _T_924 = eq(is_aligned, UInt<1>(0h0)) when _T_924 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_925 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_T_925, UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_925, UInt<1>(0h1), "") : assert_49 node _T_929 = eq(io.in.a.bits.mask, mask) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_929, UInt<1>(0h1), "") : assert_50 node _T_933 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_934 = asUInt(reset) node _T_935 = eq(_T_934, UInt<1>(0h0)) when _T_935 : node _T_936 = eq(_T_933, UInt<1>(0h0)) when _T_936 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_933, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_937 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(_T_937, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_937, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_941 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_941 : node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_945 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_945, UInt<1>(0h1), "") : assert_54 node _T_949 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_950 = asUInt(reset) node _T_951 = eq(_T_950, UInt<1>(0h0)) when _T_951 : node _T_952 = eq(_T_949, UInt<1>(0h0)) when _T_952 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_949, UInt<1>(0h1), "") : assert_55 node _T_953 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_954 = asUInt(reset) node _T_955 = eq(_T_954, UInt<1>(0h0)) when _T_955 : node _T_956 = eq(_T_953, UInt<1>(0h0)) when _T_956 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_953, UInt<1>(0h1), "") : assert_56 node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_958 = asUInt(reset) node _T_959 = eq(_T_958, UInt<1>(0h0)) when _T_959 : node _T_960 = eq(_T_957, UInt<1>(0h0)) when _T_960 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_957, UInt<1>(0h1), "") : assert_57 node _T_961 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_961 : node _T_962 = asUInt(reset) node _T_963 = eq(_T_962, UInt<1>(0h0)) when _T_963 : node _T_964 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_964 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(sink_ok, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_968 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_969 = asUInt(reset) node _T_970 = eq(_T_969, UInt<1>(0h0)) when _T_970 : node _T_971 = eq(_T_968, UInt<1>(0h0)) when _T_971 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_968, UInt<1>(0h1), "") : assert_60 node _T_972 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_973 = asUInt(reset) node _T_974 = eq(_T_973, UInt<1>(0h0)) when _T_974 : node _T_975 = eq(_T_972, UInt<1>(0h0)) when _T_975 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_972, UInt<1>(0h1), "") : assert_61 node _T_976 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_977 = asUInt(reset) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(_T_976, UInt<1>(0h0)) when _T_979 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_976, UInt<1>(0h1), "") : assert_62 node _T_980 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_981 = asUInt(reset) node _T_982 = eq(_T_981, UInt<1>(0h0)) when _T_982 : node _T_983 = eq(_T_980, UInt<1>(0h0)) when _T_983 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_980, UInt<1>(0h1), "") : assert_63 node _T_984 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_985 = or(UInt<1>(0h1), _T_984) node _T_986 = asUInt(reset) node _T_987 = eq(_T_986, UInt<1>(0h0)) when _T_987 : node _T_988 = eq(_T_985, UInt<1>(0h0)) when _T_988 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_985, UInt<1>(0h1), "") : assert_64 node _T_989 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_989 : node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_993 = asUInt(reset) node _T_994 = eq(_T_993, UInt<1>(0h0)) when _T_994 : node _T_995 = eq(sink_ok, UInt<1>(0h0)) when _T_995 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_996 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_997 = asUInt(reset) node _T_998 = eq(_T_997, UInt<1>(0h0)) when _T_998 : node _T_999 = eq(_T_996, UInt<1>(0h0)) when _T_999 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_996, UInt<1>(0h1), "") : assert_67 node _T_1000 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1001 = asUInt(reset) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(_T_1000, UInt<1>(0h0)) when _T_1003 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1000, UInt<1>(0h1), "") : assert_68 node _T_1004 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_69 node _T_1008 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1009 = or(_T_1008, io.in.d.bits.corrupt) node _T_1010 = asUInt(reset) node _T_1011 = eq(_T_1010, UInt<1>(0h0)) when _T_1011 : node _T_1012 = eq(_T_1009, UInt<1>(0h0)) when _T_1012 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1009, UInt<1>(0h1), "") : assert_70 node _T_1013 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1014 = or(UInt<1>(0h1), _T_1013) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_71 node _T_1018 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1018 : node _T_1019 = asUInt(reset) node _T_1020 = eq(_T_1019, UInt<1>(0h0)) when _T_1020 : node _T_1021 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1021 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1022 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1023 = asUInt(reset) node _T_1024 = eq(_T_1023, UInt<1>(0h0)) when _T_1024 : node _T_1025 = eq(_T_1022, UInt<1>(0h0)) when _T_1025 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1022, UInt<1>(0h1), "") : assert_73 node _T_1026 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1027 = asUInt(reset) node _T_1028 = eq(_T_1027, UInt<1>(0h0)) when _T_1028 : node _T_1029 = eq(_T_1026, UInt<1>(0h0)) when _T_1029 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1026, UInt<1>(0h1), "") : assert_74 node _T_1030 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1031 = or(UInt<1>(0h1), _T_1030) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_75 node _T_1035 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1035 : node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1039 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1040 = asUInt(reset) node _T_1041 = eq(_T_1040, UInt<1>(0h0)) when _T_1041 : node _T_1042 = eq(_T_1039, UInt<1>(0h0)) when _T_1042 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1039, UInt<1>(0h1), "") : assert_77 node _T_1043 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1044 = or(_T_1043, io.in.d.bits.corrupt) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_78 node _T_1048 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1049 = or(UInt<1>(0h1), _T_1048) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_79 node _T_1053 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1053 : node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1057 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_81 node _T_1061 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_82 node _T_1065 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1066 = or(UInt<1>(0h1), _T_1065) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1070 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1074 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1078 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1082 = eq(a_first, UInt<1>(0h0)) node _T_1083 = and(io.in.a.valid, _T_1082) when _T_1083 : node _T_1084 = eq(io.in.a.bits.opcode, opcode) node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(_T_1084, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1084, UInt<1>(0h1), "") : assert_87 node _T_1088 = eq(io.in.a.bits.param, param) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_88 node _T_1092 = eq(io.in.a.bits.size, size) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_89 node _T_1096 = eq(io.in.a.bits.source, source) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_90 node _T_1100 = eq(io.in.a.bits.address, address) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_91 node _T_1104 = and(io.in.a.ready, io.in.a.valid) node _T_1105 = and(_T_1104, a_first) when _T_1105 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1106 = eq(d_first, UInt<1>(0h0)) node _T_1107 = and(io.in.d.valid, _T_1106) when _T_1107 : node _T_1108 = eq(io.in.d.bits.opcode, opcode_1) node _T_1109 = asUInt(reset) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(_T_1108, UInt<1>(0h0)) when _T_1111 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1108, UInt<1>(0h1), "") : assert_92 node _T_1112 = eq(io.in.d.bits.param, param_1) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_93 node _T_1116 = eq(io.in.d.bits.size, size_1) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_94 node _T_1120 = eq(io.in.d.bits.source, source_1) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_95 node _T_1124 = eq(io.in.d.bits.sink, sink) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_96 node _T_1128 = eq(io.in.d.bits.denied, denied) node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(_T_1128, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1128, UInt<1>(0h1), "") : assert_97 node _T_1132 = and(io.in.d.ready, io.in.d.valid) node _T_1133 = and(_T_1132, d_first) when _T_1133 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1134 = and(io.in.a.valid, a_first_1) node _T_1135 = and(_T_1134, UInt<1>(0h1)) when _T_1135 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1136 = and(io.in.a.ready, io.in.a.valid) node _T_1137 = and(_T_1136, a_first_1) node _T_1138 = and(_T_1137, UInt<1>(0h1)) when _T_1138 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1139 = dshr(inflight, io.in.a.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_1) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = eq(d_release_ack, UInt<1>(0h0)) node _T_1148 = and(_T_1146, _T_1147) when _T_1148 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1149 = and(io.in.d.ready, io.in.d.valid) node _T_1150 = and(_T_1149, d_first_1) node _T_1151 = and(_T_1150, UInt<1>(0h1)) node _T_1152 = eq(d_release_ack, UInt<1>(0h0)) node _T_1153 = and(_T_1151, _T_1152) when _T_1153 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1154 = and(io.in.d.valid, d_first_1) node _T_1155 = and(_T_1154, UInt<1>(0h1)) node _T_1156 = eq(d_release_ack, UInt<1>(0h0)) node _T_1157 = and(_T_1155, _T_1156) when _T_1157 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1158 = dshr(inflight, io.in.d.bits.source) node _T_1159 = bits(_T_1158, 0, 0) node _T_1160 = or(_T_1159, same_cycle_resp) node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(_T_1160, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1160, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1164 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1165 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1166 = or(_T_1164, _T_1165) node _T_1167 = asUInt(reset) node _T_1168 = eq(_T_1167, UInt<1>(0h0)) when _T_1168 : node _T_1169 = eq(_T_1166, UInt<1>(0h0)) when _T_1169 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1166, UInt<1>(0h1), "") : assert_100 node _T_1170 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_101 else : node _T_1174 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1175 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_102 node _T_1180 = eq(io.in.d.bits.size, a_size_lookup) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_103 node _T_1184 = and(io.in.d.valid, d_first_1) node _T_1185 = and(_T_1184, a_first_1) node _T_1186 = and(_T_1185, io.in.a.valid) node _T_1187 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1188 = and(_T_1186, _T_1187) node _T_1189 = eq(d_release_ack, UInt<1>(0h0)) node _T_1190 = and(_T_1188, _T_1189) when _T_1190 : node _T_1191 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1192 = or(_T_1191, io.in.a.ready) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_104 node _T_1196 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1197 = orr(a_set_wo_ready) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) node _T_1199 = or(_T_1196, _T_1198) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_198 node _T_1203 = orr(inflight) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) node _T_1205 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1206 = or(_T_1204, _T_1205) node _T_1207 = lt(watchdog, plusarg_reader.out) node _T_1208 = or(_T_1206, _T_1207) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1212 = and(io.in.a.ready, io.in.a.valid) node _T_1213 = and(io.in.d.ready, io.in.d.valid) node _T_1214 = or(_T_1212, _T_1213) when _T_1214 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1215 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1216 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1217 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1218 = and(_T_1216, _T_1217) node _T_1219 = and(_T_1215, _T_1218) when _T_1219 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1220 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1221 = and(_T_1220, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1222 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1223 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = and(_T_1221, _T_1224) when _T_1225 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1226 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1227 = bits(_T_1226, 0, 0) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1232 = and(io.in.d.valid, d_first_2) node _T_1233 = and(_T_1232, UInt<1>(0h1)) node _T_1234 = and(_T_1233, d_release_ack_1) when _T_1234 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1235 = and(io.in.d.ready, io.in.d.valid) node _T_1236 = and(_T_1235, d_first_2) node _T_1237 = and(_T_1236, UInt<1>(0h1)) node _T_1238 = and(_T_1237, d_release_ack_1) when _T_1238 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1239 = and(io.in.d.valid, d_first_2) node _T_1240 = and(_T_1239, UInt<1>(0h1)) node _T_1241 = and(_T_1240, d_release_ack_1) when _T_1241 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1242 = dshr(inflight_1, io.in.d.bits.source) node _T_1243 = bits(_T_1242, 0, 0) node _T_1244 = or(_T_1243, same_cycle_resp_1) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1248 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_109 else : node _T_1252 = eq(io.in.d.bits.size, c_size_lookup) node _T_1253 = asUInt(reset) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(_T_1252, UInt<1>(0h0)) when _T_1255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1252, UInt<1>(0h1), "") : assert_110 node _T_1256 = and(io.in.d.valid, d_first_2) node _T_1257 = and(_T_1256, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1258 = and(_T_1257, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1259 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1260 = and(_T_1258, _T_1259) node _T_1261 = and(_T_1260, d_release_ack_1) node _T_1262 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1263 = and(_T_1261, _T_1262) when _T_1263 : node _T_1264 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1265 = or(_T_1264, _WIRE_23.ready) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_111 node _T_1269 = orr(c_set_wo_ready) when _T_1269 : node _T_1270 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1271 = asUInt(reset) node _T_1272 = eq(_T_1271, UInt<1>(0h0)) when _T_1272 : node _T_1273 = eq(_T_1270, UInt<1>(0h0)) when _T_1273 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1270, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_199 node _T_1274 = orr(inflight_1) node _T_1275 = eq(_T_1274, UInt<1>(0h0)) node _T_1276 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1277 = or(_T_1275, _T_1276) node _T_1278 = lt(watchdog_1, plusarg_reader_1.out) node _T_1279 = or(_T_1277, _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1283 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1284 = and(io.in.d.ready, io.in.d.valid) node _T_1285 = or(_T_1283, _T_1284) when _T_1285 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_92( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [19:0] _c_sizes_set_T_1 = 20'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [7:0] c_sizes_set = 8'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire _source_ok_T = ~io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire _source_ok_T_1 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_1; // @[Parameters.scala:1138:31] wire _T_1212 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1212; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1212; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1285 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1285; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1285; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [7:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [3:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [3:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [3:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [3:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [3:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [3:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [3:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [3:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [3:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [3:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [7:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [15:0] _a_size_lookup_T_6 = {8'h0, _a_size_lookup_T_1}; // @[Monitor.scala:641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [1:0] _GEN_3 = {1'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_4 = 2'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [1:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [1:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T & _a_set_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1138 = _T_1212 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1138 & _a_set_T[0]; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1138 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1138 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [3:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1138 ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [3:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [19:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :660:{52,77}] assign a_sizes_set = _T_1138 ? _a_sizes_set_T_1[7:0] : 8'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [7:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1184 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [1:0] _GEN_6 = {1'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [1:0] _GEN_7 = 2'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1184 & ~d_release_ack & _d_clr_wo_ready_T[0]; // @[OneHot.scala:58:35] wire _T_1153 = _T_1285 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1153 & _d_clr_T[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_5 = 31'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1153 ? _d_opcodes_clr_T_5[3:0] : 4'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [30:0] _d_sizes_clr_T_5 = 31'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1153 ? _d_sizes_clr_T_5[7:0] : 8'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [7:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [7:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [7:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [7:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [7:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [15:0] _c_size_lookup_T_6 = {8'h0, _c_size_lookup_T_1}; // @[Monitor.scala:750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [7:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1256 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1256 & d_release_ack_1 & _d_clr_wo_ready_T_1[0]; // @[OneHot.scala:58:35] wire _T_1238 = _T_1285 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1238 & _d_clr_T_1[0]; // @[OneHot.scala:58:35] wire [30:0] _d_opcodes_clr_T_11 = 31'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1238 ? _d_opcodes_clr_T_11[3:0] : 4'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [30:0] _d_sizes_clr_T_11 = 31'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1238 ? _d_sizes_clr_T_11[7:0] : 8'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = ~io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [7:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [7:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_32 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_288 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_32( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_288 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRecFM_small_e5_s11_3 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<17>, flip b : UInt<17>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} inst divSqrtRecFNToRaw of DivSqrtRecFMToRaw_small_e5_s11_3 connect divSqrtRecFNToRaw.clock, clock connect divSqrtRecFNToRaw.reset, reset connect io.inReady, divSqrtRecFNToRaw.io.inReady connect divSqrtRecFNToRaw.io.inValid, io.inValid connect divSqrtRecFNToRaw.io.sqrtOp, io.sqrtOp connect divSqrtRecFNToRaw.io.a, io.a connect divSqrtRecFNToRaw.io.b, io.b connect divSqrtRecFNToRaw.io.roundingMode, io.roundingMode connect io.outValid_div, divSqrtRecFNToRaw.io.rawOutValid_div connect io.outValid_sqrt, divSqrtRecFNToRaw.io.rawOutValid_sqrt inst roundRawFNToRecFN of RoundRawFNToRecFN_e5_s11_7 connect roundRawFNToRecFN.io.invalidExc, divSqrtRecFNToRaw.io.invalidExc connect roundRawFNToRecFN.io.infiniteExc, divSqrtRecFNToRaw.io.infiniteExc connect roundRawFNToRecFN.io.in.sig, divSqrtRecFNToRaw.io.rawOut.sig connect roundRawFNToRecFN.io.in.sExp, divSqrtRecFNToRaw.io.rawOut.sExp connect roundRawFNToRecFN.io.in.sign, divSqrtRecFNToRaw.io.rawOut.sign connect roundRawFNToRecFN.io.in.isZero, divSqrtRecFNToRaw.io.rawOut.isZero connect roundRawFNToRecFN.io.in.isInf, divSqrtRecFNToRaw.io.rawOut.isInf connect roundRawFNToRecFN.io.in.isNaN, divSqrtRecFNToRaw.io.rawOut.isNaN connect roundRawFNToRecFN.io.roundingMode, divSqrtRecFNToRaw.io.roundingModeOut connect roundRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundRawFNToRecFN.io.out connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags
module DivSqrtRecFM_small_e5_s11_3( // @[DivSqrtRecFN_small.scala:468:5] input clock, // @[DivSqrtRecFN_small.scala:468:5] input reset, // @[DivSqrtRecFN_small.scala:468:5] output io_inReady, // @[DivSqrtRecFN_small.scala:472:16] input io_inValid, // @[DivSqrtRecFN_small.scala:472:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:472:16] input [16:0] io_a, // @[DivSqrtRecFN_small.scala:472:16] input [16:0] io_b, // @[DivSqrtRecFN_small.scala:472:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:472:16] output io_outValid_div, // @[DivSqrtRecFN_small.scala:472:16] output io_outValid_sqrt, // @[DivSqrtRecFN_small.scala:472:16] output [16:0] io_out, // @[DivSqrtRecFN_small.scala:472:16] output [4:0] io_exceptionFlags // @[DivSqrtRecFN_small.scala:472:16] ); wire [2:0] _divSqrtRecFNToRaw_io_roundingModeOut; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_invalidExc; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_infiniteExc; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isNaN; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isInf; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_isZero; // @[DivSqrtRecFN_small.scala:493:15] wire _divSqrtRecFNToRaw_io_rawOut_sign; // @[DivSqrtRecFN_small.scala:493:15] wire [6:0] _divSqrtRecFNToRaw_io_rawOut_sExp; // @[DivSqrtRecFN_small.scala:493:15] wire [13:0] _divSqrtRecFNToRaw_io_rawOut_sig; // @[DivSqrtRecFN_small.scala:493:15] wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:468:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:468:5] wire [16:0] io_a_0 = io_a; // @[DivSqrtRecFN_small.scala:468:5] wire [16:0] io_b_0 = io_b; // @[DivSqrtRecFN_small.scala:468:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:468:5] wire io_detectTininess = 1'h1; // @[DivSqrtRecFN_small.scala:468:5, :472:16, :508:15] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5] wire io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5] wire io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5] wire [16:0] io_out_0; // @[DivSqrtRecFN_small.scala:468:5] wire [4:0] io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5] DivSqrtRecFMToRaw_small_e5_s11_3 divSqrtRecFNToRaw ( // @[DivSqrtRecFN_small.scala:493:15] .clock (clock), .reset (reset), .io_inReady (io_inReady_0), .io_inValid (io_inValid_0), // @[DivSqrtRecFN_small.scala:468:5] .io_sqrtOp (io_sqrtOp_0), // @[DivSqrtRecFN_small.scala:468:5] .io_a (io_a_0), // @[DivSqrtRecFN_small.scala:468:5] .io_b (io_b_0), // @[DivSqrtRecFN_small.scala:468:5] .io_roundingMode (io_roundingMode_0), // @[DivSqrtRecFN_small.scala:468:5] .io_rawOutValid_div (io_outValid_div_0), .io_rawOutValid_sqrt (io_outValid_sqrt_0), .io_roundingModeOut (_divSqrtRecFNToRaw_io_roundingModeOut), .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), .io_rawOut_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), .io_rawOut_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), .io_rawOut_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), .io_rawOut_sign (_divSqrtRecFNToRaw_io_rawOut_sign), .io_rawOut_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), .io_rawOut_sig (_divSqrtRecFNToRaw_io_rawOut_sig) ); // @[DivSqrtRecFN_small.scala:493:15] RoundRawFNToRecFN_e5_s11_7 roundRawFNToRecFN ( // @[DivSqrtRecFN_small.scala:508:15] .io_invalidExc (_divSqrtRecFNToRaw_io_invalidExc), // @[DivSqrtRecFN_small.scala:493:15] .io_infiniteExc (_divSqrtRecFNToRaw_io_infiniteExc), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isNaN (_divSqrtRecFNToRaw_io_rawOut_isNaN), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isInf (_divSqrtRecFNToRaw_io_rawOut_isInf), // @[DivSqrtRecFN_small.scala:493:15] .io_in_isZero (_divSqrtRecFNToRaw_io_rawOut_isZero), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sign (_divSqrtRecFNToRaw_io_rawOut_sign), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sExp (_divSqrtRecFNToRaw_io_rawOut_sExp), // @[DivSqrtRecFN_small.scala:493:15] .io_in_sig (_divSqrtRecFNToRaw_io_rawOut_sig), // @[DivSqrtRecFN_small.scala:493:15] .io_roundingMode (_divSqrtRecFNToRaw_io_roundingModeOut), // @[DivSqrtRecFN_small.scala:493:15] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[DivSqrtRecFN_small.scala:508:15] assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_outValid_div = io_outValid_div_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_outValid_sqrt = io_outValid_sqrt_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_out = io_out_0; // @[DivSqrtRecFN_small.scala:468:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[DivSqrtRecFN_small.scala:468:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_254 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_254( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4u_1 : input clock : Clock input reset : Reset output auto : { flip in_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip in_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready wire nodeIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_1.d.bits.corrupt invalidate nodeIn_1.d.bits.data invalidate nodeIn_1.d.bits.denied invalidate nodeIn_1.d.bits.sink invalidate nodeIn_1.d.bits.source invalidate nodeIn_1.d.bits.size invalidate nodeIn_1.d.bits.param invalidate nodeIn_1.d.bits.opcode invalidate nodeIn_1.d.valid invalidate nodeIn_1.d.ready invalidate nodeIn_1.a.bits.corrupt invalidate nodeIn_1.a.bits.data invalidate nodeIn_1.a.bits.mask invalidate nodeIn_1.a.bits.address invalidate nodeIn_1.a.bits.source invalidate nodeIn_1.a.bits.size invalidate nodeIn_1.a.bits.param invalidate nodeIn_1.a.bits.opcode invalidate nodeIn_1.a.valid invalidate nodeIn_1.a.ready wire nodeIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_2.d.bits.corrupt invalidate nodeIn_2.d.bits.data invalidate nodeIn_2.d.bits.denied invalidate nodeIn_2.d.bits.sink invalidate nodeIn_2.d.bits.source invalidate nodeIn_2.d.bits.size invalidate nodeIn_2.d.bits.param invalidate nodeIn_2.d.bits.opcode invalidate nodeIn_2.d.valid invalidate nodeIn_2.d.ready invalidate nodeIn_2.a.bits.corrupt invalidate nodeIn_2.a.bits.data invalidate nodeIn_2.a.bits.mask invalidate nodeIn_2.a.bits.address invalidate nodeIn_2.a.bits.source invalidate nodeIn_2.a.bits.size invalidate nodeIn_2.a.bits.param invalidate nodeIn_2.a.bits.opcode invalidate nodeIn_2.a.valid invalidate nodeIn_2.a.ready wire nodeIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_3.d.bits.corrupt invalidate nodeIn_3.d.bits.data invalidate nodeIn_3.d.bits.denied invalidate nodeIn_3.d.bits.sink invalidate nodeIn_3.d.bits.source invalidate nodeIn_3.d.bits.size invalidate nodeIn_3.d.bits.param invalidate nodeIn_3.d.bits.opcode invalidate nodeIn_3.d.valid invalidate nodeIn_3.d.ready invalidate nodeIn_3.a.bits.corrupt invalidate nodeIn_3.a.bits.data invalidate nodeIn_3.a.bits.mask invalidate nodeIn_3.a.bits.address invalidate nodeIn_3.a.bits.source invalidate nodeIn_3.a.bits.size invalidate nodeIn_3.a.bits.param invalidate nodeIn_3.a.bits.opcode invalidate nodeIn_3.a.valid invalidate nodeIn_3.a.ready wire nodeIn_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_4.d.bits.corrupt invalidate nodeIn_4.d.bits.data invalidate nodeIn_4.d.bits.denied invalidate nodeIn_4.d.bits.sink invalidate nodeIn_4.d.bits.source invalidate nodeIn_4.d.bits.size invalidate nodeIn_4.d.bits.param invalidate nodeIn_4.d.bits.opcode invalidate nodeIn_4.d.valid invalidate nodeIn_4.d.ready invalidate nodeIn_4.a.bits.corrupt invalidate nodeIn_4.a.bits.data invalidate nodeIn_4.a.bits.mask invalidate nodeIn_4.a.bits.address invalidate nodeIn_4.a.bits.source invalidate nodeIn_4.a.bits.size invalidate nodeIn_4.a.bits.param invalidate nodeIn_4.a.bits.opcode invalidate nodeIn_4.a.valid invalidate nodeIn_4.a.ready wire nodeIn_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_5.d.bits.corrupt invalidate nodeIn_5.d.bits.data invalidate nodeIn_5.d.bits.denied invalidate nodeIn_5.d.bits.sink invalidate nodeIn_5.d.bits.source invalidate nodeIn_5.d.bits.size invalidate nodeIn_5.d.bits.param invalidate nodeIn_5.d.bits.opcode invalidate nodeIn_5.d.valid invalidate nodeIn_5.d.ready invalidate nodeIn_5.a.bits.corrupt invalidate nodeIn_5.a.bits.data invalidate nodeIn_5.a.bits.mask invalidate nodeIn_5.a.bits.address invalidate nodeIn_5.a.bits.source invalidate nodeIn_5.a.bits.size invalidate nodeIn_5.a.bits.param invalidate nodeIn_5.a.bits.opcode invalidate nodeIn_5.a.valid invalidate nodeIn_5.a.ready wire nodeIn_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_6.d.bits.corrupt invalidate nodeIn_6.d.bits.data invalidate nodeIn_6.d.bits.denied invalidate nodeIn_6.d.bits.sink invalidate nodeIn_6.d.bits.source invalidate nodeIn_6.d.bits.size invalidate nodeIn_6.d.bits.param invalidate nodeIn_6.d.bits.opcode invalidate nodeIn_6.d.valid invalidate nodeIn_6.d.ready invalidate nodeIn_6.a.bits.corrupt invalidate nodeIn_6.a.bits.data invalidate nodeIn_6.a.bits.mask invalidate nodeIn_6.a.bits.address invalidate nodeIn_6.a.bits.source invalidate nodeIn_6.a.bits.size invalidate nodeIn_6.a.bits.param invalidate nodeIn_6.a.bits.opcode invalidate nodeIn_6.a.valid invalidate nodeIn_6.a.ready wire nodeIn_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_7.d.bits.corrupt invalidate nodeIn_7.d.bits.data invalidate nodeIn_7.d.bits.denied invalidate nodeIn_7.d.bits.sink invalidate nodeIn_7.d.bits.source invalidate nodeIn_7.d.bits.size invalidate nodeIn_7.d.bits.param invalidate nodeIn_7.d.bits.opcode invalidate nodeIn_7.d.valid invalidate nodeIn_7.d.ready invalidate nodeIn_7.a.bits.corrupt invalidate nodeIn_7.a.bits.data invalidate nodeIn_7.a.bits.mask invalidate nodeIn_7.a.bits.address invalidate nodeIn_7.a.bits.source invalidate nodeIn_7.a.bits.size invalidate nodeIn_7.a.bits.param invalidate nodeIn_7.a.bits.opcode invalidate nodeIn_7.a.valid invalidate nodeIn_7.a.ready wire nodeIn_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_8.d.bits.corrupt invalidate nodeIn_8.d.bits.data invalidate nodeIn_8.d.bits.denied invalidate nodeIn_8.d.bits.sink invalidate nodeIn_8.d.bits.source invalidate nodeIn_8.d.bits.size invalidate nodeIn_8.d.bits.param invalidate nodeIn_8.d.bits.opcode invalidate nodeIn_8.d.valid invalidate nodeIn_8.d.ready invalidate nodeIn_8.a.bits.corrupt invalidate nodeIn_8.a.bits.data invalidate nodeIn_8.a.bits.mask invalidate nodeIn_8.a.bits.address invalidate nodeIn_8.a.bits.source invalidate nodeIn_8.a.bits.size invalidate nodeIn_8.a.bits.param invalidate nodeIn_8.a.bits.opcode invalidate nodeIn_8.a.valid invalidate nodeIn_8.a.ready wire nodeIn_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_9.d.bits.corrupt invalidate nodeIn_9.d.bits.data invalidate nodeIn_9.d.bits.denied invalidate nodeIn_9.d.bits.sink invalidate nodeIn_9.d.bits.source invalidate nodeIn_9.d.bits.size invalidate nodeIn_9.d.bits.param invalidate nodeIn_9.d.bits.opcode invalidate nodeIn_9.d.valid invalidate nodeIn_9.d.ready invalidate nodeIn_9.a.bits.corrupt invalidate nodeIn_9.a.bits.data invalidate nodeIn_9.a.bits.mask invalidate nodeIn_9.a.bits.address invalidate nodeIn_9.a.bits.source invalidate nodeIn_9.a.bits.size invalidate nodeIn_9.a.bits.param invalidate nodeIn_9.a.bits.opcode invalidate nodeIn_9.a.valid invalidate nodeIn_9.a.ready wire nodeIn_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_10.d.bits.corrupt invalidate nodeIn_10.d.bits.data invalidate nodeIn_10.d.bits.denied invalidate nodeIn_10.d.bits.sink invalidate nodeIn_10.d.bits.source invalidate nodeIn_10.d.bits.size invalidate nodeIn_10.d.bits.param invalidate nodeIn_10.d.bits.opcode invalidate nodeIn_10.d.valid invalidate nodeIn_10.d.ready invalidate nodeIn_10.a.bits.corrupt invalidate nodeIn_10.a.bits.data invalidate nodeIn_10.a.bits.mask invalidate nodeIn_10.a.bits.address invalidate nodeIn_10.a.bits.source invalidate nodeIn_10.a.bits.size invalidate nodeIn_10.a.bits.param invalidate nodeIn_10.a.bits.opcode invalidate nodeIn_10.a.valid invalidate nodeIn_10.a.ready wire nodeIn_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_11.d.bits.corrupt invalidate nodeIn_11.d.bits.data invalidate nodeIn_11.d.bits.denied invalidate nodeIn_11.d.bits.sink invalidate nodeIn_11.d.bits.source invalidate nodeIn_11.d.bits.size invalidate nodeIn_11.d.bits.param invalidate nodeIn_11.d.bits.opcode invalidate nodeIn_11.d.valid invalidate nodeIn_11.d.ready invalidate nodeIn_11.a.bits.corrupt invalidate nodeIn_11.a.bits.data invalidate nodeIn_11.a.bits.mask invalidate nodeIn_11.a.bits.address invalidate nodeIn_11.a.bits.source invalidate nodeIn_11.a.bits.size invalidate nodeIn_11.a.bits.param invalidate nodeIn_11.a.bits.opcode invalidate nodeIn_11.a.valid invalidate nodeIn_11.a.ready wire nodeIn_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_12.d.bits.corrupt invalidate nodeIn_12.d.bits.data invalidate nodeIn_12.d.bits.denied invalidate nodeIn_12.d.bits.sink invalidate nodeIn_12.d.bits.source invalidate nodeIn_12.d.bits.size invalidate nodeIn_12.d.bits.param invalidate nodeIn_12.d.bits.opcode invalidate nodeIn_12.d.valid invalidate nodeIn_12.d.ready invalidate nodeIn_12.a.bits.corrupt invalidate nodeIn_12.a.bits.data invalidate nodeIn_12.a.bits.mask invalidate nodeIn_12.a.bits.address invalidate nodeIn_12.a.bits.source invalidate nodeIn_12.a.bits.size invalidate nodeIn_12.a.bits.param invalidate nodeIn_12.a.bits.opcode invalidate nodeIn_12.a.valid invalidate nodeIn_12.a.ready wire nodeIn_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_13.d.bits.corrupt invalidate nodeIn_13.d.bits.data invalidate nodeIn_13.d.bits.denied invalidate nodeIn_13.d.bits.sink invalidate nodeIn_13.d.bits.source invalidate nodeIn_13.d.bits.size invalidate nodeIn_13.d.bits.param invalidate nodeIn_13.d.bits.opcode invalidate nodeIn_13.d.valid invalidate nodeIn_13.d.ready invalidate nodeIn_13.a.bits.corrupt invalidate nodeIn_13.a.bits.data invalidate nodeIn_13.a.bits.mask invalidate nodeIn_13.a.bits.address invalidate nodeIn_13.a.bits.source invalidate nodeIn_13.a.bits.size invalidate nodeIn_13.a.bits.param invalidate nodeIn_13.a.bits.opcode invalidate nodeIn_13.a.valid invalidate nodeIn_13.a.ready wire nodeIn_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_14.d.bits.corrupt invalidate nodeIn_14.d.bits.data invalidate nodeIn_14.d.bits.denied invalidate nodeIn_14.d.bits.sink invalidate nodeIn_14.d.bits.source invalidate nodeIn_14.d.bits.size invalidate nodeIn_14.d.bits.param invalidate nodeIn_14.d.bits.opcode invalidate nodeIn_14.d.valid invalidate nodeIn_14.d.ready invalidate nodeIn_14.a.bits.corrupt invalidate nodeIn_14.a.bits.data invalidate nodeIn_14.a.bits.mask invalidate nodeIn_14.a.bits.address invalidate nodeIn_14.a.bits.source invalidate nodeIn_14.a.bits.size invalidate nodeIn_14.a.bits.param invalidate nodeIn_14.a.bits.opcode invalidate nodeIn_14.a.valid invalidate nodeIn_14.a.ready wire nodeIn_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_15.d.bits.corrupt invalidate nodeIn_15.d.bits.data invalidate nodeIn_15.d.bits.denied invalidate nodeIn_15.d.bits.sink invalidate nodeIn_15.d.bits.source invalidate nodeIn_15.d.bits.size invalidate nodeIn_15.d.bits.param invalidate nodeIn_15.d.bits.opcode invalidate nodeIn_15.d.valid invalidate nodeIn_15.d.ready invalidate nodeIn_15.a.bits.corrupt invalidate nodeIn_15.a.bits.data invalidate nodeIn_15.a.bits.mask invalidate nodeIn_15.a.bits.address invalidate nodeIn_15.a.bits.source invalidate nodeIn_15.a.bits.size invalidate nodeIn_15.a.bits.param invalidate nodeIn_15.a.bits.opcode invalidate nodeIn_15.a.valid invalidate nodeIn_15.a.ready wire nodeIn_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_16.d.bits.corrupt invalidate nodeIn_16.d.bits.data invalidate nodeIn_16.d.bits.denied invalidate nodeIn_16.d.bits.sink invalidate nodeIn_16.d.bits.source invalidate nodeIn_16.d.bits.size invalidate nodeIn_16.d.bits.param invalidate nodeIn_16.d.bits.opcode invalidate nodeIn_16.d.valid invalidate nodeIn_16.d.ready invalidate nodeIn_16.a.bits.corrupt invalidate nodeIn_16.a.bits.data invalidate nodeIn_16.a.bits.mask invalidate nodeIn_16.a.bits.address invalidate nodeIn_16.a.bits.source invalidate nodeIn_16.a.bits.size invalidate nodeIn_16.a.bits.param invalidate nodeIn_16.a.bits.opcode invalidate nodeIn_16.a.valid invalidate nodeIn_16.a.ready wire nodeIn_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn_17.d.bits.corrupt invalidate nodeIn_17.d.bits.data invalidate nodeIn_17.d.bits.denied invalidate nodeIn_17.d.bits.sink invalidate nodeIn_17.d.bits.source invalidate nodeIn_17.d.bits.size invalidate nodeIn_17.d.bits.param invalidate nodeIn_17.d.bits.opcode invalidate nodeIn_17.d.valid invalidate nodeIn_17.d.ready invalidate nodeIn_17.a.bits.corrupt invalidate nodeIn_17.a.bits.data invalidate nodeIn_17.a.bits.mask invalidate nodeIn_17.a.bits.address invalidate nodeIn_17.a.bits.source invalidate nodeIn_17.a.bits.size invalidate nodeIn_17.a.bits.param invalidate nodeIn_17.a.bits.opcode invalidate nodeIn_17.a.valid invalidate nodeIn_17.a.ready wire nodeIn_18 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate nodeIn_18.e.bits.sink invalidate nodeIn_18.e.valid invalidate nodeIn_18.e.ready invalidate nodeIn_18.d.bits.corrupt invalidate nodeIn_18.d.bits.data invalidate nodeIn_18.d.bits.denied invalidate nodeIn_18.d.bits.sink invalidate nodeIn_18.d.bits.source invalidate nodeIn_18.d.bits.size invalidate nodeIn_18.d.bits.param invalidate nodeIn_18.d.bits.opcode invalidate nodeIn_18.d.valid invalidate nodeIn_18.d.ready invalidate nodeIn_18.c.bits.corrupt invalidate nodeIn_18.c.bits.data invalidate nodeIn_18.c.bits.address invalidate nodeIn_18.c.bits.source invalidate nodeIn_18.c.bits.size invalidate nodeIn_18.c.bits.param invalidate nodeIn_18.c.bits.opcode invalidate nodeIn_18.c.valid invalidate nodeIn_18.c.ready invalidate nodeIn_18.b.bits.corrupt invalidate nodeIn_18.b.bits.data invalidate nodeIn_18.b.bits.mask invalidate nodeIn_18.b.bits.address invalidate nodeIn_18.b.bits.source invalidate nodeIn_18.b.bits.size invalidate nodeIn_18.b.bits.param invalidate nodeIn_18.b.bits.opcode invalidate nodeIn_18.b.valid invalidate nodeIn_18.b.ready invalidate nodeIn_18.a.bits.corrupt invalidate nodeIn_18.a.bits.data invalidate nodeIn_18.a.bits.mask invalidate nodeIn_18.a.bits.address invalidate nodeIn_18.a.bits.source invalidate nodeIn_18.a.bits.size invalidate nodeIn_18.a.bits.param invalidate nodeIn_18.a.bits.opcode invalidate nodeIn_18.a.valid invalidate nodeIn_18.a.ready inst monitor of TLMonitor_76 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready inst monitor_1 of TLMonitor_77 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.d.bits.corrupt, nodeIn_1.d.bits.corrupt connect monitor_1.io.in.d.bits.data, nodeIn_1.d.bits.data connect monitor_1.io.in.d.bits.denied, nodeIn_1.d.bits.denied connect monitor_1.io.in.d.bits.sink, nodeIn_1.d.bits.sink connect monitor_1.io.in.d.bits.source, nodeIn_1.d.bits.source connect monitor_1.io.in.d.bits.size, nodeIn_1.d.bits.size connect monitor_1.io.in.d.bits.param, nodeIn_1.d.bits.param connect monitor_1.io.in.d.bits.opcode, nodeIn_1.d.bits.opcode connect monitor_1.io.in.d.valid, nodeIn_1.d.valid connect monitor_1.io.in.d.ready, nodeIn_1.d.ready connect monitor_1.io.in.a.bits.corrupt, nodeIn_1.a.bits.corrupt connect monitor_1.io.in.a.bits.data, nodeIn_1.a.bits.data connect monitor_1.io.in.a.bits.mask, nodeIn_1.a.bits.mask connect monitor_1.io.in.a.bits.address, nodeIn_1.a.bits.address connect monitor_1.io.in.a.bits.source, nodeIn_1.a.bits.source connect monitor_1.io.in.a.bits.size, nodeIn_1.a.bits.size connect monitor_1.io.in.a.bits.param, nodeIn_1.a.bits.param connect monitor_1.io.in.a.bits.opcode, nodeIn_1.a.bits.opcode connect monitor_1.io.in.a.valid, nodeIn_1.a.valid connect monitor_1.io.in.a.ready, nodeIn_1.a.ready inst monitor_2 of TLMonitor_78 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.d.bits.corrupt, nodeIn_2.d.bits.corrupt connect monitor_2.io.in.d.bits.data, nodeIn_2.d.bits.data connect monitor_2.io.in.d.bits.denied, nodeIn_2.d.bits.denied connect monitor_2.io.in.d.bits.sink, nodeIn_2.d.bits.sink connect monitor_2.io.in.d.bits.source, nodeIn_2.d.bits.source connect monitor_2.io.in.d.bits.size, nodeIn_2.d.bits.size connect monitor_2.io.in.d.bits.param, nodeIn_2.d.bits.param connect monitor_2.io.in.d.bits.opcode, nodeIn_2.d.bits.opcode connect monitor_2.io.in.d.valid, nodeIn_2.d.valid connect monitor_2.io.in.d.ready, nodeIn_2.d.ready connect monitor_2.io.in.a.bits.corrupt, nodeIn_2.a.bits.corrupt connect monitor_2.io.in.a.bits.data, nodeIn_2.a.bits.data connect monitor_2.io.in.a.bits.mask, nodeIn_2.a.bits.mask connect monitor_2.io.in.a.bits.address, nodeIn_2.a.bits.address connect monitor_2.io.in.a.bits.source, nodeIn_2.a.bits.source connect monitor_2.io.in.a.bits.size, nodeIn_2.a.bits.size connect monitor_2.io.in.a.bits.param, nodeIn_2.a.bits.param connect monitor_2.io.in.a.bits.opcode, nodeIn_2.a.bits.opcode connect monitor_2.io.in.a.valid, nodeIn_2.a.valid connect monitor_2.io.in.a.ready, nodeIn_2.a.ready inst monitor_3 of TLMonitor_79 connect monitor_3.clock, clock connect monitor_3.reset, reset connect monitor_3.io.in.d.bits.corrupt, nodeIn_3.d.bits.corrupt connect monitor_3.io.in.d.bits.data, nodeIn_3.d.bits.data connect monitor_3.io.in.d.bits.denied, nodeIn_3.d.bits.denied connect monitor_3.io.in.d.bits.sink, nodeIn_3.d.bits.sink connect monitor_3.io.in.d.bits.source, nodeIn_3.d.bits.source connect monitor_3.io.in.d.bits.size, nodeIn_3.d.bits.size connect monitor_3.io.in.d.bits.param, nodeIn_3.d.bits.param connect monitor_3.io.in.d.bits.opcode, nodeIn_3.d.bits.opcode connect monitor_3.io.in.d.valid, nodeIn_3.d.valid connect monitor_3.io.in.d.ready, nodeIn_3.d.ready connect monitor_3.io.in.a.bits.corrupt, nodeIn_3.a.bits.corrupt connect monitor_3.io.in.a.bits.data, nodeIn_3.a.bits.data connect monitor_3.io.in.a.bits.mask, nodeIn_3.a.bits.mask connect monitor_3.io.in.a.bits.address, nodeIn_3.a.bits.address connect monitor_3.io.in.a.bits.source, nodeIn_3.a.bits.source connect monitor_3.io.in.a.bits.size, nodeIn_3.a.bits.size connect monitor_3.io.in.a.bits.param, nodeIn_3.a.bits.param connect monitor_3.io.in.a.bits.opcode, nodeIn_3.a.bits.opcode connect monitor_3.io.in.a.valid, nodeIn_3.a.valid connect monitor_3.io.in.a.ready, nodeIn_3.a.ready inst monitor_4 of TLMonitor_80 connect monitor_4.clock, clock connect monitor_4.reset, reset connect monitor_4.io.in.d.bits.corrupt, nodeIn_4.d.bits.corrupt connect monitor_4.io.in.d.bits.data, nodeIn_4.d.bits.data connect monitor_4.io.in.d.bits.denied, nodeIn_4.d.bits.denied connect monitor_4.io.in.d.bits.sink, nodeIn_4.d.bits.sink connect monitor_4.io.in.d.bits.source, nodeIn_4.d.bits.source connect monitor_4.io.in.d.bits.size, nodeIn_4.d.bits.size connect monitor_4.io.in.d.bits.param, nodeIn_4.d.bits.param connect monitor_4.io.in.d.bits.opcode, nodeIn_4.d.bits.opcode connect monitor_4.io.in.d.valid, nodeIn_4.d.valid connect monitor_4.io.in.d.ready, nodeIn_4.d.ready connect monitor_4.io.in.a.bits.corrupt, nodeIn_4.a.bits.corrupt connect monitor_4.io.in.a.bits.data, nodeIn_4.a.bits.data connect monitor_4.io.in.a.bits.mask, nodeIn_4.a.bits.mask connect monitor_4.io.in.a.bits.address, nodeIn_4.a.bits.address connect monitor_4.io.in.a.bits.source, nodeIn_4.a.bits.source connect monitor_4.io.in.a.bits.size, nodeIn_4.a.bits.size connect monitor_4.io.in.a.bits.param, nodeIn_4.a.bits.param connect monitor_4.io.in.a.bits.opcode, nodeIn_4.a.bits.opcode connect monitor_4.io.in.a.valid, nodeIn_4.a.valid connect monitor_4.io.in.a.ready, nodeIn_4.a.ready inst monitor_5 of TLMonitor_81 connect monitor_5.clock, clock connect monitor_5.reset, reset connect monitor_5.io.in.d.bits.corrupt, nodeIn_5.d.bits.corrupt connect monitor_5.io.in.d.bits.data, nodeIn_5.d.bits.data connect monitor_5.io.in.d.bits.denied, nodeIn_5.d.bits.denied connect monitor_5.io.in.d.bits.sink, nodeIn_5.d.bits.sink connect monitor_5.io.in.d.bits.source, nodeIn_5.d.bits.source connect monitor_5.io.in.d.bits.size, nodeIn_5.d.bits.size connect monitor_5.io.in.d.bits.param, nodeIn_5.d.bits.param connect monitor_5.io.in.d.bits.opcode, nodeIn_5.d.bits.opcode connect monitor_5.io.in.d.valid, nodeIn_5.d.valid connect monitor_5.io.in.d.ready, nodeIn_5.d.ready connect monitor_5.io.in.a.bits.corrupt, nodeIn_5.a.bits.corrupt connect monitor_5.io.in.a.bits.data, nodeIn_5.a.bits.data connect monitor_5.io.in.a.bits.mask, nodeIn_5.a.bits.mask connect monitor_5.io.in.a.bits.address, nodeIn_5.a.bits.address connect monitor_5.io.in.a.bits.source, nodeIn_5.a.bits.source connect monitor_5.io.in.a.bits.size, nodeIn_5.a.bits.size connect monitor_5.io.in.a.bits.param, nodeIn_5.a.bits.param connect monitor_5.io.in.a.bits.opcode, nodeIn_5.a.bits.opcode connect monitor_5.io.in.a.valid, nodeIn_5.a.valid connect monitor_5.io.in.a.ready, nodeIn_5.a.ready inst monitor_6 of TLMonitor_82 connect monitor_6.clock, clock connect monitor_6.reset, reset connect monitor_6.io.in.d.bits.corrupt, nodeIn_6.d.bits.corrupt connect monitor_6.io.in.d.bits.data, nodeIn_6.d.bits.data connect monitor_6.io.in.d.bits.denied, nodeIn_6.d.bits.denied connect monitor_6.io.in.d.bits.sink, nodeIn_6.d.bits.sink connect monitor_6.io.in.d.bits.source, nodeIn_6.d.bits.source connect monitor_6.io.in.d.bits.size, nodeIn_6.d.bits.size connect monitor_6.io.in.d.bits.param, nodeIn_6.d.bits.param connect monitor_6.io.in.d.bits.opcode, nodeIn_6.d.bits.opcode connect monitor_6.io.in.d.valid, nodeIn_6.d.valid connect monitor_6.io.in.d.ready, nodeIn_6.d.ready connect monitor_6.io.in.a.bits.corrupt, nodeIn_6.a.bits.corrupt connect monitor_6.io.in.a.bits.data, nodeIn_6.a.bits.data connect monitor_6.io.in.a.bits.mask, nodeIn_6.a.bits.mask connect monitor_6.io.in.a.bits.address, nodeIn_6.a.bits.address connect monitor_6.io.in.a.bits.source, nodeIn_6.a.bits.source connect monitor_6.io.in.a.bits.size, nodeIn_6.a.bits.size connect monitor_6.io.in.a.bits.param, nodeIn_6.a.bits.param connect monitor_6.io.in.a.bits.opcode, nodeIn_6.a.bits.opcode connect monitor_6.io.in.a.valid, nodeIn_6.a.valid connect monitor_6.io.in.a.ready, nodeIn_6.a.ready inst monitor_7 of TLMonitor_83 connect monitor_7.clock, clock connect monitor_7.reset, reset connect monitor_7.io.in.d.bits.corrupt, nodeIn_7.d.bits.corrupt connect monitor_7.io.in.d.bits.data, nodeIn_7.d.bits.data connect monitor_7.io.in.d.bits.denied, nodeIn_7.d.bits.denied connect monitor_7.io.in.d.bits.sink, nodeIn_7.d.bits.sink connect monitor_7.io.in.d.bits.source, nodeIn_7.d.bits.source connect monitor_7.io.in.d.bits.size, nodeIn_7.d.bits.size connect monitor_7.io.in.d.bits.param, nodeIn_7.d.bits.param connect monitor_7.io.in.d.bits.opcode, nodeIn_7.d.bits.opcode connect monitor_7.io.in.d.valid, nodeIn_7.d.valid connect monitor_7.io.in.d.ready, nodeIn_7.d.ready connect monitor_7.io.in.a.bits.corrupt, nodeIn_7.a.bits.corrupt connect monitor_7.io.in.a.bits.data, nodeIn_7.a.bits.data connect monitor_7.io.in.a.bits.mask, nodeIn_7.a.bits.mask connect monitor_7.io.in.a.bits.address, nodeIn_7.a.bits.address connect monitor_7.io.in.a.bits.source, nodeIn_7.a.bits.source connect monitor_7.io.in.a.bits.size, nodeIn_7.a.bits.size connect monitor_7.io.in.a.bits.param, nodeIn_7.a.bits.param connect monitor_7.io.in.a.bits.opcode, nodeIn_7.a.bits.opcode connect monitor_7.io.in.a.valid, nodeIn_7.a.valid connect monitor_7.io.in.a.ready, nodeIn_7.a.ready inst monitor_8 of TLMonitor_84 connect monitor_8.clock, clock connect monitor_8.reset, reset connect monitor_8.io.in.d.bits.corrupt, nodeIn_8.d.bits.corrupt connect monitor_8.io.in.d.bits.data, nodeIn_8.d.bits.data connect monitor_8.io.in.d.bits.denied, nodeIn_8.d.bits.denied connect monitor_8.io.in.d.bits.sink, nodeIn_8.d.bits.sink connect monitor_8.io.in.d.bits.source, nodeIn_8.d.bits.source connect monitor_8.io.in.d.bits.size, nodeIn_8.d.bits.size connect monitor_8.io.in.d.bits.param, nodeIn_8.d.bits.param connect monitor_8.io.in.d.bits.opcode, nodeIn_8.d.bits.opcode connect monitor_8.io.in.d.valid, nodeIn_8.d.valid connect monitor_8.io.in.d.ready, nodeIn_8.d.ready connect monitor_8.io.in.a.bits.corrupt, nodeIn_8.a.bits.corrupt connect monitor_8.io.in.a.bits.data, nodeIn_8.a.bits.data connect monitor_8.io.in.a.bits.mask, nodeIn_8.a.bits.mask connect monitor_8.io.in.a.bits.address, nodeIn_8.a.bits.address connect monitor_8.io.in.a.bits.source, nodeIn_8.a.bits.source connect monitor_8.io.in.a.bits.size, nodeIn_8.a.bits.size connect monitor_8.io.in.a.bits.param, nodeIn_8.a.bits.param connect monitor_8.io.in.a.bits.opcode, nodeIn_8.a.bits.opcode connect monitor_8.io.in.a.valid, nodeIn_8.a.valid connect monitor_8.io.in.a.ready, nodeIn_8.a.ready inst monitor_9 of TLMonitor_85 connect monitor_9.clock, clock connect monitor_9.reset, reset connect monitor_9.io.in.d.bits.corrupt, nodeIn_9.d.bits.corrupt connect monitor_9.io.in.d.bits.data, nodeIn_9.d.bits.data connect monitor_9.io.in.d.bits.denied, nodeIn_9.d.bits.denied connect monitor_9.io.in.d.bits.sink, nodeIn_9.d.bits.sink connect monitor_9.io.in.d.bits.source, nodeIn_9.d.bits.source connect monitor_9.io.in.d.bits.size, nodeIn_9.d.bits.size connect monitor_9.io.in.d.bits.param, nodeIn_9.d.bits.param connect monitor_9.io.in.d.bits.opcode, nodeIn_9.d.bits.opcode connect monitor_9.io.in.d.valid, nodeIn_9.d.valid connect monitor_9.io.in.d.ready, nodeIn_9.d.ready connect monitor_9.io.in.a.bits.corrupt, nodeIn_9.a.bits.corrupt connect monitor_9.io.in.a.bits.data, nodeIn_9.a.bits.data connect monitor_9.io.in.a.bits.mask, nodeIn_9.a.bits.mask connect monitor_9.io.in.a.bits.address, nodeIn_9.a.bits.address connect monitor_9.io.in.a.bits.source, nodeIn_9.a.bits.source connect monitor_9.io.in.a.bits.size, nodeIn_9.a.bits.size connect monitor_9.io.in.a.bits.param, nodeIn_9.a.bits.param connect monitor_9.io.in.a.bits.opcode, nodeIn_9.a.bits.opcode connect monitor_9.io.in.a.valid, nodeIn_9.a.valid connect monitor_9.io.in.a.ready, nodeIn_9.a.ready inst monitor_10 of TLMonitor_86 connect monitor_10.clock, clock connect monitor_10.reset, reset connect monitor_10.io.in.d.bits.corrupt, nodeIn_10.d.bits.corrupt connect monitor_10.io.in.d.bits.data, nodeIn_10.d.bits.data connect monitor_10.io.in.d.bits.denied, nodeIn_10.d.bits.denied connect monitor_10.io.in.d.bits.sink, nodeIn_10.d.bits.sink connect monitor_10.io.in.d.bits.source, nodeIn_10.d.bits.source connect monitor_10.io.in.d.bits.size, nodeIn_10.d.bits.size connect monitor_10.io.in.d.bits.param, nodeIn_10.d.bits.param connect monitor_10.io.in.d.bits.opcode, nodeIn_10.d.bits.opcode connect monitor_10.io.in.d.valid, nodeIn_10.d.valid connect monitor_10.io.in.d.ready, nodeIn_10.d.ready connect monitor_10.io.in.a.bits.corrupt, nodeIn_10.a.bits.corrupt connect monitor_10.io.in.a.bits.data, nodeIn_10.a.bits.data connect monitor_10.io.in.a.bits.mask, nodeIn_10.a.bits.mask connect monitor_10.io.in.a.bits.address, nodeIn_10.a.bits.address connect monitor_10.io.in.a.bits.source, nodeIn_10.a.bits.source connect monitor_10.io.in.a.bits.size, nodeIn_10.a.bits.size connect monitor_10.io.in.a.bits.param, nodeIn_10.a.bits.param connect monitor_10.io.in.a.bits.opcode, nodeIn_10.a.bits.opcode connect monitor_10.io.in.a.valid, nodeIn_10.a.valid connect monitor_10.io.in.a.ready, nodeIn_10.a.ready inst monitor_11 of TLMonitor_87 connect monitor_11.clock, clock connect monitor_11.reset, reset connect monitor_11.io.in.d.bits.corrupt, nodeIn_11.d.bits.corrupt connect monitor_11.io.in.d.bits.data, nodeIn_11.d.bits.data connect monitor_11.io.in.d.bits.denied, nodeIn_11.d.bits.denied connect monitor_11.io.in.d.bits.sink, nodeIn_11.d.bits.sink connect monitor_11.io.in.d.bits.source, nodeIn_11.d.bits.source connect monitor_11.io.in.d.bits.size, nodeIn_11.d.bits.size connect monitor_11.io.in.d.bits.param, nodeIn_11.d.bits.param connect monitor_11.io.in.d.bits.opcode, nodeIn_11.d.bits.opcode connect monitor_11.io.in.d.valid, nodeIn_11.d.valid connect monitor_11.io.in.d.ready, nodeIn_11.d.ready connect monitor_11.io.in.a.bits.corrupt, nodeIn_11.a.bits.corrupt connect monitor_11.io.in.a.bits.data, nodeIn_11.a.bits.data connect monitor_11.io.in.a.bits.mask, nodeIn_11.a.bits.mask connect monitor_11.io.in.a.bits.address, nodeIn_11.a.bits.address connect monitor_11.io.in.a.bits.source, nodeIn_11.a.bits.source connect monitor_11.io.in.a.bits.size, nodeIn_11.a.bits.size connect monitor_11.io.in.a.bits.param, nodeIn_11.a.bits.param connect monitor_11.io.in.a.bits.opcode, nodeIn_11.a.bits.opcode connect monitor_11.io.in.a.valid, nodeIn_11.a.valid connect monitor_11.io.in.a.ready, nodeIn_11.a.ready inst monitor_12 of TLMonitor_88 connect monitor_12.clock, clock connect monitor_12.reset, reset connect monitor_12.io.in.d.bits.corrupt, nodeIn_12.d.bits.corrupt connect monitor_12.io.in.d.bits.data, nodeIn_12.d.bits.data connect monitor_12.io.in.d.bits.denied, nodeIn_12.d.bits.denied connect monitor_12.io.in.d.bits.sink, nodeIn_12.d.bits.sink connect monitor_12.io.in.d.bits.source, nodeIn_12.d.bits.source connect monitor_12.io.in.d.bits.size, nodeIn_12.d.bits.size connect monitor_12.io.in.d.bits.param, nodeIn_12.d.bits.param connect monitor_12.io.in.d.bits.opcode, nodeIn_12.d.bits.opcode connect monitor_12.io.in.d.valid, nodeIn_12.d.valid connect monitor_12.io.in.d.ready, nodeIn_12.d.ready connect monitor_12.io.in.a.bits.corrupt, nodeIn_12.a.bits.corrupt connect monitor_12.io.in.a.bits.data, nodeIn_12.a.bits.data connect monitor_12.io.in.a.bits.mask, nodeIn_12.a.bits.mask connect monitor_12.io.in.a.bits.address, nodeIn_12.a.bits.address connect monitor_12.io.in.a.bits.source, nodeIn_12.a.bits.source connect monitor_12.io.in.a.bits.size, nodeIn_12.a.bits.size connect monitor_12.io.in.a.bits.param, nodeIn_12.a.bits.param connect monitor_12.io.in.a.bits.opcode, nodeIn_12.a.bits.opcode connect monitor_12.io.in.a.valid, nodeIn_12.a.valid connect monitor_12.io.in.a.ready, nodeIn_12.a.ready inst monitor_13 of TLMonitor_89 connect monitor_13.clock, clock connect monitor_13.reset, reset connect monitor_13.io.in.d.bits.corrupt, nodeIn_13.d.bits.corrupt connect monitor_13.io.in.d.bits.data, nodeIn_13.d.bits.data connect monitor_13.io.in.d.bits.denied, nodeIn_13.d.bits.denied connect monitor_13.io.in.d.bits.sink, nodeIn_13.d.bits.sink connect monitor_13.io.in.d.bits.source, nodeIn_13.d.bits.source connect monitor_13.io.in.d.bits.size, nodeIn_13.d.bits.size connect monitor_13.io.in.d.bits.param, nodeIn_13.d.bits.param connect monitor_13.io.in.d.bits.opcode, nodeIn_13.d.bits.opcode connect monitor_13.io.in.d.valid, nodeIn_13.d.valid connect monitor_13.io.in.d.ready, nodeIn_13.d.ready connect monitor_13.io.in.a.bits.corrupt, nodeIn_13.a.bits.corrupt connect monitor_13.io.in.a.bits.data, nodeIn_13.a.bits.data connect monitor_13.io.in.a.bits.mask, nodeIn_13.a.bits.mask connect monitor_13.io.in.a.bits.address, nodeIn_13.a.bits.address connect monitor_13.io.in.a.bits.source, nodeIn_13.a.bits.source connect monitor_13.io.in.a.bits.size, nodeIn_13.a.bits.size connect monitor_13.io.in.a.bits.param, nodeIn_13.a.bits.param connect monitor_13.io.in.a.bits.opcode, nodeIn_13.a.bits.opcode connect monitor_13.io.in.a.valid, nodeIn_13.a.valid connect monitor_13.io.in.a.ready, nodeIn_13.a.ready inst monitor_14 of TLMonitor_90 connect monitor_14.clock, clock connect monitor_14.reset, reset connect monitor_14.io.in.d.bits.corrupt, nodeIn_14.d.bits.corrupt connect monitor_14.io.in.d.bits.data, nodeIn_14.d.bits.data connect monitor_14.io.in.d.bits.denied, nodeIn_14.d.bits.denied connect monitor_14.io.in.d.bits.sink, nodeIn_14.d.bits.sink connect monitor_14.io.in.d.bits.source, nodeIn_14.d.bits.source connect monitor_14.io.in.d.bits.size, nodeIn_14.d.bits.size connect monitor_14.io.in.d.bits.param, nodeIn_14.d.bits.param connect monitor_14.io.in.d.bits.opcode, nodeIn_14.d.bits.opcode connect monitor_14.io.in.d.valid, nodeIn_14.d.valid connect monitor_14.io.in.d.ready, nodeIn_14.d.ready connect monitor_14.io.in.a.bits.corrupt, nodeIn_14.a.bits.corrupt connect monitor_14.io.in.a.bits.data, nodeIn_14.a.bits.data connect monitor_14.io.in.a.bits.mask, nodeIn_14.a.bits.mask connect monitor_14.io.in.a.bits.address, nodeIn_14.a.bits.address connect monitor_14.io.in.a.bits.source, nodeIn_14.a.bits.source connect monitor_14.io.in.a.bits.size, nodeIn_14.a.bits.size connect monitor_14.io.in.a.bits.param, nodeIn_14.a.bits.param connect monitor_14.io.in.a.bits.opcode, nodeIn_14.a.bits.opcode connect monitor_14.io.in.a.valid, nodeIn_14.a.valid connect monitor_14.io.in.a.ready, nodeIn_14.a.ready inst monitor_15 of TLMonitor_91 connect monitor_15.clock, clock connect monitor_15.reset, reset connect monitor_15.io.in.d.bits.corrupt, nodeIn_15.d.bits.corrupt connect monitor_15.io.in.d.bits.data, nodeIn_15.d.bits.data connect monitor_15.io.in.d.bits.denied, nodeIn_15.d.bits.denied connect monitor_15.io.in.d.bits.sink, nodeIn_15.d.bits.sink connect monitor_15.io.in.d.bits.source, nodeIn_15.d.bits.source connect monitor_15.io.in.d.bits.size, nodeIn_15.d.bits.size connect monitor_15.io.in.d.bits.param, nodeIn_15.d.bits.param connect monitor_15.io.in.d.bits.opcode, nodeIn_15.d.bits.opcode connect monitor_15.io.in.d.valid, nodeIn_15.d.valid connect monitor_15.io.in.d.ready, nodeIn_15.d.ready connect monitor_15.io.in.a.bits.corrupt, nodeIn_15.a.bits.corrupt connect monitor_15.io.in.a.bits.data, nodeIn_15.a.bits.data connect monitor_15.io.in.a.bits.mask, nodeIn_15.a.bits.mask connect monitor_15.io.in.a.bits.address, nodeIn_15.a.bits.address connect monitor_15.io.in.a.bits.source, nodeIn_15.a.bits.source connect monitor_15.io.in.a.bits.size, nodeIn_15.a.bits.size connect monitor_15.io.in.a.bits.param, nodeIn_15.a.bits.param connect monitor_15.io.in.a.bits.opcode, nodeIn_15.a.bits.opcode connect monitor_15.io.in.a.valid, nodeIn_15.a.valid connect monitor_15.io.in.a.ready, nodeIn_15.a.ready inst monitor_16 of TLMonitor_92 connect monitor_16.clock, clock connect monitor_16.reset, reset connect monitor_16.io.in.d.bits.corrupt, nodeIn_16.d.bits.corrupt connect monitor_16.io.in.d.bits.data, nodeIn_16.d.bits.data connect monitor_16.io.in.d.bits.denied, nodeIn_16.d.bits.denied connect monitor_16.io.in.d.bits.sink, nodeIn_16.d.bits.sink connect monitor_16.io.in.d.bits.source, nodeIn_16.d.bits.source connect monitor_16.io.in.d.bits.size, nodeIn_16.d.bits.size connect monitor_16.io.in.d.bits.param, nodeIn_16.d.bits.param connect monitor_16.io.in.d.bits.opcode, nodeIn_16.d.bits.opcode connect monitor_16.io.in.d.valid, nodeIn_16.d.valid connect monitor_16.io.in.d.ready, nodeIn_16.d.ready connect monitor_16.io.in.a.bits.corrupt, nodeIn_16.a.bits.corrupt connect monitor_16.io.in.a.bits.data, nodeIn_16.a.bits.data connect monitor_16.io.in.a.bits.mask, nodeIn_16.a.bits.mask connect monitor_16.io.in.a.bits.address, nodeIn_16.a.bits.address connect monitor_16.io.in.a.bits.source, nodeIn_16.a.bits.source connect monitor_16.io.in.a.bits.size, nodeIn_16.a.bits.size connect monitor_16.io.in.a.bits.param, nodeIn_16.a.bits.param connect monitor_16.io.in.a.bits.opcode, nodeIn_16.a.bits.opcode connect monitor_16.io.in.a.valid, nodeIn_16.a.valid connect monitor_16.io.in.a.ready, nodeIn_16.a.ready inst monitor_17 of TLMonitor_93 connect monitor_17.clock, clock connect monitor_17.reset, reset connect monitor_17.io.in.d.bits.corrupt, nodeIn_17.d.bits.corrupt connect monitor_17.io.in.d.bits.data, nodeIn_17.d.bits.data connect monitor_17.io.in.d.bits.denied, nodeIn_17.d.bits.denied connect monitor_17.io.in.d.bits.sink, nodeIn_17.d.bits.sink connect monitor_17.io.in.d.bits.source, nodeIn_17.d.bits.source connect monitor_17.io.in.d.bits.size, nodeIn_17.d.bits.size connect monitor_17.io.in.d.bits.param, nodeIn_17.d.bits.param connect monitor_17.io.in.d.bits.opcode, nodeIn_17.d.bits.opcode connect monitor_17.io.in.d.valid, nodeIn_17.d.valid connect monitor_17.io.in.d.ready, nodeIn_17.d.ready connect monitor_17.io.in.a.bits.corrupt, nodeIn_17.a.bits.corrupt connect monitor_17.io.in.a.bits.data, nodeIn_17.a.bits.data connect monitor_17.io.in.a.bits.mask, nodeIn_17.a.bits.mask connect monitor_17.io.in.a.bits.address, nodeIn_17.a.bits.address connect monitor_17.io.in.a.bits.source, nodeIn_17.a.bits.source connect monitor_17.io.in.a.bits.size, nodeIn_17.a.bits.size connect monitor_17.io.in.a.bits.param, nodeIn_17.a.bits.param connect monitor_17.io.in.a.bits.opcode, nodeIn_17.a.bits.opcode connect monitor_17.io.in.a.valid, nodeIn_17.a.valid connect monitor_17.io.in.a.ready, nodeIn_17.a.ready inst monitor_18 of TLMonitor_94 connect monitor_18.clock, clock connect monitor_18.reset, reset connect monitor_18.io.in.e.bits.sink, nodeIn_18.e.bits.sink connect monitor_18.io.in.e.valid, nodeIn_18.e.valid connect monitor_18.io.in.e.ready, nodeIn_18.e.ready connect monitor_18.io.in.d.bits.corrupt, nodeIn_18.d.bits.corrupt connect monitor_18.io.in.d.bits.data, nodeIn_18.d.bits.data connect monitor_18.io.in.d.bits.denied, nodeIn_18.d.bits.denied connect monitor_18.io.in.d.bits.sink, nodeIn_18.d.bits.sink connect monitor_18.io.in.d.bits.source, nodeIn_18.d.bits.source connect monitor_18.io.in.d.bits.size, nodeIn_18.d.bits.size connect monitor_18.io.in.d.bits.param, nodeIn_18.d.bits.param connect monitor_18.io.in.d.bits.opcode, nodeIn_18.d.bits.opcode connect monitor_18.io.in.d.valid, nodeIn_18.d.valid connect monitor_18.io.in.d.ready, nodeIn_18.d.ready connect monitor_18.io.in.c.bits.corrupt, nodeIn_18.c.bits.corrupt connect monitor_18.io.in.c.bits.data, nodeIn_18.c.bits.data connect monitor_18.io.in.c.bits.address, nodeIn_18.c.bits.address connect monitor_18.io.in.c.bits.source, nodeIn_18.c.bits.source connect monitor_18.io.in.c.bits.size, nodeIn_18.c.bits.size connect monitor_18.io.in.c.bits.param, nodeIn_18.c.bits.param connect monitor_18.io.in.c.bits.opcode, nodeIn_18.c.bits.opcode connect monitor_18.io.in.c.valid, nodeIn_18.c.valid connect monitor_18.io.in.c.ready, nodeIn_18.c.ready connect monitor_18.io.in.b.bits.corrupt, nodeIn_18.b.bits.corrupt connect monitor_18.io.in.b.bits.data, nodeIn_18.b.bits.data connect monitor_18.io.in.b.bits.mask, nodeIn_18.b.bits.mask connect monitor_18.io.in.b.bits.address, nodeIn_18.b.bits.address connect monitor_18.io.in.b.bits.source, nodeIn_18.b.bits.source connect monitor_18.io.in.b.bits.size, nodeIn_18.b.bits.size connect monitor_18.io.in.b.bits.param, nodeIn_18.b.bits.param connect monitor_18.io.in.b.bits.opcode, nodeIn_18.b.bits.opcode connect monitor_18.io.in.b.valid, nodeIn_18.b.valid connect monitor_18.io.in.b.ready, nodeIn_18.b.ready connect monitor_18.io.in.a.bits.corrupt, nodeIn_18.a.bits.corrupt connect monitor_18.io.in.a.bits.data, nodeIn_18.a.bits.data connect monitor_18.io.in.a.bits.mask, nodeIn_18.a.bits.mask connect monitor_18.io.in.a.bits.address, nodeIn_18.a.bits.address connect monitor_18.io.in.a.bits.source, nodeIn_18.a.bits.source connect monitor_18.io.in.a.bits.size, nodeIn_18.a.bits.size connect monitor_18.io.in.a.bits.param, nodeIn_18.a.bits.param connect monitor_18.io.in.a.bits.opcode, nodeIn_18.a.bits.opcode connect monitor_18.io.in.a.valid, nodeIn_18.a.valid connect monitor_18.io.in.a.ready, nodeIn_18.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready wire x1_nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut.d.bits.corrupt invalidate x1_nodeOut.d.bits.data invalidate x1_nodeOut.d.bits.denied invalidate x1_nodeOut.d.bits.sink invalidate x1_nodeOut.d.bits.source invalidate x1_nodeOut.d.bits.size invalidate x1_nodeOut.d.bits.param invalidate x1_nodeOut.d.bits.opcode invalidate x1_nodeOut.d.valid invalidate x1_nodeOut.d.ready invalidate x1_nodeOut.a.bits.corrupt invalidate x1_nodeOut.a.bits.data invalidate x1_nodeOut.a.bits.mask invalidate x1_nodeOut.a.bits.address invalidate x1_nodeOut.a.bits.source invalidate x1_nodeOut.a.bits.size invalidate x1_nodeOut.a.bits.param invalidate x1_nodeOut.a.bits.opcode invalidate x1_nodeOut.a.valid invalidate x1_nodeOut.a.ready wire x1_nodeOut_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_1.d.bits.corrupt invalidate x1_nodeOut_1.d.bits.data invalidate x1_nodeOut_1.d.bits.denied invalidate x1_nodeOut_1.d.bits.sink invalidate x1_nodeOut_1.d.bits.source invalidate x1_nodeOut_1.d.bits.size invalidate x1_nodeOut_1.d.bits.param invalidate x1_nodeOut_1.d.bits.opcode invalidate x1_nodeOut_1.d.valid invalidate x1_nodeOut_1.d.ready invalidate x1_nodeOut_1.a.bits.corrupt invalidate x1_nodeOut_1.a.bits.data invalidate x1_nodeOut_1.a.bits.mask invalidate x1_nodeOut_1.a.bits.address invalidate x1_nodeOut_1.a.bits.source invalidate x1_nodeOut_1.a.bits.size invalidate x1_nodeOut_1.a.bits.param invalidate x1_nodeOut_1.a.bits.opcode invalidate x1_nodeOut_1.a.valid invalidate x1_nodeOut_1.a.ready wire x1_nodeOut_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_2.d.bits.corrupt invalidate x1_nodeOut_2.d.bits.data invalidate x1_nodeOut_2.d.bits.denied invalidate x1_nodeOut_2.d.bits.sink invalidate x1_nodeOut_2.d.bits.source invalidate x1_nodeOut_2.d.bits.size invalidate x1_nodeOut_2.d.bits.param invalidate x1_nodeOut_2.d.bits.opcode invalidate x1_nodeOut_2.d.valid invalidate x1_nodeOut_2.d.ready invalidate x1_nodeOut_2.a.bits.corrupt invalidate x1_nodeOut_2.a.bits.data invalidate x1_nodeOut_2.a.bits.mask invalidate x1_nodeOut_2.a.bits.address invalidate x1_nodeOut_2.a.bits.source invalidate x1_nodeOut_2.a.bits.size invalidate x1_nodeOut_2.a.bits.param invalidate x1_nodeOut_2.a.bits.opcode invalidate x1_nodeOut_2.a.valid invalidate x1_nodeOut_2.a.ready wire x1_nodeOut_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_3.d.bits.corrupt invalidate x1_nodeOut_3.d.bits.data invalidate x1_nodeOut_3.d.bits.denied invalidate x1_nodeOut_3.d.bits.sink invalidate x1_nodeOut_3.d.bits.source invalidate x1_nodeOut_3.d.bits.size invalidate x1_nodeOut_3.d.bits.param invalidate x1_nodeOut_3.d.bits.opcode invalidate x1_nodeOut_3.d.valid invalidate x1_nodeOut_3.d.ready invalidate x1_nodeOut_3.a.bits.corrupt invalidate x1_nodeOut_3.a.bits.data invalidate x1_nodeOut_3.a.bits.mask invalidate x1_nodeOut_3.a.bits.address invalidate x1_nodeOut_3.a.bits.source invalidate x1_nodeOut_3.a.bits.size invalidate x1_nodeOut_3.a.bits.param invalidate x1_nodeOut_3.a.bits.opcode invalidate x1_nodeOut_3.a.valid invalidate x1_nodeOut_3.a.ready wire x1_nodeOut_4 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_4.d.bits.corrupt invalidate x1_nodeOut_4.d.bits.data invalidate x1_nodeOut_4.d.bits.denied invalidate x1_nodeOut_4.d.bits.sink invalidate x1_nodeOut_4.d.bits.source invalidate x1_nodeOut_4.d.bits.size invalidate x1_nodeOut_4.d.bits.param invalidate x1_nodeOut_4.d.bits.opcode invalidate x1_nodeOut_4.d.valid invalidate x1_nodeOut_4.d.ready invalidate x1_nodeOut_4.a.bits.corrupt invalidate x1_nodeOut_4.a.bits.data invalidate x1_nodeOut_4.a.bits.mask invalidate x1_nodeOut_4.a.bits.address invalidate x1_nodeOut_4.a.bits.source invalidate x1_nodeOut_4.a.bits.size invalidate x1_nodeOut_4.a.bits.param invalidate x1_nodeOut_4.a.bits.opcode invalidate x1_nodeOut_4.a.valid invalidate x1_nodeOut_4.a.ready wire x1_nodeOut_5 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_5.d.bits.corrupt invalidate x1_nodeOut_5.d.bits.data invalidate x1_nodeOut_5.d.bits.denied invalidate x1_nodeOut_5.d.bits.sink invalidate x1_nodeOut_5.d.bits.source invalidate x1_nodeOut_5.d.bits.size invalidate x1_nodeOut_5.d.bits.param invalidate x1_nodeOut_5.d.bits.opcode invalidate x1_nodeOut_5.d.valid invalidate x1_nodeOut_5.d.ready invalidate x1_nodeOut_5.a.bits.corrupt invalidate x1_nodeOut_5.a.bits.data invalidate x1_nodeOut_5.a.bits.mask invalidate x1_nodeOut_5.a.bits.address invalidate x1_nodeOut_5.a.bits.source invalidate x1_nodeOut_5.a.bits.size invalidate x1_nodeOut_5.a.bits.param invalidate x1_nodeOut_5.a.bits.opcode invalidate x1_nodeOut_5.a.valid invalidate x1_nodeOut_5.a.ready wire x1_nodeOut_6 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_6.d.bits.corrupt invalidate x1_nodeOut_6.d.bits.data invalidate x1_nodeOut_6.d.bits.denied invalidate x1_nodeOut_6.d.bits.sink invalidate x1_nodeOut_6.d.bits.source invalidate x1_nodeOut_6.d.bits.size invalidate x1_nodeOut_6.d.bits.param invalidate x1_nodeOut_6.d.bits.opcode invalidate x1_nodeOut_6.d.valid invalidate x1_nodeOut_6.d.ready invalidate x1_nodeOut_6.a.bits.corrupt invalidate x1_nodeOut_6.a.bits.data invalidate x1_nodeOut_6.a.bits.mask invalidate x1_nodeOut_6.a.bits.address invalidate x1_nodeOut_6.a.bits.source invalidate x1_nodeOut_6.a.bits.size invalidate x1_nodeOut_6.a.bits.param invalidate x1_nodeOut_6.a.bits.opcode invalidate x1_nodeOut_6.a.valid invalidate x1_nodeOut_6.a.ready wire x1_nodeOut_7 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_7.d.bits.corrupt invalidate x1_nodeOut_7.d.bits.data invalidate x1_nodeOut_7.d.bits.denied invalidate x1_nodeOut_7.d.bits.sink invalidate x1_nodeOut_7.d.bits.source invalidate x1_nodeOut_7.d.bits.size invalidate x1_nodeOut_7.d.bits.param invalidate x1_nodeOut_7.d.bits.opcode invalidate x1_nodeOut_7.d.valid invalidate x1_nodeOut_7.d.ready invalidate x1_nodeOut_7.a.bits.corrupt invalidate x1_nodeOut_7.a.bits.data invalidate x1_nodeOut_7.a.bits.mask invalidate x1_nodeOut_7.a.bits.address invalidate x1_nodeOut_7.a.bits.source invalidate x1_nodeOut_7.a.bits.size invalidate x1_nodeOut_7.a.bits.param invalidate x1_nodeOut_7.a.bits.opcode invalidate x1_nodeOut_7.a.valid invalidate x1_nodeOut_7.a.ready wire x1_nodeOut_8 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_8.d.bits.corrupt invalidate x1_nodeOut_8.d.bits.data invalidate x1_nodeOut_8.d.bits.denied invalidate x1_nodeOut_8.d.bits.sink invalidate x1_nodeOut_8.d.bits.source invalidate x1_nodeOut_8.d.bits.size invalidate x1_nodeOut_8.d.bits.param invalidate x1_nodeOut_8.d.bits.opcode invalidate x1_nodeOut_8.d.valid invalidate x1_nodeOut_8.d.ready invalidate x1_nodeOut_8.a.bits.corrupt invalidate x1_nodeOut_8.a.bits.data invalidate x1_nodeOut_8.a.bits.mask invalidate x1_nodeOut_8.a.bits.address invalidate x1_nodeOut_8.a.bits.source invalidate x1_nodeOut_8.a.bits.size invalidate x1_nodeOut_8.a.bits.param invalidate x1_nodeOut_8.a.bits.opcode invalidate x1_nodeOut_8.a.valid invalidate x1_nodeOut_8.a.ready wire x1_nodeOut_9 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_9.d.bits.corrupt invalidate x1_nodeOut_9.d.bits.data invalidate x1_nodeOut_9.d.bits.denied invalidate x1_nodeOut_9.d.bits.sink invalidate x1_nodeOut_9.d.bits.source invalidate x1_nodeOut_9.d.bits.size invalidate x1_nodeOut_9.d.bits.param invalidate x1_nodeOut_9.d.bits.opcode invalidate x1_nodeOut_9.d.valid invalidate x1_nodeOut_9.d.ready invalidate x1_nodeOut_9.a.bits.corrupt invalidate x1_nodeOut_9.a.bits.data invalidate x1_nodeOut_9.a.bits.mask invalidate x1_nodeOut_9.a.bits.address invalidate x1_nodeOut_9.a.bits.source invalidate x1_nodeOut_9.a.bits.size invalidate x1_nodeOut_9.a.bits.param invalidate x1_nodeOut_9.a.bits.opcode invalidate x1_nodeOut_9.a.valid invalidate x1_nodeOut_9.a.ready wire x1_nodeOut_10 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_10.d.bits.corrupt invalidate x1_nodeOut_10.d.bits.data invalidate x1_nodeOut_10.d.bits.denied invalidate x1_nodeOut_10.d.bits.sink invalidate x1_nodeOut_10.d.bits.source invalidate x1_nodeOut_10.d.bits.size invalidate x1_nodeOut_10.d.bits.param invalidate x1_nodeOut_10.d.bits.opcode invalidate x1_nodeOut_10.d.valid invalidate x1_nodeOut_10.d.ready invalidate x1_nodeOut_10.a.bits.corrupt invalidate x1_nodeOut_10.a.bits.data invalidate x1_nodeOut_10.a.bits.mask invalidate x1_nodeOut_10.a.bits.address invalidate x1_nodeOut_10.a.bits.source invalidate x1_nodeOut_10.a.bits.size invalidate x1_nodeOut_10.a.bits.param invalidate x1_nodeOut_10.a.bits.opcode invalidate x1_nodeOut_10.a.valid invalidate x1_nodeOut_10.a.ready wire x1_nodeOut_11 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_11.d.bits.corrupt invalidate x1_nodeOut_11.d.bits.data invalidate x1_nodeOut_11.d.bits.denied invalidate x1_nodeOut_11.d.bits.sink invalidate x1_nodeOut_11.d.bits.source invalidate x1_nodeOut_11.d.bits.size invalidate x1_nodeOut_11.d.bits.param invalidate x1_nodeOut_11.d.bits.opcode invalidate x1_nodeOut_11.d.valid invalidate x1_nodeOut_11.d.ready invalidate x1_nodeOut_11.a.bits.corrupt invalidate x1_nodeOut_11.a.bits.data invalidate x1_nodeOut_11.a.bits.mask invalidate x1_nodeOut_11.a.bits.address invalidate x1_nodeOut_11.a.bits.source invalidate x1_nodeOut_11.a.bits.size invalidate x1_nodeOut_11.a.bits.param invalidate x1_nodeOut_11.a.bits.opcode invalidate x1_nodeOut_11.a.valid invalidate x1_nodeOut_11.a.ready wire x1_nodeOut_12 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_12.d.bits.corrupt invalidate x1_nodeOut_12.d.bits.data invalidate x1_nodeOut_12.d.bits.denied invalidate x1_nodeOut_12.d.bits.sink invalidate x1_nodeOut_12.d.bits.source invalidate x1_nodeOut_12.d.bits.size invalidate x1_nodeOut_12.d.bits.param invalidate x1_nodeOut_12.d.bits.opcode invalidate x1_nodeOut_12.d.valid invalidate x1_nodeOut_12.d.ready invalidate x1_nodeOut_12.a.bits.corrupt invalidate x1_nodeOut_12.a.bits.data invalidate x1_nodeOut_12.a.bits.mask invalidate x1_nodeOut_12.a.bits.address invalidate x1_nodeOut_12.a.bits.source invalidate x1_nodeOut_12.a.bits.size invalidate x1_nodeOut_12.a.bits.param invalidate x1_nodeOut_12.a.bits.opcode invalidate x1_nodeOut_12.a.valid invalidate x1_nodeOut_12.a.ready wire x1_nodeOut_13 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_13.d.bits.corrupt invalidate x1_nodeOut_13.d.bits.data invalidate x1_nodeOut_13.d.bits.denied invalidate x1_nodeOut_13.d.bits.sink invalidate x1_nodeOut_13.d.bits.source invalidate x1_nodeOut_13.d.bits.size invalidate x1_nodeOut_13.d.bits.param invalidate x1_nodeOut_13.d.bits.opcode invalidate x1_nodeOut_13.d.valid invalidate x1_nodeOut_13.d.ready invalidate x1_nodeOut_13.a.bits.corrupt invalidate x1_nodeOut_13.a.bits.data invalidate x1_nodeOut_13.a.bits.mask invalidate x1_nodeOut_13.a.bits.address invalidate x1_nodeOut_13.a.bits.source invalidate x1_nodeOut_13.a.bits.size invalidate x1_nodeOut_13.a.bits.param invalidate x1_nodeOut_13.a.bits.opcode invalidate x1_nodeOut_13.a.valid invalidate x1_nodeOut_13.a.ready wire x1_nodeOut_14 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_14.d.bits.corrupt invalidate x1_nodeOut_14.d.bits.data invalidate x1_nodeOut_14.d.bits.denied invalidate x1_nodeOut_14.d.bits.sink invalidate x1_nodeOut_14.d.bits.source invalidate x1_nodeOut_14.d.bits.size invalidate x1_nodeOut_14.d.bits.param invalidate x1_nodeOut_14.d.bits.opcode invalidate x1_nodeOut_14.d.valid invalidate x1_nodeOut_14.d.ready invalidate x1_nodeOut_14.a.bits.corrupt invalidate x1_nodeOut_14.a.bits.data invalidate x1_nodeOut_14.a.bits.mask invalidate x1_nodeOut_14.a.bits.address invalidate x1_nodeOut_14.a.bits.source invalidate x1_nodeOut_14.a.bits.size invalidate x1_nodeOut_14.a.bits.param invalidate x1_nodeOut_14.a.bits.opcode invalidate x1_nodeOut_14.a.valid invalidate x1_nodeOut_14.a.ready wire x1_nodeOut_15 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_15.d.bits.corrupt invalidate x1_nodeOut_15.d.bits.data invalidate x1_nodeOut_15.d.bits.denied invalidate x1_nodeOut_15.d.bits.sink invalidate x1_nodeOut_15.d.bits.source invalidate x1_nodeOut_15.d.bits.size invalidate x1_nodeOut_15.d.bits.param invalidate x1_nodeOut_15.d.bits.opcode invalidate x1_nodeOut_15.d.valid invalidate x1_nodeOut_15.d.ready invalidate x1_nodeOut_15.a.bits.corrupt invalidate x1_nodeOut_15.a.bits.data invalidate x1_nodeOut_15.a.bits.mask invalidate x1_nodeOut_15.a.bits.address invalidate x1_nodeOut_15.a.bits.source invalidate x1_nodeOut_15.a.bits.size invalidate x1_nodeOut_15.a.bits.param invalidate x1_nodeOut_15.a.bits.opcode invalidate x1_nodeOut_15.a.valid invalidate x1_nodeOut_15.a.ready wire x1_nodeOut_16 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate x1_nodeOut_16.d.bits.corrupt invalidate x1_nodeOut_16.d.bits.data invalidate x1_nodeOut_16.d.bits.denied invalidate x1_nodeOut_16.d.bits.sink invalidate x1_nodeOut_16.d.bits.source invalidate x1_nodeOut_16.d.bits.size invalidate x1_nodeOut_16.d.bits.param invalidate x1_nodeOut_16.d.bits.opcode invalidate x1_nodeOut_16.d.valid invalidate x1_nodeOut_16.d.ready invalidate x1_nodeOut_16.a.bits.corrupt invalidate x1_nodeOut_16.a.bits.data invalidate x1_nodeOut_16.a.bits.mask invalidate x1_nodeOut_16.a.bits.address invalidate x1_nodeOut_16.a.bits.source invalidate x1_nodeOut_16.a.bits.size invalidate x1_nodeOut_16.a.bits.param invalidate x1_nodeOut_16.a.bits.opcode invalidate x1_nodeOut_16.a.valid invalidate x1_nodeOut_16.a.ready wire x1_nodeOut_17 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}} invalidate x1_nodeOut_17.e.bits.sink invalidate x1_nodeOut_17.e.valid invalidate x1_nodeOut_17.e.ready invalidate x1_nodeOut_17.d.bits.corrupt invalidate x1_nodeOut_17.d.bits.data invalidate x1_nodeOut_17.d.bits.denied invalidate x1_nodeOut_17.d.bits.sink invalidate x1_nodeOut_17.d.bits.source invalidate x1_nodeOut_17.d.bits.size invalidate x1_nodeOut_17.d.bits.param invalidate x1_nodeOut_17.d.bits.opcode invalidate x1_nodeOut_17.d.valid invalidate x1_nodeOut_17.d.ready invalidate x1_nodeOut_17.c.bits.corrupt invalidate x1_nodeOut_17.c.bits.data invalidate x1_nodeOut_17.c.bits.address invalidate x1_nodeOut_17.c.bits.source invalidate x1_nodeOut_17.c.bits.size invalidate x1_nodeOut_17.c.bits.param invalidate x1_nodeOut_17.c.bits.opcode invalidate x1_nodeOut_17.c.valid invalidate x1_nodeOut_17.c.ready invalidate x1_nodeOut_17.b.bits.corrupt invalidate x1_nodeOut_17.b.bits.data invalidate x1_nodeOut_17.b.bits.mask invalidate x1_nodeOut_17.b.bits.address invalidate x1_nodeOut_17.b.bits.source invalidate x1_nodeOut_17.b.bits.size invalidate x1_nodeOut_17.b.bits.param invalidate x1_nodeOut_17.b.bits.opcode invalidate x1_nodeOut_17.b.valid invalidate x1_nodeOut_17.b.ready invalidate x1_nodeOut_17.a.bits.corrupt invalidate x1_nodeOut_17.a.bits.data invalidate x1_nodeOut_17.a.bits.mask invalidate x1_nodeOut_17.a.bits.address invalidate x1_nodeOut_17.a.bits.source invalidate x1_nodeOut_17.a.bits.size invalidate x1_nodeOut_17.a.bits.param invalidate x1_nodeOut_17.a.bits.opcode invalidate x1_nodeOut_17.a.valid invalidate x1_nodeOut_17.a.ready connect auto.out_0, nodeOut connect auto.out_1, x1_nodeOut connect auto.out_2, x1_nodeOut_1 connect auto.out_3, x1_nodeOut_2 connect auto.out_4, x1_nodeOut_3 connect auto.out_5, x1_nodeOut_4 connect auto.out_6, x1_nodeOut_5 connect auto.out_7, x1_nodeOut_6 connect auto.out_8, x1_nodeOut_7 connect auto.out_9, x1_nodeOut_8 connect auto.out_10, x1_nodeOut_9 connect auto.out_11, x1_nodeOut_10 connect auto.out_12, x1_nodeOut_11 connect auto.out_13, x1_nodeOut_12 connect auto.out_14, x1_nodeOut_13 connect auto.out_15, x1_nodeOut_14 connect auto.out_16, x1_nodeOut_15 connect auto.out_17, x1_nodeOut_16 connect auto.out_18, x1_nodeOut_17 connect nodeIn, auto.in_0 connect nodeIn_1, auto.in_1 connect nodeIn_2, auto.in_2 connect nodeIn_3, auto.in_3 connect nodeIn_4, auto.in_4 connect nodeIn_5, auto.in_5 connect nodeIn_6, auto.in_6 connect nodeIn_7, auto.in_7 connect nodeIn_8, auto.in_8 connect nodeIn_9, auto.in_9 connect nodeIn_10, auto.in_10 connect nodeIn_11, auto.in_11 connect nodeIn_12, auto.in_12 connect nodeIn_13, auto.in_13 connect nodeIn_14, auto.in_14 connect nodeIn_15, auto.in_15 connect nodeIn_16, auto.in_16 connect nodeIn_17, auto.in_17 connect nodeIn_18, auto.in_18 inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<2>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<2>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<2>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<2>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_10.bits.sink, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0) inst nodeOut_a_q_1 of Queue2_TLBundleA_a32d64s2k3z4u_1 connect nodeOut_a_q_1.clock, clock connect nodeOut_a_q_1.reset, reset connect nodeOut_a_q_1.io.enq.valid, nodeIn_1.a.valid connect nodeOut_a_q_1.io.enq.bits.corrupt, nodeIn_1.a.bits.corrupt connect nodeOut_a_q_1.io.enq.bits.data, nodeIn_1.a.bits.data connect nodeOut_a_q_1.io.enq.bits.mask, nodeIn_1.a.bits.mask connect nodeOut_a_q_1.io.enq.bits.address, nodeIn_1.a.bits.address connect nodeOut_a_q_1.io.enq.bits.source, nodeIn_1.a.bits.source connect nodeOut_a_q_1.io.enq.bits.size, nodeIn_1.a.bits.size connect nodeOut_a_q_1.io.enq.bits.param, nodeIn_1.a.bits.param connect nodeOut_a_q_1.io.enq.bits.opcode, nodeIn_1.a.bits.opcode connect nodeIn_1.a.ready, nodeOut_a_q_1.io.enq.ready connect x1_nodeOut.a.bits, nodeOut_a_q_1.io.deq.bits connect x1_nodeOut.a.valid, nodeOut_a_q_1.io.deq.valid connect nodeOut_a_q_1.io.deq.ready, x1_nodeOut.a.ready inst nodeIn_d_q_1 of Queue2_TLBundleD_a32d64s2k3z4u_1 connect nodeIn_d_q_1.clock, clock connect nodeIn_d_q_1.reset, reset connect nodeIn_d_q_1.io.enq.valid, x1_nodeOut.d.valid connect nodeIn_d_q_1.io.enq.bits.corrupt, x1_nodeOut.d.bits.corrupt connect nodeIn_d_q_1.io.enq.bits.data, x1_nodeOut.d.bits.data connect nodeIn_d_q_1.io.enq.bits.denied, x1_nodeOut.d.bits.denied connect nodeIn_d_q_1.io.enq.bits.sink, x1_nodeOut.d.bits.sink connect nodeIn_d_q_1.io.enq.bits.source, x1_nodeOut.d.bits.source connect nodeIn_d_q_1.io.enq.bits.size, x1_nodeOut.d.bits.size connect nodeIn_d_q_1.io.enq.bits.param, x1_nodeOut.d.bits.param connect nodeIn_d_q_1.io.enq.bits.opcode, x1_nodeOut.d.bits.opcode connect x1_nodeOut.d.ready, nodeIn_d_q_1.io.enq.ready connect nodeIn_1.d.bits, nodeIn_d_q_1.io.deq.bits connect nodeIn_1.d.valid, nodeIn_d_q_1.io.deq.valid connect nodeIn_d_q_1.io.deq.ready, nodeIn_1.d.ready wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.mask, UInt<8>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<2>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<2>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready connect _WIRE_13.valid, UInt<1>(0h0) wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<2>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready connect _WIRE_15.ready, UInt<1>(0h1) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_16.bits.sink, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready connect _WIRE_17.ready, UInt<1>(0h1) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.mask, UInt<8>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<2>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<2>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready connect _WIRE_19.ready, UInt<1>(0h1) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<2>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready connect _WIRE_21.valid, UInt<1>(0h0) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_22.bits.sink, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready connect _WIRE_23.valid, UInt<1>(0h0) inst nodeOut_a_q_2 of Queue2_TLBundleA_a32d64s5k3z4u_1 connect nodeOut_a_q_2.clock, clock connect nodeOut_a_q_2.reset, reset connect nodeOut_a_q_2.io.enq.valid, nodeIn_2.a.valid connect nodeOut_a_q_2.io.enq.bits.corrupt, nodeIn_2.a.bits.corrupt connect nodeOut_a_q_2.io.enq.bits.data, nodeIn_2.a.bits.data connect nodeOut_a_q_2.io.enq.bits.mask, nodeIn_2.a.bits.mask connect nodeOut_a_q_2.io.enq.bits.address, nodeIn_2.a.bits.address connect nodeOut_a_q_2.io.enq.bits.source, nodeIn_2.a.bits.source connect nodeOut_a_q_2.io.enq.bits.size, nodeIn_2.a.bits.size connect nodeOut_a_q_2.io.enq.bits.param, nodeIn_2.a.bits.param connect nodeOut_a_q_2.io.enq.bits.opcode, nodeIn_2.a.bits.opcode connect nodeIn_2.a.ready, nodeOut_a_q_2.io.enq.ready connect x1_nodeOut_1.a.bits, nodeOut_a_q_2.io.deq.bits connect x1_nodeOut_1.a.valid, nodeOut_a_q_2.io.deq.valid connect nodeOut_a_q_2.io.deq.ready, x1_nodeOut_1.a.ready inst nodeIn_d_q_2 of Queue2_TLBundleD_a32d64s5k3z4u_1 connect nodeIn_d_q_2.clock, clock connect nodeIn_d_q_2.reset, reset connect nodeIn_d_q_2.io.enq.valid, x1_nodeOut_1.d.valid connect nodeIn_d_q_2.io.enq.bits.corrupt, x1_nodeOut_1.d.bits.corrupt connect nodeIn_d_q_2.io.enq.bits.data, x1_nodeOut_1.d.bits.data connect nodeIn_d_q_2.io.enq.bits.denied, x1_nodeOut_1.d.bits.denied connect nodeIn_d_q_2.io.enq.bits.sink, x1_nodeOut_1.d.bits.sink connect nodeIn_d_q_2.io.enq.bits.source, x1_nodeOut_1.d.bits.source connect nodeIn_d_q_2.io.enq.bits.size, x1_nodeOut_1.d.bits.size connect nodeIn_d_q_2.io.enq.bits.param, x1_nodeOut_1.d.bits.param connect nodeIn_d_q_2.io.enq.bits.opcode, x1_nodeOut_1.d.bits.opcode connect x1_nodeOut_1.d.ready, nodeIn_d_q_2.io.enq.ready connect nodeIn_2.d.bits, nodeIn_d_q_2.io.deq.bits connect nodeIn_2.d.valid, nodeIn_d_q_2.io.deq.valid connect nodeIn_d_q_2.io.deq.ready, nodeIn_2.d.ready wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.mask, UInt<8>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<2>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready connect _WIRE_25.valid, UInt<1>(0h0) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<32>(0h0) connect _WIRE_26.bits.source, UInt<5>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready connect _WIRE_27.ready, UInt<1>(0h1) wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_28.bits.sink, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready connect _WIRE_29.ready, UInt<1>(0h1) wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_30.bits.corrupt, UInt<1>(0h0) connect _WIRE_30.bits.data, UInt<64>(0h0) connect _WIRE_30.bits.mask, UInt<8>(0h0) connect _WIRE_30.bits.address, UInt<32>(0h0) connect _WIRE_30.bits.source, UInt<5>(0h0) connect _WIRE_30.bits.size, UInt<4>(0h0) connect _WIRE_30.bits.param, UInt<2>(0h0) connect _WIRE_30.bits.opcode, UInt<3>(0h0) connect _WIRE_30.valid, UInt<1>(0h0) connect _WIRE_30.ready, UInt<1>(0h0) wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_31.bits, _WIRE_30.bits connect _WIRE_31.valid, _WIRE_30.valid connect _WIRE_31.ready, _WIRE_30.ready connect _WIRE_31.ready, UInt<1>(0h1) wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_32.bits.corrupt, UInt<1>(0h0) connect _WIRE_32.bits.data, UInt<64>(0h0) connect _WIRE_32.bits.address, UInt<32>(0h0) connect _WIRE_32.bits.source, UInt<5>(0h0) connect _WIRE_32.bits.size, UInt<4>(0h0) connect _WIRE_32.bits.param, UInt<3>(0h0) connect _WIRE_32.bits.opcode, UInt<3>(0h0) connect _WIRE_32.valid, UInt<1>(0h0) connect _WIRE_32.ready, UInt<1>(0h0) wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_33.bits, _WIRE_32.bits connect _WIRE_33.valid, _WIRE_32.valid connect _WIRE_33.ready, _WIRE_32.ready connect _WIRE_33.valid, UInt<1>(0h0) wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_34.bits.sink, UInt<3>(0h0) connect _WIRE_34.valid, UInt<1>(0h0) connect _WIRE_34.ready, UInt<1>(0h0) wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_35.bits, _WIRE_34.bits connect _WIRE_35.valid, _WIRE_34.valid connect _WIRE_35.ready, _WIRE_34.ready connect _WIRE_35.valid, UInt<1>(0h0) inst nodeOut_a_q_3 of Queue2_TLBundleA_a32d64s5k3z4u_2 connect nodeOut_a_q_3.clock, clock connect nodeOut_a_q_3.reset, reset connect nodeOut_a_q_3.io.enq.valid, nodeIn_3.a.valid connect nodeOut_a_q_3.io.enq.bits.corrupt, nodeIn_3.a.bits.corrupt connect nodeOut_a_q_3.io.enq.bits.data, nodeIn_3.a.bits.data connect nodeOut_a_q_3.io.enq.bits.mask, nodeIn_3.a.bits.mask connect nodeOut_a_q_3.io.enq.bits.address, nodeIn_3.a.bits.address connect nodeOut_a_q_3.io.enq.bits.source, nodeIn_3.a.bits.source connect nodeOut_a_q_3.io.enq.bits.size, nodeIn_3.a.bits.size connect nodeOut_a_q_3.io.enq.bits.param, nodeIn_3.a.bits.param connect nodeOut_a_q_3.io.enq.bits.opcode, nodeIn_3.a.bits.opcode connect nodeIn_3.a.ready, nodeOut_a_q_3.io.enq.ready connect x1_nodeOut_2.a.bits, nodeOut_a_q_3.io.deq.bits connect x1_nodeOut_2.a.valid, nodeOut_a_q_3.io.deq.valid connect nodeOut_a_q_3.io.deq.ready, x1_nodeOut_2.a.ready inst nodeIn_d_q_3 of Queue2_TLBundleD_a32d64s5k3z4u_2 connect nodeIn_d_q_3.clock, clock connect nodeIn_d_q_3.reset, reset connect nodeIn_d_q_3.io.enq.valid, x1_nodeOut_2.d.valid connect nodeIn_d_q_3.io.enq.bits.corrupt, x1_nodeOut_2.d.bits.corrupt connect nodeIn_d_q_3.io.enq.bits.data, x1_nodeOut_2.d.bits.data connect nodeIn_d_q_3.io.enq.bits.denied, x1_nodeOut_2.d.bits.denied connect nodeIn_d_q_3.io.enq.bits.sink, x1_nodeOut_2.d.bits.sink connect nodeIn_d_q_3.io.enq.bits.source, x1_nodeOut_2.d.bits.source connect nodeIn_d_q_3.io.enq.bits.size, x1_nodeOut_2.d.bits.size connect nodeIn_d_q_3.io.enq.bits.param, x1_nodeOut_2.d.bits.param connect nodeIn_d_q_3.io.enq.bits.opcode, x1_nodeOut_2.d.bits.opcode connect x1_nodeOut_2.d.ready, nodeIn_d_q_3.io.enq.ready connect nodeIn_3.d.bits, nodeIn_d_q_3.io.deq.bits connect nodeIn_3.d.valid, nodeIn_d_q_3.io.deq.valid connect nodeIn_d_q_3.io.deq.ready, nodeIn_3.d.ready wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_36.bits.corrupt, UInt<1>(0h0) connect _WIRE_36.bits.data, UInt<64>(0h0) connect _WIRE_36.bits.mask, UInt<8>(0h0) connect _WIRE_36.bits.address, UInt<32>(0h0) connect _WIRE_36.bits.source, UInt<5>(0h0) connect _WIRE_36.bits.size, UInt<4>(0h0) connect _WIRE_36.bits.param, UInt<2>(0h0) connect _WIRE_36.bits.opcode, UInt<3>(0h0) connect _WIRE_36.valid, UInt<1>(0h0) connect _WIRE_36.ready, UInt<1>(0h0) wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_37.bits, _WIRE_36.bits connect _WIRE_37.valid, _WIRE_36.valid connect _WIRE_37.ready, _WIRE_36.ready connect _WIRE_37.valid, UInt<1>(0h0) wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_38.bits.corrupt, UInt<1>(0h0) connect _WIRE_38.bits.data, UInt<64>(0h0) connect _WIRE_38.bits.address, UInt<32>(0h0) connect _WIRE_38.bits.source, UInt<5>(0h0) connect _WIRE_38.bits.size, UInt<4>(0h0) connect _WIRE_38.bits.param, UInt<3>(0h0) connect _WIRE_38.bits.opcode, UInt<3>(0h0) connect _WIRE_38.valid, UInt<1>(0h0) connect _WIRE_38.ready, UInt<1>(0h0) wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_39.bits, _WIRE_38.bits connect _WIRE_39.valid, _WIRE_38.valid connect _WIRE_39.ready, _WIRE_38.ready connect _WIRE_39.ready, UInt<1>(0h1) wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_40.bits.sink, UInt<3>(0h0) connect _WIRE_40.valid, UInt<1>(0h0) connect _WIRE_40.ready, UInt<1>(0h0) wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_41.bits, _WIRE_40.bits connect _WIRE_41.valid, _WIRE_40.valid connect _WIRE_41.ready, _WIRE_40.ready connect _WIRE_41.ready, UInt<1>(0h1) wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_42.bits.corrupt, UInt<1>(0h0) connect _WIRE_42.bits.data, UInt<64>(0h0) connect _WIRE_42.bits.mask, UInt<8>(0h0) connect _WIRE_42.bits.address, UInt<32>(0h0) connect _WIRE_42.bits.source, UInt<5>(0h0) connect _WIRE_42.bits.size, UInt<4>(0h0) connect _WIRE_42.bits.param, UInt<2>(0h0) connect _WIRE_42.bits.opcode, UInt<3>(0h0) connect _WIRE_42.valid, UInt<1>(0h0) connect _WIRE_42.ready, UInt<1>(0h0) wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_43.bits, _WIRE_42.bits connect _WIRE_43.valid, _WIRE_42.valid connect _WIRE_43.ready, _WIRE_42.ready connect _WIRE_43.ready, UInt<1>(0h1) wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_44.bits.corrupt, UInt<1>(0h0) connect _WIRE_44.bits.data, UInt<64>(0h0) connect _WIRE_44.bits.address, UInt<32>(0h0) connect _WIRE_44.bits.source, UInt<5>(0h0) connect _WIRE_44.bits.size, UInt<4>(0h0) connect _WIRE_44.bits.param, UInt<3>(0h0) connect _WIRE_44.bits.opcode, UInt<3>(0h0) connect _WIRE_44.valid, UInt<1>(0h0) connect _WIRE_44.ready, UInt<1>(0h0) wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_45.bits, _WIRE_44.bits connect _WIRE_45.valid, _WIRE_44.valid connect _WIRE_45.ready, _WIRE_44.ready connect _WIRE_45.valid, UInt<1>(0h0) wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_46.bits.sink, UInt<3>(0h0) connect _WIRE_46.valid, UInt<1>(0h0) connect _WIRE_46.ready, UInt<1>(0h0) wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_47.bits, _WIRE_46.bits connect _WIRE_47.valid, _WIRE_46.valid connect _WIRE_47.ready, _WIRE_46.ready connect _WIRE_47.valid, UInt<1>(0h0) inst nodeOut_a_q_4 of Queue2_TLBundleA_a32d64s5k3z4u_3 connect nodeOut_a_q_4.clock, clock connect nodeOut_a_q_4.reset, reset connect nodeOut_a_q_4.io.enq.valid, nodeIn_4.a.valid connect nodeOut_a_q_4.io.enq.bits.corrupt, nodeIn_4.a.bits.corrupt connect nodeOut_a_q_4.io.enq.bits.data, nodeIn_4.a.bits.data connect nodeOut_a_q_4.io.enq.bits.mask, nodeIn_4.a.bits.mask connect nodeOut_a_q_4.io.enq.bits.address, nodeIn_4.a.bits.address connect nodeOut_a_q_4.io.enq.bits.source, nodeIn_4.a.bits.source connect nodeOut_a_q_4.io.enq.bits.size, nodeIn_4.a.bits.size connect nodeOut_a_q_4.io.enq.bits.param, nodeIn_4.a.bits.param connect nodeOut_a_q_4.io.enq.bits.opcode, nodeIn_4.a.bits.opcode connect nodeIn_4.a.ready, nodeOut_a_q_4.io.enq.ready connect x1_nodeOut_3.a.bits, nodeOut_a_q_4.io.deq.bits connect x1_nodeOut_3.a.valid, nodeOut_a_q_4.io.deq.valid connect nodeOut_a_q_4.io.deq.ready, x1_nodeOut_3.a.ready inst nodeIn_d_q_4 of Queue2_TLBundleD_a32d64s5k3z4u_3 connect nodeIn_d_q_4.clock, clock connect nodeIn_d_q_4.reset, reset connect nodeIn_d_q_4.io.enq.valid, x1_nodeOut_3.d.valid connect nodeIn_d_q_4.io.enq.bits.corrupt, x1_nodeOut_3.d.bits.corrupt connect nodeIn_d_q_4.io.enq.bits.data, x1_nodeOut_3.d.bits.data connect nodeIn_d_q_4.io.enq.bits.denied, x1_nodeOut_3.d.bits.denied connect nodeIn_d_q_4.io.enq.bits.sink, x1_nodeOut_3.d.bits.sink connect nodeIn_d_q_4.io.enq.bits.source, x1_nodeOut_3.d.bits.source connect nodeIn_d_q_4.io.enq.bits.size, x1_nodeOut_3.d.bits.size connect nodeIn_d_q_4.io.enq.bits.param, x1_nodeOut_3.d.bits.param connect nodeIn_d_q_4.io.enq.bits.opcode, x1_nodeOut_3.d.bits.opcode connect x1_nodeOut_3.d.ready, nodeIn_d_q_4.io.enq.ready connect nodeIn_4.d.bits, nodeIn_d_q_4.io.deq.bits connect nodeIn_4.d.valid, nodeIn_d_q_4.io.deq.valid connect nodeIn_d_q_4.io.deq.ready, nodeIn_4.d.ready wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_48.bits.corrupt, UInt<1>(0h0) connect _WIRE_48.bits.data, UInt<64>(0h0) connect _WIRE_48.bits.mask, UInt<8>(0h0) connect _WIRE_48.bits.address, UInt<32>(0h0) connect _WIRE_48.bits.source, UInt<5>(0h0) connect _WIRE_48.bits.size, UInt<4>(0h0) connect _WIRE_48.bits.param, UInt<2>(0h0) connect _WIRE_48.bits.opcode, UInt<3>(0h0) connect _WIRE_48.valid, UInt<1>(0h0) connect _WIRE_48.ready, UInt<1>(0h0) wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_49.bits, _WIRE_48.bits connect _WIRE_49.valid, _WIRE_48.valid connect _WIRE_49.ready, _WIRE_48.ready connect _WIRE_49.valid, UInt<1>(0h0) wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_50.bits.corrupt, UInt<1>(0h0) connect _WIRE_50.bits.data, UInt<64>(0h0) connect _WIRE_50.bits.address, UInt<32>(0h0) connect _WIRE_50.bits.source, UInt<5>(0h0) connect _WIRE_50.bits.size, UInt<4>(0h0) connect _WIRE_50.bits.param, UInt<3>(0h0) connect _WIRE_50.bits.opcode, UInt<3>(0h0) connect _WIRE_50.valid, UInt<1>(0h0) connect _WIRE_50.ready, UInt<1>(0h0) wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_51.bits, _WIRE_50.bits connect _WIRE_51.valid, _WIRE_50.valid connect _WIRE_51.ready, _WIRE_50.ready connect _WIRE_51.ready, UInt<1>(0h1) wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_52.bits.sink, UInt<3>(0h0) connect _WIRE_52.valid, UInt<1>(0h0) connect _WIRE_52.ready, UInt<1>(0h0) wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_53.bits, _WIRE_52.bits connect _WIRE_53.valid, _WIRE_52.valid connect _WIRE_53.ready, _WIRE_52.ready connect _WIRE_53.ready, UInt<1>(0h1) wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_54.bits.corrupt, UInt<1>(0h0) connect _WIRE_54.bits.data, UInt<64>(0h0) connect _WIRE_54.bits.mask, UInt<8>(0h0) connect _WIRE_54.bits.address, UInt<32>(0h0) connect _WIRE_54.bits.source, UInt<5>(0h0) connect _WIRE_54.bits.size, UInt<4>(0h0) connect _WIRE_54.bits.param, UInt<2>(0h0) connect _WIRE_54.bits.opcode, UInt<3>(0h0) connect _WIRE_54.valid, UInt<1>(0h0) connect _WIRE_54.ready, UInt<1>(0h0) wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_55.bits, _WIRE_54.bits connect _WIRE_55.valid, _WIRE_54.valid connect _WIRE_55.ready, _WIRE_54.ready connect _WIRE_55.ready, UInt<1>(0h1) wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_56.bits.corrupt, UInt<1>(0h0) connect _WIRE_56.bits.data, UInt<64>(0h0) connect _WIRE_56.bits.address, UInt<32>(0h0) connect _WIRE_56.bits.source, UInt<5>(0h0) connect _WIRE_56.bits.size, UInt<4>(0h0) connect _WIRE_56.bits.param, UInt<3>(0h0) connect _WIRE_56.bits.opcode, UInt<3>(0h0) connect _WIRE_56.valid, UInt<1>(0h0) connect _WIRE_56.ready, UInt<1>(0h0) wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_57.bits, _WIRE_56.bits connect _WIRE_57.valid, _WIRE_56.valid connect _WIRE_57.ready, _WIRE_56.ready connect _WIRE_57.valid, UInt<1>(0h0) wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_58.bits.sink, UInt<3>(0h0) connect _WIRE_58.valid, UInt<1>(0h0) connect _WIRE_58.ready, UInt<1>(0h0) wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_59.bits, _WIRE_58.bits connect _WIRE_59.valid, _WIRE_58.valid connect _WIRE_59.ready, _WIRE_58.ready connect _WIRE_59.valid, UInt<1>(0h0) inst nodeOut_a_q_5 of Queue2_TLBundleA_a32d64s5k3z4u_4 connect nodeOut_a_q_5.clock, clock connect nodeOut_a_q_5.reset, reset connect nodeOut_a_q_5.io.enq.valid, nodeIn_5.a.valid connect nodeOut_a_q_5.io.enq.bits.corrupt, nodeIn_5.a.bits.corrupt connect nodeOut_a_q_5.io.enq.bits.data, nodeIn_5.a.bits.data connect nodeOut_a_q_5.io.enq.bits.mask, nodeIn_5.a.bits.mask connect nodeOut_a_q_5.io.enq.bits.address, nodeIn_5.a.bits.address connect nodeOut_a_q_5.io.enq.bits.source, nodeIn_5.a.bits.source connect nodeOut_a_q_5.io.enq.bits.size, nodeIn_5.a.bits.size connect nodeOut_a_q_5.io.enq.bits.param, nodeIn_5.a.bits.param connect nodeOut_a_q_5.io.enq.bits.opcode, nodeIn_5.a.bits.opcode connect nodeIn_5.a.ready, nodeOut_a_q_5.io.enq.ready connect x1_nodeOut_4.a.bits, nodeOut_a_q_5.io.deq.bits connect x1_nodeOut_4.a.valid, nodeOut_a_q_5.io.deq.valid connect nodeOut_a_q_5.io.deq.ready, x1_nodeOut_4.a.ready inst nodeIn_d_q_5 of Queue2_TLBundleD_a32d64s5k3z4u_4 connect nodeIn_d_q_5.clock, clock connect nodeIn_d_q_5.reset, reset connect nodeIn_d_q_5.io.enq.valid, x1_nodeOut_4.d.valid connect nodeIn_d_q_5.io.enq.bits.corrupt, x1_nodeOut_4.d.bits.corrupt connect nodeIn_d_q_5.io.enq.bits.data, x1_nodeOut_4.d.bits.data connect nodeIn_d_q_5.io.enq.bits.denied, x1_nodeOut_4.d.bits.denied connect nodeIn_d_q_5.io.enq.bits.sink, x1_nodeOut_4.d.bits.sink connect nodeIn_d_q_5.io.enq.bits.source, x1_nodeOut_4.d.bits.source connect nodeIn_d_q_5.io.enq.bits.size, x1_nodeOut_4.d.bits.size connect nodeIn_d_q_5.io.enq.bits.param, x1_nodeOut_4.d.bits.param connect nodeIn_d_q_5.io.enq.bits.opcode, x1_nodeOut_4.d.bits.opcode connect x1_nodeOut_4.d.ready, nodeIn_d_q_5.io.enq.ready connect nodeIn_5.d.bits, nodeIn_d_q_5.io.deq.bits connect nodeIn_5.d.valid, nodeIn_d_q_5.io.deq.valid connect nodeIn_d_q_5.io.deq.ready, nodeIn_5.d.ready wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_60.bits.corrupt, UInt<1>(0h0) connect _WIRE_60.bits.data, UInt<64>(0h0) connect _WIRE_60.bits.mask, UInt<8>(0h0) connect _WIRE_60.bits.address, UInt<32>(0h0) connect _WIRE_60.bits.source, UInt<5>(0h0) connect _WIRE_60.bits.size, UInt<4>(0h0) connect _WIRE_60.bits.param, UInt<2>(0h0) connect _WIRE_60.bits.opcode, UInt<3>(0h0) connect _WIRE_60.valid, UInt<1>(0h0) connect _WIRE_60.ready, UInt<1>(0h0) wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_61.bits, _WIRE_60.bits connect _WIRE_61.valid, _WIRE_60.valid connect _WIRE_61.ready, _WIRE_60.ready connect _WIRE_61.valid, UInt<1>(0h0) wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_62.bits.corrupt, UInt<1>(0h0) connect _WIRE_62.bits.data, UInt<64>(0h0) connect _WIRE_62.bits.address, UInt<32>(0h0) connect _WIRE_62.bits.source, UInt<5>(0h0) connect _WIRE_62.bits.size, UInt<4>(0h0) connect _WIRE_62.bits.param, UInt<3>(0h0) connect _WIRE_62.bits.opcode, UInt<3>(0h0) connect _WIRE_62.valid, UInt<1>(0h0) connect _WIRE_62.ready, UInt<1>(0h0) wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_63.bits, _WIRE_62.bits connect _WIRE_63.valid, _WIRE_62.valid connect _WIRE_63.ready, _WIRE_62.ready connect _WIRE_63.ready, UInt<1>(0h1) wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_64.bits.sink, UInt<3>(0h0) connect _WIRE_64.valid, UInt<1>(0h0) connect _WIRE_64.ready, UInt<1>(0h0) wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_65.bits, _WIRE_64.bits connect _WIRE_65.valid, _WIRE_64.valid connect _WIRE_65.ready, _WIRE_64.ready connect _WIRE_65.ready, UInt<1>(0h1) wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_66.bits.corrupt, UInt<1>(0h0) connect _WIRE_66.bits.data, UInt<64>(0h0) connect _WIRE_66.bits.mask, UInt<8>(0h0) connect _WIRE_66.bits.address, UInt<32>(0h0) connect _WIRE_66.bits.source, UInt<5>(0h0) connect _WIRE_66.bits.size, UInt<4>(0h0) connect _WIRE_66.bits.param, UInt<2>(0h0) connect _WIRE_66.bits.opcode, UInt<3>(0h0) connect _WIRE_66.valid, UInt<1>(0h0) connect _WIRE_66.ready, UInt<1>(0h0) wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_67.bits, _WIRE_66.bits connect _WIRE_67.valid, _WIRE_66.valid connect _WIRE_67.ready, _WIRE_66.ready connect _WIRE_67.ready, UInt<1>(0h1) wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_68.bits.corrupt, UInt<1>(0h0) connect _WIRE_68.bits.data, UInt<64>(0h0) connect _WIRE_68.bits.address, UInt<32>(0h0) connect _WIRE_68.bits.source, UInt<5>(0h0) connect _WIRE_68.bits.size, UInt<4>(0h0) connect _WIRE_68.bits.param, UInt<3>(0h0) connect _WIRE_68.bits.opcode, UInt<3>(0h0) connect _WIRE_68.valid, UInt<1>(0h0) connect _WIRE_68.ready, UInt<1>(0h0) wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_69.bits, _WIRE_68.bits connect _WIRE_69.valid, _WIRE_68.valid connect _WIRE_69.ready, _WIRE_68.ready connect _WIRE_69.valid, UInt<1>(0h0) wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_70.bits.sink, UInt<3>(0h0) connect _WIRE_70.valid, UInt<1>(0h0) connect _WIRE_70.ready, UInt<1>(0h0) wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_71.bits, _WIRE_70.bits connect _WIRE_71.valid, _WIRE_70.valid connect _WIRE_71.ready, _WIRE_70.ready connect _WIRE_71.valid, UInt<1>(0h0) inst nodeOut_a_q_6 of Queue2_TLBundleA_a32d64s5k3z4u_5 connect nodeOut_a_q_6.clock, clock connect nodeOut_a_q_6.reset, reset connect nodeOut_a_q_6.io.enq.valid, nodeIn_6.a.valid connect nodeOut_a_q_6.io.enq.bits.corrupt, nodeIn_6.a.bits.corrupt connect nodeOut_a_q_6.io.enq.bits.data, nodeIn_6.a.bits.data connect nodeOut_a_q_6.io.enq.bits.mask, nodeIn_6.a.bits.mask connect nodeOut_a_q_6.io.enq.bits.address, nodeIn_6.a.bits.address connect nodeOut_a_q_6.io.enq.bits.source, nodeIn_6.a.bits.source connect nodeOut_a_q_6.io.enq.bits.size, nodeIn_6.a.bits.size connect nodeOut_a_q_6.io.enq.bits.param, nodeIn_6.a.bits.param connect nodeOut_a_q_6.io.enq.bits.opcode, nodeIn_6.a.bits.opcode connect nodeIn_6.a.ready, nodeOut_a_q_6.io.enq.ready connect x1_nodeOut_5.a.bits, nodeOut_a_q_6.io.deq.bits connect x1_nodeOut_5.a.valid, nodeOut_a_q_6.io.deq.valid connect nodeOut_a_q_6.io.deq.ready, x1_nodeOut_5.a.ready inst nodeIn_d_q_6 of Queue2_TLBundleD_a32d64s5k3z4u_5 connect nodeIn_d_q_6.clock, clock connect nodeIn_d_q_6.reset, reset connect nodeIn_d_q_6.io.enq.valid, x1_nodeOut_5.d.valid connect nodeIn_d_q_6.io.enq.bits.corrupt, x1_nodeOut_5.d.bits.corrupt connect nodeIn_d_q_6.io.enq.bits.data, x1_nodeOut_5.d.bits.data connect nodeIn_d_q_6.io.enq.bits.denied, x1_nodeOut_5.d.bits.denied connect nodeIn_d_q_6.io.enq.bits.sink, x1_nodeOut_5.d.bits.sink connect nodeIn_d_q_6.io.enq.bits.source, x1_nodeOut_5.d.bits.source connect nodeIn_d_q_6.io.enq.bits.size, x1_nodeOut_5.d.bits.size connect nodeIn_d_q_6.io.enq.bits.param, x1_nodeOut_5.d.bits.param connect nodeIn_d_q_6.io.enq.bits.opcode, x1_nodeOut_5.d.bits.opcode connect x1_nodeOut_5.d.ready, nodeIn_d_q_6.io.enq.ready connect nodeIn_6.d.bits, nodeIn_d_q_6.io.deq.bits connect nodeIn_6.d.valid, nodeIn_d_q_6.io.deq.valid connect nodeIn_d_q_6.io.deq.ready, nodeIn_6.d.ready wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_72.bits.corrupt, UInt<1>(0h0) connect _WIRE_72.bits.data, UInt<64>(0h0) connect _WIRE_72.bits.mask, UInt<8>(0h0) connect _WIRE_72.bits.address, UInt<32>(0h0) connect _WIRE_72.bits.source, UInt<5>(0h0) connect _WIRE_72.bits.size, UInt<4>(0h0) connect _WIRE_72.bits.param, UInt<2>(0h0) connect _WIRE_72.bits.opcode, UInt<3>(0h0) connect _WIRE_72.valid, UInt<1>(0h0) connect _WIRE_72.ready, UInt<1>(0h0) wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_73.bits, _WIRE_72.bits connect _WIRE_73.valid, _WIRE_72.valid connect _WIRE_73.ready, _WIRE_72.ready connect _WIRE_73.valid, UInt<1>(0h0) wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_74.bits.corrupt, UInt<1>(0h0) connect _WIRE_74.bits.data, UInt<64>(0h0) connect _WIRE_74.bits.address, UInt<32>(0h0) connect _WIRE_74.bits.source, UInt<5>(0h0) connect _WIRE_74.bits.size, UInt<4>(0h0) connect _WIRE_74.bits.param, UInt<3>(0h0) connect _WIRE_74.bits.opcode, UInt<3>(0h0) connect _WIRE_74.valid, UInt<1>(0h0) connect _WIRE_74.ready, UInt<1>(0h0) wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_75.bits, _WIRE_74.bits connect _WIRE_75.valid, _WIRE_74.valid connect _WIRE_75.ready, _WIRE_74.ready connect _WIRE_75.ready, UInt<1>(0h1) wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_76.bits.sink, UInt<3>(0h0) connect _WIRE_76.valid, UInt<1>(0h0) connect _WIRE_76.ready, UInt<1>(0h0) wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_77.bits, _WIRE_76.bits connect _WIRE_77.valid, _WIRE_76.valid connect _WIRE_77.ready, _WIRE_76.ready connect _WIRE_77.ready, UInt<1>(0h1) wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_78.bits.corrupt, UInt<1>(0h0) connect _WIRE_78.bits.data, UInt<64>(0h0) connect _WIRE_78.bits.mask, UInt<8>(0h0) connect _WIRE_78.bits.address, UInt<32>(0h0) connect _WIRE_78.bits.source, UInt<5>(0h0) connect _WIRE_78.bits.size, UInt<4>(0h0) connect _WIRE_78.bits.param, UInt<2>(0h0) connect _WIRE_78.bits.opcode, UInt<3>(0h0) connect _WIRE_78.valid, UInt<1>(0h0) connect _WIRE_78.ready, UInt<1>(0h0) wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_79.bits, _WIRE_78.bits connect _WIRE_79.valid, _WIRE_78.valid connect _WIRE_79.ready, _WIRE_78.ready connect _WIRE_79.ready, UInt<1>(0h1) wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_80.bits.corrupt, UInt<1>(0h0) connect _WIRE_80.bits.data, UInt<64>(0h0) connect _WIRE_80.bits.address, UInt<32>(0h0) connect _WIRE_80.bits.source, UInt<5>(0h0) connect _WIRE_80.bits.size, UInt<4>(0h0) connect _WIRE_80.bits.param, UInt<3>(0h0) connect _WIRE_80.bits.opcode, UInt<3>(0h0) connect _WIRE_80.valid, UInt<1>(0h0) connect _WIRE_80.ready, UInt<1>(0h0) wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_81.bits, _WIRE_80.bits connect _WIRE_81.valid, _WIRE_80.valid connect _WIRE_81.ready, _WIRE_80.ready connect _WIRE_81.valid, UInt<1>(0h0) wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_82.bits.sink, UInt<3>(0h0) connect _WIRE_82.valid, UInt<1>(0h0) connect _WIRE_82.ready, UInt<1>(0h0) wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_83.bits, _WIRE_82.bits connect _WIRE_83.valid, _WIRE_82.valid connect _WIRE_83.ready, _WIRE_82.ready connect _WIRE_83.valid, UInt<1>(0h0) inst nodeOut_a_q_7 of Queue2_TLBundleA_a32d64s5k3z4u_6 connect nodeOut_a_q_7.clock, clock connect nodeOut_a_q_7.reset, reset connect nodeOut_a_q_7.io.enq.valid, nodeIn_7.a.valid connect nodeOut_a_q_7.io.enq.bits.corrupt, nodeIn_7.a.bits.corrupt connect nodeOut_a_q_7.io.enq.bits.data, nodeIn_7.a.bits.data connect nodeOut_a_q_7.io.enq.bits.mask, nodeIn_7.a.bits.mask connect nodeOut_a_q_7.io.enq.bits.address, nodeIn_7.a.bits.address connect nodeOut_a_q_7.io.enq.bits.source, nodeIn_7.a.bits.source connect nodeOut_a_q_7.io.enq.bits.size, nodeIn_7.a.bits.size connect nodeOut_a_q_7.io.enq.bits.param, nodeIn_7.a.bits.param connect nodeOut_a_q_7.io.enq.bits.opcode, nodeIn_7.a.bits.opcode connect nodeIn_7.a.ready, nodeOut_a_q_7.io.enq.ready connect x1_nodeOut_6.a.bits, nodeOut_a_q_7.io.deq.bits connect x1_nodeOut_6.a.valid, nodeOut_a_q_7.io.deq.valid connect nodeOut_a_q_7.io.deq.ready, x1_nodeOut_6.a.ready inst nodeIn_d_q_7 of Queue2_TLBundleD_a32d64s5k3z4u_6 connect nodeIn_d_q_7.clock, clock connect nodeIn_d_q_7.reset, reset connect nodeIn_d_q_7.io.enq.valid, x1_nodeOut_6.d.valid connect nodeIn_d_q_7.io.enq.bits.corrupt, x1_nodeOut_6.d.bits.corrupt connect nodeIn_d_q_7.io.enq.bits.data, x1_nodeOut_6.d.bits.data connect nodeIn_d_q_7.io.enq.bits.denied, x1_nodeOut_6.d.bits.denied connect nodeIn_d_q_7.io.enq.bits.sink, x1_nodeOut_6.d.bits.sink connect nodeIn_d_q_7.io.enq.bits.source, x1_nodeOut_6.d.bits.source connect nodeIn_d_q_7.io.enq.bits.size, x1_nodeOut_6.d.bits.size connect nodeIn_d_q_7.io.enq.bits.param, x1_nodeOut_6.d.bits.param connect nodeIn_d_q_7.io.enq.bits.opcode, x1_nodeOut_6.d.bits.opcode connect x1_nodeOut_6.d.ready, nodeIn_d_q_7.io.enq.ready connect nodeIn_7.d.bits, nodeIn_d_q_7.io.deq.bits connect nodeIn_7.d.valid, nodeIn_d_q_7.io.deq.valid connect nodeIn_d_q_7.io.deq.ready, nodeIn_7.d.ready wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_84.bits.corrupt, UInt<1>(0h0) connect _WIRE_84.bits.data, UInt<64>(0h0) connect _WIRE_84.bits.mask, UInt<8>(0h0) connect _WIRE_84.bits.address, UInt<32>(0h0) connect _WIRE_84.bits.source, UInt<5>(0h0) connect _WIRE_84.bits.size, UInt<4>(0h0) connect _WIRE_84.bits.param, UInt<2>(0h0) connect _WIRE_84.bits.opcode, UInt<3>(0h0) connect _WIRE_84.valid, UInt<1>(0h0) connect _WIRE_84.ready, UInt<1>(0h0) wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_85.bits, _WIRE_84.bits connect _WIRE_85.valid, _WIRE_84.valid connect _WIRE_85.ready, _WIRE_84.ready connect _WIRE_85.valid, UInt<1>(0h0) wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_86.bits.corrupt, UInt<1>(0h0) connect _WIRE_86.bits.data, UInt<64>(0h0) connect _WIRE_86.bits.address, UInt<32>(0h0) connect _WIRE_86.bits.source, UInt<5>(0h0) connect _WIRE_86.bits.size, UInt<4>(0h0) connect _WIRE_86.bits.param, UInt<3>(0h0) connect _WIRE_86.bits.opcode, UInt<3>(0h0) connect _WIRE_86.valid, UInt<1>(0h0) connect _WIRE_86.ready, UInt<1>(0h0) wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_87.bits, _WIRE_86.bits connect _WIRE_87.valid, _WIRE_86.valid connect _WIRE_87.ready, _WIRE_86.ready connect _WIRE_87.ready, UInt<1>(0h1) wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_88.bits.sink, UInt<3>(0h0) connect _WIRE_88.valid, UInt<1>(0h0) connect _WIRE_88.ready, UInt<1>(0h0) wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_89.bits, _WIRE_88.bits connect _WIRE_89.valid, _WIRE_88.valid connect _WIRE_89.ready, _WIRE_88.ready connect _WIRE_89.ready, UInt<1>(0h1) wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_90.bits.corrupt, UInt<1>(0h0) connect _WIRE_90.bits.data, UInt<64>(0h0) connect _WIRE_90.bits.mask, UInt<8>(0h0) connect _WIRE_90.bits.address, UInt<32>(0h0) connect _WIRE_90.bits.source, UInt<5>(0h0) connect _WIRE_90.bits.size, UInt<4>(0h0) connect _WIRE_90.bits.param, UInt<2>(0h0) connect _WIRE_90.bits.opcode, UInt<3>(0h0) connect _WIRE_90.valid, UInt<1>(0h0) connect _WIRE_90.ready, UInt<1>(0h0) wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_91.bits, _WIRE_90.bits connect _WIRE_91.valid, _WIRE_90.valid connect _WIRE_91.ready, _WIRE_90.ready connect _WIRE_91.ready, UInt<1>(0h1) wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_92.bits.corrupt, UInt<1>(0h0) connect _WIRE_92.bits.data, UInt<64>(0h0) connect _WIRE_92.bits.address, UInt<32>(0h0) connect _WIRE_92.bits.source, UInt<5>(0h0) connect _WIRE_92.bits.size, UInt<4>(0h0) connect _WIRE_92.bits.param, UInt<3>(0h0) connect _WIRE_92.bits.opcode, UInt<3>(0h0) connect _WIRE_92.valid, UInt<1>(0h0) connect _WIRE_92.ready, UInt<1>(0h0) wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_93.bits, _WIRE_92.bits connect _WIRE_93.valid, _WIRE_92.valid connect _WIRE_93.ready, _WIRE_92.ready connect _WIRE_93.valid, UInt<1>(0h0) wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_94.bits.sink, UInt<3>(0h0) connect _WIRE_94.valid, UInt<1>(0h0) connect _WIRE_94.ready, UInt<1>(0h0) wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_95.bits, _WIRE_94.bits connect _WIRE_95.valid, _WIRE_94.valid connect _WIRE_95.ready, _WIRE_94.ready connect _WIRE_95.valid, UInt<1>(0h0) inst nodeOut_a_q_8 of Queue2_TLBundleA_a32d64s2k3z4u_2 connect nodeOut_a_q_8.clock, clock connect nodeOut_a_q_8.reset, reset connect nodeOut_a_q_8.io.enq.valid, nodeIn_8.a.valid connect nodeOut_a_q_8.io.enq.bits.corrupt, nodeIn_8.a.bits.corrupt connect nodeOut_a_q_8.io.enq.bits.data, nodeIn_8.a.bits.data connect nodeOut_a_q_8.io.enq.bits.mask, nodeIn_8.a.bits.mask connect nodeOut_a_q_8.io.enq.bits.address, nodeIn_8.a.bits.address connect nodeOut_a_q_8.io.enq.bits.source, nodeIn_8.a.bits.source connect nodeOut_a_q_8.io.enq.bits.size, nodeIn_8.a.bits.size connect nodeOut_a_q_8.io.enq.bits.param, nodeIn_8.a.bits.param connect nodeOut_a_q_8.io.enq.bits.opcode, nodeIn_8.a.bits.opcode connect nodeIn_8.a.ready, nodeOut_a_q_8.io.enq.ready connect x1_nodeOut_7.a.bits, nodeOut_a_q_8.io.deq.bits connect x1_nodeOut_7.a.valid, nodeOut_a_q_8.io.deq.valid connect nodeOut_a_q_8.io.deq.ready, x1_nodeOut_7.a.ready inst nodeIn_d_q_8 of Queue2_TLBundleD_a32d64s2k3z4u_2 connect nodeIn_d_q_8.clock, clock connect nodeIn_d_q_8.reset, reset connect nodeIn_d_q_8.io.enq.valid, x1_nodeOut_7.d.valid connect nodeIn_d_q_8.io.enq.bits.corrupt, x1_nodeOut_7.d.bits.corrupt connect nodeIn_d_q_8.io.enq.bits.data, x1_nodeOut_7.d.bits.data connect nodeIn_d_q_8.io.enq.bits.denied, x1_nodeOut_7.d.bits.denied connect nodeIn_d_q_8.io.enq.bits.sink, x1_nodeOut_7.d.bits.sink connect nodeIn_d_q_8.io.enq.bits.source, x1_nodeOut_7.d.bits.source connect nodeIn_d_q_8.io.enq.bits.size, x1_nodeOut_7.d.bits.size connect nodeIn_d_q_8.io.enq.bits.param, x1_nodeOut_7.d.bits.param connect nodeIn_d_q_8.io.enq.bits.opcode, x1_nodeOut_7.d.bits.opcode connect x1_nodeOut_7.d.ready, nodeIn_d_q_8.io.enq.ready connect nodeIn_8.d.bits, nodeIn_d_q_8.io.deq.bits connect nodeIn_8.d.valid, nodeIn_d_q_8.io.deq.valid connect nodeIn_d_q_8.io.deq.ready, nodeIn_8.d.ready wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_96.bits.corrupt, UInt<1>(0h0) connect _WIRE_96.bits.data, UInt<64>(0h0) connect _WIRE_96.bits.mask, UInt<8>(0h0) connect _WIRE_96.bits.address, UInt<32>(0h0) connect _WIRE_96.bits.source, UInt<2>(0h0) connect _WIRE_96.bits.size, UInt<4>(0h0) connect _WIRE_96.bits.param, UInt<2>(0h0) connect _WIRE_96.bits.opcode, UInt<3>(0h0) connect _WIRE_96.valid, UInt<1>(0h0) connect _WIRE_96.ready, UInt<1>(0h0) wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_97.bits, _WIRE_96.bits connect _WIRE_97.valid, _WIRE_96.valid connect _WIRE_97.ready, _WIRE_96.ready connect _WIRE_97.valid, UInt<1>(0h0) wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_98.bits.corrupt, UInt<1>(0h0) connect _WIRE_98.bits.data, UInt<64>(0h0) connect _WIRE_98.bits.address, UInt<32>(0h0) connect _WIRE_98.bits.source, UInt<2>(0h0) connect _WIRE_98.bits.size, UInt<4>(0h0) connect _WIRE_98.bits.param, UInt<3>(0h0) connect _WIRE_98.bits.opcode, UInt<3>(0h0) connect _WIRE_98.valid, UInt<1>(0h0) connect _WIRE_98.ready, UInt<1>(0h0) wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_99.bits, _WIRE_98.bits connect _WIRE_99.valid, _WIRE_98.valid connect _WIRE_99.ready, _WIRE_98.ready connect _WIRE_99.ready, UInt<1>(0h1) wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_100.bits.sink, UInt<3>(0h0) connect _WIRE_100.valid, UInt<1>(0h0) connect _WIRE_100.ready, UInt<1>(0h0) wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_101.bits, _WIRE_100.bits connect _WIRE_101.valid, _WIRE_100.valid connect _WIRE_101.ready, _WIRE_100.ready connect _WIRE_101.ready, UInt<1>(0h1) wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_102.bits.corrupt, UInt<1>(0h0) connect _WIRE_102.bits.data, UInt<64>(0h0) connect _WIRE_102.bits.mask, UInt<8>(0h0) connect _WIRE_102.bits.address, UInt<32>(0h0) connect _WIRE_102.bits.source, UInt<2>(0h0) connect _WIRE_102.bits.size, UInt<4>(0h0) connect _WIRE_102.bits.param, UInt<2>(0h0) connect _WIRE_102.bits.opcode, UInt<3>(0h0) connect _WIRE_102.valid, UInt<1>(0h0) connect _WIRE_102.ready, UInt<1>(0h0) wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_103.bits, _WIRE_102.bits connect _WIRE_103.valid, _WIRE_102.valid connect _WIRE_103.ready, _WIRE_102.ready connect _WIRE_103.ready, UInt<1>(0h1) wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_104.bits.corrupt, UInt<1>(0h0) connect _WIRE_104.bits.data, UInt<64>(0h0) connect _WIRE_104.bits.address, UInt<32>(0h0) connect _WIRE_104.bits.source, UInt<2>(0h0) connect _WIRE_104.bits.size, UInt<4>(0h0) connect _WIRE_104.bits.param, UInt<3>(0h0) connect _WIRE_104.bits.opcode, UInt<3>(0h0) connect _WIRE_104.valid, UInt<1>(0h0) connect _WIRE_104.ready, UInt<1>(0h0) wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_105.bits, _WIRE_104.bits connect _WIRE_105.valid, _WIRE_104.valid connect _WIRE_105.ready, _WIRE_104.ready connect _WIRE_105.valid, UInt<1>(0h0) wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_106.bits.sink, UInt<3>(0h0) connect _WIRE_106.valid, UInt<1>(0h0) connect _WIRE_106.ready, UInt<1>(0h0) wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_107.bits, _WIRE_106.bits connect _WIRE_107.valid, _WIRE_106.valid connect _WIRE_107.ready, _WIRE_106.ready connect _WIRE_107.valid, UInt<1>(0h0) inst nodeOut_a_q_9 of Queue2_TLBundleA_a32d64s2k3z4u_3 connect nodeOut_a_q_9.clock, clock connect nodeOut_a_q_9.reset, reset connect nodeOut_a_q_9.io.enq.valid, nodeIn_9.a.valid connect nodeOut_a_q_9.io.enq.bits.corrupt, nodeIn_9.a.bits.corrupt connect nodeOut_a_q_9.io.enq.bits.data, nodeIn_9.a.bits.data connect nodeOut_a_q_9.io.enq.bits.mask, nodeIn_9.a.bits.mask connect nodeOut_a_q_9.io.enq.bits.address, nodeIn_9.a.bits.address connect nodeOut_a_q_9.io.enq.bits.source, nodeIn_9.a.bits.source connect nodeOut_a_q_9.io.enq.bits.size, nodeIn_9.a.bits.size connect nodeOut_a_q_9.io.enq.bits.param, nodeIn_9.a.bits.param connect nodeOut_a_q_9.io.enq.bits.opcode, nodeIn_9.a.bits.opcode connect nodeIn_9.a.ready, nodeOut_a_q_9.io.enq.ready connect x1_nodeOut_8.a.bits, nodeOut_a_q_9.io.deq.bits connect x1_nodeOut_8.a.valid, nodeOut_a_q_9.io.deq.valid connect nodeOut_a_q_9.io.deq.ready, x1_nodeOut_8.a.ready inst nodeIn_d_q_9 of Queue2_TLBundleD_a32d64s2k3z4u_3 connect nodeIn_d_q_9.clock, clock connect nodeIn_d_q_9.reset, reset connect nodeIn_d_q_9.io.enq.valid, x1_nodeOut_8.d.valid connect nodeIn_d_q_9.io.enq.bits.corrupt, x1_nodeOut_8.d.bits.corrupt connect nodeIn_d_q_9.io.enq.bits.data, x1_nodeOut_8.d.bits.data connect nodeIn_d_q_9.io.enq.bits.denied, x1_nodeOut_8.d.bits.denied connect nodeIn_d_q_9.io.enq.bits.sink, x1_nodeOut_8.d.bits.sink connect nodeIn_d_q_9.io.enq.bits.source, x1_nodeOut_8.d.bits.source connect nodeIn_d_q_9.io.enq.bits.size, x1_nodeOut_8.d.bits.size connect nodeIn_d_q_9.io.enq.bits.param, x1_nodeOut_8.d.bits.param connect nodeIn_d_q_9.io.enq.bits.opcode, x1_nodeOut_8.d.bits.opcode connect x1_nodeOut_8.d.ready, nodeIn_d_q_9.io.enq.ready connect nodeIn_9.d.bits, nodeIn_d_q_9.io.deq.bits connect nodeIn_9.d.valid, nodeIn_d_q_9.io.deq.valid connect nodeIn_d_q_9.io.deq.ready, nodeIn_9.d.ready wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_108.bits.corrupt, UInt<1>(0h0) connect _WIRE_108.bits.data, UInt<64>(0h0) connect _WIRE_108.bits.mask, UInt<8>(0h0) connect _WIRE_108.bits.address, UInt<32>(0h0) connect _WIRE_108.bits.source, UInt<2>(0h0) connect _WIRE_108.bits.size, UInt<4>(0h0) connect _WIRE_108.bits.param, UInt<2>(0h0) connect _WIRE_108.bits.opcode, UInt<3>(0h0) connect _WIRE_108.valid, UInt<1>(0h0) connect _WIRE_108.ready, UInt<1>(0h0) wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_109.bits, _WIRE_108.bits connect _WIRE_109.valid, _WIRE_108.valid connect _WIRE_109.ready, _WIRE_108.ready connect _WIRE_109.valid, UInt<1>(0h0) wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_110.bits.corrupt, UInt<1>(0h0) connect _WIRE_110.bits.data, UInt<64>(0h0) connect _WIRE_110.bits.address, UInt<32>(0h0) connect _WIRE_110.bits.source, UInt<2>(0h0) connect _WIRE_110.bits.size, UInt<4>(0h0) connect _WIRE_110.bits.param, UInt<3>(0h0) connect _WIRE_110.bits.opcode, UInt<3>(0h0) connect _WIRE_110.valid, UInt<1>(0h0) connect _WIRE_110.ready, UInt<1>(0h0) wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_111.bits, _WIRE_110.bits connect _WIRE_111.valid, _WIRE_110.valid connect _WIRE_111.ready, _WIRE_110.ready connect _WIRE_111.ready, UInt<1>(0h1) wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_112.bits.sink, UInt<3>(0h0) connect _WIRE_112.valid, UInt<1>(0h0) connect _WIRE_112.ready, UInt<1>(0h0) wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_113.bits, _WIRE_112.bits connect _WIRE_113.valid, _WIRE_112.valid connect _WIRE_113.ready, _WIRE_112.ready connect _WIRE_113.ready, UInt<1>(0h1) wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_114.bits.corrupt, UInt<1>(0h0) connect _WIRE_114.bits.data, UInt<64>(0h0) connect _WIRE_114.bits.mask, UInt<8>(0h0) connect _WIRE_114.bits.address, UInt<32>(0h0) connect _WIRE_114.bits.source, UInt<2>(0h0) connect _WIRE_114.bits.size, UInt<4>(0h0) connect _WIRE_114.bits.param, UInt<2>(0h0) connect _WIRE_114.bits.opcode, UInt<3>(0h0) connect _WIRE_114.valid, UInt<1>(0h0) connect _WIRE_114.ready, UInt<1>(0h0) wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_115.bits, _WIRE_114.bits connect _WIRE_115.valid, _WIRE_114.valid connect _WIRE_115.ready, _WIRE_114.ready connect _WIRE_115.ready, UInt<1>(0h1) wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_116.bits.corrupt, UInt<1>(0h0) connect _WIRE_116.bits.data, UInt<64>(0h0) connect _WIRE_116.bits.address, UInt<32>(0h0) connect _WIRE_116.bits.source, UInt<2>(0h0) connect _WIRE_116.bits.size, UInt<4>(0h0) connect _WIRE_116.bits.param, UInt<3>(0h0) connect _WIRE_116.bits.opcode, UInt<3>(0h0) connect _WIRE_116.valid, UInt<1>(0h0) connect _WIRE_116.ready, UInt<1>(0h0) wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_117.bits, _WIRE_116.bits connect _WIRE_117.valid, _WIRE_116.valid connect _WIRE_117.ready, _WIRE_116.ready connect _WIRE_117.valid, UInt<1>(0h0) wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_118.bits.sink, UInt<3>(0h0) connect _WIRE_118.valid, UInt<1>(0h0) connect _WIRE_118.ready, UInt<1>(0h0) wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_119.bits, _WIRE_118.bits connect _WIRE_119.valid, _WIRE_118.valid connect _WIRE_119.ready, _WIRE_118.ready connect _WIRE_119.valid, UInt<1>(0h0) inst nodeOut_a_q_10 of Queue2_TLBundleA_a32d64s5k3z4u_7 connect nodeOut_a_q_10.clock, clock connect nodeOut_a_q_10.reset, reset connect nodeOut_a_q_10.io.enq.valid, nodeIn_10.a.valid connect nodeOut_a_q_10.io.enq.bits.corrupt, nodeIn_10.a.bits.corrupt connect nodeOut_a_q_10.io.enq.bits.data, nodeIn_10.a.bits.data connect nodeOut_a_q_10.io.enq.bits.mask, nodeIn_10.a.bits.mask connect nodeOut_a_q_10.io.enq.bits.address, nodeIn_10.a.bits.address connect nodeOut_a_q_10.io.enq.bits.source, nodeIn_10.a.bits.source connect nodeOut_a_q_10.io.enq.bits.size, nodeIn_10.a.bits.size connect nodeOut_a_q_10.io.enq.bits.param, nodeIn_10.a.bits.param connect nodeOut_a_q_10.io.enq.bits.opcode, nodeIn_10.a.bits.opcode connect nodeIn_10.a.ready, nodeOut_a_q_10.io.enq.ready connect x1_nodeOut_9.a.bits, nodeOut_a_q_10.io.deq.bits connect x1_nodeOut_9.a.valid, nodeOut_a_q_10.io.deq.valid connect nodeOut_a_q_10.io.deq.ready, x1_nodeOut_9.a.ready inst nodeIn_d_q_10 of Queue2_TLBundleD_a32d64s5k3z4u_7 connect nodeIn_d_q_10.clock, clock connect nodeIn_d_q_10.reset, reset connect nodeIn_d_q_10.io.enq.valid, x1_nodeOut_9.d.valid connect nodeIn_d_q_10.io.enq.bits.corrupt, x1_nodeOut_9.d.bits.corrupt connect nodeIn_d_q_10.io.enq.bits.data, x1_nodeOut_9.d.bits.data connect nodeIn_d_q_10.io.enq.bits.denied, x1_nodeOut_9.d.bits.denied connect nodeIn_d_q_10.io.enq.bits.sink, x1_nodeOut_9.d.bits.sink connect nodeIn_d_q_10.io.enq.bits.source, x1_nodeOut_9.d.bits.source connect nodeIn_d_q_10.io.enq.bits.size, x1_nodeOut_9.d.bits.size connect nodeIn_d_q_10.io.enq.bits.param, x1_nodeOut_9.d.bits.param connect nodeIn_d_q_10.io.enq.bits.opcode, x1_nodeOut_9.d.bits.opcode connect x1_nodeOut_9.d.ready, nodeIn_d_q_10.io.enq.ready connect nodeIn_10.d.bits, nodeIn_d_q_10.io.deq.bits connect nodeIn_10.d.valid, nodeIn_d_q_10.io.deq.valid connect nodeIn_d_q_10.io.deq.ready, nodeIn_10.d.ready wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_120.bits.corrupt, UInt<1>(0h0) connect _WIRE_120.bits.data, UInt<64>(0h0) connect _WIRE_120.bits.mask, UInt<8>(0h0) connect _WIRE_120.bits.address, UInt<32>(0h0) connect _WIRE_120.bits.source, UInt<5>(0h0) connect _WIRE_120.bits.size, UInt<4>(0h0) connect _WIRE_120.bits.param, UInt<2>(0h0) connect _WIRE_120.bits.opcode, UInt<3>(0h0) connect _WIRE_120.valid, UInt<1>(0h0) connect _WIRE_120.ready, UInt<1>(0h0) wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_121.bits, _WIRE_120.bits connect _WIRE_121.valid, _WIRE_120.valid connect _WIRE_121.ready, _WIRE_120.ready connect _WIRE_121.valid, UInt<1>(0h0) wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_122.bits.corrupt, UInt<1>(0h0) connect _WIRE_122.bits.data, UInt<64>(0h0) connect _WIRE_122.bits.address, UInt<32>(0h0) connect _WIRE_122.bits.source, UInt<5>(0h0) connect _WIRE_122.bits.size, UInt<4>(0h0) connect _WIRE_122.bits.param, UInt<3>(0h0) connect _WIRE_122.bits.opcode, UInt<3>(0h0) connect _WIRE_122.valid, UInt<1>(0h0) connect _WIRE_122.ready, UInt<1>(0h0) wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_123.bits, _WIRE_122.bits connect _WIRE_123.valid, _WIRE_122.valid connect _WIRE_123.ready, _WIRE_122.ready connect _WIRE_123.ready, UInt<1>(0h1) wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_124.bits.sink, UInt<3>(0h0) connect _WIRE_124.valid, UInt<1>(0h0) connect _WIRE_124.ready, UInt<1>(0h0) wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_125.bits, _WIRE_124.bits connect _WIRE_125.valid, _WIRE_124.valid connect _WIRE_125.ready, _WIRE_124.ready connect _WIRE_125.ready, UInt<1>(0h1) wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_126.bits.corrupt, UInt<1>(0h0) connect _WIRE_126.bits.data, UInt<64>(0h0) connect _WIRE_126.bits.mask, UInt<8>(0h0) connect _WIRE_126.bits.address, UInt<32>(0h0) connect _WIRE_126.bits.source, UInt<5>(0h0) connect _WIRE_126.bits.size, UInt<4>(0h0) connect _WIRE_126.bits.param, UInt<2>(0h0) connect _WIRE_126.bits.opcode, UInt<3>(0h0) connect _WIRE_126.valid, UInt<1>(0h0) connect _WIRE_126.ready, UInt<1>(0h0) wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_127.bits, _WIRE_126.bits connect _WIRE_127.valid, _WIRE_126.valid connect _WIRE_127.ready, _WIRE_126.ready connect _WIRE_127.ready, UInt<1>(0h1) wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_128.bits.corrupt, UInt<1>(0h0) connect _WIRE_128.bits.data, UInt<64>(0h0) connect _WIRE_128.bits.address, UInt<32>(0h0) connect _WIRE_128.bits.source, UInt<5>(0h0) connect _WIRE_128.bits.size, UInt<4>(0h0) connect _WIRE_128.bits.param, UInt<3>(0h0) connect _WIRE_128.bits.opcode, UInt<3>(0h0) connect _WIRE_128.valid, UInt<1>(0h0) connect _WIRE_128.ready, UInt<1>(0h0) wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_129.bits, _WIRE_128.bits connect _WIRE_129.valid, _WIRE_128.valid connect _WIRE_129.ready, _WIRE_128.ready connect _WIRE_129.valid, UInt<1>(0h0) wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_130.bits.sink, UInt<3>(0h0) connect _WIRE_130.valid, UInt<1>(0h0) connect _WIRE_130.ready, UInt<1>(0h0) wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_131.bits, _WIRE_130.bits connect _WIRE_131.valid, _WIRE_130.valid connect _WIRE_131.ready, _WIRE_130.ready connect _WIRE_131.valid, UInt<1>(0h0) inst nodeOut_a_q_11 of Queue2_TLBundleA_a32d64s5k3z4u_8 connect nodeOut_a_q_11.clock, clock connect nodeOut_a_q_11.reset, reset connect nodeOut_a_q_11.io.enq.valid, nodeIn_11.a.valid connect nodeOut_a_q_11.io.enq.bits.corrupt, nodeIn_11.a.bits.corrupt connect nodeOut_a_q_11.io.enq.bits.data, nodeIn_11.a.bits.data connect nodeOut_a_q_11.io.enq.bits.mask, nodeIn_11.a.bits.mask connect nodeOut_a_q_11.io.enq.bits.address, nodeIn_11.a.bits.address connect nodeOut_a_q_11.io.enq.bits.source, nodeIn_11.a.bits.source connect nodeOut_a_q_11.io.enq.bits.size, nodeIn_11.a.bits.size connect nodeOut_a_q_11.io.enq.bits.param, nodeIn_11.a.bits.param connect nodeOut_a_q_11.io.enq.bits.opcode, nodeIn_11.a.bits.opcode connect nodeIn_11.a.ready, nodeOut_a_q_11.io.enq.ready connect x1_nodeOut_10.a.bits, nodeOut_a_q_11.io.deq.bits connect x1_nodeOut_10.a.valid, nodeOut_a_q_11.io.deq.valid connect nodeOut_a_q_11.io.deq.ready, x1_nodeOut_10.a.ready inst nodeIn_d_q_11 of Queue2_TLBundleD_a32d64s5k3z4u_8 connect nodeIn_d_q_11.clock, clock connect nodeIn_d_q_11.reset, reset connect nodeIn_d_q_11.io.enq.valid, x1_nodeOut_10.d.valid connect nodeIn_d_q_11.io.enq.bits.corrupt, x1_nodeOut_10.d.bits.corrupt connect nodeIn_d_q_11.io.enq.bits.data, x1_nodeOut_10.d.bits.data connect nodeIn_d_q_11.io.enq.bits.denied, x1_nodeOut_10.d.bits.denied connect nodeIn_d_q_11.io.enq.bits.sink, x1_nodeOut_10.d.bits.sink connect nodeIn_d_q_11.io.enq.bits.source, x1_nodeOut_10.d.bits.source connect nodeIn_d_q_11.io.enq.bits.size, x1_nodeOut_10.d.bits.size connect nodeIn_d_q_11.io.enq.bits.param, x1_nodeOut_10.d.bits.param connect nodeIn_d_q_11.io.enq.bits.opcode, x1_nodeOut_10.d.bits.opcode connect x1_nodeOut_10.d.ready, nodeIn_d_q_11.io.enq.ready connect nodeIn_11.d.bits, nodeIn_d_q_11.io.deq.bits connect nodeIn_11.d.valid, nodeIn_d_q_11.io.deq.valid connect nodeIn_d_q_11.io.deq.ready, nodeIn_11.d.ready wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_132.bits.corrupt, UInt<1>(0h0) connect _WIRE_132.bits.data, UInt<64>(0h0) connect _WIRE_132.bits.mask, UInt<8>(0h0) connect _WIRE_132.bits.address, UInt<32>(0h0) connect _WIRE_132.bits.source, UInt<5>(0h0) connect _WIRE_132.bits.size, UInt<4>(0h0) connect _WIRE_132.bits.param, UInt<2>(0h0) connect _WIRE_132.bits.opcode, UInt<3>(0h0) connect _WIRE_132.valid, UInt<1>(0h0) connect _WIRE_132.ready, UInt<1>(0h0) wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_133.bits, _WIRE_132.bits connect _WIRE_133.valid, _WIRE_132.valid connect _WIRE_133.ready, _WIRE_132.ready connect _WIRE_133.valid, UInt<1>(0h0) wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_134.bits.corrupt, UInt<1>(0h0) connect _WIRE_134.bits.data, UInt<64>(0h0) connect _WIRE_134.bits.address, UInt<32>(0h0) connect _WIRE_134.bits.source, UInt<5>(0h0) connect _WIRE_134.bits.size, UInt<4>(0h0) connect _WIRE_134.bits.param, UInt<3>(0h0) connect _WIRE_134.bits.opcode, UInt<3>(0h0) connect _WIRE_134.valid, UInt<1>(0h0) connect _WIRE_134.ready, UInt<1>(0h0) wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_135.bits, _WIRE_134.bits connect _WIRE_135.valid, _WIRE_134.valid connect _WIRE_135.ready, _WIRE_134.ready connect _WIRE_135.ready, UInt<1>(0h1) wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_136.bits.sink, UInt<3>(0h0) connect _WIRE_136.valid, UInt<1>(0h0) connect _WIRE_136.ready, UInt<1>(0h0) wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_137.bits, _WIRE_136.bits connect _WIRE_137.valid, _WIRE_136.valid connect _WIRE_137.ready, _WIRE_136.ready connect _WIRE_137.ready, UInt<1>(0h1) wire _WIRE_138 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_138.bits.corrupt, UInt<1>(0h0) connect _WIRE_138.bits.data, UInt<64>(0h0) connect _WIRE_138.bits.mask, UInt<8>(0h0) connect _WIRE_138.bits.address, UInt<32>(0h0) connect _WIRE_138.bits.source, UInt<5>(0h0) connect _WIRE_138.bits.size, UInt<4>(0h0) connect _WIRE_138.bits.param, UInt<2>(0h0) connect _WIRE_138.bits.opcode, UInt<3>(0h0) connect _WIRE_138.valid, UInt<1>(0h0) connect _WIRE_138.ready, UInt<1>(0h0) wire _WIRE_139 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_139.bits, _WIRE_138.bits connect _WIRE_139.valid, _WIRE_138.valid connect _WIRE_139.ready, _WIRE_138.ready connect _WIRE_139.ready, UInt<1>(0h1) wire _WIRE_140 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_140.bits.corrupt, UInt<1>(0h0) connect _WIRE_140.bits.data, UInt<64>(0h0) connect _WIRE_140.bits.address, UInt<32>(0h0) connect _WIRE_140.bits.source, UInt<5>(0h0) connect _WIRE_140.bits.size, UInt<4>(0h0) connect _WIRE_140.bits.param, UInt<3>(0h0) connect _WIRE_140.bits.opcode, UInt<3>(0h0) connect _WIRE_140.valid, UInt<1>(0h0) connect _WIRE_140.ready, UInt<1>(0h0) wire _WIRE_141 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_141.bits, _WIRE_140.bits connect _WIRE_141.valid, _WIRE_140.valid connect _WIRE_141.ready, _WIRE_140.ready connect _WIRE_141.valid, UInt<1>(0h0) wire _WIRE_142 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_142.bits.sink, UInt<3>(0h0) connect _WIRE_142.valid, UInt<1>(0h0) connect _WIRE_142.ready, UInt<1>(0h0) wire _WIRE_143 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_143.bits, _WIRE_142.bits connect _WIRE_143.valid, _WIRE_142.valid connect _WIRE_143.ready, _WIRE_142.ready connect _WIRE_143.valid, UInt<1>(0h0) inst nodeOut_a_q_12 of Queue2_TLBundleA_a32d64s5k3z4u_9 connect nodeOut_a_q_12.clock, clock connect nodeOut_a_q_12.reset, reset connect nodeOut_a_q_12.io.enq.valid, nodeIn_12.a.valid connect nodeOut_a_q_12.io.enq.bits.corrupt, nodeIn_12.a.bits.corrupt connect nodeOut_a_q_12.io.enq.bits.data, nodeIn_12.a.bits.data connect nodeOut_a_q_12.io.enq.bits.mask, nodeIn_12.a.bits.mask connect nodeOut_a_q_12.io.enq.bits.address, nodeIn_12.a.bits.address connect nodeOut_a_q_12.io.enq.bits.source, nodeIn_12.a.bits.source connect nodeOut_a_q_12.io.enq.bits.size, nodeIn_12.a.bits.size connect nodeOut_a_q_12.io.enq.bits.param, nodeIn_12.a.bits.param connect nodeOut_a_q_12.io.enq.bits.opcode, nodeIn_12.a.bits.opcode connect nodeIn_12.a.ready, nodeOut_a_q_12.io.enq.ready connect x1_nodeOut_11.a.bits, nodeOut_a_q_12.io.deq.bits connect x1_nodeOut_11.a.valid, nodeOut_a_q_12.io.deq.valid connect nodeOut_a_q_12.io.deq.ready, x1_nodeOut_11.a.ready inst nodeIn_d_q_12 of Queue2_TLBundleD_a32d64s5k3z4u_9 connect nodeIn_d_q_12.clock, clock connect nodeIn_d_q_12.reset, reset connect nodeIn_d_q_12.io.enq.valid, x1_nodeOut_11.d.valid connect nodeIn_d_q_12.io.enq.bits.corrupt, x1_nodeOut_11.d.bits.corrupt connect nodeIn_d_q_12.io.enq.bits.data, x1_nodeOut_11.d.bits.data connect nodeIn_d_q_12.io.enq.bits.denied, x1_nodeOut_11.d.bits.denied connect nodeIn_d_q_12.io.enq.bits.sink, x1_nodeOut_11.d.bits.sink connect nodeIn_d_q_12.io.enq.bits.source, x1_nodeOut_11.d.bits.source connect nodeIn_d_q_12.io.enq.bits.size, x1_nodeOut_11.d.bits.size connect nodeIn_d_q_12.io.enq.bits.param, x1_nodeOut_11.d.bits.param connect nodeIn_d_q_12.io.enq.bits.opcode, x1_nodeOut_11.d.bits.opcode connect x1_nodeOut_11.d.ready, nodeIn_d_q_12.io.enq.ready connect nodeIn_12.d.bits, nodeIn_d_q_12.io.deq.bits connect nodeIn_12.d.valid, nodeIn_d_q_12.io.deq.valid connect nodeIn_d_q_12.io.deq.ready, nodeIn_12.d.ready wire _WIRE_144 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_144.bits.corrupt, UInt<1>(0h0) connect _WIRE_144.bits.data, UInt<64>(0h0) connect _WIRE_144.bits.mask, UInt<8>(0h0) connect _WIRE_144.bits.address, UInt<32>(0h0) connect _WIRE_144.bits.source, UInt<5>(0h0) connect _WIRE_144.bits.size, UInt<4>(0h0) connect _WIRE_144.bits.param, UInt<2>(0h0) connect _WIRE_144.bits.opcode, UInt<3>(0h0) connect _WIRE_144.valid, UInt<1>(0h0) connect _WIRE_144.ready, UInt<1>(0h0) wire _WIRE_145 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_145.bits, _WIRE_144.bits connect _WIRE_145.valid, _WIRE_144.valid connect _WIRE_145.ready, _WIRE_144.ready connect _WIRE_145.valid, UInt<1>(0h0) wire _WIRE_146 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_146.bits.corrupt, UInt<1>(0h0) connect _WIRE_146.bits.data, UInt<64>(0h0) connect _WIRE_146.bits.address, UInt<32>(0h0) connect _WIRE_146.bits.source, UInt<5>(0h0) connect _WIRE_146.bits.size, UInt<4>(0h0) connect _WIRE_146.bits.param, UInt<3>(0h0) connect _WIRE_146.bits.opcode, UInt<3>(0h0) connect _WIRE_146.valid, UInt<1>(0h0) connect _WIRE_146.ready, UInt<1>(0h0) wire _WIRE_147 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_147.bits, _WIRE_146.bits connect _WIRE_147.valid, _WIRE_146.valid connect _WIRE_147.ready, _WIRE_146.ready connect _WIRE_147.ready, UInt<1>(0h1) wire _WIRE_148 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_148.bits.sink, UInt<3>(0h0) connect _WIRE_148.valid, UInt<1>(0h0) connect _WIRE_148.ready, UInt<1>(0h0) wire _WIRE_149 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_149.bits, _WIRE_148.bits connect _WIRE_149.valid, _WIRE_148.valid connect _WIRE_149.ready, _WIRE_148.ready connect _WIRE_149.ready, UInt<1>(0h1) wire _WIRE_150 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_150.bits.corrupt, UInt<1>(0h0) connect _WIRE_150.bits.data, UInt<64>(0h0) connect _WIRE_150.bits.mask, UInt<8>(0h0) connect _WIRE_150.bits.address, UInt<32>(0h0) connect _WIRE_150.bits.source, UInt<5>(0h0) connect _WIRE_150.bits.size, UInt<4>(0h0) connect _WIRE_150.bits.param, UInt<2>(0h0) connect _WIRE_150.bits.opcode, UInt<3>(0h0) connect _WIRE_150.valid, UInt<1>(0h0) connect _WIRE_150.ready, UInt<1>(0h0) wire _WIRE_151 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_151.bits, _WIRE_150.bits connect _WIRE_151.valid, _WIRE_150.valid connect _WIRE_151.ready, _WIRE_150.ready connect _WIRE_151.ready, UInt<1>(0h1) wire _WIRE_152 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_152.bits.corrupt, UInt<1>(0h0) connect _WIRE_152.bits.data, UInt<64>(0h0) connect _WIRE_152.bits.address, UInt<32>(0h0) connect _WIRE_152.bits.source, UInt<5>(0h0) connect _WIRE_152.bits.size, UInt<4>(0h0) connect _WIRE_152.bits.param, UInt<3>(0h0) connect _WIRE_152.bits.opcode, UInt<3>(0h0) connect _WIRE_152.valid, UInt<1>(0h0) connect _WIRE_152.ready, UInt<1>(0h0) wire _WIRE_153 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_153.bits, _WIRE_152.bits connect _WIRE_153.valid, _WIRE_152.valid connect _WIRE_153.ready, _WIRE_152.ready connect _WIRE_153.valid, UInt<1>(0h0) wire _WIRE_154 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_154.bits.sink, UInt<3>(0h0) connect _WIRE_154.valid, UInt<1>(0h0) connect _WIRE_154.ready, UInt<1>(0h0) wire _WIRE_155 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_155.bits, _WIRE_154.bits connect _WIRE_155.valid, _WIRE_154.valid connect _WIRE_155.ready, _WIRE_154.ready connect _WIRE_155.valid, UInt<1>(0h0) inst nodeOut_a_q_13 of Queue2_TLBundleA_a32d64s5k3z4u_10 connect nodeOut_a_q_13.clock, clock connect nodeOut_a_q_13.reset, reset connect nodeOut_a_q_13.io.enq.valid, nodeIn_13.a.valid connect nodeOut_a_q_13.io.enq.bits.corrupt, nodeIn_13.a.bits.corrupt connect nodeOut_a_q_13.io.enq.bits.data, nodeIn_13.a.bits.data connect nodeOut_a_q_13.io.enq.bits.mask, nodeIn_13.a.bits.mask connect nodeOut_a_q_13.io.enq.bits.address, nodeIn_13.a.bits.address connect nodeOut_a_q_13.io.enq.bits.source, nodeIn_13.a.bits.source connect nodeOut_a_q_13.io.enq.bits.size, nodeIn_13.a.bits.size connect nodeOut_a_q_13.io.enq.bits.param, nodeIn_13.a.bits.param connect nodeOut_a_q_13.io.enq.bits.opcode, nodeIn_13.a.bits.opcode connect nodeIn_13.a.ready, nodeOut_a_q_13.io.enq.ready connect x1_nodeOut_12.a.bits, nodeOut_a_q_13.io.deq.bits connect x1_nodeOut_12.a.valid, nodeOut_a_q_13.io.deq.valid connect nodeOut_a_q_13.io.deq.ready, x1_nodeOut_12.a.ready inst nodeIn_d_q_13 of Queue2_TLBundleD_a32d64s5k3z4u_10 connect nodeIn_d_q_13.clock, clock connect nodeIn_d_q_13.reset, reset connect nodeIn_d_q_13.io.enq.valid, x1_nodeOut_12.d.valid connect nodeIn_d_q_13.io.enq.bits.corrupt, x1_nodeOut_12.d.bits.corrupt connect nodeIn_d_q_13.io.enq.bits.data, x1_nodeOut_12.d.bits.data connect nodeIn_d_q_13.io.enq.bits.denied, x1_nodeOut_12.d.bits.denied connect nodeIn_d_q_13.io.enq.bits.sink, x1_nodeOut_12.d.bits.sink connect nodeIn_d_q_13.io.enq.bits.source, x1_nodeOut_12.d.bits.source connect nodeIn_d_q_13.io.enq.bits.size, x1_nodeOut_12.d.bits.size connect nodeIn_d_q_13.io.enq.bits.param, x1_nodeOut_12.d.bits.param connect nodeIn_d_q_13.io.enq.bits.opcode, x1_nodeOut_12.d.bits.opcode connect x1_nodeOut_12.d.ready, nodeIn_d_q_13.io.enq.ready connect nodeIn_13.d.bits, nodeIn_d_q_13.io.deq.bits connect nodeIn_13.d.valid, nodeIn_d_q_13.io.deq.valid connect nodeIn_d_q_13.io.deq.ready, nodeIn_13.d.ready wire _WIRE_156 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_156.bits.corrupt, UInt<1>(0h0) connect _WIRE_156.bits.data, UInt<64>(0h0) connect _WIRE_156.bits.mask, UInt<8>(0h0) connect _WIRE_156.bits.address, UInt<32>(0h0) connect _WIRE_156.bits.source, UInt<5>(0h0) connect _WIRE_156.bits.size, UInt<4>(0h0) connect _WIRE_156.bits.param, UInt<2>(0h0) connect _WIRE_156.bits.opcode, UInt<3>(0h0) connect _WIRE_156.valid, UInt<1>(0h0) connect _WIRE_156.ready, UInt<1>(0h0) wire _WIRE_157 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_157.bits, _WIRE_156.bits connect _WIRE_157.valid, _WIRE_156.valid connect _WIRE_157.ready, _WIRE_156.ready connect _WIRE_157.valid, UInt<1>(0h0) wire _WIRE_158 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_158.bits.corrupt, UInt<1>(0h0) connect _WIRE_158.bits.data, UInt<64>(0h0) connect _WIRE_158.bits.address, UInt<32>(0h0) connect _WIRE_158.bits.source, UInt<5>(0h0) connect _WIRE_158.bits.size, UInt<4>(0h0) connect _WIRE_158.bits.param, UInt<3>(0h0) connect _WIRE_158.bits.opcode, UInt<3>(0h0) connect _WIRE_158.valid, UInt<1>(0h0) connect _WIRE_158.ready, UInt<1>(0h0) wire _WIRE_159 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_159.bits, _WIRE_158.bits connect _WIRE_159.valid, _WIRE_158.valid connect _WIRE_159.ready, _WIRE_158.ready connect _WIRE_159.ready, UInt<1>(0h1) wire _WIRE_160 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_160.bits.sink, UInt<3>(0h0) connect _WIRE_160.valid, UInt<1>(0h0) connect _WIRE_160.ready, UInt<1>(0h0) wire _WIRE_161 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_161.bits, _WIRE_160.bits connect _WIRE_161.valid, _WIRE_160.valid connect _WIRE_161.ready, _WIRE_160.ready connect _WIRE_161.ready, UInt<1>(0h1) wire _WIRE_162 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_162.bits.corrupt, UInt<1>(0h0) connect _WIRE_162.bits.data, UInt<64>(0h0) connect _WIRE_162.bits.mask, UInt<8>(0h0) connect _WIRE_162.bits.address, UInt<32>(0h0) connect _WIRE_162.bits.source, UInt<5>(0h0) connect _WIRE_162.bits.size, UInt<4>(0h0) connect _WIRE_162.bits.param, UInt<2>(0h0) connect _WIRE_162.bits.opcode, UInt<3>(0h0) connect _WIRE_162.valid, UInt<1>(0h0) connect _WIRE_162.ready, UInt<1>(0h0) wire _WIRE_163 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_163.bits, _WIRE_162.bits connect _WIRE_163.valid, _WIRE_162.valid connect _WIRE_163.ready, _WIRE_162.ready connect _WIRE_163.ready, UInt<1>(0h1) wire _WIRE_164 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_164.bits.corrupt, UInt<1>(0h0) connect _WIRE_164.bits.data, UInt<64>(0h0) connect _WIRE_164.bits.address, UInt<32>(0h0) connect _WIRE_164.bits.source, UInt<5>(0h0) connect _WIRE_164.bits.size, UInt<4>(0h0) connect _WIRE_164.bits.param, UInt<3>(0h0) connect _WIRE_164.bits.opcode, UInt<3>(0h0) connect _WIRE_164.valid, UInt<1>(0h0) connect _WIRE_164.ready, UInt<1>(0h0) wire _WIRE_165 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_165.bits, _WIRE_164.bits connect _WIRE_165.valid, _WIRE_164.valid connect _WIRE_165.ready, _WIRE_164.ready connect _WIRE_165.valid, UInt<1>(0h0) wire _WIRE_166 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_166.bits.sink, UInt<3>(0h0) connect _WIRE_166.valid, UInt<1>(0h0) connect _WIRE_166.ready, UInt<1>(0h0) wire _WIRE_167 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_167.bits, _WIRE_166.bits connect _WIRE_167.valid, _WIRE_166.valid connect _WIRE_167.ready, _WIRE_166.ready connect _WIRE_167.valid, UInt<1>(0h0) inst nodeOut_a_q_14 of Queue2_TLBundleA_a32d64s5k3z4u_11 connect nodeOut_a_q_14.clock, clock connect nodeOut_a_q_14.reset, reset connect nodeOut_a_q_14.io.enq.valid, nodeIn_14.a.valid connect nodeOut_a_q_14.io.enq.bits.corrupt, nodeIn_14.a.bits.corrupt connect nodeOut_a_q_14.io.enq.bits.data, nodeIn_14.a.bits.data connect nodeOut_a_q_14.io.enq.bits.mask, nodeIn_14.a.bits.mask connect nodeOut_a_q_14.io.enq.bits.address, nodeIn_14.a.bits.address connect nodeOut_a_q_14.io.enq.bits.source, nodeIn_14.a.bits.source connect nodeOut_a_q_14.io.enq.bits.size, nodeIn_14.a.bits.size connect nodeOut_a_q_14.io.enq.bits.param, nodeIn_14.a.bits.param connect nodeOut_a_q_14.io.enq.bits.opcode, nodeIn_14.a.bits.opcode connect nodeIn_14.a.ready, nodeOut_a_q_14.io.enq.ready connect x1_nodeOut_13.a.bits, nodeOut_a_q_14.io.deq.bits connect x1_nodeOut_13.a.valid, nodeOut_a_q_14.io.deq.valid connect nodeOut_a_q_14.io.deq.ready, x1_nodeOut_13.a.ready inst nodeIn_d_q_14 of Queue2_TLBundleD_a32d64s5k3z4u_11 connect nodeIn_d_q_14.clock, clock connect nodeIn_d_q_14.reset, reset connect nodeIn_d_q_14.io.enq.valid, x1_nodeOut_13.d.valid connect nodeIn_d_q_14.io.enq.bits.corrupt, x1_nodeOut_13.d.bits.corrupt connect nodeIn_d_q_14.io.enq.bits.data, x1_nodeOut_13.d.bits.data connect nodeIn_d_q_14.io.enq.bits.denied, x1_nodeOut_13.d.bits.denied connect nodeIn_d_q_14.io.enq.bits.sink, x1_nodeOut_13.d.bits.sink connect nodeIn_d_q_14.io.enq.bits.source, x1_nodeOut_13.d.bits.source connect nodeIn_d_q_14.io.enq.bits.size, x1_nodeOut_13.d.bits.size connect nodeIn_d_q_14.io.enq.bits.param, x1_nodeOut_13.d.bits.param connect nodeIn_d_q_14.io.enq.bits.opcode, x1_nodeOut_13.d.bits.opcode connect x1_nodeOut_13.d.ready, nodeIn_d_q_14.io.enq.ready connect nodeIn_14.d.bits, nodeIn_d_q_14.io.deq.bits connect nodeIn_14.d.valid, nodeIn_d_q_14.io.deq.valid connect nodeIn_d_q_14.io.deq.ready, nodeIn_14.d.ready wire _WIRE_168 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_168.bits.corrupt, UInt<1>(0h0) connect _WIRE_168.bits.data, UInt<64>(0h0) connect _WIRE_168.bits.mask, UInt<8>(0h0) connect _WIRE_168.bits.address, UInt<32>(0h0) connect _WIRE_168.bits.source, UInt<5>(0h0) connect _WIRE_168.bits.size, UInt<4>(0h0) connect _WIRE_168.bits.param, UInt<2>(0h0) connect _WIRE_168.bits.opcode, UInt<3>(0h0) connect _WIRE_168.valid, UInt<1>(0h0) connect _WIRE_168.ready, UInt<1>(0h0) wire _WIRE_169 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_169.bits, _WIRE_168.bits connect _WIRE_169.valid, _WIRE_168.valid connect _WIRE_169.ready, _WIRE_168.ready connect _WIRE_169.valid, UInt<1>(0h0) wire _WIRE_170 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_170.bits.corrupt, UInt<1>(0h0) connect _WIRE_170.bits.data, UInt<64>(0h0) connect _WIRE_170.bits.address, UInt<32>(0h0) connect _WIRE_170.bits.source, UInt<5>(0h0) connect _WIRE_170.bits.size, UInt<4>(0h0) connect _WIRE_170.bits.param, UInt<3>(0h0) connect _WIRE_170.bits.opcode, UInt<3>(0h0) connect _WIRE_170.valid, UInt<1>(0h0) connect _WIRE_170.ready, UInt<1>(0h0) wire _WIRE_171 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_171.bits, _WIRE_170.bits connect _WIRE_171.valid, _WIRE_170.valid connect _WIRE_171.ready, _WIRE_170.ready connect _WIRE_171.ready, UInt<1>(0h1) wire _WIRE_172 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_172.bits.sink, UInt<3>(0h0) connect _WIRE_172.valid, UInt<1>(0h0) connect _WIRE_172.ready, UInt<1>(0h0) wire _WIRE_173 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_173.bits, _WIRE_172.bits connect _WIRE_173.valid, _WIRE_172.valid connect _WIRE_173.ready, _WIRE_172.ready connect _WIRE_173.ready, UInt<1>(0h1) wire _WIRE_174 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_174.bits.corrupt, UInt<1>(0h0) connect _WIRE_174.bits.data, UInt<64>(0h0) connect _WIRE_174.bits.mask, UInt<8>(0h0) connect _WIRE_174.bits.address, UInt<32>(0h0) connect _WIRE_174.bits.source, UInt<5>(0h0) connect _WIRE_174.bits.size, UInt<4>(0h0) connect _WIRE_174.bits.param, UInt<2>(0h0) connect _WIRE_174.bits.opcode, UInt<3>(0h0) connect _WIRE_174.valid, UInt<1>(0h0) connect _WIRE_174.ready, UInt<1>(0h0) wire _WIRE_175 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_175.bits, _WIRE_174.bits connect _WIRE_175.valid, _WIRE_174.valid connect _WIRE_175.ready, _WIRE_174.ready connect _WIRE_175.ready, UInt<1>(0h1) wire _WIRE_176 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_176.bits.corrupt, UInt<1>(0h0) connect _WIRE_176.bits.data, UInt<64>(0h0) connect _WIRE_176.bits.address, UInt<32>(0h0) connect _WIRE_176.bits.source, UInt<5>(0h0) connect _WIRE_176.bits.size, UInt<4>(0h0) connect _WIRE_176.bits.param, UInt<3>(0h0) connect _WIRE_176.bits.opcode, UInt<3>(0h0) connect _WIRE_176.valid, UInt<1>(0h0) connect _WIRE_176.ready, UInt<1>(0h0) wire _WIRE_177 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_177.bits, _WIRE_176.bits connect _WIRE_177.valid, _WIRE_176.valid connect _WIRE_177.ready, _WIRE_176.ready connect _WIRE_177.valid, UInt<1>(0h0) wire _WIRE_178 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_178.bits.sink, UInt<3>(0h0) connect _WIRE_178.valid, UInt<1>(0h0) connect _WIRE_178.ready, UInt<1>(0h0) wire _WIRE_179 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_179.bits, _WIRE_178.bits connect _WIRE_179.valid, _WIRE_178.valid connect _WIRE_179.ready, _WIRE_178.ready connect _WIRE_179.valid, UInt<1>(0h0) inst nodeOut_a_q_15 of Queue2_TLBundleA_a32d64s5k3z4u_12 connect nodeOut_a_q_15.clock, clock connect nodeOut_a_q_15.reset, reset connect nodeOut_a_q_15.io.enq.valid, nodeIn_15.a.valid connect nodeOut_a_q_15.io.enq.bits.corrupt, nodeIn_15.a.bits.corrupt connect nodeOut_a_q_15.io.enq.bits.data, nodeIn_15.a.bits.data connect nodeOut_a_q_15.io.enq.bits.mask, nodeIn_15.a.bits.mask connect nodeOut_a_q_15.io.enq.bits.address, nodeIn_15.a.bits.address connect nodeOut_a_q_15.io.enq.bits.source, nodeIn_15.a.bits.source connect nodeOut_a_q_15.io.enq.bits.size, nodeIn_15.a.bits.size connect nodeOut_a_q_15.io.enq.bits.param, nodeIn_15.a.bits.param connect nodeOut_a_q_15.io.enq.bits.opcode, nodeIn_15.a.bits.opcode connect nodeIn_15.a.ready, nodeOut_a_q_15.io.enq.ready connect x1_nodeOut_14.a.bits, nodeOut_a_q_15.io.deq.bits connect x1_nodeOut_14.a.valid, nodeOut_a_q_15.io.deq.valid connect nodeOut_a_q_15.io.deq.ready, x1_nodeOut_14.a.ready inst nodeIn_d_q_15 of Queue2_TLBundleD_a32d64s5k3z4u_12 connect nodeIn_d_q_15.clock, clock connect nodeIn_d_q_15.reset, reset connect nodeIn_d_q_15.io.enq.valid, x1_nodeOut_14.d.valid connect nodeIn_d_q_15.io.enq.bits.corrupt, x1_nodeOut_14.d.bits.corrupt connect nodeIn_d_q_15.io.enq.bits.data, x1_nodeOut_14.d.bits.data connect nodeIn_d_q_15.io.enq.bits.denied, x1_nodeOut_14.d.bits.denied connect nodeIn_d_q_15.io.enq.bits.sink, x1_nodeOut_14.d.bits.sink connect nodeIn_d_q_15.io.enq.bits.source, x1_nodeOut_14.d.bits.source connect nodeIn_d_q_15.io.enq.bits.size, x1_nodeOut_14.d.bits.size connect nodeIn_d_q_15.io.enq.bits.param, x1_nodeOut_14.d.bits.param connect nodeIn_d_q_15.io.enq.bits.opcode, x1_nodeOut_14.d.bits.opcode connect x1_nodeOut_14.d.ready, nodeIn_d_q_15.io.enq.ready connect nodeIn_15.d.bits, nodeIn_d_q_15.io.deq.bits connect nodeIn_15.d.valid, nodeIn_d_q_15.io.deq.valid connect nodeIn_d_q_15.io.deq.ready, nodeIn_15.d.ready wire _WIRE_180 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_180.bits.corrupt, UInt<1>(0h0) connect _WIRE_180.bits.data, UInt<64>(0h0) connect _WIRE_180.bits.mask, UInt<8>(0h0) connect _WIRE_180.bits.address, UInt<32>(0h0) connect _WIRE_180.bits.source, UInt<5>(0h0) connect _WIRE_180.bits.size, UInt<4>(0h0) connect _WIRE_180.bits.param, UInt<2>(0h0) connect _WIRE_180.bits.opcode, UInt<3>(0h0) connect _WIRE_180.valid, UInt<1>(0h0) connect _WIRE_180.ready, UInt<1>(0h0) wire _WIRE_181 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_181.bits, _WIRE_180.bits connect _WIRE_181.valid, _WIRE_180.valid connect _WIRE_181.ready, _WIRE_180.ready connect _WIRE_181.valid, UInt<1>(0h0) wire _WIRE_182 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_182.bits.corrupt, UInt<1>(0h0) connect _WIRE_182.bits.data, UInt<64>(0h0) connect _WIRE_182.bits.address, UInt<32>(0h0) connect _WIRE_182.bits.source, UInt<5>(0h0) connect _WIRE_182.bits.size, UInt<4>(0h0) connect _WIRE_182.bits.param, UInt<3>(0h0) connect _WIRE_182.bits.opcode, UInt<3>(0h0) connect _WIRE_182.valid, UInt<1>(0h0) connect _WIRE_182.ready, UInt<1>(0h0) wire _WIRE_183 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_183.bits, _WIRE_182.bits connect _WIRE_183.valid, _WIRE_182.valid connect _WIRE_183.ready, _WIRE_182.ready connect _WIRE_183.ready, UInt<1>(0h1) wire _WIRE_184 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_184.bits.sink, UInt<3>(0h0) connect _WIRE_184.valid, UInt<1>(0h0) connect _WIRE_184.ready, UInt<1>(0h0) wire _WIRE_185 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_185.bits, _WIRE_184.bits connect _WIRE_185.valid, _WIRE_184.valid connect _WIRE_185.ready, _WIRE_184.ready connect _WIRE_185.ready, UInt<1>(0h1) wire _WIRE_186 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_186.bits.corrupt, UInt<1>(0h0) connect _WIRE_186.bits.data, UInt<64>(0h0) connect _WIRE_186.bits.mask, UInt<8>(0h0) connect _WIRE_186.bits.address, UInt<32>(0h0) connect _WIRE_186.bits.source, UInt<5>(0h0) connect _WIRE_186.bits.size, UInt<4>(0h0) connect _WIRE_186.bits.param, UInt<2>(0h0) connect _WIRE_186.bits.opcode, UInt<3>(0h0) connect _WIRE_186.valid, UInt<1>(0h0) connect _WIRE_186.ready, UInt<1>(0h0) wire _WIRE_187 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_187.bits, _WIRE_186.bits connect _WIRE_187.valid, _WIRE_186.valid connect _WIRE_187.ready, _WIRE_186.ready connect _WIRE_187.ready, UInt<1>(0h1) wire _WIRE_188 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_188.bits.corrupt, UInt<1>(0h0) connect _WIRE_188.bits.data, UInt<64>(0h0) connect _WIRE_188.bits.address, UInt<32>(0h0) connect _WIRE_188.bits.source, UInt<5>(0h0) connect _WIRE_188.bits.size, UInt<4>(0h0) connect _WIRE_188.bits.param, UInt<3>(0h0) connect _WIRE_188.bits.opcode, UInt<3>(0h0) connect _WIRE_188.valid, UInt<1>(0h0) connect _WIRE_188.ready, UInt<1>(0h0) wire _WIRE_189 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_189.bits, _WIRE_188.bits connect _WIRE_189.valid, _WIRE_188.valid connect _WIRE_189.ready, _WIRE_188.ready connect _WIRE_189.valid, UInt<1>(0h0) wire _WIRE_190 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_190.bits.sink, UInt<3>(0h0) connect _WIRE_190.valid, UInt<1>(0h0) connect _WIRE_190.ready, UInt<1>(0h0) wire _WIRE_191 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_191.bits, _WIRE_190.bits connect _WIRE_191.valid, _WIRE_190.valid connect _WIRE_191.ready, _WIRE_190.ready connect _WIRE_191.valid, UInt<1>(0h0) inst nodeOut_a_q_16 of Queue2_TLBundleA_a32d64s5k3z4u_13 connect nodeOut_a_q_16.clock, clock connect nodeOut_a_q_16.reset, reset connect nodeOut_a_q_16.io.enq.valid, nodeIn_16.a.valid connect nodeOut_a_q_16.io.enq.bits.corrupt, nodeIn_16.a.bits.corrupt connect nodeOut_a_q_16.io.enq.bits.data, nodeIn_16.a.bits.data connect nodeOut_a_q_16.io.enq.bits.mask, nodeIn_16.a.bits.mask connect nodeOut_a_q_16.io.enq.bits.address, nodeIn_16.a.bits.address connect nodeOut_a_q_16.io.enq.bits.source, nodeIn_16.a.bits.source connect nodeOut_a_q_16.io.enq.bits.size, nodeIn_16.a.bits.size connect nodeOut_a_q_16.io.enq.bits.param, nodeIn_16.a.bits.param connect nodeOut_a_q_16.io.enq.bits.opcode, nodeIn_16.a.bits.opcode connect nodeIn_16.a.ready, nodeOut_a_q_16.io.enq.ready connect x1_nodeOut_15.a.bits, nodeOut_a_q_16.io.deq.bits connect x1_nodeOut_15.a.valid, nodeOut_a_q_16.io.deq.valid connect nodeOut_a_q_16.io.deq.ready, x1_nodeOut_15.a.ready inst nodeIn_d_q_16 of Queue2_TLBundleD_a32d64s5k3z4u_13 connect nodeIn_d_q_16.clock, clock connect nodeIn_d_q_16.reset, reset connect nodeIn_d_q_16.io.enq.valid, x1_nodeOut_15.d.valid connect nodeIn_d_q_16.io.enq.bits.corrupt, x1_nodeOut_15.d.bits.corrupt connect nodeIn_d_q_16.io.enq.bits.data, x1_nodeOut_15.d.bits.data connect nodeIn_d_q_16.io.enq.bits.denied, x1_nodeOut_15.d.bits.denied connect nodeIn_d_q_16.io.enq.bits.sink, x1_nodeOut_15.d.bits.sink connect nodeIn_d_q_16.io.enq.bits.source, x1_nodeOut_15.d.bits.source connect nodeIn_d_q_16.io.enq.bits.size, x1_nodeOut_15.d.bits.size connect nodeIn_d_q_16.io.enq.bits.param, x1_nodeOut_15.d.bits.param connect nodeIn_d_q_16.io.enq.bits.opcode, x1_nodeOut_15.d.bits.opcode connect x1_nodeOut_15.d.ready, nodeIn_d_q_16.io.enq.ready connect nodeIn_16.d.bits, nodeIn_d_q_16.io.deq.bits connect nodeIn_16.d.valid, nodeIn_d_q_16.io.deq.valid connect nodeIn_d_q_16.io.deq.ready, nodeIn_16.d.ready wire _WIRE_192 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_192.bits.corrupt, UInt<1>(0h0) connect _WIRE_192.bits.data, UInt<64>(0h0) connect _WIRE_192.bits.mask, UInt<8>(0h0) connect _WIRE_192.bits.address, UInt<32>(0h0) connect _WIRE_192.bits.source, UInt<5>(0h0) connect _WIRE_192.bits.size, UInt<4>(0h0) connect _WIRE_192.bits.param, UInt<2>(0h0) connect _WIRE_192.bits.opcode, UInt<3>(0h0) connect _WIRE_192.valid, UInt<1>(0h0) connect _WIRE_192.ready, UInt<1>(0h0) wire _WIRE_193 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_193.bits, _WIRE_192.bits connect _WIRE_193.valid, _WIRE_192.valid connect _WIRE_193.ready, _WIRE_192.ready connect _WIRE_193.valid, UInt<1>(0h0) wire _WIRE_194 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_194.bits.corrupt, UInt<1>(0h0) connect _WIRE_194.bits.data, UInt<64>(0h0) connect _WIRE_194.bits.address, UInt<32>(0h0) connect _WIRE_194.bits.source, UInt<5>(0h0) connect _WIRE_194.bits.size, UInt<4>(0h0) connect _WIRE_194.bits.param, UInt<3>(0h0) connect _WIRE_194.bits.opcode, UInt<3>(0h0) connect _WIRE_194.valid, UInt<1>(0h0) connect _WIRE_194.ready, UInt<1>(0h0) wire _WIRE_195 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_195.bits, _WIRE_194.bits connect _WIRE_195.valid, _WIRE_194.valid connect _WIRE_195.ready, _WIRE_194.ready connect _WIRE_195.ready, UInt<1>(0h1) wire _WIRE_196 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_196.bits.sink, UInt<3>(0h0) connect _WIRE_196.valid, UInt<1>(0h0) connect _WIRE_196.ready, UInt<1>(0h0) wire _WIRE_197 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_197.bits, _WIRE_196.bits connect _WIRE_197.valid, _WIRE_196.valid connect _WIRE_197.ready, _WIRE_196.ready connect _WIRE_197.ready, UInt<1>(0h1) wire _WIRE_198 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_198.bits.corrupt, UInt<1>(0h0) connect _WIRE_198.bits.data, UInt<64>(0h0) connect _WIRE_198.bits.mask, UInt<8>(0h0) connect _WIRE_198.bits.address, UInt<32>(0h0) connect _WIRE_198.bits.source, UInt<5>(0h0) connect _WIRE_198.bits.size, UInt<4>(0h0) connect _WIRE_198.bits.param, UInt<2>(0h0) connect _WIRE_198.bits.opcode, UInt<3>(0h0) connect _WIRE_198.valid, UInt<1>(0h0) connect _WIRE_198.ready, UInt<1>(0h0) wire _WIRE_199 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_199.bits, _WIRE_198.bits connect _WIRE_199.valid, _WIRE_198.valid connect _WIRE_199.ready, _WIRE_198.ready connect _WIRE_199.ready, UInt<1>(0h1) wire _WIRE_200 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_200.bits.corrupt, UInt<1>(0h0) connect _WIRE_200.bits.data, UInt<64>(0h0) connect _WIRE_200.bits.address, UInt<32>(0h0) connect _WIRE_200.bits.source, UInt<5>(0h0) connect _WIRE_200.bits.size, UInt<4>(0h0) connect _WIRE_200.bits.param, UInt<3>(0h0) connect _WIRE_200.bits.opcode, UInt<3>(0h0) connect _WIRE_200.valid, UInt<1>(0h0) connect _WIRE_200.ready, UInt<1>(0h0) wire _WIRE_201 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_201.bits, _WIRE_200.bits connect _WIRE_201.valid, _WIRE_200.valid connect _WIRE_201.ready, _WIRE_200.ready connect _WIRE_201.valid, UInt<1>(0h0) wire _WIRE_202 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_202.bits.sink, UInt<3>(0h0) connect _WIRE_202.valid, UInt<1>(0h0) connect _WIRE_202.ready, UInt<1>(0h0) wire _WIRE_203 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_203.bits, _WIRE_202.bits connect _WIRE_203.valid, _WIRE_202.valid connect _WIRE_203.ready, _WIRE_202.ready connect _WIRE_203.valid, UInt<1>(0h0) inst nodeOut_a_q_17 of Queue2_TLBundleA_a32d64s5k3z4u_14 connect nodeOut_a_q_17.clock, clock connect nodeOut_a_q_17.reset, reset connect nodeOut_a_q_17.io.enq.valid, nodeIn_17.a.valid connect nodeOut_a_q_17.io.enq.bits.corrupt, nodeIn_17.a.bits.corrupt connect nodeOut_a_q_17.io.enq.bits.data, nodeIn_17.a.bits.data connect nodeOut_a_q_17.io.enq.bits.mask, nodeIn_17.a.bits.mask connect nodeOut_a_q_17.io.enq.bits.address, nodeIn_17.a.bits.address connect nodeOut_a_q_17.io.enq.bits.source, nodeIn_17.a.bits.source connect nodeOut_a_q_17.io.enq.bits.size, nodeIn_17.a.bits.size connect nodeOut_a_q_17.io.enq.bits.param, nodeIn_17.a.bits.param connect nodeOut_a_q_17.io.enq.bits.opcode, nodeIn_17.a.bits.opcode connect nodeIn_17.a.ready, nodeOut_a_q_17.io.enq.ready connect x1_nodeOut_16.a.bits, nodeOut_a_q_17.io.deq.bits connect x1_nodeOut_16.a.valid, nodeOut_a_q_17.io.deq.valid connect nodeOut_a_q_17.io.deq.ready, x1_nodeOut_16.a.ready inst nodeIn_d_q_17 of Queue2_TLBundleD_a32d64s5k3z4u_14 connect nodeIn_d_q_17.clock, clock connect nodeIn_d_q_17.reset, reset connect nodeIn_d_q_17.io.enq.valid, x1_nodeOut_16.d.valid connect nodeIn_d_q_17.io.enq.bits.corrupt, x1_nodeOut_16.d.bits.corrupt connect nodeIn_d_q_17.io.enq.bits.data, x1_nodeOut_16.d.bits.data connect nodeIn_d_q_17.io.enq.bits.denied, x1_nodeOut_16.d.bits.denied connect nodeIn_d_q_17.io.enq.bits.sink, x1_nodeOut_16.d.bits.sink connect nodeIn_d_q_17.io.enq.bits.source, x1_nodeOut_16.d.bits.source connect nodeIn_d_q_17.io.enq.bits.size, x1_nodeOut_16.d.bits.size connect nodeIn_d_q_17.io.enq.bits.param, x1_nodeOut_16.d.bits.param connect nodeIn_d_q_17.io.enq.bits.opcode, x1_nodeOut_16.d.bits.opcode connect x1_nodeOut_16.d.ready, nodeIn_d_q_17.io.enq.ready connect nodeIn_17.d.bits, nodeIn_d_q_17.io.deq.bits connect nodeIn_17.d.valid, nodeIn_d_q_17.io.deq.valid connect nodeIn_d_q_17.io.deq.ready, nodeIn_17.d.ready wire _WIRE_204 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_204.bits.corrupt, UInt<1>(0h0) connect _WIRE_204.bits.data, UInt<64>(0h0) connect _WIRE_204.bits.mask, UInt<8>(0h0) connect _WIRE_204.bits.address, UInt<32>(0h0) connect _WIRE_204.bits.source, UInt<5>(0h0) connect _WIRE_204.bits.size, UInt<4>(0h0) connect _WIRE_204.bits.param, UInt<2>(0h0) connect _WIRE_204.bits.opcode, UInt<3>(0h0) connect _WIRE_204.valid, UInt<1>(0h0) connect _WIRE_204.ready, UInt<1>(0h0) wire _WIRE_205 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_205.bits, _WIRE_204.bits connect _WIRE_205.valid, _WIRE_204.valid connect _WIRE_205.ready, _WIRE_204.ready connect _WIRE_205.valid, UInt<1>(0h0) wire _WIRE_206 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_206.bits.corrupt, UInt<1>(0h0) connect _WIRE_206.bits.data, UInt<64>(0h0) connect _WIRE_206.bits.address, UInt<32>(0h0) connect _WIRE_206.bits.source, UInt<5>(0h0) connect _WIRE_206.bits.size, UInt<4>(0h0) connect _WIRE_206.bits.param, UInt<3>(0h0) connect _WIRE_206.bits.opcode, UInt<3>(0h0) connect _WIRE_206.valid, UInt<1>(0h0) connect _WIRE_206.ready, UInt<1>(0h0) wire _WIRE_207 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_207.bits, _WIRE_206.bits connect _WIRE_207.valid, _WIRE_206.valid connect _WIRE_207.ready, _WIRE_206.ready connect _WIRE_207.ready, UInt<1>(0h1) wire _WIRE_208 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_208.bits.sink, UInt<3>(0h0) connect _WIRE_208.valid, UInt<1>(0h0) connect _WIRE_208.ready, UInt<1>(0h0) wire _WIRE_209 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_209.bits, _WIRE_208.bits connect _WIRE_209.valid, _WIRE_208.valid connect _WIRE_209.ready, _WIRE_208.ready connect _WIRE_209.ready, UInt<1>(0h1) wire _WIRE_210 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_210.bits.corrupt, UInt<1>(0h0) connect _WIRE_210.bits.data, UInt<64>(0h0) connect _WIRE_210.bits.mask, UInt<8>(0h0) connect _WIRE_210.bits.address, UInt<32>(0h0) connect _WIRE_210.bits.source, UInt<5>(0h0) connect _WIRE_210.bits.size, UInt<4>(0h0) connect _WIRE_210.bits.param, UInt<2>(0h0) connect _WIRE_210.bits.opcode, UInt<3>(0h0) connect _WIRE_210.valid, UInt<1>(0h0) connect _WIRE_210.ready, UInt<1>(0h0) wire _WIRE_211 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_211.bits, _WIRE_210.bits connect _WIRE_211.valid, _WIRE_210.valid connect _WIRE_211.ready, _WIRE_210.ready connect _WIRE_211.ready, UInt<1>(0h1) wire _WIRE_212 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_212.bits.corrupt, UInt<1>(0h0) connect _WIRE_212.bits.data, UInt<64>(0h0) connect _WIRE_212.bits.address, UInt<32>(0h0) connect _WIRE_212.bits.source, UInt<5>(0h0) connect _WIRE_212.bits.size, UInt<4>(0h0) connect _WIRE_212.bits.param, UInt<3>(0h0) connect _WIRE_212.bits.opcode, UInt<3>(0h0) connect _WIRE_212.valid, UInt<1>(0h0) connect _WIRE_212.ready, UInt<1>(0h0) wire _WIRE_213 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_213.bits, _WIRE_212.bits connect _WIRE_213.valid, _WIRE_212.valid connect _WIRE_213.ready, _WIRE_212.ready connect _WIRE_213.valid, UInt<1>(0h0) wire _WIRE_214 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_214.bits.sink, UInt<3>(0h0) connect _WIRE_214.valid, UInt<1>(0h0) connect _WIRE_214.ready, UInt<1>(0h0) wire _WIRE_215 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_215.bits, _WIRE_214.bits connect _WIRE_215.valid, _WIRE_214.valid connect _WIRE_215.ready, _WIRE_214.ready connect _WIRE_215.valid, UInt<1>(0h0) inst nodeOut_a_q_18 of Queue2_TLBundleA_a32d64s2k3z4c connect nodeOut_a_q_18.clock, clock connect nodeOut_a_q_18.reset, reset connect nodeOut_a_q_18.io.enq.valid, nodeIn_18.a.valid connect nodeOut_a_q_18.io.enq.bits.corrupt, nodeIn_18.a.bits.corrupt connect nodeOut_a_q_18.io.enq.bits.data, nodeIn_18.a.bits.data connect nodeOut_a_q_18.io.enq.bits.mask, nodeIn_18.a.bits.mask connect nodeOut_a_q_18.io.enq.bits.address, nodeIn_18.a.bits.address connect nodeOut_a_q_18.io.enq.bits.source, nodeIn_18.a.bits.source connect nodeOut_a_q_18.io.enq.bits.size, nodeIn_18.a.bits.size connect nodeOut_a_q_18.io.enq.bits.param, nodeIn_18.a.bits.param connect nodeOut_a_q_18.io.enq.bits.opcode, nodeIn_18.a.bits.opcode connect nodeIn_18.a.ready, nodeOut_a_q_18.io.enq.ready connect x1_nodeOut_17.a.bits, nodeOut_a_q_18.io.deq.bits connect x1_nodeOut_17.a.valid, nodeOut_a_q_18.io.deq.valid connect nodeOut_a_q_18.io.deq.ready, x1_nodeOut_17.a.ready inst nodeIn_d_q_18 of Queue2_TLBundleD_a32d64s2k3z4c connect nodeIn_d_q_18.clock, clock connect nodeIn_d_q_18.reset, reset connect nodeIn_d_q_18.io.enq.valid, x1_nodeOut_17.d.valid connect nodeIn_d_q_18.io.enq.bits.corrupt, x1_nodeOut_17.d.bits.corrupt connect nodeIn_d_q_18.io.enq.bits.data, x1_nodeOut_17.d.bits.data connect nodeIn_d_q_18.io.enq.bits.denied, x1_nodeOut_17.d.bits.denied connect nodeIn_d_q_18.io.enq.bits.sink, x1_nodeOut_17.d.bits.sink connect nodeIn_d_q_18.io.enq.bits.source, x1_nodeOut_17.d.bits.source connect nodeIn_d_q_18.io.enq.bits.size, x1_nodeOut_17.d.bits.size connect nodeIn_d_q_18.io.enq.bits.param, x1_nodeOut_17.d.bits.param connect nodeIn_d_q_18.io.enq.bits.opcode, x1_nodeOut_17.d.bits.opcode connect x1_nodeOut_17.d.ready, nodeIn_d_q_18.io.enq.ready connect nodeIn_18.d.bits, nodeIn_d_q_18.io.deq.bits connect nodeIn_18.d.valid, nodeIn_d_q_18.io.deq.valid connect nodeIn_d_q_18.io.deq.ready, nodeIn_18.d.ready inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c connect nodeIn_b_q.clock, clock connect nodeIn_b_q.reset, reset connect nodeIn_b_q.io.enq.valid, x1_nodeOut_17.b.valid connect nodeIn_b_q.io.enq.bits.corrupt, x1_nodeOut_17.b.bits.corrupt connect nodeIn_b_q.io.enq.bits.data, x1_nodeOut_17.b.bits.data connect nodeIn_b_q.io.enq.bits.mask, x1_nodeOut_17.b.bits.mask connect nodeIn_b_q.io.enq.bits.address, x1_nodeOut_17.b.bits.address connect nodeIn_b_q.io.enq.bits.source, x1_nodeOut_17.b.bits.source connect nodeIn_b_q.io.enq.bits.size, x1_nodeOut_17.b.bits.size connect nodeIn_b_q.io.enq.bits.param, x1_nodeOut_17.b.bits.param connect nodeIn_b_q.io.enq.bits.opcode, x1_nodeOut_17.b.bits.opcode connect x1_nodeOut_17.b.ready, nodeIn_b_q.io.enq.ready connect nodeIn_18.b.bits, nodeIn_b_q.io.deq.bits connect nodeIn_18.b.valid, nodeIn_b_q.io.deq.valid connect nodeIn_b_q.io.deq.ready, nodeIn_18.b.ready inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c connect nodeOut_c_q.clock, clock connect nodeOut_c_q.reset, reset connect nodeOut_c_q.io.enq.valid, nodeIn_18.c.valid connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn_18.c.bits.corrupt connect nodeOut_c_q.io.enq.bits.data, nodeIn_18.c.bits.data connect nodeOut_c_q.io.enq.bits.address, nodeIn_18.c.bits.address connect nodeOut_c_q.io.enq.bits.source, nodeIn_18.c.bits.source connect nodeOut_c_q.io.enq.bits.size, nodeIn_18.c.bits.size connect nodeOut_c_q.io.enq.bits.param, nodeIn_18.c.bits.param connect nodeOut_c_q.io.enq.bits.opcode, nodeIn_18.c.bits.opcode connect nodeIn_18.c.ready, nodeOut_c_q.io.enq.ready connect x1_nodeOut_17.c.bits, nodeOut_c_q.io.deq.bits connect x1_nodeOut_17.c.valid, nodeOut_c_q.io.deq.valid connect nodeOut_c_q.io.deq.ready, x1_nodeOut_17.c.ready inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c connect nodeOut_e_q.clock, clock connect nodeOut_e_q.reset, reset connect nodeOut_e_q.io.enq.valid, nodeIn_18.e.valid connect nodeOut_e_q.io.enq.bits.sink, nodeIn_18.e.bits.sink connect nodeIn_18.e.ready, nodeOut_e_q.io.enq.ready connect x1_nodeOut_17.e.bits, nodeOut_e_q.io.deq.bits connect x1_nodeOut_17.e.valid, nodeOut_e_q.io.deq.valid connect nodeOut_e_q.io.deq.ready, x1_nodeOut_17.e.ready
module TLBuffer_a32d64s2k3z4u_1( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_18_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_18_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_18_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_18_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_18_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_18_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_18_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_18_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_18_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_18_b_ready, // @[LazyModuleImp.scala:107:25] output auto_in_18_b_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_18_b_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_18_b_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_18_b_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_18_b_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_in_18_b_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_in_18_b_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_18_b_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_18_b_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_18_c_ready, // @[LazyModuleImp.scala:107:25] input auto_in_18_c_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_18_c_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_18_c_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_18_c_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_18_c_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_18_c_bits_address, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_18_c_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_18_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_18_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_18_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_18_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_18_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_18_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_18_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_18_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_18_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_18_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_18_e_ready, // @[LazyModuleImp.scala:107:25] input auto_in_18_e_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_18_e_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_17_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_17_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_17_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_17_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_17_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_17_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_17_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_17_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_17_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_17_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_17_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_17_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_17_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_17_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_17_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_17_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_16_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_16_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_16_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_16_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_16_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_16_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_16_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_16_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_16_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_16_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_16_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_16_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_16_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_16_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_16_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_16_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_15_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_15_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_15_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_15_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_15_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_15_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_15_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_15_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_15_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_15_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_15_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_15_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_15_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_15_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_15_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_15_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_14_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_14_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_14_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_14_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_14_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_14_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_14_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_14_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_14_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_14_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_14_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_14_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_14_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_14_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_14_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_14_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_13_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_13_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_13_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_13_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_13_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_13_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_13_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_13_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_13_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_13_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_13_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_13_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_13_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_13_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_13_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_13_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_12_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_12_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_12_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_12_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_12_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_12_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_12_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_12_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_12_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_12_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_12_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_12_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_12_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_12_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_12_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_12_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_11_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_11_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_11_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_11_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_11_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_11_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_11_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_11_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_11_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_11_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_11_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_11_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_11_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_11_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_11_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_11_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_10_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_10_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_10_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_10_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_10_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_10_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_10_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_10_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_10_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_10_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_10_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_10_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_10_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_10_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_10_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_10_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_9_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_9_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_9_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_9_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_9_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_9_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_9_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_9_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_9_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_9_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_9_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_9_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_9_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_9_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_9_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_9_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_8_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_8_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_8_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_8_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_8_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_8_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_8_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_8_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_8_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_8_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_8_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_8_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_8_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_8_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_8_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_8_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_7_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_7_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_7_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_7_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_7_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_7_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_7_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_7_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_7_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_7_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_7_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_7_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_7_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_6_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_6_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_6_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_6_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_6_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_6_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_6_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_6_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_6_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_6_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_6_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_6_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_6_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_6_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_6_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_5_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_5_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_5_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_5_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_5_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_5_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_5_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_5_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_5_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_5_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_5_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_5_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_5_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_4_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_4_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_4_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_4_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_4_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_4_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_4_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_4_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_4_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_4_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_4_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_4_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_4_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_3_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_3_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_3_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_2_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_2_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_2_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_in_0_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_0_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_18_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_18_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_18_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_18_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_18_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_18_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_18_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_18_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_18_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_18_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_18_b_ready, // @[LazyModuleImp.scala:107:25] input auto_out_18_b_valid, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_18_b_bits_param, // @[LazyModuleImp.scala:107:25] input [31:0] auto_out_18_b_bits_address, // @[LazyModuleImp.scala:107:25] input auto_out_18_c_ready, // @[LazyModuleImp.scala:107:25] output auto_out_18_c_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_18_c_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_18_c_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_18_c_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_18_c_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_18_c_bits_address, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_18_c_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_18_c_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_18_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_18_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_18_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_18_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_18_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_18_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_18_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_18_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_18_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_18_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_18_e_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_18_e_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_17_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_17_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_17_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_17_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_17_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_17_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_17_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_17_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_17_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_17_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_17_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_17_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_17_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_17_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_17_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_17_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_17_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_17_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_17_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_17_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_16_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_16_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_16_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_16_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_16_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_16_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_16_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_16_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_16_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_16_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_16_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_16_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_16_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_16_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_16_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_16_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_16_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_16_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_16_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_16_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_15_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_15_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_15_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_15_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_15_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_15_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_15_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_15_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_15_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_15_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_15_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_15_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_15_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_15_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_15_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_15_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_15_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_15_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_15_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_15_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_14_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_14_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_14_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_14_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_14_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_14_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_14_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_14_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_14_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_14_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_14_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_14_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_14_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_14_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_14_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_14_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_14_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_14_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_14_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_14_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_13_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_13_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_13_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_13_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_13_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_13_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_13_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_13_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_13_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_13_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_13_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_13_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_13_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_13_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_13_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_13_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_13_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_13_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_13_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_13_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_12_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_12_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_12_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_12_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_12_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_12_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_12_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_12_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_12_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_12_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_12_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_12_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_12_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_12_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_12_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_12_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_12_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_12_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_12_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_12_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_11_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_11_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_11_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_11_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_11_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_11_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_11_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_11_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_11_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_11_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_11_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_11_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_11_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_11_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_11_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_11_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_11_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_11_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_11_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_11_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_10_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_10_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_10_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_10_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_10_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_10_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_10_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_10_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_10_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_10_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_10_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_10_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_10_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_10_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_10_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_10_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_10_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_10_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_10_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_10_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_9_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_9_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_9_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_9_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_9_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_9_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_9_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_9_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_9_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_9_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_9_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_9_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_9_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_9_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_9_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_9_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_9_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_9_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_9_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_9_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_8_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_8_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_8_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_8_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_8_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_8_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_8_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_8_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_8_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_8_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_8_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_8_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_8_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_8_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_8_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_8_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_8_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_8_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_8_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_8_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_7_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_7_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_7_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_7_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_7_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_7_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_7_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_7_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_7_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_7_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_7_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_7_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_7_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_7_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_7_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_7_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_7_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_7_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_7_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_7_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_6_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_6_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_6_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_6_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_6_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_6_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_6_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_6_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_6_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_6_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_6_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_6_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_6_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_6_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_6_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_6_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_6_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_6_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_6_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_6_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_5_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_5_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_5_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_5_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_5_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_5_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_5_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_5_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_5_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_5_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_5_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_5_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_5_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_5_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_5_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_5_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_5_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_5_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_5_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_5_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_4_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_4_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_4_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_4_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_4_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_4_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_4_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_4_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_4_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_4_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_4_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_4_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_4_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_4_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_4_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_4_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_4_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_4_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_4_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_4_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_3_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_3_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_3_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_3_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_3_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_3_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_3_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_3_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_3_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_3_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_3_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_3_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_3_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_3_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_2_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_2_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_2_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_2_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_out_2_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_2_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_2_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_2_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_2_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_2_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_2_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_2_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_2_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_2_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_1_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_1_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_0_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25] output [1:0] auto_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_0_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_0_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire auto_in_18_a_valid_0 = auto_in_18_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_a_bits_opcode_0 = auto_in_18_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_a_bits_param_0 = auto_in_18_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_18_a_bits_size_0 = auto_in_18_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_18_a_bits_source_0 = auto_in_18_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_18_a_bits_address_0 = auto_in_18_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_18_a_bits_mask_0 = auto_in_18_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_18_a_bits_data_0 = auto_in_18_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_18_b_ready_0 = auto_in_18_b_ready; // @[Buffer.scala:40:9] wire auto_in_18_c_valid_0 = auto_in_18_c_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_c_bits_opcode_0 = auto_in_18_c_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_c_bits_param_0 = auto_in_18_c_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_18_c_bits_size_0 = auto_in_18_c_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_18_c_bits_source_0 = auto_in_18_c_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_18_c_bits_address_0 = auto_in_18_c_bits_address; // @[Buffer.scala:40:9] wire [63:0] auto_in_18_c_bits_data_0 = auto_in_18_c_bits_data; // @[Buffer.scala:40:9] wire auto_in_18_d_ready_0 = auto_in_18_d_ready; // @[Buffer.scala:40:9] wire auto_in_18_e_valid_0 = auto_in_18_e_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_e_bits_sink_0 = auto_in_18_e_bits_sink; // @[Buffer.scala:40:9] wire auto_in_17_a_valid_0 = auto_in_17_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_17_a_bits_opcode_0 = auto_in_17_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_17_a_bits_param_0 = auto_in_17_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_17_a_bits_size_0 = auto_in_17_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_17_a_bits_source_0 = auto_in_17_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_17_a_bits_address_0 = auto_in_17_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_17_a_bits_mask_0 = auto_in_17_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_17_a_bits_data_0 = auto_in_17_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_17_a_bits_corrupt_0 = auto_in_17_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_17_d_ready_0 = auto_in_17_d_ready; // @[Buffer.scala:40:9] wire auto_in_16_a_valid_0 = auto_in_16_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_16_a_bits_opcode_0 = auto_in_16_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_16_a_bits_param_0 = auto_in_16_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_16_a_bits_size_0 = auto_in_16_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_16_a_bits_source_0 = auto_in_16_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_16_a_bits_address_0 = auto_in_16_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_16_a_bits_mask_0 = auto_in_16_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_16_a_bits_data_0 = auto_in_16_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_16_a_bits_corrupt_0 = auto_in_16_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_16_d_ready_0 = auto_in_16_d_ready; // @[Buffer.scala:40:9] wire auto_in_15_a_valid_0 = auto_in_15_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_15_a_bits_opcode_0 = auto_in_15_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_15_a_bits_param_0 = auto_in_15_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_15_a_bits_size_0 = auto_in_15_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_15_a_bits_source_0 = auto_in_15_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_15_a_bits_address_0 = auto_in_15_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_15_a_bits_mask_0 = auto_in_15_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_15_a_bits_data_0 = auto_in_15_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_15_a_bits_corrupt_0 = auto_in_15_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_15_d_ready_0 = auto_in_15_d_ready; // @[Buffer.scala:40:9] wire auto_in_14_a_valid_0 = auto_in_14_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_14_a_bits_opcode_0 = auto_in_14_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_14_a_bits_param_0 = auto_in_14_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_14_a_bits_size_0 = auto_in_14_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_14_a_bits_source_0 = auto_in_14_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_14_a_bits_address_0 = auto_in_14_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_14_a_bits_mask_0 = auto_in_14_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_14_a_bits_data_0 = auto_in_14_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_14_a_bits_corrupt_0 = auto_in_14_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_14_d_ready_0 = auto_in_14_d_ready; // @[Buffer.scala:40:9] wire auto_in_13_a_valid_0 = auto_in_13_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_13_a_bits_opcode_0 = auto_in_13_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_13_a_bits_param_0 = auto_in_13_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_13_a_bits_size_0 = auto_in_13_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_13_a_bits_source_0 = auto_in_13_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_13_a_bits_address_0 = auto_in_13_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_13_a_bits_mask_0 = auto_in_13_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_13_a_bits_data_0 = auto_in_13_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_13_a_bits_corrupt_0 = auto_in_13_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_13_d_ready_0 = auto_in_13_d_ready; // @[Buffer.scala:40:9] wire auto_in_12_a_valid_0 = auto_in_12_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_12_a_bits_opcode_0 = auto_in_12_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_12_a_bits_param_0 = auto_in_12_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_12_a_bits_size_0 = auto_in_12_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_12_a_bits_source_0 = auto_in_12_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_12_a_bits_address_0 = auto_in_12_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_12_a_bits_mask_0 = auto_in_12_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_12_a_bits_data_0 = auto_in_12_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_12_a_bits_corrupt_0 = auto_in_12_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_12_d_ready_0 = auto_in_12_d_ready; // @[Buffer.scala:40:9] wire auto_in_11_a_valid_0 = auto_in_11_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_11_a_bits_opcode_0 = auto_in_11_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_11_a_bits_param_0 = auto_in_11_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_11_a_bits_size_0 = auto_in_11_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_11_a_bits_source_0 = auto_in_11_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_11_a_bits_address_0 = auto_in_11_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_11_a_bits_mask_0 = auto_in_11_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_11_a_bits_data_0 = auto_in_11_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_11_a_bits_corrupt_0 = auto_in_11_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_11_d_ready_0 = auto_in_11_d_ready; // @[Buffer.scala:40:9] wire auto_in_10_a_valid_0 = auto_in_10_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_10_a_bits_opcode_0 = auto_in_10_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_10_a_bits_param_0 = auto_in_10_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_10_a_bits_size_0 = auto_in_10_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_10_a_bits_source_0 = auto_in_10_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_10_a_bits_address_0 = auto_in_10_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_10_a_bits_mask_0 = auto_in_10_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_10_a_bits_data_0 = auto_in_10_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_10_a_bits_corrupt_0 = auto_in_10_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_10_d_ready_0 = auto_in_10_d_ready; // @[Buffer.scala:40:9] wire auto_in_9_a_valid_0 = auto_in_9_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_9_a_bits_opcode_0 = auto_in_9_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_9_a_bits_param_0 = auto_in_9_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_9_a_bits_size_0 = auto_in_9_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_9_a_bits_source_0 = auto_in_9_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_9_a_bits_address_0 = auto_in_9_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_9_a_bits_mask_0 = auto_in_9_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_9_a_bits_data_0 = auto_in_9_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_9_a_bits_corrupt_0 = auto_in_9_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_9_d_ready_0 = auto_in_9_d_ready; // @[Buffer.scala:40:9] wire auto_in_8_a_valid_0 = auto_in_8_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_8_a_bits_opcode_0 = auto_in_8_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_8_a_bits_param_0 = auto_in_8_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_8_a_bits_size_0 = auto_in_8_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_8_a_bits_source_0 = auto_in_8_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_8_a_bits_address_0 = auto_in_8_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_8_a_bits_mask_0 = auto_in_8_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_8_a_bits_data_0 = auto_in_8_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_8_a_bits_corrupt_0 = auto_in_8_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_8_d_ready_0 = auto_in_8_d_ready; // @[Buffer.scala:40:9] wire auto_in_7_a_valid_0 = auto_in_7_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_7_a_bits_opcode_0 = auto_in_7_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_7_a_bits_param_0 = auto_in_7_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_7_a_bits_size_0 = auto_in_7_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_7_a_bits_source_0 = auto_in_7_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_7_a_bits_address_0 = auto_in_7_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_7_a_bits_mask_0 = auto_in_7_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_7_a_bits_data_0 = auto_in_7_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_7_a_bits_corrupt_0 = auto_in_7_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_7_d_ready_0 = auto_in_7_d_ready; // @[Buffer.scala:40:9] wire auto_in_6_a_valid_0 = auto_in_6_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_6_a_bits_opcode_0 = auto_in_6_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_6_a_bits_param_0 = auto_in_6_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_6_a_bits_size_0 = auto_in_6_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_6_a_bits_source_0 = auto_in_6_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_6_a_bits_address_0 = auto_in_6_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_6_a_bits_mask_0 = auto_in_6_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_6_a_bits_data_0 = auto_in_6_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_6_a_bits_corrupt_0 = auto_in_6_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_6_d_ready_0 = auto_in_6_d_ready; // @[Buffer.scala:40:9] wire auto_in_5_a_valid_0 = auto_in_5_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_5_a_bits_opcode_0 = auto_in_5_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_5_a_bits_param_0 = auto_in_5_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_5_a_bits_size_0 = auto_in_5_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_5_a_bits_source_0 = auto_in_5_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_5_a_bits_address_0 = auto_in_5_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_5_a_bits_mask_0 = auto_in_5_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_5_a_bits_data_0 = auto_in_5_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_5_a_bits_corrupt_0 = auto_in_5_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_5_d_ready_0 = auto_in_5_d_ready; // @[Buffer.scala:40:9] wire auto_in_4_a_valid_0 = auto_in_4_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_4_a_bits_opcode_0 = auto_in_4_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_4_a_bits_param_0 = auto_in_4_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_4_a_bits_size_0 = auto_in_4_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_4_a_bits_source_0 = auto_in_4_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_4_a_bits_address_0 = auto_in_4_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_4_a_bits_mask_0 = auto_in_4_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_4_a_bits_data_0 = auto_in_4_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_4_a_bits_corrupt_0 = auto_in_4_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_4_d_ready_0 = auto_in_4_d_ready; // @[Buffer.scala:40:9] wire auto_in_3_a_valid_0 = auto_in_3_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_3_a_bits_opcode_0 = auto_in_3_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_3_a_bits_param_0 = auto_in_3_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_3_a_bits_size_0 = auto_in_3_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_3_a_bits_source_0 = auto_in_3_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_3_a_bits_address_0 = auto_in_3_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_3_a_bits_mask_0 = auto_in_3_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_3_a_bits_data_0 = auto_in_3_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_3_a_bits_corrupt_0 = auto_in_3_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_3_d_ready_0 = auto_in_3_d_ready; // @[Buffer.scala:40:9] wire auto_in_2_a_valid_0 = auto_in_2_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_2_a_bits_opcode_0 = auto_in_2_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_2_a_bits_param_0 = auto_in_2_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_2_a_bits_size_0 = auto_in_2_a_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_in_2_a_bits_source_0 = auto_in_2_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_2_a_bits_address_0 = auto_in_2_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_2_a_bits_mask_0 = auto_in_2_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_2_a_bits_data_0 = auto_in_2_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_2_a_bits_corrupt_0 = auto_in_2_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_2_d_ready_0 = auto_in_2_d_ready; // @[Buffer.scala:40:9] wire auto_in_1_a_valid_0 = auto_in_1_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_a_bits_opcode_0 = auto_in_1_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_a_bits_param_0 = auto_in_1_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_1_a_bits_size_0 = auto_in_1_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_a_bits_source_0 = auto_in_1_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_1_a_bits_address_0 = auto_in_1_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_1_a_bits_mask_0 = auto_in_1_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_1_a_bits_data_0 = auto_in_1_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_1_a_bits_corrupt_0 = auto_in_1_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_1_d_ready_0 = auto_in_1_d_ready; // @[Buffer.scala:40:9] wire auto_in_0_a_valid_0 = auto_in_0_a_valid; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_a_bits_opcode_0 = auto_in_0_a_bits_opcode; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_a_bits_param_0 = auto_in_0_a_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_in_0_a_bits_size_0 = auto_in_0_a_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_in_0_a_bits_source_0 = auto_in_0_a_bits_source; // @[Buffer.scala:40:9] wire [31:0] auto_in_0_a_bits_address_0 = auto_in_0_a_bits_address; // @[Buffer.scala:40:9] wire [7:0] auto_in_0_a_bits_mask_0 = auto_in_0_a_bits_mask; // @[Buffer.scala:40:9] wire [63:0] auto_in_0_a_bits_data_0 = auto_in_0_a_bits_data; // @[Buffer.scala:40:9] wire auto_in_0_a_bits_corrupt_0 = auto_in_0_a_bits_corrupt; // @[Buffer.scala:40:9] wire auto_in_0_d_ready_0 = auto_in_0_d_ready; // @[Buffer.scala:40:9] wire auto_out_18_a_ready_0 = auto_out_18_a_ready; // @[Buffer.scala:40:9] wire auto_out_18_b_valid_0 = auto_out_18_b_valid; // @[Buffer.scala:40:9] wire [1:0] auto_out_18_b_bits_param_0 = auto_out_18_b_bits_param; // @[Buffer.scala:40:9] wire [31:0] auto_out_18_b_bits_address_0 = auto_out_18_b_bits_address; // @[Buffer.scala:40:9] wire auto_out_18_c_ready_0 = auto_out_18_c_ready; // @[Buffer.scala:40:9] wire auto_out_18_d_valid_0 = auto_out_18_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_d_bits_opcode_0 = auto_out_18_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_18_d_bits_param_0 = auto_out_18_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_18_d_bits_size_0 = auto_out_18_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_18_d_bits_source_0 = auto_out_18_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_d_bits_sink_0 = auto_out_18_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_18_d_bits_denied_0 = auto_out_18_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_18_d_bits_data_0 = auto_out_18_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_18_d_bits_corrupt_0 = auto_out_18_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_17_a_ready_0 = auto_out_17_a_ready; // @[Buffer.scala:40:9] wire auto_out_17_d_valid_0 = auto_out_17_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_17_d_bits_opcode_0 = auto_out_17_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_17_d_bits_param_0 = auto_out_17_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_17_d_bits_size_0 = auto_out_17_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_17_d_bits_source_0 = auto_out_17_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_17_d_bits_sink_0 = auto_out_17_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_17_d_bits_denied_0 = auto_out_17_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_17_d_bits_data_0 = auto_out_17_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_17_d_bits_corrupt_0 = auto_out_17_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_16_a_ready_0 = auto_out_16_a_ready; // @[Buffer.scala:40:9] wire auto_out_16_d_valid_0 = auto_out_16_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_16_d_bits_opcode_0 = auto_out_16_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_16_d_bits_param_0 = auto_out_16_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_16_d_bits_size_0 = auto_out_16_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_16_d_bits_source_0 = auto_out_16_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_16_d_bits_sink_0 = auto_out_16_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_16_d_bits_denied_0 = auto_out_16_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_16_d_bits_data_0 = auto_out_16_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_16_d_bits_corrupt_0 = auto_out_16_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_15_a_ready_0 = auto_out_15_a_ready; // @[Buffer.scala:40:9] wire auto_out_15_d_valid_0 = auto_out_15_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_15_d_bits_opcode_0 = auto_out_15_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_15_d_bits_param_0 = auto_out_15_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_15_d_bits_size_0 = auto_out_15_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_15_d_bits_source_0 = auto_out_15_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_15_d_bits_sink_0 = auto_out_15_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_15_d_bits_denied_0 = auto_out_15_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_15_d_bits_data_0 = auto_out_15_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_15_d_bits_corrupt_0 = auto_out_15_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_14_a_ready_0 = auto_out_14_a_ready; // @[Buffer.scala:40:9] wire auto_out_14_d_valid_0 = auto_out_14_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_14_d_bits_opcode_0 = auto_out_14_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_14_d_bits_param_0 = auto_out_14_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_14_d_bits_size_0 = auto_out_14_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_14_d_bits_source_0 = auto_out_14_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_14_d_bits_sink_0 = auto_out_14_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_14_d_bits_denied_0 = auto_out_14_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_14_d_bits_data_0 = auto_out_14_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_14_d_bits_corrupt_0 = auto_out_14_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_13_a_ready_0 = auto_out_13_a_ready; // @[Buffer.scala:40:9] wire auto_out_13_d_valid_0 = auto_out_13_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_13_d_bits_opcode_0 = auto_out_13_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_13_d_bits_param_0 = auto_out_13_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_13_d_bits_size_0 = auto_out_13_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_13_d_bits_source_0 = auto_out_13_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_13_d_bits_sink_0 = auto_out_13_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_13_d_bits_denied_0 = auto_out_13_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_13_d_bits_data_0 = auto_out_13_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_13_d_bits_corrupt_0 = auto_out_13_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_12_a_ready_0 = auto_out_12_a_ready; // @[Buffer.scala:40:9] wire auto_out_12_d_valid_0 = auto_out_12_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_12_d_bits_opcode_0 = auto_out_12_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_12_d_bits_param_0 = auto_out_12_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_12_d_bits_size_0 = auto_out_12_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_12_d_bits_source_0 = auto_out_12_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_12_d_bits_sink_0 = auto_out_12_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_12_d_bits_denied_0 = auto_out_12_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_12_d_bits_data_0 = auto_out_12_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_12_d_bits_corrupt_0 = auto_out_12_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_11_a_ready_0 = auto_out_11_a_ready; // @[Buffer.scala:40:9] wire auto_out_11_d_valid_0 = auto_out_11_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_11_d_bits_opcode_0 = auto_out_11_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_11_d_bits_param_0 = auto_out_11_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_11_d_bits_size_0 = auto_out_11_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_11_d_bits_source_0 = auto_out_11_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_11_d_bits_sink_0 = auto_out_11_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_11_d_bits_denied_0 = auto_out_11_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_11_d_bits_data_0 = auto_out_11_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_11_d_bits_corrupt_0 = auto_out_11_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_10_a_ready_0 = auto_out_10_a_ready; // @[Buffer.scala:40:9] wire auto_out_10_d_valid_0 = auto_out_10_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_10_d_bits_opcode_0 = auto_out_10_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_10_d_bits_param_0 = auto_out_10_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_10_d_bits_size_0 = auto_out_10_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_10_d_bits_source_0 = auto_out_10_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_10_d_bits_sink_0 = auto_out_10_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_10_d_bits_denied_0 = auto_out_10_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_10_d_bits_data_0 = auto_out_10_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_10_d_bits_corrupt_0 = auto_out_10_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_9_a_ready_0 = auto_out_9_a_ready; // @[Buffer.scala:40:9] wire auto_out_9_d_valid_0 = auto_out_9_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_9_d_bits_opcode_0 = auto_out_9_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_9_d_bits_param_0 = auto_out_9_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_9_d_bits_size_0 = auto_out_9_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_9_d_bits_source_0 = auto_out_9_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_9_d_bits_sink_0 = auto_out_9_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_9_d_bits_denied_0 = auto_out_9_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_9_d_bits_data_0 = auto_out_9_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_9_d_bits_corrupt_0 = auto_out_9_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_8_a_ready_0 = auto_out_8_a_ready; // @[Buffer.scala:40:9] wire auto_out_8_d_valid_0 = auto_out_8_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_8_d_bits_opcode_0 = auto_out_8_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_8_d_bits_param_0 = auto_out_8_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_8_d_bits_size_0 = auto_out_8_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_8_d_bits_source_0 = auto_out_8_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_8_d_bits_sink_0 = auto_out_8_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_8_d_bits_denied_0 = auto_out_8_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_8_d_bits_data_0 = auto_out_8_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_8_d_bits_corrupt_0 = auto_out_8_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_7_a_ready_0 = auto_out_7_a_ready; // @[Buffer.scala:40:9] wire auto_out_7_d_valid_0 = auto_out_7_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_7_d_bits_opcode_0 = auto_out_7_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_7_d_bits_param_0 = auto_out_7_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_7_d_bits_size_0 = auto_out_7_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_7_d_bits_source_0 = auto_out_7_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_7_d_bits_sink_0 = auto_out_7_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_7_d_bits_denied_0 = auto_out_7_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_7_d_bits_data_0 = auto_out_7_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_7_d_bits_corrupt_0 = auto_out_7_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_6_a_ready_0 = auto_out_6_a_ready; // @[Buffer.scala:40:9] wire auto_out_6_d_valid_0 = auto_out_6_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_6_d_bits_opcode_0 = auto_out_6_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_6_d_bits_param_0 = auto_out_6_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_6_d_bits_size_0 = auto_out_6_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_6_d_bits_source_0 = auto_out_6_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_6_d_bits_sink_0 = auto_out_6_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_6_d_bits_denied_0 = auto_out_6_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_6_d_bits_data_0 = auto_out_6_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_6_d_bits_corrupt_0 = auto_out_6_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_5_a_ready_0 = auto_out_5_a_ready; // @[Buffer.scala:40:9] wire auto_out_5_d_valid_0 = auto_out_5_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_5_d_bits_opcode_0 = auto_out_5_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_5_d_bits_param_0 = auto_out_5_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_5_d_bits_size_0 = auto_out_5_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_5_d_bits_source_0 = auto_out_5_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_5_d_bits_sink_0 = auto_out_5_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_5_d_bits_denied_0 = auto_out_5_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_5_d_bits_data_0 = auto_out_5_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_5_d_bits_corrupt_0 = auto_out_5_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_4_a_ready_0 = auto_out_4_a_ready; // @[Buffer.scala:40:9] wire auto_out_4_d_valid_0 = auto_out_4_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_4_d_bits_opcode_0 = auto_out_4_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_4_d_bits_param_0 = auto_out_4_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_4_d_bits_size_0 = auto_out_4_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_4_d_bits_source_0 = auto_out_4_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_4_d_bits_sink_0 = auto_out_4_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_4_d_bits_denied_0 = auto_out_4_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_4_d_bits_data_0 = auto_out_4_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_4_d_bits_corrupt_0 = auto_out_4_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_3_a_ready_0 = auto_out_3_a_ready; // @[Buffer.scala:40:9] wire auto_out_3_d_valid_0 = auto_out_3_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_3_d_bits_opcode_0 = auto_out_3_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_3_d_bits_param_0 = auto_out_3_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_3_d_bits_size_0 = auto_out_3_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_3_d_bits_source_0 = auto_out_3_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_3_d_bits_sink_0 = auto_out_3_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_3_d_bits_denied_0 = auto_out_3_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_3_d_bits_data_0 = auto_out_3_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_3_d_bits_corrupt_0 = auto_out_3_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_2_a_ready_0 = auto_out_2_a_ready; // @[Buffer.scala:40:9] wire auto_out_2_d_valid_0 = auto_out_2_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_2_d_bits_opcode_0 = auto_out_2_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_2_d_bits_param_0 = auto_out_2_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_2_d_bits_size_0 = auto_out_2_d_bits_size; // @[Buffer.scala:40:9] wire [4:0] auto_out_2_d_bits_source_0 = auto_out_2_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_2_d_bits_sink_0 = auto_out_2_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_2_d_bits_denied_0 = auto_out_2_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_2_d_bits_data_0 = auto_out_2_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_2_d_bits_corrupt_0 = auto_out_2_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_1_a_ready_0 = auto_out_1_a_ready; // @[Buffer.scala:40:9] wire auto_out_1_d_valid_0 = auto_out_1_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_d_bits_opcode_0 = auto_out_1_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_d_bits_param_0 = auto_out_1_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_1_d_bits_size_0 = auto_out_1_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_d_bits_source_0 = auto_out_1_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_d_bits_sink_0 = auto_out_1_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_1_d_bits_denied_0 = auto_out_1_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_1_d_bits_data_0 = auto_out_1_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_1_d_bits_corrupt_0 = auto_out_1_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_0_a_ready_0 = auto_out_0_a_ready; // @[Buffer.scala:40:9] wire auto_out_0_d_valid_0 = auto_out_0_d_valid; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_d_bits_opcode_0 = auto_out_0_d_bits_opcode; // @[Buffer.scala:40:9] wire [1:0] auto_out_0_d_bits_param_0 = auto_out_0_d_bits_param; // @[Buffer.scala:40:9] wire [3:0] auto_out_0_d_bits_size_0 = auto_out_0_d_bits_size; // @[Buffer.scala:40:9] wire [1:0] auto_out_0_d_bits_source_0 = auto_out_0_d_bits_source; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_d_bits_sink_0 = auto_out_0_d_bits_sink; // @[Buffer.scala:40:9] wire auto_out_0_d_bits_denied_0 = auto_out_0_d_bits_denied; // @[Buffer.scala:40:9] wire [63:0] auto_out_0_d_bits_data_0 = auto_out_0_d_bits_data; // @[Buffer.scala:40:9] wire auto_out_0_d_bits_corrupt_0 = auto_out_0_d_bits_corrupt; // @[Buffer.scala:40:9] wire auto_out_18_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire x1_nodeOut_17_e_ready = 1'h1; // @[Decoupled.scala:362:21] wire [63:0] auto_out_18_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [63:0] x1_nodeOut_17_b_bits_data = 64'h0; // @[Decoupled.scala:362:21] wire [7:0] auto_out_18_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [7:0] x1_nodeOut_17_b_bits_mask = 8'hFF; // @[Decoupled.scala:362:21] wire [1:0] auto_out_18_b_bits_source = 2'h0; // @[Decoupled.scala:362:21] wire [1:0] x1_nodeOut_17_b_bits_source = 2'h0; // @[Decoupled.scala:362:21] wire [3:0] auto_out_18_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [3:0] x1_nodeOut_17_b_bits_size = 4'h6; // @[Decoupled.scala:362:21] wire [2:0] auto_out_18_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire [2:0] x1_nodeOut_17_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21] wire auto_in_18_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_in_18_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire auto_out_18_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_18_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_18_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_18_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire x1_nodeOut_17_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21] wire nodeIn_18_a_valid = auto_in_18_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_18_a_bits_opcode = auto_in_18_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_18_a_bits_param = auto_in_18_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_18_a_bits_size = auto_in_18_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_18_a_bits_source = auto_in_18_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_18_a_bits_address = auto_in_18_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_18_a_bits_mask = auto_in_18_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_18_a_bits_data = auto_in_18_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_18_b_ready = auto_in_18_b_ready_0; // @[Buffer.scala:40:9] wire nodeIn_18_b_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_18_b_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_18_b_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_18_b_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_18_b_bits_source; // @[MixedNode.scala:551:17] wire [31:0] nodeIn_18_b_bits_address; // @[MixedNode.scala:551:17] wire [7:0] nodeIn_18_b_bits_mask; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_18_b_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_18_b_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_18_c_ready; // @[MixedNode.scala:551:17] wire nodeIn_18_c_valid = auto_in_18_c_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_18_c_bits_opcode = auto_in_18_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_18_c_bits_param = auto_in_18_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_18_c_bits_size = auto_in_18_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_18_c_bits_source = auto_in_18_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_18_c_bits_address = auto_in_18_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_18_c_bits_data = auto_in_18_c_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_18_d_ready = auto_in_18_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_18_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_18_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_18_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_18_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_18_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_18_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_18_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_18_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_18_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_18_e_ready; // @[MixedNode.scala:551:17] wire nodeIn_18_e_valid = auto_in_18_e_valid_0; // @[Buffer.scala:40:9] wire nodeIn_17_a_ready; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_18_e_bits_sink = auto_in_18_e_bits_sink_0; // @[Buffer.scala:40:9] wire nodeIn_17_a_valid = auto_in_17_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_17_a_bits_opcode = auto_in_17_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_17_a_bits_param = auto_in_17_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_17_a_bits_size = auto_in_17_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_17_a_bits_source = auto_in_17_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_17_a_bits_address = auto_in_17_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_17_a_bits_mask = auto_in_17_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_17_a_bits_data = auto_in_17_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_17_a_bits_corrupt = auto_in_17_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_17_d_ready = auto_in_17_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_17_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_17_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_17_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_17_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_17_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_17_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_17_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_17_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_17_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_16_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_16_a_valid = auto_in_16_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_16_a_bits_opcode = auto_in_16_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_16_a_bits_param = auto_in_16_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_16_a_bits_size = auto_in_16_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_16_a_bits_source = auto_in_16_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_16_a_bits_address = auto_in_16_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_16_a_bits_mask = auto_in_16_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_16_a_bits_data = auto_in_16_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_16_a_bits_corrupt = auto_in_16_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_16_d_ready = auto_in_16_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_16_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_16_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_16_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_16_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_16_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_16_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_16_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_16_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_16_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_15_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_15_a_valid = auto_in_15_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_15_a_bits_opcode = auto_in_15_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_15_a_bits_param = auto_in_15_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_15_a_bits_size = auto_in_15_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_15_a_bits_source = auto_in_15_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_15_a_bits_address = auto_in_15_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_15_a_bits_mask = auto_in_15_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_15_a_bits_data = auto_in_15_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_15_a_bits_corrupt = auto_in_15_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_15_d_ready = auto_in_15_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_15_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_15_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_15_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_15_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_15_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_15_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_15_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_15_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_15_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_14_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_14_a_valid = auto_in_14_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_14_a_bits_opcode = auto_in_14_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_14_a_bits_param = auto_in_14_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_14_a_bits_size = auto_in_14_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_14_a_bits_source = auto_in_14_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_14_a_bits_address = auto_in_14_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_14_a_bits_mask = auto_in_14_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_14_a_bits_data = auto_in_14_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_14_a_bits_corrupt = auto_in_14_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_14_d_ready = auto_in_14_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_14_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_14_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_14_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_14_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_14_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_14_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_14_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_14_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_14_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_13_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_13_a_valid = auto_in_13_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_13_a_bits_opcode = auto_in_13_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_13_a_bits_param = auto_in_13_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_13_a_bits_size = auto_in_13_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_13_a_bits_source = auto_in_13_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_13_a_bits_address = auto_in_13_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_13_a_bits_mask = auto_in_13_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_13_a_bits_data = auto_in_13_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_13_a_bits_corrupt = auto_in_13_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_13_d_ready = auto_in_13_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_13_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_13_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_13_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_13_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_13_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_13_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_13_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_13_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_13_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_12_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_12_a_valid = auto_in_12_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_12_a_bits_opcode = auto_in_12_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_12_a_bits_param = auto_in_12_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_12_a_bits_size = auto_in_12_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_12_a_bits_source = auto_in_12_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_12_a_bits_address = auto_in_12_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_12_a_bits_mask = auto_in_12_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_12_a_bits_data = auto_in_12_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_12_a_bits_corrupt = auto_in_12_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_12_d_ready = auto_in_12_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_12_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_12_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_12_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_12_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_12_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_12_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_12_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_12_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_12_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_11_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_11_a_valid = auto_in_11_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_11_a_bits_opcode = auto_in_11_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_11_a_bits_param = auto_in_11_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_11_a_bits_size = auto_in_11_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_11_a_bits_source = auto_in_11_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_11_a_bits_address = auto_in_11_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_11_a_bits_mask = auto_in_11_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_11_a_bits_data = auto_in_11_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_11_a_bits_corrupt = auto_in_11_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_11_d_ready = auto_in_11_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_11_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_11_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_11_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_11_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_11_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_11_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_11_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_11_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_11_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_10_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_10_a_valid = auto_in_10_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_10_a_bits_opcode = auto_in_10_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_10_a_bits_param = auto_in_10_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_10_a_bits_size = auto_in_10_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_10_a_bits_source = auto_in_10_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_10_a_bits_address = auto_in_10_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_10_a_bits_mask = auto_in_10_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_10_a_bits_data = auto_in_10_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_10_a_bits_corrupt = auto_in_10_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_10_d_ready = auto_in_10_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_10_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_10_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_10_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_10_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_10_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_10_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_10_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_10_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_10_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_9_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_9_a_valid = auto_in_9_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_9_a_bits_opcode = auto_in_9_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_9_a_bits_param = auto_in_9_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_9_a_bits_size = auto_in_9_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_9_a_bits_source = auto_in_9_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_9_a_bits_address = auto_in_9_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_9_a_bits_mask = auto_in_9_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_9_a_bits_data = auto_in_9_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_9_a_bits_corrupt = auto_in_9_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_9_d_ready = auto_in_9_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_9_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_9_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_9_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_9_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_9_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_9_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_9_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_9_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_9_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_8_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_8_a_valid = auto_in_8_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_8_a_bits_opcode = auto_in_8_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_8_a_bits_param = auto_in_8_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_8_a_bits_size = auto_in_8_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_8_a_bits_source = auto_in_8_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_8_a_bits_address = auto_in_8_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_8_a_bits_mask = auto_in_8_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_8_a_bits_data = auto_in_8_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_8_a_bits_corrupt = auto_in_8_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_8_d_ready = auto_in_8_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_8_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_8_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_8_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_8_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_8_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_8_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_8_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_8_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_8_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_7_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_7_a_valid = auto_in_7_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_7_a_bits_opcode = auto_in_7_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_7_a_bits_param = auto_in_7_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_7_a_bits_size = auto_in_7_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_7_a_bits_source = auto_in_7_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_7_a_bits_address = auto_in_7_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_7_a_bits_mask = auto_in_7_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_7_a_bits_data = auto_in_7_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_7_a_bits_corrupt = auto_in_7_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_7_d_ready = auto_in_7_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_7_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_7_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_7_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_7_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_7_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_7_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_7_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_7_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_7_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_6_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_6_a_valid = auto_in_6_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_6_a_bits_opcode = auto_in_6_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_6_a_bits_param = auto_in_6_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_6_a_bits_size = auto_in_6_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_6_a_bits_source = auto_in_6_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_6_a_bits_address = auto_in_6_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_6_a_bits_mask = auto_in_6_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_6_a_bits_data = auto_in_6_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_6_a_bits_corrupt = auto_in_6_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_6_d_ready = auto_in_6_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_6_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_6_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_6_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_6_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_6_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_6_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_6_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_6_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_6_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_5_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_5_a_valid = auto_in_5_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_5_a_bits_opcode = auto_in_5_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_5_a_bits_param = auto_in_5_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_5_a_bits_size = auto_in_5_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_5_a_bits_source = auto_in_5_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_5_a_bits_address = auto_in_5_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_5_a_bits_mask = auto_in_5_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_5_a_bits_data = auto_in_5_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_5_a_bits_corrupt = auto_in_5_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_5_d_ready = auto_in_5_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_5_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_5_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_5_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_5_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_5_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_5_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_5_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_5_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_5_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_4_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_4_a_valid = auto_in_4_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_4_a_bits_opcode = auto_in_4_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_4_a_bits_param = auto_in_4_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_4_a_bits_size = auto_in_4_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_4_a_bits_source = auto_in_4_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_4_a_bits_address = auto_in_4_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_4_a_bits_mask = auto_in_4_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_4_a_bits_data = auto_in_4_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_4_a_bits_corrupt = auto_in_4_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_4_d_ready = auto_in_4_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_4_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_4_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_4_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_4_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_4_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_4_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_4_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_4_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_4_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_3_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_3_a_valid = auto_in_3_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_3_a_bits_opcode = auto_in_3_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_3_a_bits_param = auto_in_3_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_3_a_bits_size = auto_in_3_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_3_a_bits_source = auto_in_3_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_3_a_bits_address = auto_in_3_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_3_a_bits_mask = auto_in_3_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_3_a_bits_data = auto_in_3_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_3_a_bits_corrupt = auto_in_3_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_3_d_ready = auto_in_3_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_3_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_3_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_3_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_3_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_3_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_3_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_3_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_3_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_3_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_2_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_2_a_valid = auto_in_2_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_2_a_bits_opcode = auto_in_2_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_2_a_bits_param = auto_in_2_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_2_a_bits_size = auto_in_2_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] nodeIn_2_a_bits_source = auto_in_2_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_2_a_bits_address = auto_in_2_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_2_a_bits_mask = auto_in_2_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_2_a_bits_data = auto_in_2_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_2_a_bits_corrupt = auto_in_2_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_2_d_ready = auto_in_2_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_2_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_2_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_2_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_2_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] nodeIn_2_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_2_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_2_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_2_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_2_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_1_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_1_a_valid = auto_in_1_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_1_a_bits_opcode = auto_in_1_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_1_a_bits_param = auto_in_1_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_1_a_bits_size = auto_in_1_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_1_a_bits_source = auto_in_1_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_1_a_bits_address = auto_in_1_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_1_a_bits_mask = auto_in_1_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_1_a_bits_data = auto_in_1_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_1_a_bits_corrupt = auto_in_1_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_1_d_ready = auto_in_1_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_1_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_1_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_1_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_1_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_1_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_1_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17] wire nodeIn_a_ready; // @[MixedNode.scala:551:17] wire nodeIn_a_valid = auto_in_0_a_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_opcode = auto_in_0_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] nodeIn_a_bits_param = auto_in_0_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeIn_a_bits_size = auto_in_0_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeIn_a_bits_source = auto_in_0_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] nodeIn_a_bits_address = auto_in_0_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] nodeIn_a_bits_mask = auto_in_0_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] nodeIn_a_bits_data = auto_in_0_a_bits_data_0; // @[Buffer.scala:40:9] wire nodeIn_a_bits_corrupt = auto_in_0_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeIn_d_ready = auto_in_0_d_ready_0; // @[Buffer.scala:40:9] wire nodeIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17] wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17] wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17] wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire x1_nodeOut_17_a_ready = auto_out_18_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_17_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_17_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_17_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_17_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_17_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_17_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_17_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_17_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_17_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_17_b_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_17_b_valid = auto_out_18_b_valid_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_17_b_bits_param = auto_out_18_b_bits_param_0; // @[Buffer.scala:40:9] wire [31:0] x1_nodeOut_17_b_bits_address = auto_out_18_b_bits_address_0; // @[Buffer.scala:40:9] wire x1_nodeOut_17_c_ready = auto_out_18_c_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_17_c_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_17_c_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_17_c_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_17_c_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_17_c_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_17_c_bits_address; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_17_c_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_17_c_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_17_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_17_d_valid = auto_out_18_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_17_d_bits_opcode = auto_out_18_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_17_d_bits_param = auto_out_18_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_17_d_bits_size = auto_out_18_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_17_d_bits_source = auto_out_18_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_17_d_bits_sink = auto_out_18_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_17_d_bits_denied = auto_out_18_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_17_d_bits_data = auto_out_18_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_17_d_bits_corrupt = auto_out_18_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_17_e_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_17_e_bits_sink; // @[MixedNode.scala:542:17] wire x1_nodeOut_16_a_ready = auto_out_17_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_16_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_16_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_16_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_16_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_16_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_16_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_16_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_16_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_16_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_16_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_16_d_valid = auto_out_17_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_16_d_bits_opcode = auto_out_17_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_16_d_bits_param = auto_out_17_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_16_d_bits_size = auto_out_17_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_16_d_bits_source = auto_out_17_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_16_d_bits_sink = auto_out_17_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_16_d_bits_denied = auto_out_17_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_16_d_bits_data = auto_out_17_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_16_d_bits_corrupt = auto_out_17_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_15_a_ready = auto_out_16_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_15_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_15_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_15_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_15_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_15_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_15_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_15_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_15_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_15_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_15_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_15_d_valid = auto_out_16_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_15_d_bits_opcode = auto_out_16_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_15_d_bits_param = auto_out_16_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_15_d_bits_size = auto_out_16_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_15_d_bits_source = auto_out_16_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_15_d_bits_sink = auto_out_16_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_15_d_bits_denied = auto_out_16_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_15_d_bits_data = auto_out_16_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_15_d_bits_corrupt = auto_out_16_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_14_a_ready = auto_out_15_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_14_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_14_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_14_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_14_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_14_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_14_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_14_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_14_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_14_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_14_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_14_d_valid = auto_out_15_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_14_d_bits_opcode = auto_out_15_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_14_d_bits_param = auto_out_15_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_14_d_bits_size = auto_out_15_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_14_d_bits_source = auto_out_15_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_14_d_bits_sink = auto_out_15_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_14_d_bits_denied = auto_out_15_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_14_d_bits_data = auto_out_15_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_14_d_bits_corrupt = auto_out_15_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_13_a_ready = auto_out_14_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_13_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_13_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_13_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_13_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_13_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_13_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_13_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_13_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_13_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_13_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_13_d_valid = auto_out_14_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_13_d_bits_opcode = auto_out_14_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_13_d_bits_param = auto_out_14_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_13_d_bits_size = auto_out_14_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_13_d_bits_source = auto_out_14_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_13_d_bits_sink = auto_out_14_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_13_d_bits_denied = auto_out_14_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_13_d_bits_data = auto_out_14_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_13_d_bits_corrupt = auto_out_14_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_12_a_ready = auto_out_13_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_12_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_12_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_12_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_12_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_12_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_12_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_12_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_12_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_12_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_12_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_12_d_valid = auto_out_13_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_12_d_bits_opcode = auto_out_13_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_12_d_bits_param = auto_out_13_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_12_d_bits_size = auto_out_13_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_12_d_bits_source = auto_out_13_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_12_d_bits_sink = auto_out_13_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_12_d_bits_denied = auto_out_13_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_12_d_bits_data = auto_out_13_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_12_d_bits_corrupt = auto_out_13_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_11_a_ready = auto_out_12_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_11_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_11_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_11_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_11_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_11_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_11_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_11_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_11_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_11_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_11_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_11_d_valid = auto_out_12_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_11_d_bits_opcode = auto_out_12_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_11_d_bits_param = auto_out_12_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_11_d_bits_size = auto_out_12_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_11_d_bits_source = auto_out_12_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_11_d_bits_sink = auto_out_12_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_11_d_bits_denied = auto_out_12_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_11_d_bits_data = auto_out_12_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_11_d_bits_corrupt = auto_out_12_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_10_a_ready = auto_out_11_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_10_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_10_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_10_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_10_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_10_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_10_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_10_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_10_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_10_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_10_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_10_d_valid = auto_out_11_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_10_d_bits_opcode = auto_out_11_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_10_d_bits_param = auto_out_11_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_10_d_bits_size = auto_out_11_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_10_d_bits_source = auto_out_11_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_10_d_bits_sink = auto_out_11_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_10_d_bits_denied = auto_out_11_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_10_d_bits_data = auto_out_11_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_10_d_bits_corrupt = auto_out_11_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_9_a_ready = auto_out_10_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_9_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_9_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_9_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_9_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_9_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_9_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_9_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_9_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_9_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_9_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_9_d_valid = auto_out_10_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_9_d_bits_opcode = auto_out_10_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_9_d_bits_param = auto_out_10_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_9_d_bits_size = auto_out_10_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_9_d_bits_source = auto_out_10_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_9_d_bits_sink = auto_out_10_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_9_d_bits_denied = auto_out_10_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_9_d_bits_data = auto_out_10_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_9_d_bits_corrupt = auto_out_10_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_8_a_ready = auto_out_9_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_8_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_8_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_8_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_8_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_8_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_8_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_8_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_8_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_8_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_8_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_8_d_valid = auto_out_9_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_8_d_bits_opcode = auto_out_9_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_8_d_bits_param = auto_out_9_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_8_d_bits_size = auto_out_9_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_8_d_bits_source = auto_out_9_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_8_d_bits_sink = auto_out_9_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_8_d_bits_denied = auto_out_9_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_8_d_bits_data = auto_out_9_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_8_d_bits_corrupt = auto_out_9_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_7_a_ready = auto_out_8_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_7_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_7_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_7_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_7_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_7_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_7_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_7_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_7_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_7_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_7_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_7_d_valid = auto_out_8_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_7_d_bits_opcode = auto_out_8_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_7_d_bits_param = auto_out_8_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_7_d_bits_size = auto_out_8_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_7_d_bits_source = auto_out_8_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_7_d_bits_sink = auto_out_8_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_7_d_bits_denied = auto_out_8_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_7_d_bits_data = auto_out_8_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_7_d_bits_corrupt = auto_out_8_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_6_a_ready = auto_out_7_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_6_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_6_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_6_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_6_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_6_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_6_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_6_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_6_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_6_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_6_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_6_d_valid = auto_out_7_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_6_d_bits_opcode = auto_out_7_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_6_d_bits_param = auto_out_7_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_6_d_bits_size = auto_out_7_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_6_d_bits_source = auto_out_7_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_6_d_bits_sink = auto_out_7_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_6_d_bits_denied = auto_out_7_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_6_d_bits_data = auto_out_7_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_6_d_bits_corrupt = auto_out_7_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_5_a_ready = auto_out_6_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_5_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_5_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_5_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_5_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_5_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_5_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_5_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_5_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_5_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_5_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_5_d_valid = auto_out_6_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_5_d_bits_opcode = auto_out_6_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_5_d_bits_param = auto_out_6_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_5_d_bits_size = auto_out_6_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_5_d_bits_source = auto_out_6_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_5_d_bits_sink = auto_out_6_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_5_d_bits_denied = auto_out_6_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_5_d_bits_data = auto_out_6_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_5_d_bits_corrupt = auto_out_6_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_4_a_ready = auto_out_5_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_4_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_4_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_4_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_4_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_4_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_4_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_4_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_4_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_4_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_4_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_4_d_valid = auto_out_5_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_4_d_bits_opcode = auto_out_5_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_4_d_bits_param = auto_out_5_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_4_d_bits_size = auto_out_5_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_4_d_bits_source = auto_out_5_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_4_d_bits_sink = auto_out_5_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_4_d_bits_denied = auto_out_5_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_4_d_bits_data = auto_out_5_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_4_d_bits_corrupt = auto_out_5_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_3_a_ready = auto_out_4_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_3_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_3_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_3_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_3_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_3_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_3_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_3_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_3_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_3_d_valid = auto_out_4_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_3_d_bits_opcode = auto_out_4_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_3_d_bits_param = auto_out_4_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_3_d_bits_size = auto_out_4_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_3_d_bits_source = auto_out_4_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_3_d_bits_sink = auto_out_4_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_3_d_bits_denied = auto_out_4_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_3_d_bits_data = auto_out_4_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_3_d_bits_corrupt = auto_out_4_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_2_a_ready = auto_out_3_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_2_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_2_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_2_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_2_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_2_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_2_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_2_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_2_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_2_d_valid = auto_out_3_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_2_d_bits_opcode = auto_out_3_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_2_d_bits_param = auto_out_3_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_2_d_bits_size = auto_out_3_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_2_d_bits_source = auto_out_3_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_2_d_bits_sink = auto_out_3_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_2_d_bits_denied = auto_out_3_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_2_d_bits_data = auto_out_3_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_2_d_bits_corrupt = auto_out_3_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_1_a_ready = auto_out_2_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_1_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_1_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_1_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_1_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] x1_nodeOut_1_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_1_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_1_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_1_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_1_d_valid = auto_out_2_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_1_d_bits_opcode = auto_out_2_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_1_d_bits_param = auto_out_2_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_1_d_bits_size = auto_out_2_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] x1_nodeOut_1_d_bits_source = auto_out_2_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_1_d_bits_sink = auto_out_2_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_1_d_bits_denied = auto_out_2_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_1_d_bits_data = auto_out_2_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_1_d_bits_corrupt = auto_out_2_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire x1_nodeOut_a_ready = auto_out_1_a_ready_0; // @[Buffer.scala:40:9] wire x1_nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] x1_nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] x1_nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] x1_nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] x1_nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] x1_nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] x1_nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire x1_nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_ready; // @[MixedNode.scala:542:17] wire x1_nodeOut_d_valid = auto_out_1_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_d_bits_opcode = auto_out_1_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_d_bits_param = auto_out_1_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] x1_nodeOut_d_bits_size = auto_out_1_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] x1_nodeOut_d_bits_source = auto_out_1_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] x1_nodeOut_d_bits_sink = auto_out_1_d_bits_sink_0; // @[Buffer.scala:40:9] wire x1_nodeOut_d_bits_denied = auto_out_1_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] x1_nodeOut_d_bits_data = auto_out_1_d_bits_data_0; // @[Buffer.scala:40:9] wire x1_nodeOut_d_bits_corrupt = auto_out_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire nodeOut_a_ready = auto_out_0_a_ready_0; // @[Buffer.scala:40:9] wire nodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire nodeOut_d_ready; // @[MixedNode.scala:542:17] wire nodeOut_d_valid = auto_out_0_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_opcode = auto_out_0_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_param = auto_out_0_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] nodeOut_d_bits_size = auto_out_0_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] nodeOut_d_bits_source = auto_out_0_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] nodeOut_d_bits_sink = auto_out_0_d_bits_sink_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_denied = auto_out_0_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] nodeOut_d_bits_data = auto_out_0_d_bits_data_0; // @[Buffer.scala:40:9] wire nodeOut_d_bits_corrupt = auto_out_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_18_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_b_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_18_b_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_18_b_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_18_b_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_in_18_b_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_in_18_b_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_18_b_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_18_b_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_18_b_valid_0; // @[Buffer.scala:40:9] wire auto_in_18_c_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_18_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_18_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_18_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_18_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_18_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_18_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_18_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_18_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_18_e_ready_0; // @[Buffer.scala:40:9] wire auto_in_17_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_17_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_17_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_17_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_17_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_17_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_17_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_17_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_17_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_17_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_16_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_16_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_16_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_16_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_16_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_16_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_16_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_16_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_16_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_16_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_15_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_15_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_15_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_15_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_15_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_15_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_15_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_15_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_15_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_15_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_14_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_14_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_14_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_14_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_14_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_14_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_14_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_14_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_14_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_14_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_13_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_13_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_13_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_13_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_13_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_13_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_13_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_13_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_13_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_13_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_12_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_12_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_12_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_12_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_12_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_12_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_12_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_12_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_12_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_12_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_11_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_11_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_11_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_11_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_11_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_11_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_11_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_11_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_11_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_11_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_10_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_10_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_10_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_10_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_10_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_10_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_10_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_10_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_10_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_10_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_9_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_9_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_9_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_9_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_9_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_9_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_9_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_9_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_9_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_9_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_8_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_8_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_8_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_8_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_8_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_8_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_8_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_8_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_8_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_8_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_7_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_7_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_7_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_7_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_7_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_7_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_7_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_7_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_7_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_7_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_6_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_6_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_6_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_6_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_6_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_6_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_6_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_6_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_6_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_6_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_5_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_5_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_5_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_5_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_5_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_5_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_5_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_5_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_5_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_5_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_4_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_4_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_4_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_4_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_4_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_4_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_4_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_4_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_4_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_4_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_3_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_3_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_3_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_3_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_3_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_3_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_3_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_3_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_3_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_3_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_2_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_2_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_2_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_2_d_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_in_2_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_2_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_2_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_2_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_2_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_2_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_1_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_1_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_1_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_1_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_1_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_1_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_1_d_valid_0; // @[Buffer.scala:40:9] wire auto_in_0_a_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_d_bits_opcode_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_0_d_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_in_0_d_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_in_0_d_bits_source_0; // @[Buffer.scala:40:9] wire [2:0] auto_in_0_d_bits_sink_0; // @[Buffer.scala:40:9] wire auto_in_0_d_bits_denied_0; // @[Buffer.scala:40:9] wire [63:0] auto_in_0_d_bits_data_0; // @[Buffer.scala:40:9] wire auto_in_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_in_0_d_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_18_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_18_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_18_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_18_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_18_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_18_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_18_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_18_b_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_c_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_c_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_18_c_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_18_c_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_18_c_bits_address_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_18_c_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_18_c_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_18_c_valid_0; // @[Buffer.scala:40:9] wire auto_out_18_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_18_e_bits_sink_0; // @[Buffer.scala:40:9] wire auto_out_18_e_valid_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_17_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_17_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_17_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_17_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_17_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_17_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_17_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_17_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_17_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_17_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_16_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_16_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_16_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_16_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_16_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_16_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_16_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_16_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_16_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_16_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_15_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_15_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_15_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_15_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_15_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_15_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_15_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_15_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_15_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_15_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_14_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_14_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_14_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_14_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_14_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_14_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_14_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_14_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_14_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_14_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_13_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_13_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_13_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_13_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_13_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_13_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_13_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_13_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_13_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_13_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_12_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_12_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_12_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_12_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_12_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_12_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_12_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_12_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_12_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_12_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_11_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_11_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_11_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_11_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_11_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_11_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_11_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_11_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_11_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_11_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_10_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_10_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_10_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_10_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_10_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_10_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_10_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_10_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_10_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_10_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_9_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_9_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_9_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_9_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_9_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_9_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_9_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_9_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_9_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_9_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_8_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_8_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_8_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_8_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_8_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_8_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_8_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_8_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_8_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_8_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_7_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_7_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_7_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_7_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_7_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_7_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_7_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_7_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_7_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_7_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_6_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_6_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_6_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_6_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_6_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_6_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_6_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_6_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_6_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_6_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_5_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_5_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_5_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_5_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_5_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_5_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_5_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_5_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_5_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_5_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_4_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_4_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_4_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_4_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_4_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_4_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_4_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_4_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_4_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_4_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_3_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_3_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_3_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_3_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_3_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_3_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_3_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_3_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_3_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_3_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_2_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_2_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_2_a_bits_size_0; // @[Buffer.scala:40:9] wire [4:0] auto_out_2_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_2_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_2_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_2_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_2_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_2_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_2_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_1_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_1_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_1_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_1_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_1_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_1_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_1_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_1_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_1_d_ready_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_a_bits_opcode_0; // @[Buffer.scala:40:9] wire [2:0] auto_out_0_a_bits_param_0; // @[Buffer.scala:40:9] wire [3:0] auto_out_0_a_bits_size_0; // @[Buffer.scala:40:9] wire [1:0] auto_out_0_a_bits_source_0; // @[Buffer.scala:40:9] wire [31:0] auto_out_0_a_bits_address_0; // @[Buffer.scala:40:9] wire [7:0] auto_out_0_a_bits_mask_0; // @[Buffer.scala:40:9] wire [63:0] auto_out_0_a_bits_data_0; // @[Buffer.scala:40:9] wire auto_out_0_a_bits_corrupt_0; // @[Buffer.scala:40:9] wire auto_out_0_a_valid_0; // @[Buffer.scala:40:9] wire auto_out_0_d_ready_0; // @[Buffer.scala:40:9] assign auto_in_0_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9] assign auto_in_0_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_1_a_ready_0 = nodeIn_1_a_ready; // @[Buffer.scala:40:9] assign auto_in_1_d_valid_0 = nodeIn_1_d_valid; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_opcode_0 = nodeIn_1_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_param_0 = nodeIn_1_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_size_0 = nodeIn_1_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_source_0 = nodeIn_1_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_sink_0 = nodeIn_1_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_denied_0 = nodeIn_1_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_data_0 = nodeIn_1_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_corrupt_0 = nodeIn_1_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_2_a_ready_0 = nodeIn_2_a_ready; // @[Buffer.scala:40:9] assign auto_in_2_d_valid_0 = nodeIn_2_d_valid; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_opcode_0 = nodeIn_2_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_param_0 = nodeIn_2_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_size_0 = nodeIn_2_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_source_0 = nodeIn_2_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_sink_0 = nodeIn_2_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_denied_0 = nodeIn_2_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_data_0 = nodeIn_2_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_corrupt_0 = nodeIn_2_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_3_a_ready_0 = nodeIn_3_a_ready; // @[Buffer.scala:40:9] assign auto_in_3_d_valid_0 = nodeIn_3_d_valid; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_opcode_0 = nodeIn_3_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_param_0 = nodeIn_3_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_size_0 = nodeIn_3_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_source_0 = nodeIn_3_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_sink_0 = nodeIn_3_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_denied_0 = nodeIn_3_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_data_0 = nodeIn_3_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_corrupt_0 = nodeIn_3_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_4_a_ready_0 = nodeIn_4_a_ready; // @[Buffer.scala:40:9] assign auto_in_4_d_valid_0 = nodeIn_4_d_valid; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_opcode_0 = nodeIn_4_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_param_0 = nodeIn_4_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_size_0 = nodeIn_4_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_source_0 = nodeIn_4_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_sink_0 = nodeIn_4_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_denied_0 = nodeIn_4_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_data_0 = nodeIn_4_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_corrupt_0 = nodeIn_4_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_5_a_ready_0 = nodeIn_5_a_ready; // @[Buffer.scala:40:9] assign auto_in_5_d_valid_0 = nodeIn_5_d_valid; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_opcode_0 = nodeIn_5_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_param_0 = nodeIn_5_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_size_0 = nodeIn_5_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_source_0 = nodeIn_5_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_sink_0 = nodeIn_5_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_denied_0 = nodeIn_5_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_data_0 = nodeIn_5_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_corrupt_0 = nodeIn_5_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_6_a_ready_0 = nodeIn_6_a_ready; // @[Buffer.scala:40:9] assign auto_in_6_d_valid_0 = nodeIn_6_d_valid; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_opcode_0 = nodeIn_6_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_param_0 = nodeIn_6_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_size_0 = nodeIn_6_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_source_0 = nodeIn_6_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_sink_0 = nodeIn_6_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_denied_0 = nodeIn_6_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_data_0 = nodeIn_6_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_corrupt_0 = nodeIn_6_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_7_a_ready_0 = nodeIn_7_a_ready; // @[Buffer.scala:40:9] assign auto_in_7_d_valid_0 = nodeIn_7_d_valid; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_opcode_0 = nodeIn_7_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_param_0 = nodeIn_7_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_size_0 = nodeIn_7_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_source_0 = nodeIn_7_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_sink_0 = nodeIn_7_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_denied_0 = nodeIn_7_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_data_0 = nodeIn_7_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_corrupt_0 = nodeIn_7_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_8_a_ready_0 = nodeIn_8_a_ready; // @[Buffer.scala:40:9] assign auto_in_8_d_valid_0 = nodeIn_8_d_valid; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_opcode_0 = nodeIn_8_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_param_0 = nodeIn_8_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_size_0 = nodeIn_8_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_source_0 = nodeIn_8_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_sink_0 = nodeIn_8_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_denied_0 = nodeIn_8_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_data_0 = nodeIn_8_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_corrupt_0 = nodeIn_8_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_9_a_ready_0 = nodeIn_9_a_ready; // @[Buffer.scala:40:9] assign auto_in_9_d_valid_0 = nodeIn_9_d_valid; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_opcode_0 = nodeIn_9_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_param_0 = nodeIn_9_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_size_0 = nodeIn_9_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_source_0 = nodeIn_9_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_sink_0 = nodeIn_9_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_denied_0 = nodeIn_9_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_data_0 = nodeIn_9_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_corrupt_0 = nodeIn_9_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_10_a_ready_0 = nodeIn_10_a_ready; // @[Buffer.scala:40:9] assign auto_in_10_d_valid_0 = nodeIn_10_d_valid; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_opcode_0 = nodeIn_10_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_param_0 = nodeIn_10_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_size_0 = nodeIn_10_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_source_0 = nodeIn_10_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_sink_0 = nodeIn_10_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_denied_0 = nodeIn_10_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_data_0 = nodeIn_10_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_corrupt_0 = nodeIn_10_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_11_a_ready_0 = nodeIn_11_a_ready; // @[Buffer.scala:40:9] assign auto_in_11_d_valid_0 = nodeIn_11_d_valid; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_opcode_0 = nodeIn_11_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_param_0 = nodeIn_11_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_size_0 = nodeIn_11_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_source_0 = nodeIn_11_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_sink_0 = nodeIn_11_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_denied_0 = nodeIn_11_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_data_0 = nodeIn_11_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_corrupt_0 = nodeIn_11_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_12_a_ready_0 = nodeIn_12_a_ready; // @[Buffer.scala:40:9] assign auto_in_12_d_valid_0 = nodeIn_12_d_valid; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_opcode_0 = nodeIn_12_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_param_0 = nodeIn_12_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_size_0 = nodeIn_12_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_source_0 = nodeIn_12_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_sink_0 = nodeIn_12_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_denied_0 = nodeIn_12_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_data_0 = nodeIn_12_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_corrupt_0 = nodeIn_12_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_13_a_ready_0 = nodeIn_13_a_ready; // @[Buffer.scala:40:9] assign auto_in_13_d_valid_0 = nodeIn_13_d_valid; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_opcode_0 = nodeIn_13_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_param_0 = nodeIn_13_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_size_0 = nodeIn_13_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_source_0 = nodeIn_13_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_sink_0 = nodeIn_13_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_denied_0 = nodeIn_13_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_data_0 = nodeIn_13_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_corrupt_0 = nodeIn_13_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_14_a_ready_0 = nodeIn_14_a_ready; // @[Buffer.scala:40:9] assign auto_in_14_d_valid_0 = nodeIn_14_d_valid; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_opcode_0 = nodeIn_14_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_param_0 = nodeIn_14_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_size_0 = nodeIn_14_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_source_0 = nodeIn_14_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_sink_0 = nodeIn_14_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_denied_0 = nodeIn_14_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_data_0 = nodeIn_14_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_corrupt_0 = nodeIn_14_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_15_a_ready_0 = nodeIn_15_a_ready; // @[Buffer.scala:40:9] assign auto_in_15_d_valid_0 = nodeIn_15_d_valid; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_opcode_0 = nodeIn_15_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_param_0 = nodeIn_15_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_size_0 = nodeIn_15_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_source_0 = nodeIn_15_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_sink_0 = nodeIn_15_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_denied_0 = nodeIn_15_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_data_0 = nodeIn_15_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_corrupt_0 = nodeIn_15_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_16_a_ready_0 = nodeIn_16_a_ready; // @[Buffer.scala:40:9] assign auto_in_16_d_valid_0 = nodeIn_16_d_valid; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_opcode_0 = nodeIn_16_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_param_0 = nodeIn_16_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_size_0 = nodeIn_16_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_source_0 = nodeIn_16_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_sink_0 = nodeIn_16_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_denied_0 = nodeIn_16_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_data_0 = nodeIn_16_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_corrupt_0 = nodeIn_16_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_17_a_ready_0 = nodeIn_17_a_ready; // @[Buffer.scala:40:9] assign auto_in_17_d_valid_0 = nodeIn_17_d_valid; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_opcode_0 = nodeIn_17_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_param_0 = nodeIn_17_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_size_0 = nodeIn_17_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_source_0 = nodeIn_17_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_sink_0 = nodeIn_17_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_denied_0 = nodeIn_17_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_data_0 = nodeIn_17_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_corrupt_0 = nodeIn_17_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_18_a_ready_0 = nodeIn_18_a_ready; // @[Buffer.scala:40:9] assign auto_in_18_b_valid_0 = nodeIn_18_b_valid; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_opcode_0 = nodeIn_18_b_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_param_0 = nodeIn_18_b_bits_param; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_size_0 = nodeIn_18_b_bits_size; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_source_0 = nodeIn_18_b_bits_source; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_address_0 = nodeIn_18_b_bits_address; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_mask_0 = nodeIn_18_b_bits_mask; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_data_0 = nodeIn_18_b_bits_data; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_corrupt_0 = nodeIn_18_b_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_18_c_ready_0 = nodeIn_18_c_ready; // @[Buffer.scala:40:9] assign auto_in_18_d_valid_0 = nodeIn_18_d_valid; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_opcode_0 = nodeIn_18_d_bits_opcode; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_param_0 = nodeIn_18_d_bits_param; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_size_0 = nodeIn_18_d_bits_size; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_source_0 = nodeIn_18_d_bits_source; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_sink_0 = nodeIn_18_d_bits_sink; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_denied_0 = nodeIn_18_d_bits_denied; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_data_0 = nodeIn_18_d_bits_data; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_corrupt_0 = nodeIn_18_d_bits_corrupt; // @[Buffer.scala:40:9] assign auto_in_18_e_ready_0 = nodeIn_18_e_ready; // @[Buffer.scala:40:9] assign auto_out_0_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_0_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_1_a_valid_0 = x1_nodeOut_a_valid; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_opcode_0 = x1_nodeOut_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_param_0 = x1_nodeOut_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_size_0 = x1_nodeOut_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_source_0 = x1_nodeOut_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_address_0 = x1_nodeOut_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_mask_0 = x1_nodeOut_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_data_0 = x1_nodeOut_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_corrupt_0 = x1_nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_1_d_ready_0 = x1_nodeOut_d_ready; // @[Buffer.scala:40:9] assign auto_out_2_a_valid_0 = x1_nodeOut_1_a_valid; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_opcode_0 = x1_nodeOut_1_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_param_0 = x1_nodeOut_1_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_size_0 = x1_nodeOut_1_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_source_0 = x1_nodeOut_1_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_address_0 = x1_nodeOut_1_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_mask_0 = x1_nodeOut_1_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_data_0 = x1_nodeOut_1_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_corrupt_0 = x1_nodeOut_1_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_2_d_ready_0 = x1_nodeOut_1_d_ready; // @[Buffer.scala:40:9] assign auto_out_3_a_valid_0 = x1_nodeOut_2_a_valid; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_opcode_0 = x1_nodeOut_2_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_param_0 = x1_nodeOut_2_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_size_0 = x1_nodeOut_2_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_source_0 = x1_nodeOut_2_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_address_0 = x1_nodeOut_2_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_mask_0 = x1_nodeOut_2_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_data_0 = x1_nodeOut_2_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_corrupt_0 = x1_nodeOut_2_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_3_d_ready_0 = x1_nodeOut_2_d_ready; // @[Buffer.scala:40:9] assign auto_out_4_a_valid_0 = x1_nodeOut_3_a_valid; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_opcode_0 = x1_nodeOut_3_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_param_0 = x1_nodeOut_3_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_size_0 = x1_nodeOut_3_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_source_0 = x1_nodeOut_3_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_address_0 = x1_nodeOut_3_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_mask_0 = x1_nodeOut_3_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_data_0 = x1_nodeOut_3_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_corrupt_0 = x1_nodeOut_3_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_4_d_ready_0 = x1_nodeOut_3_d_ready; // @[Buffer.scala:40:9] assign auto_out_5_a_valid_0 = x1_nodeOut_4_a_valid; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_opcode_0 = x1_nodeOut_4_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_param_0 = x1_nodeOut_4_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_size_0 = x1_nodeOut_4_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_source_0 = x1_nodeOut_4_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_address_0 = x1_nodeOut_4_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_mask_0 = x1_nodeOut_4_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_data_0 = x1_nodeOut_4_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_corrupt_0 = x1_nodeOut_4_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_5_d_ready_0 = x1_nodeOut_4_d_ready; // @[Buffer.scala:40:9] assign auto_out_6_a_valid_0 = x1_nodeOut_5_a_valid; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_opcode_0 = x1_nodeOut_5_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_param_0 = x1_nodeOut_5_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_size_0 = x1_nodeOut_5_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_source_0 = x1_nodeOut_5_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_address_0 = x1_nodeOut_5_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_mask_0 = x1_nodeOut_5_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_data_0 = x1_nodeOut_5_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_corrupt_0 = x1_nodeOut_5_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_6_d_ready_0 = x1_nodeOut_5_d_ready; // @[Buffer.scala:40:9] assign auto_out_7_a_valid_0 = x1_nodeOut_6_a_valid; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_opcode_0 = x1_nodeOut_6_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_param_0 = x1_nodeOut_6_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_size_0 = x1_nodeOut_6_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_source_0 = x1_nodeOut_6_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_address_0 = x1_nodeOut_6_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_mask_0 = x1_nodeOut_6_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_data_0 = x1_nodeOut_6_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_corrupt_0 = x1_nodeOut_6_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_7_d_ready_0 = x1_nodeOut_6_d_ready; // @[Buffer.scala:40:9] assign auto_out_8_a_valid_0 = x1_nodeOut_7_a_valid; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_opcode_0 = x1_nodeOut_7_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_param_0 = x1_nodeOut_7_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_size_0 = x1_nodeOut_7_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_source_0 = x1_nodeOut_7_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_address_0 = x1_nodeOut_7_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_mask_0 = x1_nodeOut_7_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_data_0 = x1_nodeOut_7_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_corrupt_0 = x1_nodeOut_7_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_8_d_ready_0 = x1_nodeOut_7_d_ready; // @[Buffer.scala:40:9] assign auto_out_9_a_valid_0 = x1_nodeOut_8_a_valid; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_opcode_0 = x1_nodeOut_8_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_param_0 = x1_nodeOut_8_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_size_0 = x1_nodeOut_8_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_source_0 = x1_nodeOut_8_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_address_0 = x1_nodeOut_8_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_mask_0 = x1_nodeOut_8_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_data_0 = x1_nodeOut_8_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_corrupt_0 = x1_nodeOut_8_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_9_d_ready_0 = x1_nodeOut_8_d_ready; // @[Buffer.scala:40:9] assign auto_out_10_a_valid_0 = x1_nodeOut_9_a_valid; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_opcode_0 = x1_nodeOut_9_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_param_0 = x1_nodeOut_9_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_size_0 = x1_nodeOut_9_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_source_0 = x1_nodeOut_9_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_address_0 = x1_nodeOut_9_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_mask_0 = x1_nodeOut_9_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_data_0 = x1_nodeOut_9_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_corrupt_0 = x1_nodeOut_9_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_10_d_ready_0 = x1_nodeOut_9_d_ready; // @[Buffer.scala:40:9] assign auto_out_11_a_valid_0 = x1_nodeOut_10_a_valid; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_opcode_0 = x1_nodeOut_10_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_param_0 = x1_nodeOut_10_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_size_0 = x1_nodeOut_10_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_source_0 = x1_nodeOut_10_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_address_0 = x1_nodeOut_10_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_mask_0 = x1_nodeOut_10_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_data_0 = x1_nodeOut_10_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_corrupt_0 = x1_nodeOut_10_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_11_d_ready_0 = x1_nodeOut_10_d_ready; // @[Buffer.scala:40:9] assign auto_out_12_a_valid_0 = x1_nodeOut_11_a_valid; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_opcode_0 = x1_nodeOut_11_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_param_0 = x1_nodeOut_11_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_size_0 = x1_nodeOut_11_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_source_0 = x1_nodeOut_11_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_address_0 = x1_nodeOut_11_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_mask_0 = x1_nodeOut_11_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_data_0 = x1_nodeOut_11_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_corrupt_0 = x1_nodeOut_11_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_12_d_ready_0 = x1_nodeOut_11_d_ready; // @[Buffer.scala:40:9] assign auto_out_13_a_valid_0 = x1_nodeOut_12_a_valid; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_opcode_0 = x1_nodeOut_12_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_param_0 = x1_nodeOut_12_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_size_0 = x1_nodeOut_12_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_source_0 = x1_nodeOut_12_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_address_0 = x1_nodeOut_12_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_mask_0 = x1_nodeOut_12_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_data_0 = x1_nodeOut_12_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_corrupt_0 = x1_nodeOut_12_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_13_d_ready_0 = x1_nodeOut_12_d_ready; // @[Buffer.scala:40:9] assign auto_out_14_a_valid_0 = x1_nodeOut_13_a_valid; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_opcode_0 = x1_nodeOut_13_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_param_0 = x1_nodeOut_13_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_size_0 = x1_nodeOut_13_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_source_0 = x1_nodeOut_13_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_address_0 = x1_nodeOut_13_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_mask_0 = x1_nodeOut_13_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_data_0 = x1_nodeOut_13_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_corrupt_0 = x1_nodeOut_13_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_14_d_ready_0 = x1_nodeOut_13_d_ready; // @[Buffer.scala:40:9] assign auto_out_15_a_valid_0 = x1_nodeOut_14_a_valid; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_opcode_0 = x1_nodeOut_14_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_param_0 = x1_nodeOut_14_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_size_0 = x1_nodeOut_14_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_source_0 = x1_nodeOut_14_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_address_0 = x1_nodeOut_14_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_mask_0 = x1_nodeOut_14_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_data_0 = x1_nodeOut_14_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_corrupt_0 = x1_nodeOut_14_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_15_d_ready_0 = x1_nodeOut_14_d_ready; // @[Buffer.scala:40:9] assign auto_out_16_a_valid_0 = x1_nodeOut_15_a_valid; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_opcode_0 = x1_nodeOut_15_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_param_0 = x1_nodeOut_15_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_size_0 = x1_nodeOut_15_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_source_0 = x1_nodeOut_15_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_address_0 = x1_nodeOut_15_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_mask_0 = x1_nodeOut_15_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_data_0 = x1_nodeOut_15_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_corrupt_0 = x1_nodeOut_15_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_16_d_ready_0 = x1_nodeOut_15_d_ready; // @[Buffer.scala:40:9] assign auto_out_17_a_valid_0 = x1_nodeOut_16_a_valid; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_opcode_0 = x1_nodeOut_16_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_param_0 = x1_nodeOut_16_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_size_0 = x1_nodeOut_16_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_source_0 = x1_nodeOut_16_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_address_0 = x1_nodeOut_16_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_mask_0 = x1_nodeOut_16_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_data_0 = x1_nodeOut_16_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_corrupt_0 = x1_nodeOut_16_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_17_d_ready_0 = x1_nodeOut_16_d_ready; // @[Buffer.scala:40:9] assign auto_out_18_a_valid_0 = x1_nodeOut_17_a_valid; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_opcode_0 = x1_nodeOut_17_a_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_param_0 = x1_nodeOut_17_a_bits_param; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_size_0 = x1_nodeOut_17_a_bits_size; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_source_0 = x1_nodeOut_17_a_bits_source; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_address_0 = x1_nodeOut_17_a_bits_address; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_mask_0 = x1_nodeOut_17_a_bits_mask; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_data_0 = x1_nodeOut_17_a_bits_data; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_corrupt_0 = x1_nodeOut_17_a_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_18_b_ready_0 = x1_nodeOut_17_b_ready; // @[Buffer.scala:40:9] assign auto_out_18_c_valid_0 = x1_nodeOut_17_c_valid; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_opcode_0 = x1_nodeOut_17_c_bits_opcode; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_param_0 = x1_nodeOut_17_c_bits_param; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_size_0 = x1_nodeOut_17_c_bits_size; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_source_0 = x1_nodeOut_17_c_bits_source; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_address_0 = x1_nodeOut_17_c_bits_address; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_data_0 = x1_nodeOut_17_c_bits_data; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_corrupt_0 = x1_nodeOut_17_c_bits_corrupt; // @[Buffer.scala:40:9] assign auto_out_18_d_ready_0 = x1_nodeOut_17_d_ready; // @[Buffer.scala:40:9] assign auto_out_18_e_valid_0 = x1_nodeOut_17_e_valid; // @[Buffer.scala:40:9] assign auto_out_18_e_bits_sink_0 = x1_nodeOut_17_e_bits_sink; // @[Buffer.scala:40:9] TLMonitor_76 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_77 monitor_1 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_1_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_1_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_1_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_1_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_1_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_1_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_1_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_1_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_1_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_1_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_78 monitor_2 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_2_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_2_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_2_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_2_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_2_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_2_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_2_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_2_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_2_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_2_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_2_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_2_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_2_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_2_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_2_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_2_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_2_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_2_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_2_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_2_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_79 monitor_3 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_3_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_3_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_3_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_3_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_3_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_3_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_3_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_3_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_3_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_3_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_3_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_3_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_3_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_3_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_3_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_3_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_3_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_3_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_3_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_3_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_80 monitor_4 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_4_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_4_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_4_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_4_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_4_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_4_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_4_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_4_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_4_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_4_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_4_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_4_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_4_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_4_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_4_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_4_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_4_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_4_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_4_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_4_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_81 monitor_5 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_5_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_5_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_5_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_5_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_5_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_5_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_5_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_5_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_5_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_5_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_5_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_5_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_5_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_5_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_5_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_5_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_5_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_5_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_5_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_5_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_82 monitor_6 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_6_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_6_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_6_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_6_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_6_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_6_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_6_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_6_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_6_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_6_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_6_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_6_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_6_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_6_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_6_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_6_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_6_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_6_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_6_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_6_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_83 monitor_7 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_7_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_7_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_7_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_7_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_7_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_7_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_7_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_7_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_7_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_7_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_7_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_7_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_7_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_7_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_7_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_7_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_7_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_7_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_7_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_7_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_84 monitor_8 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_8_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_8_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_8_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_8_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_8_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_8_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_8_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_8_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_8_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_8_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_8_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_8_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_8_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_8_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_8_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_8_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_8_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_8_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_8_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_8_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_85 monitor_9 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_9_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_9_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_9_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_9_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_9_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_9_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_9_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_9_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_9_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_9_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_9_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_9_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_9_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_9_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_9_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_9_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_9_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_9_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_9_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_9_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_86 monitor_10 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_10_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_10_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_10_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_10_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_10_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_10_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_10_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_10_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_10_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_10_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_10_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_10_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_10_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_10_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_10_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_10_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_10_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_10_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_10_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_10_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_87 monitor_11 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_11_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_11_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_11_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_11_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_11_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_11_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_11_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_11_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_11_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_11_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_11_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_11_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_11_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_11_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_11_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_11_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_11_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_11_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_11_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_11_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_88 monitor_12 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_12_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_12_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_12_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_12_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_12_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_12_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_12_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_12_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_12_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_12_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_12_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_12_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_12_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_12_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_12_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_12_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_12_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_12_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_12_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_12_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_89 monitor_13 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_13_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_13_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_13_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_13_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_13_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_13_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_13_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_13_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_13_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_13_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_13_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_13_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_13_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_13_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_13_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_13_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_13_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_13_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_13_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_13_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_90 monitor_14 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_14_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_14_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_14_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_14_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_14_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_14_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_14_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_14_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_14_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_14_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_14_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_14_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_14_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_14_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_14_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_14_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_14_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_14_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_14_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_14_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_91 monitor_15 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_15_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_15_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_15_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_15_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_15_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_15_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_15_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_15_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_15_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_15_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_15_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_15_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_15_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_15_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_15_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_15_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_15_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_15_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_15_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_15_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_92 monitor_16 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_16_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_16_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_16_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_16_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_16_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_16_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_16_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_16_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_16_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_16_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_16_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_16_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_16_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_16_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_16_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_16_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_16_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_16_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_16_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_16_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_93 monitor_17 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_17_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_17_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_17_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_17_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_17_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_17_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_17_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_17_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_17_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (nodeIn_17_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_17_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_17_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_17_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_17_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_17_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_17_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_17_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_17_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_17_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_17_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] TLMonitor_94 monitor_18 ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (nodeIn_18_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (nodeIn_18_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (nodeIn_18_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (nodeIn_18_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (nodeIn_18_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (nodeIn_18_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (nodeIn_18_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (nodeIn_18_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (nodeIn_18_a_bits_data), // @[MixedNode.scala:551:17] .io_in_b_ready (nodeIn_18_b_ready), // @[MixedNode.scala:551:17] .io_in_b_valid (nodeIn_18_b_valid), // @[MixedNode.scala:551:17] .io_in_b_bits_opcode (nodeIn_18_b_bits_opcode), // @[MixedNode.scala:551:17] .io_in_b_bits_param (nodeIn_18_b_bits_param), // @[MixedNode.scala:551:17] .io_in_b_bits_size (nodeIn_18_b_bits_size), // @[MixedNode.scala:551:17] .io_in_b_bits_source (nodeIn_18_b_bits_source), // @[MixedNode.scala:551:17] .io_in_b_bits_address (nodeIn_18_b_bits_address), // @[MixedNode.scala:551:17] .io_in_b_bits_mask (nodeIn_18_b_bits_mask), // @[MixedNode.scala:551:17] .io_in_b_bits_data (nodeIn_18_b_bits_data), // @[MixedNode.scala:551:17] .io_in_b_bits_corrupt (nodeIn_18_b_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_c_ready (nodeIn_18_c_ready), // @[MixedNode.scala:551:17] .io_in_c_valid (nodeIn_18_c_valid), // @[MixedNode.scala:551:17] .io_in_c_bits_opcode (nodeIn_18_c_bits_opcode), // @[MixedNode.scala:551:17] .io_in_c_bits_param (nodeIn_18_c_bits_param), // @[MixedNode.scala:551:17] .io_in_c_bits_size (nodeIn_18_c_bits_size), // @[MixedNode.scala:551:17] .io_in_c_bits_source (nodeIn_18_c_bits_source), // @[MixedNode.scala:551:17] .io_in_c_bits_address (nodeIn_18_c_bits_address), // @[MixedNode.scala:551:17] .io_in_c_bits_data (nodeIn_18_c_bits_data), // @[MixedNode.scala:551:17] .io_in_d_ready (nodeIn_18_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (nodeIn_18_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (nodeIn_18_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (nodeIn_18_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (nodeIn_18_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (nodeIn_18_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (nodeIn_18_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (nodeIn_18_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (nodeIn_18_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (nodeIn_18_d_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_e_ready (nodeIn_18_e_ready), // @[MixedNode.scala:551:17] .io_in_e_valid (nodeIn_18_e_valid), // @[MixedNode.scala:551:17] .io_in_e_bits_sink (nodeIn_18_e_bits_sink) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s2k3z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_a_ready), .io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (nodeOut_a_valid), .io_deq_bits_opcode (nodeOut_a_bits_opcode), .io_deq_bits_param (nodeOut_a_bits_param), .io_deq_bits_size (nodeOut_a_bits_size), .io_deq_bits_source (nodeOut_a_bits_source), .io_deq_bits_address (nodeOut_a_bits_address), .io_deq_bits_mask (nodeOut_a_bits_mask), .io_deq_bits_data (nodeOut_a_bits_data), .io_deq_bits_corrupt (nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeOut_d_ready), .io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_d_valid), .io_deq_bits_opcode (nodeIn_d_bits_opcode), .io_deq_bits_param (nodeIn_d_bits_param), .io_deq_bits_size (nodeIn_d_bits_size), .io_deq_bits_source (nodeIn_d_bits_source), .io_deq_bits_sink (nodeIn_d_bits_sink), .io_deq_bits_denied (nodeIn_d_bits_denied), .io_deq_bits_data (nodeIn_d_bits_data), .io_deq_bits_corrupt (nodeIn_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s2k3z4u_1 nodeOut_a_q_1 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_1_a_ready), .io_enq_valid (nodeIn_1_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_1_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_1_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_1_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_1_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_1_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_1_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_1_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_1_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_a_valid), .io_deq_bits_opcode (x1_nodeOut_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_a_bits_param), .io_deq_bits_size (x1_nodeOut_a_bits_size), .io_deq_bits_source (x1_nodeOut_a_bits_source), .io_deq_bits_address (x1_nodeOut_a_bits_address), .io_deq_bits_mask (x1_nodeOut_a_bits_mask), .io_deq_bits_data (x1_nodeOut_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4u_1 nodeIn_d_q_1 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_d_ready), .io_enq_valid (x1_nodeOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_1_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_1_d_valid), .io_deq_bits_opcode (nodeIn_1_d_bits_opcode), .io_deq_bits_param (nodeIn_1_d_bits_param), .io_deq_bits_size (nodeIn_1_d_bits_size), .io_deq_bits_source (nodeIn_1_d_bits_source), .io_deq_bits_sink (nodeIn_1_d_bits_sink), .io_deq_bits_denied (nodeIn_1_d_bits_denied), .io_deq_bits_data (nodeIn_1_d_bits_data), .io_deq_bits_corrupt (nodeIn_1_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_1 nodeOut_a_q_2 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_2_a_ready), .io_enq_valid (nodeIn_2_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_2_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_2_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_2_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_2_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_2_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_2_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_2_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_2_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_1_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_1_a_valid), .io_deq_bits_opcode (x1_nodeOut_1_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_1_a_bits_param), .io_deq_bits_size (x1_nodeOut_1_a_bits_size), .io_deq_bits_source (x1_nodeOut_1_a_bits_source), .io_deq_bits_address (x1_nodeOut_1_a_bits_address), .io_deq_bits_mask (x1_nodeOut_1_a_bits_mask), .io_deq_bits_data (x1_nodeOut_1_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_1_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_1 nodeIn_d_q_2 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_1_d_ready), .io_enq_valid (x1_nodeOut_1_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_1_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_1_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_1_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_1_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_1_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_1_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_1_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_1_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_2_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_2_d_valid), .io_deq_bits_opcode (nodeIn_2_d_bits_opcode), .io_deq_bits_param (nodeIn_2_d_bits_param), .io_deq_bits_size (nodeIn_2_d_bits_size), .io_deq_bits_source (nodeIn_2_d_bits_source), .io_deq_bits_sink (nodeIn_2_d_bits_sink), .io_deq_bits_denied (nodeIn_2_d_bits_denied), .io_deq_bits_data (nodeIn_2_d_bits_data), .io_deq_bits_corrupt (nodeIn_2_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_2 nodeOut_a_q_3 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_3_a_ready), .io_enq_valid (nodeIn_3_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_3_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_3_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_3_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_3_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_3_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_3_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_3_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_3_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_2_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_2_a_valid), .io_deq_bits_opcode (x1_nodeOut_2_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_2_a_bits_param), .io_deq_bits_size (x1_nodeOut_2_a_bits_size), .io_deq_bits_source (x1_nodeOut_2_a_bits_source), .io_deq_bits_address (x1_nodeOut_2_a_bits_address), .io_deq_bits_mask (x1_nodeOut_2_a_bits_mask), .io_deq_bits_data (x1_nodeOut_2_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_2_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_2 nodeIn_d_q_3 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_2_d_ready), .io_enq_valid (x1_nodeOut_2_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_2_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_2_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_2_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_2_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_2_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_2_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_2_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_2_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_3_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_3_d_valid), .io_deq_bits_opcode (nodeIn_3_d_bits_opcode), .io_deq_bits_param (nodeIn_3_d_bits_param), .io_deq_bits_size (nodeIn_3_d_bits_size), .io_deq_bits_source (nodeIn_3_d_bits_source), .io_deq_bits_sink (nodeIn_3_d_bits_sink), .io_deq_bits_denied (nodeIn_3_d_bits_denied), .io_deq_bits_data (nodeIn_3_d_bits_data), .io_deq_bits_corrupt (nodeIn_3_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_3 nodeOut_a_q_4 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_4_a_ready), .io_enq_valid (nodeIn_4_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_4_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_4_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_4_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_4_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_4_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_4_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_4_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_4_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_3_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_3_a_valid), .io_deq_bits_opcode (x1_nodeOut_3_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_3_a_bits_param), .io_deq_bits_size (x1_nodeOut_3_a_bits_size), .io_deq_bits_source (x1_nodeOut_3_a_bits_source), .io_deq_bits_address (x1_nodeOut_3_a_bits_address), .io_deq_bits_mask (x1_nodeOut_3_a_bits_mask), .io_deq_bits_data (x1_nodeOut_3_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_3_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_3 nodeIn_d_q_4 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_3_d_ready), .io_enq_valid (x1_nodeOut_3_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_3_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_3_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_3_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_3_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_3_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_3_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_3_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_3_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_4_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_4_d_valid), .io_deq_bits_opcode (nodeIn_4_d_bits_opcode), .io_deq_bits_param (nodeIn_4_d_bits_param), .io_deq_bits_size (nodeIn_4_d_bits_size), .io_deq_bits_source (nodeIn_4_d_bits_source), .io_deq_bits_sink (nodeIn_4_d_bits_sink), .io_deq_bits_denied (nodeIn_4_d_bits_denied), .io_deq_bits_data (nodeIn_4_d_bits_data), .io_deq_bits_corrupt (nodeIn_4_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_4 nodeOut_a_q_5 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_5_a_ready), .io_enq_valid (nodeIn_5_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_5_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_5_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_5_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_5_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_5_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_5_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_5_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_5_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_4_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_4_a_valid), .io_deq_bits_opcode (x1_nodeOut_4_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_4_a_bits_param), .io_deq_bits_size (x1_nodeOut_4_a_bits_size), .io_deq_bits_source (x1_nodeOut_4_a_bits_source), .io_deq_bits_address (x1_nodeOut_4_a_bits_address), .io_deq_bits_mask (x1_nodeOut_4_a_bits_mask), .io_deq_bits_data (x1_nodeOut_4_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_4_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_4 nodeIn_d_q_5 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_4_d_ready), .io_enq_valid (x1_nodeOut_4_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_4_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_4_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_4_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_4_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_4_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_4_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_4_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_4_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_5_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_5_d_valid), .io_deq_bits_opcode (nodeIn_5_d_bits_opcode), .io_deq_bits_param (nodeIn_5_d_bits_param), .io_deq_bits_size (nodeIn_5_d_bits_size), .io_deq_bits_source (nodeIn_5_d_bits_source), .io_deq_bits_sink (nodeIn_5_d_bits_sink), .io_deq_bits_denied (nodeIn_5_d_bits_denied), .io_deq_bits_data (nodeIn_5_d_bits_data), .io_deq_bits_corrupt (nodeIn_5_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_5 nodeOut_a_q_6 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_6_a_ready), .io_enq_valid (nodeIn_6_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_6_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_6_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_6_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_6_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_6_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_6_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_6_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_6_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_5_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_5_a_valid), .io_deq_bits_opcode (x1_nodeOut_5_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_5_a_bits_param), .io_deq_bits_size (x1_nodeOut_5_a_bits_size), .io_deq_bits_source (x1_nodeOut_5_a_bits_source), .io_deq_bits_address (x1_nodeOut_5_a_bits_address), .io_deq_bits_mask (x1_nodeOut_5_a_bits_mask), .io_deq_bits_data (x1_nodeOut_5_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_5_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_5 nodeIn_d_q_6 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_5_d_ready), .io_enq_valid (x1_nodeOut_5_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_5_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_5_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_5_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_5_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_5_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_5_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_5_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_5_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_6_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_6_d_valid), .io_deq_bits_opcode (nodeIn_6_d_bits_opcode), .io_deq_bits_param (nodeIn_6_d_bits_param), .io_deq_bits_size (nodeIn_6_d_bits_size), .io_deq_bits_source (nodeIn_6_d_bits_source), .io_deq_bits_sink (nodeIn_6_d_bits_sink), .io_deq_bits_denied (nodeIn_6_d_bits_denied), .io_deq_bits_data (nodeIn_6_d_bits_data), .io_deq_bits_corrupt (nodeIn_6_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_6 nodeOut_a_q_7 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_7_a_ready), .io_enq_valid (nodeIn_7_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_7_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_7_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_7_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_7_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_7_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_7_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_7_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_7_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_6_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_6_a_valid), .io_deq_bits_opcode (x1_nodeOut_6_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_6_a_bits_param), .io_deq_bits_size (x1_nodeOut_6_a_bits_size), .io_deq_bits_source (x1_nodeOut_6_a_bits_source), .io_deq_bits_address (x1_nodeOut_6_a_bits_address), .io_deq_bits_mask (x1_nodeOut_6_a_bits_mask), .io_deq_bits_data (x1_nodeOut_6_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_6_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_6 nodeIn_d_q_7 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_6_d_ready), .io_enq_valid (x1_nodeOut_6_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_6_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_6_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_6_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_6_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_6_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_6_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_6_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_6_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_7_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_7_d_valid), .io_deq_bits_opcode (nodeIn_7_d_bits_opcode), .io_deq_bits_param (nodeIn_7_d_bits_param), .io_deq_bits_size (nodeIn_7_d_bits_size), .io_deq_bits_source (nodeIn_7_d_bits_source), .io_deq_bits_sink (nodeIn_7_d_bits_sink), .io_deq_bits_denied (nodeIn_7_d_bits_denied), .io_deq_bits_data (nodeIn_7_d_bits_data), .io_deq_bits_corrupt (nodeIn_7_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s2k3z4u_2 nodeOut_a_q_8 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_8_a_ready), .io_enq_valid (nodeIn_8_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_8_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_8_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_8_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_8_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_8_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_8_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_8_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_8_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_7_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_7_a_valid), .io_deq_bits_opcode (x1_nodeOut_7_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_7_a_bits_param), .io_deq_bits_size (x1_nodeOut_7_a_bits_size), .io_deq_bits_source (x1_nodeOut_7_a_bits_source), .io_deq_bits_address (x1_nodeOut_7_a_bits_address), .io_deq_bits_mask (x1_nodeOut_7_a_bits_mask), .io_deq_bits_data (x1_nodeOut_7_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_7_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4u_2 nodeIn_d_q_8 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_7_d_ready), .io_enq_valid (x1_nodeOut_7_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_7_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_7_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_7_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_7_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_7_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_7_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_7_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_7_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_8_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_8_d_valid), .io_deq_bits_opcode (nodeIn_8_d_bits_opcode), .io_deq_bits_param (nodeIn_8_d_bits_param), .io_deq_bits_size (nodeIn_8_d_bits_size), .io_deq_bits_source (nodeIn_8_d_bits_source), .io_deq_bits_sink (nodeIn_8_d_bits_sink), .io_deq_bits_denied (nodeIn_8_d_bits_denied), .io_deq_bits_data (nodeIn_8_d_bits_data), .io_deq_bits_corrupt (nodeIn_8_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s2k3z4u_3 nodeOut_a_q_9 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_9_a_ready), .io_enq_valid (nodeIn_9_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_9_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_9_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_9_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_9_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_9_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_9_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_9_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_9_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_8_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_8_a_valid), .io_deq_bits_opcode (x1_nodeOut_8_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_8_a_bits_param), .io_deq_bits_size (x1_nodeOut_8_a_bits_size), .io_deq_bits_source (x1_nodeOut_8_a_bits_source), .io_deq_bits_address (x1_nodeOut_8_a_bits_address), .io_deq_bits_mask (x1_nodeOut_8_a_bits_mask), .io_deq_bits_data (x1_nodeOut_8_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_8_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4u_3 nodeIn_d_q_9 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_8_d_ready), .io_enq_valid (x1_nodeOut_8_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_8_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_8_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_8_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_8_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_8_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_8_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_8_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_8_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_9_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_9_d_valid), .io_deq_bits_opcode (nodeIn_9_d_bits_opcode), .io_deq_bits_param (nodeIn_9_d_bits_param), .io_deq_bits_size (nodeIn_9_d_bits_size), .io_deq_bits_source (nodeIn_9_d_bits_source), .io_deq_bits_sink (nodeIn_9_d_bits_sink), .io_deq_bits_denied (nodeIn_9_d_bits_denied), .io_deq_bits_data (nodeIn_9_d_bits_data), .io_deq_bits_corrupt (nodeIn_9_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_7 nodeOut_a_q_10 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_10_a_ready), .io_enq_valid (nodeIn_10_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_10_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_10_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_10_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_10_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_10_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_10_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_10_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_10_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_9_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_9_a_valid), .io_deq_bits_opcode (x1_nodeOut_9_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_9_a_bits_param), .io_deq_bits_size (x1_nodeOut_9_a_bits_size), .io_deq_bits_source (x1_nodeOut_9_a_bits_source), .io_deq_bits_address (x1_nodeOut_9_a_bits_address), .io_deq_bits_mask (x1_nodeOut_9_a_bits_mask), .io_deq_bits_data (x1_nodeOut_9_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_9_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_7 nodeIn_d_q_10 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_9_d_ready), .io_enq_valid (x1_nodeOut_9_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_9_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_9_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_9_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_9_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_9_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_9_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_9_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_9_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_10_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_10_d_valid), .io_deq_bits_opcode (nodeIn_10_d_bits_opcode), .io_deq_bits_param (nodeIn_10_d_bits_param), .io_deq_bits_size (nodeIn_10_d_bits_size), .io_deq_bits_source (nodeIn_10_d_bits_source), .io_deq_bits_sink (nodeIn_10_d_bits_sink), .io_deq_bits_denied (nodeIn_10_d_bits_denied), .io_deq_bits_data (nodeIn_10_d_bits_data), .io_deq_bits_corrupt (nodeIn_10_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_8 nodeOut_a_q_11 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_11_a_ready), .io_enq_valid (nodeIn_11_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_11_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_11_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_11_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_11_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_11_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_11_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_11_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_11_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_10_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_10_a_valid), .io_deq_bits_opcode (x1_nodeOut_10_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_10_a_bits_param), .io_deq_bits_size (x1_nodeOut_10_a_bits_size), .io_deq_bits_source (x1_nodeOut_10_a_bits_source), .io_deq_bits_address (x1_nodeOut_10_a_bits_address), .io_deq_bits_mask (x1_nodeOut_10_a_bits_mask), .io_deq_bits_data (x1_nodeOut_10_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_10_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_8 nodeIn_d_q_11 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_10_d_ready), .io_enq_valid (x1_nodeOut_10_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_10_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_10_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_10_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_10_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_10_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_10_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_10_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_10_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_11_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_11_d_valid), .io_deq_bits_opcode (nodeIn_11_d_bits_opcode), .io_deq_bits_param (nodeIn_11_d_bits_param), .io_deq_bits_size (nodeIn_11_d_bits_size), .io_deq_bits_source (nodeIn_11_d_bits_source), .io_deq_bits_sink (nodeIn_11_d_bits_sink), .io_deq_bits_denied (nodeIn_11_d_bits_denied), .io_deq_bits_data (nodeIn_11_d_bits_data), .io_deq_bits_corrupt (nodeIn_11_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_9 nodeOut_a_q_12 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_12_a_ready), .io_enq_valid (nodeIn_12_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_12_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_12_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_12_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_12_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_12_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_12_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_12_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_12_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_11_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_11_a_valid), .io_deq_bits_opcode (x1_nodeOut_11_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_11_a_bits_param), .io_deq_bits_size (x1_nodeOut_11_a_bits_size), .io_deq_bits_source (x1_nodeOut_11_a_bits_source), .io_deq_bits_address (x1_nodeOut_11_a_bits_address), .io_deq_bits_mask (x1_nodeOut_11_a_bits_mask), .io_deq_bits_data (x1_nodeOut_11_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_11_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_9 nodeIn_d_q_12 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_11_d_ready), .io_enq_valid (x1_nodeOut_11_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_11_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_11_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_11_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_11_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_11_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_11_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_11_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_11_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_12_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_12_d_valid), .io_deq_bits_opcode (nodeIn_12_d_bits_opcode), .io_deq_bits_param (nodeIn_12_d_bits_param), .io_deq_bits_size (nodeIn_12_d_bits_size), .io_deq_bits_source (nodeIn_12_d_bits_source), .io_deq_bits_sink (nodeIn_12_d_bits_sink), .io_deq_bits_denied (nodeIn_12_d_bits_denied), .io_deq_bits_data (nodeIn_12_d_bits_data), .io_deq_bits_corrupt (nodeIn_12_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_10 nodeOut_a_q_13 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_13_a_ready), .io_enq_valid (nodeIn_13_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_13_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_13_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_13_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_13_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_13_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_13_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_13_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_13_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_12_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_12_a_valid), .io_deq_bits_opcode (x1_nodeOut_12_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_12_a_bits_param), .io_deq_bits_size (x1_nodeOut_12_a_bits_size), .io_deq_bits_source (x1_nodeOut_12_a_bits_source), .io_deq_bits_address (x1_nodeOut_12_a_bits_address), .io_deq_bits_mask (x1_nodeOut_12_a_bits_mask), .io_deq_bits_data (x1_nodeOut_12_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_12_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_10 nodeIn_d_q_13 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_12_d_ready), .io_enq_valid (x1_nodeOut_12_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_12_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_12_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_12_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_12_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_12_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_12_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_12_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_12_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_13_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_13_d_valid), .io_deq_bits_opcode (nodeIn_13_d_bits_opcode), .io_deq_bits_param (nodeIn_13_d_bits_param), .io_deq_bits_size (nodeIn_13_d_bits_size), .io_deq_bits_source (nodeIn_13_d_bits_source), .io_deq_bits_sink (nodeIn_13_d_bits_sink), .io_deq_bits_denied (nodeIn_13_d_bits_denied), .io_deq_bits_data (nodeIn_13_d_bits_data), .io_deq_bits_corrupt (nodeIn_13_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_11 nodeOut_a_q_14 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_14_a_ready), .io_enq_valid (nodeIn_14_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_14_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_14_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_14_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_14_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_14_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_14_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_14_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_14_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_13_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_13_a_valid), .io_deq_bits_opcode (x1_nodeOut_13_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_13_a_bits_param), .io_deq_bits_size (x1_nodeOut_13_a_bits_size), .io_deq_bits_source (x1_nodeOut_13_a_bits_source), .io_deq_bits_address (x1_nodeOut_13_a_bits_address), .io_deq_bits_mask (x1_nodeOut_13_a_bits_mask), .io_deq_bits_data (x1_nodeOut_13_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_13_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_11 nodeIn_d_q_14 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_13_d_ready), .io_enq_valid (x1_nodeOut_13_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_13_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_13_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_13_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_13_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_13_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_13_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_13_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_13_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_14_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_14_d_valid), .io_deq_bits_opcode (nodeIn_14_d_bits_opcode), .io_deq_bits_param (nodeIn_14_d_bits_param), .io_deq_bits_size (nodeIn_14_d_bits_size), .io_deq_bits_source (nodeIn_14_d_bits_source), .io_deq_bits_sink (nodeIn_14_d_bits_sink), .io_deq_bits_denied (nodeIn_14_d_bits_denied), .io_deq_bits_data (nodeIn_14_d_bits_data), .io_deq_bits_corrupt (nodeIn_14_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_12 nodeOut_a_q_15 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_15_a_ready), .io_enq_valid (nodeIn_15_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_15_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_15_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_15_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_15_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_15_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_15_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_15_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_15_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_14_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_14_a_valid), .io_deq_bits_opcode (x1_nodeOut_14_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_14_a_bits_param), .io_deq_bits_size (x1_nodeOut_14_a_bits_size), .io_deq_bits_source (x1_nodeOut_14_a_bits_source), .io_deq_bits_address (x1_nodeOut_14_a_bits_address), .io_deq_bits_mask (x1_nodeOut_14_a_bits_mask), .io_deq_bits_data (x1_nodeOut_14_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_14_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_12 nodeIn_d_q_15 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_14_d_ready), .io_enq_valid (x1_nodeOut_14_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_14_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_14_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_14_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_14_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_14_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_14_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_14_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_14_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_15_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_15_d_valid), .io_deq_bits_opcode (nodeIn_15_d_bits_opcode), .io_deq_bits_param (nodeIn_15_d_bits_param), .io_deq_bits_size (nodeIn_15_d_bits_size), .io_deq_bits_source (nodeIn_15_d_bits_source), .io_deq_bits_sink (nodeIn_15_d_bits_sink), .io_deq_bits_denied (nodeIn_15_d_bits_denied), .io_deq_bits_data (nodeIn_15_d_bits_data), .io_deq_bits_corrupt (nodeIn_15_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_13 nodeOut_a_q_16 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_16_a_ready), .io_enq_valid (nodeIn_16_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_16_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_16_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_16_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_16_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_16_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_16_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_16_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_16_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_15_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_15_a_valid), .io_deq_bits_opcode (x1_nodeOut_15_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_15_a_bits_param), .io_deq_bits_size (x1_nodeOut_15_a_bits_size), .io_deq_bits_source (x1_nodeOut_15_a_bits_source), .io_deq_bits_address (x1_nodeOut_15_a_bits_address), .io_deq_bits_mask (x1_nodeOut_15_a_bits_mask), .io_deq_bits_data (x1_nodeOut_15_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_15_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_13 nodeIn_d_q_16 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_15_d_ready), .io_enq_valid (x1_nodeOut_15_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_15_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_15_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_15_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_15_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_15_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_15_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_15_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_15_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_16_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_16_d_valid), .io_deq_bits_opcode (nodeIn_16_d_bits_opcode), .io_deq_bits_param (nodeIn_16_d_bits_param), .io_deq_bits_size (nodeIn_16_d_bits_size), .io_deq_bits_source (nodeIn_16_d_bits_source), .io_deq_bits_sink (nodeIn_16_d_bits_sink), .io_deq_bits_denied (nodeIn_16_d_bits_denied), .io_deq_bits_data (nodeIn_16_d_bits_data), .io_deq_bits_corrupt (nodeIn_16_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s5k3z4u_14 nodeOut_a_q_17 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_17_a_ready), .io_enq_valid (nodeIn_17_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_17_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_17_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_17_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_17_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_17_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_17_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_17_a_bits_data), // @[MixedNode.scala:551:17] .io_enq_bits_corrupt (nodeIn_17_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_16_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_16_a_valid), .io_deq_bits_opcode (x1_nodeOut_16_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_16_a_bits_param), .io_deq_bits_size (x1_nodeOut_16_a_bits_size), .io_deq_bits_source (x1_nodeOut_16_a_bits_source), .io_deq_bits_address (x1_nodeOut_16_a_bits_address), .io_deq_bits_mask (x1_nodeOut_16_a_bits_mask), .io_deq_bits_data (x1_nodeOut_16_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_16_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s5k3z4u_14 nodeIn_d_q_17 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_16_d_ready), .io_enq_valid (x1_nodeOut_16_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_16_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_16_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_16_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_16_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_16_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_16_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_16_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_16_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_17_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_17_d_valid), .io_deq_bits_opcode (nodeIn_17_d_bits_opcode), .io_deq_bits_param (nodeIn_17_d_bits_param), .io_deq_bits_size (nodeIn_17_d_bits_size), .io_deq_bits_source (nodeIn_17_d_bits_source), .io_deq_bits_sink (nodeIn_17_d_bits_sink), .io_deq_bits_denied (nodeIn_17_d_bits_denied), .io_deq_bits_data (nodeIn_17_d_bits_data), .io_deq_bits_corrupt (nodeIn_17_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleA_a32d64s2k3z4c nodeOut_a_q_18 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_18_a_ready), .io_enq_valid (nodeIn_18_a_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_18_a_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_18_a_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_18_a_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_18_a_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_18_a_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_mask (nodeIn_18_a_bits_mask), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_18_a_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_17_a_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_17_a_valid), .io_deq_bits_opcode (x1_nodeOut_17_a_bits_opcode), .io_deq_bits_param (x1_nodeOut_17_a_bits_param), .io_deq_bits_size (x1_nodeOut_17_a_bits_size), .io_deq_bits_source (x1_nodeOut_17_a_bits_source), .io_deq_bits_address (x1_nodeOut_17_a_bits_address), .io_deq_bits_mask (x1_nodeOut_17_a_bits_mask), .io_deq_bits_data (x1_nodeOut_17_a_bits_data), .io_deq_bits_corrupt (x1_nodeOut_17_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s2k3z4c nodeIn_d_q_18 ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_17_d_ready), .io_enq_valid (x1_nodeOut_17_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (x1_nodeOut_17_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_17_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (x1_nodeOut_17_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (x1_nodeOut_17_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (x1_nodeOut_17_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (x1_nodeOut_17_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (x1_nodeOut_17_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (x1_nodeOut_17_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_18_d_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_18_d_valid), .io_deq_bits_opcode (nodeIn_18_d_bits_opcode), .io_deq_bits_param (nodeIn_18_d_bits_param), .io_deq_bits_size (nodeIn_18_d_bits_size), .io_deq_bits_source (nodeIn_18_d_bits_source), .io_deq_bits_sink (nodeIn_18_d_bits_sink), .io_deq_bits_denied (nodeIn_18_d_bits_denied), .io_deq_bits_data (nodeIn_18_d_bits_data), .io_deq_bits_corrupt (nodeIn_18_d_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleB_a32d64s2k3z4c nodeIn_b_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (x1_nodeOut_17_b_ready), .io_enq_valid (x1_nodeOut_17_b_valid), // @[MixedNode.scala:542:17] .io_enq_bits_param (x1_nodeOut_17_b_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_address (x1_nodeOut_17_b_bits_address), // @[MixedNode.scala:542:17] .io_deq_ready (nodeIn_18_b_ready), // @[MixedNode.scala:551:17] .io_deq_valid (nodeIn_18_b_valid), .io_deq_bits_opcode (nodeIn_18_b_bits_opcode), .io_deq_bits_param (nodeIn_18_b_bits_param), .io_deq_bits_size (nodeIn_18_b_bits_size), .io_deq_bits_source (nodeIn_18_b_bits_source), .io_deq_bits_address (nodeIn_18_b_bits_address), .io_deq_bits_mask (nodeIn_18_b_bits_mask), .io_deq_bits_data (nodeIn_18_b_bits_data), .io_deq_bits_corrupt (nodeIn_18_b_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleC_a32d64s2k3z4c nodeOut_c_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_18_c_ready), .io_enq_valid (nodeIn_18_c_valid), // @[MixedNode.scala:551:17] .io_enq_bits_opcode (nodeIn_18_c_bits_opcode), // @[MixedNode.scala:551:17] .io_enq_bits_param (nodeIn_18_c_bits_param), // @[MixedNode.scala:551:17] .io_enq_bits_size (nodeIn_18_c_bits_size), // @[MixedNode.scala:551:17] .io_enq_bits_source (nodeIn_18_c_bits_source), // @[MixedNode.scala:551:17] .io_enq_bits_address (nodeIn_18_c_bits_address), // @[MixedNode.scala:551:17] .io_enq_bits_data (nodeIn_18_c_bits_data), // @[MixedNode.scala:551:17] .io_deq_ready (x1_nodeOut_17_c_ready), // @[MixedNode.scala:542:17] .io_deq_valid (x1_nodeOut_17_c_valid), .io_deq_bits_opcode (x1_nodeOut_17_c_bits_opcode), .io_deq_bits_param (x1_nodeOut_17_c_bits_param), .io_deq_bits_size (x1_nodeOut_17_c_bits_size), .io_deq_bits_source (x1_nodeOut_17_c_bits_source), .io_deq_bits_address (x1_nodeOut_17_c_bits_address), .io_deq_bits_data (x1_nodeOut_17_c_bits_data), .io_deq_bits_corrupt (x1_nodeOut_17_c_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleE_a32d64s2k3z4c nodeOut_e_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (nodeIn_18_e_ready), .io_enq_valid (nodeIn_18_e_valid), // @[MixedNode.scala:551:17] .io_enq_bits_sink (nodeIn_18_e_bits_sink), // @[MixedNode.scala:551:17] .io_deq_valid (x1_nodeOut_17_e_valid), .io_deq_bits_sink (x1_nodeOut_17_e_bits_sink) ); // @[Decoupled.scala:362:21] assign auto_in_18_a_ready = auto_in_18_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_18_b_valid = auto_in_18_b_valid_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_opcode = auto_in_18_b_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_param = auto_in_18_b_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_size = auto_in_18_b_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_source = auto_in_18_b_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_address = auto_in_18_b_bits_address_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_mask = auto_in_18_b_bits_mask_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_data = auto_in_18_b_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_18_b_bits_corrupt = auto_in_18_b_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_18_c_ready = auto_in_18_c_ready_0; // @[Buffer.scala:40:9] assign auto_in_18_d_valid = auto_in_18_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_opcode = auto_in_18_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_param = auto_in_18_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_size = auto_in_18_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_source = auto_in_18_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_sink = auto_in_18_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_denied = auto_in_18_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_data = auto_in_18_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_18_d_bits_corrupt = auto_in_18_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_18_e_ready = auto_in_18_e_ready_0; // @[Buffer.scala:40:9] assign auto_in_17_a_ready = auto_in_17_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_17_d_valid = auto_in_17_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_opcode = auto_in_17_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_param = auto_in_17_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_size = auto_in_17_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_source = auto_in_17_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_sink = auto_in_17_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_denied = auto_in_17_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_data = auto_in_17_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_17_d_bits_corrupt = auto_in_17_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_16_a_ready = auto_in_16_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_16_d_valid = auto_in_16_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_opcode = auto_in_16_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_param = auto_in_16_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_size = auto_in_16_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_source = auto_in_16_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_sink = auto_in_16_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_denied = auto_in_16_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_data = auto_in_16_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_16_d_bits_corrupt = auto_in_16_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_15_a_ready = auto_in_15_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_15_d_valid = auto_in_15_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_opcode = auto_in_15_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_param = auto_in_15_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_size = auto_in_15_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_source = auto_in_15_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_sink = auto_in_15_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_denied = auto_in_15_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_data = auto_in_15_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_15_d_bits_corrupt = auto_in_15_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_14_a_ready = auto_in_14_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_14_d_valid = auto_in_14_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_opcode = auto_in_14_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_param = auto_in_14_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_size = auto_in_14_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_source = auto_in_14_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_sink = auto_in_14_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_denied = auto_in_14_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_data = auto_in_14_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_14_d_bits_corrupt = auto_in_14_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_13_a_ready = auto_in_13_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_13_d_valid = auto_in_13_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_opcode = auto_in_13_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_param = auto_in_13_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_size = auto_in_13_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_source = auto_in_13_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_sink = auto_in_13_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_denied = auto_in_13_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_data = auto_in_13_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_13_d_bits_corrupt = auto_in_13_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_12_a_ready = auto_in_12_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_12_d_valid = auto_in_12_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_opcode = auto_in_12_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_param = auto_in_12_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_size = auto_in_12_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_source = auto_in_12_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_sink = auto_in_12_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_denied = auto_in_12_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_data = auto_in_12_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_12_d_bits_corrupt = auto_in_12_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_11_a_ready = auto_in_11_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_11_d_valid = auto_in_11_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_opcode = auto_in_11_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_param = auto_in_11_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_size = auto_in_11_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_source = auto_in_11_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_sink = auto_in_11_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_denied = auto_in_11_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_data = auto_in_11_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_11_d_bits_corrupt = auto_in_11_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_10_a_ready = auto_in_10_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_10_d_valid = auto_in_10_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_opcode = auto_in_10_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_param = auto_in_10_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_size = auto_in_10_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_source = auto_in_10_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_sink = auto_in_10_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_denied = auto_in_10_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_data = auto_in_10_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_10_d_bits_corrupt = auto_in_10_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_9_a_ready = auto_in_9_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_9_d_valid = auto_in_9_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_opcode = auto_in_9_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_param = auto_in_9_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_size = auto_in_9_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_source = auto_in_9_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_sink = auto_in_9_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_denied = auto_in_9_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_data = auto_in_9_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_9_d_bits_corrupt = auto_in_9_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_8_a_ready = auto_in_8_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_8_d_valid = auto_in_8_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_opcode = auto_in_8_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_param = auto_in_8_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_size = auto_in_8_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_source = auto_in_8_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_sink = auto_in_8_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_denied = auto_in_8_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_data = auto_in_8_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_8_d_bits_corrupt = auto_in_8_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_7_a_ready = auto_in_7_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_7_d_valid = auto_in_7_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_opcode = auto_in_7_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_param = auto_in_7_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_size = auto_in_7_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_source = auto_in_7_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_sink = auto_in_7_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_denied = auto_in_7_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_data = auto_in_7_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_7_d_bits_corrupt = auto_in_7_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_6_a_ready = auto_in_6_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_6_d_valid = auto_in_6_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_opcode = auto_in_6_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_param = auto_in_6_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_size = auto_in_6_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_source = auto_in_6_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_sink = auto_in_6_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_denied = auto_in_6_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_data = auto_in_6_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_6_d_bits_corrupt = auto_in_6_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_5_a_ready = auto_in_5_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_5_d_valid = auto_in_5_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_opcode = auto_in_5_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_param = auto_in_5_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_size = auto_in_5_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_source = auto_in_5_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_sink = auto_in_5_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_denied = auto_in_5_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_data = auto_in_5_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_5_d_bits_corrupt = auto_in_5_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_4_a_ready = auto_in_4_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_4_d_valid = auto_in_4_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_opcode = auto_in_4_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_param = auto_in_4_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_size = auto_in_4_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_source = auto_in_4_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_sink = auto_in_4_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_denied = auto_in_4_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_data = auto_in_4_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_4_d_bits_corrupt = auto_in_4_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_3_a_ready = auto_in_3_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_3_d_valid = auto_in_3_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_opcode = auto_in_3_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_param = auto_in_3_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_size = auto_in_3_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_source = auto_in_3_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_sink = auto_in_3_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_denied = auto_in_3_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_data = auto_in_3_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_3_d_bits_corrupt = auto_in_3_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_2_a_ready = auto_in_2_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_2_d_valid = auto_in_2_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_opcode = auto_in_2_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_param = auto_in_2_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_size = auto_in_2_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_source = auto_in_2_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_sink = auto_in_2_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_denied = auto_in_2_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_data = auto_in_2_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_2_d_bits_corrupt = auto_in_2_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_1_a_ready = auto_in_1_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_1_d_valid = auto_in_1_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_opcode = auto_in_1_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_param = auto_in_1_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_size = auto_in_1_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_source = auto_in_1_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_sink = auto_in_1_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_denied = auto_in_1_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_data = auto_in_1_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_1_d_bits_corrupt = auto_in_1_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_in_0_a_ready = auto_in_0_a_ready_0; // @[Buffer.scala:40:9] assign auto_in_0_d_valid = auto_in_0_d_valid_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_opcode = auto_in_0_d_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_param = auto_in_0_d_bits_param_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_size = auto_in_0_d_bits_size_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_source = auto_in_0_d_bits_source_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_sink = auto_in_0_d_bits_sink_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_denied = auto_in_0_d_bits_denied_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_data = auto_in_0_d_bits_data_0; // @[Buffer.scala:40:9] assign auto_in_0_d_bits_corrupt = auto_in_0_d_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_18_a_valid = auto_out_18_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_opcode = auto_out_18_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_param = auto_out_18_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_size = auto_out_18_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_source = auto_out_18_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_address = auto_out_18_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_mask = auto_out_18_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_data = auto_out_18_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_18_a_bits_corrupt = auto_out_18_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_18_b_ready = auto_out_18_b_ready_0; // @[Buffer.scala:40:9] assign auto_out_18_c_valid = auto_out_18_c_valid_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_opcode = auto_out_18_c_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_param = auto_out_18_c_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_size = auto_out_18_c_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_source = auto_out_18_c_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_address = auto_out_18_c_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_data = auto_out_18_c_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_18_c_bits_corrupt = auto_out_18_c_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_18_d_ready = auto_out_18_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_18_e_valid = auto_out_18_e_valid_0; // @[Buffer.scala:40:9] assign auto_out_18_e_bits_sink = auto_out_18_e_bits_sink_0; // @[Buffer.scala:40:9] assign auto_out_17_a_valid = auto_out_17_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_opcode = auto_out_17_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_param = auto_out_17_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_size = auto_out_17_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_source = auto_out_17_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_address = auto_out_17_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_mask = auto_out_17_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_data = auto_out_17_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_17_a_bits_corrupt = auto_out_17_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_17_d_ready = auto_out_17_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_16_a_valid = auto_out_16_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_opcode = auto_out_16_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_param = auto_out_16_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_size = auto_out_16_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_source = auto_out_16_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_address = auto_out_16_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_mask = auto_out_16_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_data = auto_out_16_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_16_a_bits_corrupt = auto_out_16_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_16_d_ready = auto_out_16_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_15_a_valid = auto_out_15_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_opcode = auto_out_15_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_param = auto_out_15_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_size = auto_out_15_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_source = auto_out_15_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_address = auto_out_15_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_mask = auto_out_15_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_data = auto_out_15_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_15_a_bits_corrupt = auto_out_15_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_15_d_ready = auto_out_15_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_14_a_valid = auto_out_14_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_opcode = auto_out_14_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_param = auto_out_14_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_size = auto_out_14_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_source = auto_out_14_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_address = auto_out_14_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_mask = auto_out_14_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_data = auto_out_14_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_14_a_bits_corrupt = auto_out_14_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_14_d_ready = auto_out_14_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_13_a_valid = auto_out_13_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_opcode = auto_out_13_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_param = auto_out_13_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_size = auto_out_13_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_source = auto_out_13_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_address = auto_out_13_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_mask = auto_out_13_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_data = auto_out_13_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_13_a_bits_corrupt = auto_out_13_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_13_d_ready = auto_out_13_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_12_a_valid = auto_out_12_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_opcode = auto_out_12_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_param = auto_out_12_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_size = auto_out_12_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_source = auto_out_12_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_address = auto_out_12_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_mask = auto_out_12_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_data = auto_out_12_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_12_a_bits_corrupt = auto_out_12_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_12_d_ready = auto_out_12_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_11_a_valid = auto_out_11_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_opcode = auto_out_11_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_param = auto_out_11_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_size = auto_out_11_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_source = auto_out_11_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_address = auto_out_11_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_mask = auto_out_11_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_data = auto_out_11_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_11_a_bits_corrupt = auto_out_11_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_11_d_ready = auto_out_11_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_10_a_valid = auto_out_10_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_opcode = auto_out_10_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_param = auto_out_10_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_size = auto_out_10_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_source = auto_out_10_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_address = auto_out_10_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_mask = auto_out_10_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_data = auto_out_10_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_10_a_bits_corrupt = auto_out_10_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_10_d_ready = auto_out_10_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_9_a_valid = auto_out_9_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_opcode = auto_out_9_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_param = auto_out_9_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_size = auto_out_9_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_source = auto_out_9_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_address = auto_out_9_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_mask = auto_out_9_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_data = auto_out_9_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_9_a_bits_corrupt = auto_out_9_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_9_d_ready = auto_out_9_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_8_a_valid = auto_out_8_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_opcode = auto_out_8_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_param = auto_out_8_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_size = auto_out_8_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_source = auto_out_8_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_address = auto_out_8_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_mask = auto_out_8_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_data = auto_out_8_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_8_a_bits_corrupt = auto_out_8_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_8_d_ready = auto_out_8_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_7_a_valid = auto_out_7_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_opcode = auto_out_7_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_param = auto_out_7_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_size = auto_out_7_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_source = auto_out_7_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_address = auto_out_7_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_mask = auto_out_7_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_data = auto_out_7_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_7_a_bits_corrupt = auto_out_7_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_7_d_ready = auto_out_7_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_6_a_valid = auto_out_6_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_opcode = auto_out_6_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_param = auto_out_6_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_size = auto_out_6_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_source = auto_out_6_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_address = auto_out_6_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_mask = auto_out_6_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_data = auto_out_6_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_6_a_bits_corrupt = auto_out_6_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_6_d_ready = auto_out_6_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_5_a_valid = auto_out_5_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_opcode = auto_out_5_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_param = auto_out_5_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_size = auto_out_5_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_source = auto_out_5_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_address = auto_out_5_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_mask = auto_out_5_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_data = auto_out_5_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_5_a_bits_corrupt = auto_out_5_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_5_d_ready = auto_out_5_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_4_a_valid = auto_out_4_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_opcode = auto_out_4_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_param = auto_out_4_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_size = auto_out_4_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_source = auto_out_4_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_address = auto_out_4_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_mask = auto_out_4_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_data = auto_out_4_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_4_a_bits_corrupt = auto_out_4_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_4_d_ready = auto_out_4_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_3_a_valid = auto_out_3_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_opcode = auto_out_3_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_param = auto_out_3_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_size = auto_out_3_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_source = auto_out_3_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_address = auto_out_3_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_mask = auto_out_3_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_data = auto_out_3_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_3_a_bits_corrupt = auto_out_3_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_3_d_ready = auto_out_3_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_2_a_valid = auto_out_2_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_opcode = auto_out_2_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_param = auto_out_2_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_size = auto_out_2_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_source = auto_out_2_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_address = auto_out_2_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_mask = auto_out_2_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_data = auto_out_2_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_2_a_bits_corrupt = auto_out_2_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_2_d_ready = auto_out_2_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_1_a_valid = auto_out_1_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_opcode = auto_out_1_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_param = auto_out_1_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_size = auto_out_1_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_source = auto_out_1_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_address = auto_out_1_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_mask = auto_out_1_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_data = auto_out_1_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_1_a_bits_corrupt = auto_out_1_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_1_d_ready = auto_out_1_d_ready_0; // @[Buffer.scala:40:9] assign auto_out_0_a_valid = auto_out_0_a_valid_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_opcode = auto_out_0_a_bits_opcode_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_param = auto_out_0_a_bits_param_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_size = auto_out_0_a_bits_size_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_source = auto_out_0_a_bits_source_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_address = auto_out_0_a_bits_address_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_mask = auto_out_0_a_bits_mask_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_data = auto_out_0_a_bits_data_0; // @[Buffer.scala:40:9] assign auto_out_0_a_bits_corrupt = auto_out_0_a_bits_corrupt_0; // @[Buffer.scala:40:9] assign auto_out_0_d_ready = auto_out_0_d_ready_0; // @[Buffer.scala:40:9] endmodule