id
int64 0
39
| language
stringclasses 1
value | instruction
stringclasses 10
values | sleigh_code
stringlengths 83
242
| sleigh_comments
stringlengths 54
101
⌀ | functionality
float64 | documentation.official_documentation
stringclasses 1
value | documentation.processor
stringclasses 1
value | documentation.instruction_details
stringlengths 47
626
⌀ | documentation.feature
stringclasses 1
value | documentation.opcode
stringlengths 4
10
| documentation.example_usage
stringlengths 53
209
| documentation.possible_exceptions
stringclasses 7
values | annotations.complexity
float64 | annotations.use_cases
float64 | annotations.known_issues
float64 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | Sleigh | mov | :mov rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0011
{
rn_08_11 = rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0110 | void MOV (int m, int n)
{
R[n] = R[m];
PC += 2;
} | null | null | null | null |
1 | Sleigh | mov | :mov imm8,rn_08_11 is opcode_12_15=0b1110 & rn_08_11 & imm8
{
rn_08_11 = imm8;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Stores immediate data, sign-extended to longword, in general register Rn. | Data Transfer Instruction | 1110 | void MOVI (int i, int n)
{
if ((i & 0x80) == 0)
R[n] = (0x000000FF & i);
else
R[n] = (0xFFFFFF00 | i);
PC += 2;
} | null | null | null | null |
2 | Sleigh | movi20 | :movi20 simm20, l_rn_24_27
is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0000 & simm20
{
l_rn_24_27 = simm20;
} | # MOVI20 #imm20, Rn 0000nnnniiii0000 iiiiiiiiiiiiiiii imm → sign extension → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Stores immediate data that has been sign-extended to longword in general register Rn. | Data Transfer Instruction | 0b0000 | void MOVI20 (int i, int n)
{
if (i & 0x00080000) == 0)
R[n] = (0x000FFFFF & (long)i);
else
R[n] = (0xFFF00000 | (long)i);
PC += 4;
}
| null | null | null | null |
3 | Sleigh | movi20s | :movi20s simm20s, l_rn_24_27
is l_opcode_28_31=0b0000 & l_rn_24_27 & l_opcode_16_19=0b0001 & simm20s
{
l_rn_24_27 = simm20s;
} | # MOVI20S #imm20, Rn 0000nnnniiii0001 iiiiiiiiiiiiiiii imm<<8 → sign extension → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Shifts immediate data 8 bits to the left and performs sign extension to longword, then stores the resulting data in general register Rn. Using an OR or ADD instruction as the next instruction enables a 28-bit absolute address to be generated. | Data Transfer Instruction | 0b0000 | void MOVI20S (int i, int n)
{
if (i & 0x00080000) == 0)
R[n] = (0x000FFFFF & (long)i);
else
R[n] = (0xFFF00000 | (long)i);
R[n] <<= 8;
PC += 4;
} | null | null | null | null |
4 | Sleigh | mova | :mova disppc4,r0 is r0 & opcode_08_15=0b11000111 & disppc4
{
r0 = disppc4;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Stores the effective address of the source operand into general register R0. The 8-bit displacement is zero-extended and quadrupled. Consequently, the relative interval from the operand is PC + 1020 bytes. The PC is the address four bytes after this instruction, but the lowest two bits of the PC are fixed at 00.
Note
SH1*, SH2*, SH3*:
If this instruction is placed immediately after a delayed branch instruction, the PC must point to an address specified by (the starting address of the branch destination) + 2.
SH4*:
If this instruction is executed in a delay slot, a slot illegal instruction exception will be generated. | Data Transfer Instruction | 0b11000111 | void MOVA (int d)
{
unsigned int disp;
disp = (unsigned int)(0x000000FF & d);
R[0] = (PC & 0xFFFFFFFC) + 4 + (disp << 2);
PC += 2;
} | Slot illegal instruction | null | null | null |
5 | Sleigh | mov.w | :mov.w disppc2,rn_08_11 is opcode_12_15=0b1001 & rn_08_11 & disppc2
{
rn_08_11 = sext(*:2 disppc2);
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 2). The 8-bit displacement is multiplied by two after zero-extension, and so the relative distance from the table is in the range up to PC + 4 + 510 bytes. The PC value is the address of this instruction.
Note
If the following instruction is a branch instruction, it is identified as a slot illegal instruction. | Data Transfer Instruction | 0b1001 | void MOVWI (int d, int n)
{
unsigned int disp = (0x000000FF & d);
R[n] = Read_16 (PC + 4 + (disp << 1));
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
} | Data TLB multiple-hit exception
Slot illegal instruction exception
Data TLB miss exception
Data TLB protection violation exception | null | null | null |
6 | Sleigh | mov.l | :mov.l disppc4,rn_08_11 is opcode_12_15=0b1101 & rn_08_11 & disppc4
{
rn_08_11 = *:4 disppc4;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Stores immediate data, sign-extended to longword, in general register Rn. The data is stored from memory address (PC + 4 + displacement * 4). The 8-bit displacement is multiplied by four after zero-extension, and so the relative distance from the operand is in the range up to PC + 4 + 1020 bytes. The PC value is the address of this instruction. A value with the lower 2 bits adjusted to 00 is used in address calculation.
Note
If the following instruction is a branch instruction, it is identified as a slot illegal instruction. | Data Transfer Instruction | 0b1101 | void MOVLI (int d, int n)
{
unsigned int disp = (0x000000FF & d);
R[n] = Read_32 ((PC & 0xFFFFFFFC) + 4 + (disp << 2));
PC += 2;
} | Data TLB multiple-hit exception
Slot illegal instruction exception
Data TLB miss exception
Data TLB protection violation exception | null | null | null |
7 | Sleigh | mov.b | :mov.b @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000
{
rn_08_11 = sext(*:1 rm_04_07);
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0b0110 | void MOVBL (int m, int n)
{
R[n] = Read_8 (R[m]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
8 | Sleigh | mov.w | :mov.w @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001
{
rn_08_11 = sext(*:2 rm_04_07);
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0b0110 | void MOVWL (int m, int n)
{
R[n] = Read_16 (R[m]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
9 | Sleigh | mov.l | :mov.l @rm_04_07,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010
{
rn_08_11 = *:4 rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination | Data Transfer Instruction | 0b0110 | void MOVLL (int m, int n)
{
R[n] = Read_32 (R[m]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
10 | Sleigh | mov.b | :mov.b rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0000
{
*:1 rn_08_11 = rm_04_07:1;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0010 | void MOVBS (int m, int n)
{
Write_8 (R[n], R[m]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
11 | Sleigh | mov.w | :mov.w rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0001
{
*:2 rn_08_11 = rm_04_07:2;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0010 | void MOVWS (int m, int n)
{
Write_16 (R[n], R[m]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
12 | Sleigh | mov.l | :mov.l rm_04_07,@rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0010
{
*:4 rn_08_11 = rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0010 | void MOVLS (int m, int n)
{
Write_32 (R[n], R[m]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
13 | Sleigh | mov.b | :mov.b @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100 & (opcode_04_07=opcode_08_11)
{
rn_08_11 = sext(*:1 rm_04_07);
} | the following two instructions share the same opcodes but differ if rm == rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0110 | void MOVBP (int m, int n)
{
R[n] = Read_8 (R[m]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
if (n != m)
R[m] += 1;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
14 | Sleigh | mov.w | :mov.w @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101 & (opcode_04_07=opcode_08_11)
{
rn_08_11 = sext(*:2 rm_04_07);
} | the following two instructions share the same opcodes but differ if rm == rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination.The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0110 | void MOVWP (int m, int n)
{
R[n] = Read_16 (R[m]);
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
if (n != m)
R[m] += 2;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
15 | Sleigh | mov.l | :mov.l @rm_04_07+,rn_08_11 is opcode_12_15=0b0110 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110 & (opcode_04_07=opcode_08_11)
{
rn_08_11 = *:4 rm_04_07;
} | the following two instructions share the same opcodes but differ if rm == rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0110 | void MOVLP (int m, int n)
{
R[n] = Read_32 (R[m]);
if (n != m)
R[m] += 4;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
16 | Sleigh | mov.b | :mov.b rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0100
{
rn_08_11 = rn_08_11 -1;
*:1 rn_08_11 = rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0010 | void MOVBM (int m, int n)
{
Write_8 (R[n] - 1, R[m]);
R[n] -= 1;
PC += 2;
} | Data address error | null | null | null |
17 | Sleigh | mov.w | :mov.w rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0101
{
rn_08_11 = rn_08_11 -2;
*:2 rn_08_11 = rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0010 | void MOVWM (int m, int n)
{
Write_16 (R[n] - 2, R[m]);
R[n] -= 2;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
18 | Sleigh | mov.l | :mov.l rm_04_07,@-rn_08_11 is opcode_12_15=0b0010 & rn_08_11 & rm_04_07 & opcode_00_03=0b0110
{
rn_08_11 = rn_08_11 -4;
*:4 rn_08_11 = rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0010 | void MOVLM (int m, int n)
{
Write_32 (R[n] - 4, R[m]);
R[n] -= 4;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
19 | Sleigh | mov.b | :mov.b @-rm_08_11, r0
is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11001011
{
rm_08_11 = rm_08_11 - 1;
r0 = sext(*:1 (rm_08_11));
} | MOV.B @-Rm, R0 0100mmmm11001011 Rm - 1 → Rm, (Rm) → sign extension → R0 | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0100 | void MOVRSBM (int m)
{
R[m] -= 1;
R[0] = Read_16 (R[m]);
if ((R[0] & 0x80) == 0)
R[0] &= 0x000000FF;
else
R[0] |= 0xFFFFFF00;
PC+=2;
} | Data address error | null | null | null |
20 | Sleigh | mov.w | :mov.w @-rm_08_11, r0 is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11011011
{
rm_08_11 = rm_08_11 - 2;
r0 = sext(*:2 (rm_08_11));
} | MOV.W @-Rm, R0 0100mmmm11011011 Rm - 2 → Rm, (Rm) → sign extension → R0 | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0100 | void MOVRSWM (int m)
{
R[m]-= 2;
R[0] = Read_16 (R[m]);
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
} | Data address error | null | null | null |
21 | Sleigh | mov.l | :mov.l @-rm_08_11, r0
is r0 & opcode_12_15=0b0100 & rm_08_11 & opcode_00_07=0b11101011
{
rm_08_11 = rm_08_11 - 4;
r0 = *:4 (rm_08_11);
} | MOV.L @-Rm, R0 0100mmmm11101011 Rm - 4 → Rm, (Rm) → R0 | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination.. | Data Transfer Instruction | 0100 | void MOVRSLM (int m)
{
R[m] -= 4;
R[0] = Read_32 (R[m]);
PC += 2;
} | Data address error | null | null | null |
22 | Sleigh | mov.b | :mov.b r0, @rn_08_11+
is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10001011
{
*:1 (rn_08_11) = r0;
rn_08_11 = rn_08_11 + 1;
} | MOV.B R0, @Rn+ 0100nnnn10001011 R0 → (Rn), Rn + 1 → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0100 | void MOVRSBP (int n)
{
Write_8 (R[n], R[0]);
R[n] += 1;
PC += 2;
} | Data address error | null | null | null |
23 | Sleigh | mov.w | :mov.w r0, @rn_08_11+
is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10011011
{
*:2 (rn_08_11) = r0;
rn_08_11 = rn_08_11 + 2;
} | MOV.W R0, @Rn+ 0100nnnn10011011 R0 → (Rn), Rn + 2 → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0100 | void MOVRSWP (int n)
{
Write_16 (R[n], R[0]);
R[n] += 2;
PC += 2;
} | Data address error | null | null | null |
24 | Sleigh | mov.l | :mov.l r0, @rn_08_11+
is r0 & opcode_12_15=0b0100 & rn_08_11 & opcode_00_07=0b10101011
{
*:4 (rn_08_11) = r0;
rn_08_11 = rn_08_11 + 4;
} | MOV.L R0, @Rn+ 0100nnnn10101011 R0 → (Rn), Rn + 4 → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. | Data Transfer Instruction | 0100 | void MOVRSLP (int n)
{
Write_32 (R[n], R[0]);
R[n] += 4;
PC += 2;
} | Data address error | null | null | null |
25 | Sleigh | mov.b | :mov.b @(disp_00_03,rm_04_07),r0 is r0 & opcode_08_15=0b10000100 & rm_04_07 & disp_00_03
{
r0 = sext(*:1 (disp_00_03 + rm_04_07));
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. The 4-bit displacement is only zero-extended, so a range up to +15 bytes can be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 10000100 | void MOVBL4 (int m, int d)
{
long disp = (0x0000000F & (long)d);
R[0] = Read_8 (R[m] + disp);
if ((R[0] & 0x80) == 0)
R[0] &= 0x000000FF;
else
R[0] |= 0xFFFFFF00;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
26 | Sleigh | mov.b | :mov.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27 is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0100 & l_disp_00_11
{
l_rn_24_27 = sext(*:1 (l_rm_20_23 + l_disp_00_11));
} | MOV.B @(disp12, Rm), Rn 0011nnnnmmmm0001 0100dddddddddddd (disp+Rm) → sign extension → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0011 | void MOVBL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_8 (R[m] + disp);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else
R[n] |= 0xFFFFFF00;
PC += 4;
} | Data address error | null | null | null |
27 | Sleigh | movu.b | :movu.b @(l_disp_00_11, l_rm_20_23), l_rn_24_27
is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1000 & l_disp_00_11
{
l_rn_24_27 = zext(*:1 (l_disp_00_11 + l_rm_20_23));
} | MOVU.B @(disp12,Rm), Rn 0011nnnnmmmm0001 1000dddddddddddd (disp+Rm) → zero extension → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0011 | void MOVBUL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_8 (R[m] + disp);
R[n] &= 0x000000FF;
PC += 4;
} | null | null | null | null |
28 | Sleigh | mov.w | :mov.w @(disp,rm_04_07),r0 is r0 & opcode_08_15=0b10000101 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ]
{
r0 = sext(*:2 (disp + rm_04_07));
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. The 4-bit displacement is multiplied by two after zero-extension, enabling a range up to +30 bytes to be specified. If a memory operand cannot be reached, the @(R0,Rn) mode can be used instead. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 10000101 | void MOVWL4 (int m, int d)
long disp = (0x0000000F & (long)d);
R[0] = Read_16 (R[m] + (disp << 1));
if ((R[0] & 0x8000) == 0)
R[0] &= 0x0000FFFF;
else
R[0] |= 0xFFFF0000;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
29 | Sleigh | mov.w | :mov.w @(disp, l_rm_20_23), l_rn_24_27
is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0101 & l_disp_00_11
[ disp = 2*l_disp_00_11; ]
{
l_rn_24_27 = sext(*:2 (l_rm_20_23 + disp));
} | MOV.W @(disp12, Rm), Rn 0011nnnnmmmm0001 0101dddddddddddd (disp×2+Rm) → sign extension → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | Transfers the source operand to the destination. This instruction is ideal for data access in a structure or the stack. The loaded data is sign-extended to 32 bit before being stored in the destination register. | Data Transfer Instruction | 0011 | void MOVWL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_16 (R[m] + (disp << 1));
if ((R[n] & 0x8000) == 0)
R[n] &= 0x0000FFFF;
else
R[n] |= 0xFFFF0000;
PC += 4;
} | Data address error | null | null | null |
30 | Sleigh | movu.w | :movu.w @(disp, l_rm_20_23), l_rn_24_27
is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b1001 & l_disp_00_11
[ disp = l_disp_00_11 * 2; ]
{
l_rn_24_27 = zext(*:2 (disp + l_rm_20_23));
} | MOVU.W @(disp12,Rm), Rn 0011nnnnmmmm0001 1001dddddddddddd (disp×2+Rm) → zero extension → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0011 | void MOVWUL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_16 (R[m] + (disp << 1));
R[n] &= 0x0000FFFF;
PC += 4;
} | null | null | null | null |
31 | Sleigh | mov.l | :mov.l @(disp,rm_04_07),rn_08_11 is opcode_12_15=0b0101 & rn_08_11 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 2; ]
{
rn_08_11 = *:4 (disp + rm_04_07);
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0101 | void MOVLL4 (int m, int d, int n)
{
long disp = (0x0000000F & (long)d);
R[n] = Read_32 (R[m] + (disp << 2));
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
32 | Sleigh | 0011 | :mov.l @(disp, l_rm_20_23), l_rn_24_27
is l_opcode_28_31=0b011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0110 & l_disp_00_11
[ disp = (4*l_disp_00_11); ]
{
l_rn_24_27 = *:4 (l_rm_20_23 + disp);
} | MOV.L @(disp12, Rm), Rn 0011nnnnmmmm0001 0110dddddddddddd (disp×4+Rm) → Rn | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0011 | void MOVLL12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
R[n] = Read_32 (R[m] + (disp << 2));
PC += 4;
} | Data address error | null | null | null |
33 | Sleigh | mov.b | :mov.b r0,@(disp_00_03,rn_04_07) is r0 & opcode_08_15=0b10000000 & rn_04_07 & disp_00_03
{ *:1 (rn_04_07 + disp_00_03) = r0:1;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 10000000 | void MOVBS4 (int d, int n)
{
long disp = (0x0000000F & (long)d);
Write_8 (R[n] + disp, R[0]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
34 | Sleigh | mov.b | :mov.b l_rm_20_23, @(l_disp_00_11, l_rn_24_27) is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0000 & l_disp_00_11
{
*:1 (l_rn_24_27 + l_disp_00_11) = l_rm_20_23;
} | MOV.B Rm, @(disp12, Rn) 0011nnnnmmmm0001 0000dddddddddddd Rm -> (disp+Rn) | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0011 | void MOVBS12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
Write_8 (R[n] + disp, R[m]);
PC += 4;
} | Data address error | null | null | null |
35 | Sleigh | mov.w | :mov.w r0,@(disp,rn_04_07) is r0 & opcode_08_15=0b10000001 & rn_04_07 & disp_00_03 [ disp = disp_00_03 << 1; ]
{
*:2 (rn_04_07 + disp) = r0:2;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 10000001 | void MOVWS4 (int d, int n)
{
long disp = (0x0000000F & (long)d);
Write_16 (R[n] + (disp << 1), R[0]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
36 | Sleigh | mov.w | :mov.w l_rm_20_23, @(disp, l_rn_24_27)
is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0001 & l_disp_00_11
[ disp = 2*l_disp_00_11; ]
{
*:2 (l_rn_24_27 + disp) = l_rm_20_23;
} | MOV.W Rm, @(disp12, Rn) 0011nnnnmmmm0001 0001dddddddddddd Rm → (disp×2+Rn) | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0011 | void MOVWS12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
Write_16 (R[n] + (disp << 1), R[m]);
PC += 4;
} | Data address error | null | null | null |
37 | Sleigh | mov.l | :mov.l rm_04_07,@(disp,rn_08_11) is opcode_12_15=0b0001 & rn_08_11 & rm_04_07 & disp_00_03 [ disp = disp_00_03 << 2; ]
{
*:4 (rn_08_11 + disp) = rm_04_07;
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0001 | void MOVLS4 (int m, int d, int n)
{
long disp = (0x0000000F & (long)d);
Write_32 (R[n] + (disp << 2), R[m]);
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error
Initial page write exception | null | null | null |
38 | Sleigh | mov.l | :mov.l l_rm_20_23, @(disp, l_rn_24_27)
is l_opcode_28_31=0b0011 & l_rn_24_27 & l_rm_20_23 & l_opcode_16_19=0b0001 & l_opcode_12_15=0b0010 & l_disp_00_11
[ disp = 4*l_disp_00_11; ]
{
*:4 (l_rn_24_27 + disp) = l_rm_20_23;
} | MOV.L Rm, @(disp12, Rn) 0011nnnnmmmm0001 0010dddddddddddd Rm → (disp×4+Rn) | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0011 | void MOVLS12 (int d, int m, int n)
{
long disp = (0x00000FFF & (long)d);
Write_32 (R[n] + (disp << 2), R[m]);
PC += 4;
} | Data address error | null | null | null |
39 | Sleigh | mov.b | :mov.b @(r0,rm_04_07),rn_08_11 is r0 & opcode_12_15=0b0000 & rn_08_11 & rm_04_07 & opcode_00_03=0b1100
{
rn_08_11 = sext(*:1 (rm_04_07 + r0));
} | null | null | Renesas 32-Bit RISC Microcomputer SuperH | SuperH | null | Data Transfer Instruction | 0000 | void MOVBL0 (int m, int n)
{
R[n] = Read_8 (R[m] + R[0]);
if ((R[n] & 0x80) == 0)
R[n] &= 0x000000FF;
else R[n] |= 0xFFFFFF00;
PC += 2;
} | Data TLB multiple-hit exception
Data TLB miss exception
Data TLB protection violation exception
Data address error | null | null | null |
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