Patent Document ID: 8949519
Application ID: 12507682
Patent Status: 1

Claim One:
1. A memory apparatus, comprising: a plurality of first memory circuits, each of the first memory circuits being associated with a first latency specific to a first operation; and an interface circuit coupled to the plurality of first memory circuits, the interface circuit being operable to: simulate one or more second simulated memory circuits such that the plurality of first memory circuits appears to a host system as the one or more second simulated memory circuits, each second simulated memory circuit having at least one aspect that is different from at least one corresponding aspect of at least one first memory circuit of the plurality of first memory circuits, where the at least one aspect includes a second latency specific to the first operation that is larger than the first latency; receive first signals from the host system to be used in the first operation; receive second signals from the host system, wherein a difference in timing between the first signals and the second signals received from the host system satisfies the second latency associated with the second simulated memory circuits; based on the second latency associated with the second simulated memory circuits, determine a variable delay for sending the first signals to one or more first memory circuits of the plurality of first memory circuits, wherein the variable delay is determined such that a difference in timing between the first signals and the second signals sent to the one or more first memory circuits satisfies the first latency; apply the variable delay to send the first signals to the one or more first memory circuits of the plurality of first memory circuits; and send the second signals to the one or more first memory circuits of the plurality of first memory circuits such that the difference in timing between the first signals and the second signals sent to the one or more first memory circuits satisfies the first latency.