Patent Document ID: 20040041249
Application ID: 10232729
Patent Status: 0

Claim One:
1. A stacked chip package comprising: a substrate having an upper surface, a lower surface and a through hole extended from the upper surface to the lower surface; a first chip having an active side and an inactive side, the first chip being received in the through hole of the substrate in such a way that the active side of the first chip and the upper surface of the substrate face to a same direction, the active side electrically connected to the upper surface of the substrate through first bonding wires; a thermally and electrically conductive adhesive layer disposed on the inactive side of the first chip and the lower surface of the substrate in a completely enclosing way around the through hole; a thermally and electrically conductive planar member having an upper surface and a lower surface, the planar member being attached to the adhesive layer with the upper surface thereof; a first encapsulant being disposed on the active side of the first chip; a second chip having an active side and an inactive side, the second chip being attached to the first encapsulant with the inactive side thereof, the active side of the second chip electrically connected to the upper surface of the substrate through second bonding wires; a second encapsulant being disposed on the upper surface of the substrate, the second encapsulant covering the first chip, the first bonding wires, the first encapsulant, the second chip and the second bonding wires, the second encapsulant also filling the through hole; and a plurality of solder balls being electrically connected to the lower surface of the substrate.