Patent Document ID: 20160378888
Application ID: 14748643
Patent Status: 0

Claim One:
1. A system comprising: a memory storing a base model and a design layout, the base model being for modeling a performance attribute of a transistor and comprising a model parameter and a model parameter adjuster for the model parameter, the design layout being for an integrated circuit and defining, within a design of the integrated circuit, placement of the transistor, placement of a local layout effect-inducing feature adjacent to the transistor and a shape that is non-uniform and that extends between a side of a channel region of the transistor and an edge of the local layout effect-inducing feature, the edge of the local layout effect-inducing feature being non-linear such that different points on the edge are separated from the side by different distances; and, a processor accessing the base model and the design layout from the memory, the processor extracting layout information from the design layout, the layout information comprising at least a minimum distance between the side and the edge, a maximum distance between the side and the edge, a maximum width of the shape and an area of the shape, the processor further determining a first width of a first portion of the shape associated with the maximum distance and a second width of a second portion of the shape associated with the minimum distance, based on the layout information, the processor further calculating a value for the model parameter adjuster, based on the maximum distance, the first width, the minimum distance and the second width, and the processor further using the base model with the model parameter adjuster set at the value to generate a compact model that models the performance attribute of the transistor within the integrated circuit.