Patent Document ID: 8751976
Application ID: 13534300
Patent Status: 1

Claim One:
1. An integrated circuit (IC) method comprising: building a pattern bank including a pattern having an area of interest; receiving a data file including an IC design layout; recognizing that the pattern of the pattern bank corresponds to a pattern of the IC design layout; identifying an area of interest of the pattern of the IC design layout that corresponds to the area of interest of the pattern of the pattern bank; performing pattern recognition dissection on the area of interest of the pattern of the IC design layout to dissect edges of the area of interest of the pattern of the IC design layout into a plurality of segments; after performing pattern recognition dissection, performing pattern recognition retargeting of the pattern of the IC design layout to assign a plurality of target points to the plurality of segments of the area of interest of the pattern of the IC design layout; after performing pattern recognition retargeting, performing, using a computer, an optical proximity correction (OPC) to the IC design layout; and producing a modified IC design layout based on the IC design layout that has been performed by the OPC and the pattern recognition retargeting.