Patent Document ID: 10055531
Application ID: 14622009
Patent Status: 1

Claim One:
1. A layout checking method performed by at least one processor, comprising: analyzing, by the at least one processor, spaces among a plurality of layout segments of an integrated circuit to determine at least one first-type conflicted edge according to a first predetermined length; analyzing, by the at least one processor, spaces among the plurality of layout segments of the integrated circuit to determine a plurality of potential conflicted edges according to a second predetermined length different from the first predetermined length; determining, by the at least one processor, at least one second-type conflicted edge according to the plurality of potential conflicted edges; checking, by the at least one processor, if at least one odd-vertex loop is formed in the plurality of layout segments according to the at least one first-type conflicted edge and the at least one second-type conflicted edge to determine if a violation occurs in the plurality of layout segments; wherein analyzing spaces among the plurality of layout segments of the integrated circuit to determine the at least one first-type conflicted edge according to the first predetermined length comprises: analyzing spaces among the plurality of layout segments of the integrated circuit to determine a plurality of third-type conflicted edges according to the first predetermined length; grouping the plurality of layout segments into a plurality of independent groups according to the plurality of third-type conflicted edges; grouping each independent group in the plurality of independent groups into a first sub-group and a second sub-group; and for the first sub-group and the second sub-group in each independent group in the plurality of independent groups, defining one first-type conflicted edge in between the first sub-group and the second sub-group; and causing the first sub-group and the second sub-group to be fabricated by a first mask and a second mask, respectively, wherein the first mask is different from the second mask; wherein no third-type conflicted edge exists in the first sub-group and the second sub-group, no third-type conflicted edge exists between two independent groups in the plurality of independent groups, and, for at least one independent group in the plurality of independent groups, the at least one independent group comprises a plurality of related layout segments where each related layout segment forms a third type conflicted edge with at least one adjacent related layout segment in the plurality of related layout segments.