Patent Document ID: 9195395
Application ID: 14589934
Patent Status: 1

Claim One:
1. An apparatus, comprising: NAND flash memory; random access memory; a first circuit for receiving DDR signals and outputting SATA signals; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a first memory bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a second memory bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said first circuit capable of being communicatively coupled to a third memory bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; said apparatus configured for: receiving, over the third memory bus associated with the DDR protocol, a command that enables DDR protocol-compliant communication via the third memory bus for controlling the second circuit to cause one or more results that are undescribed in a specification of a JEDEC standard, after the receipt of the command, causing at least one of the results that is undescribed in the specification of the JEDEC standard, including causing particular data in the NAND flash memory to be written to the random access memory, utilizing the second circuit, and allowing a status in connection with the data.