Patent Document ID: 5459841
Application ID: 08174642
Patent Status: 1

Claim One:
1. In a microcomputer containing an implementation of a finite state machine (FSM) that controls a process wherein a plurality of input signals received by the FSM correspond to monitored process conditions and output signals generated by the FSM correspond to commands that effect changes in parameters associated with the process, the FSM having sets of selection vectors, and target vectors against which the sets of selection vectors are compared, logical data is selectively stored as binary bits in the selection vectors and target vectors, a method for minimizing time required by the microcomputer implemented FSM comprising the steps of: a) selecting selection vectors having a single bit that is set, said selection vector having a bit position associated with said single bit, said selected selection vectors defining a first group of vectors and unselected selection vectors defining a second group of vectors; b) generating for each of said selected selection vectors a corresponding index vector encoded with a flag and containing a binary number identifying the bit position of said single bit that was set; c) replacing said selected selection vector with said index vector; d) before comparing a target vector with one of said unselected selection vectors and index vectors, determining if said one vector contains said flag; e) if said one vector contains said flag, utilizing said binary number contained therein to identify a bit position in the corresponding target vector to which the comparison is to be made; f) if said one vector to be compared contains said flag, making a logical comparison by determining if said bit position in the target vector is TRUE, thus avoiding a bit by bit comparison of said target vector with said one vector and reducing the time required for such comparison.