Patent Document ID: 7979815
Application ID: 11970990
Patent Status: 1

Claim One:
1. A computer-implemented method for modeling performance of a semiconductor transistor device structure having an active device area, a gate structure, and including a conductive line feature connected to said gate structure and disposed above said active device area, said conductive line feature including a first conductive landing pad feature disposed near an edge of said active device area, the method comprising the steps of: a) modeling, by a processor device, said transistor device structure, said modeling including determining a polynomial function for calculating a lithographic rounding effect of said first landing pad feature as a function of distance between an edge defined by said first landing pad feature to an edge of said active device area; b) obtaining, by said processor device, a function representing a current flow modification created by said lithographic rounding effect as a function of an effective length of said conductive line feature; c) providing to said processor device said obtained current flow modification as a function of a width of said active device area; and, d) relating, by said processor device, an effective change in active device area width (deltaW adder) with a distance from an edge defined by said first landing pad feature to an edge of said active device area of the transistor device being modeled; and, e) updating, by said processor device, transistor model parameter values in a transistor compact model for said transistor device to include deltaW adder values to be added to a built-in deltaW value, wherein a netlist used in a simulation include the deltaW adder values to describe the characteristics of the transistor device, wherein effects of lithographic rounding effect of said first landing pad feature on transistor device parametrics is modeled.