Patent Document ID: 20090182448
Application ID: 12015077
Patent Status: 0

Claim One:
1. A method for optimizing a lithographic process for manufacturing semiconductor integrated circuits, the lithographic process including using an empirically calibrated process model, the method comprising: providing a calibration test structure; computing an optical image for said calibration test structure using an optical model; forming a printed image of said calibration test structure on a wafer using the lithographic process; determining measurement data from said printed calibration test structure and optical image parameters from said optical image at selected calibration points of said calibration test structure; providing a process model for determining a predicted on-wafer response value, said process model comprising a function of optical image parameters; calibrating said process model so that said predicted on-wafer response value predicts said measurement data within a predetermined metric; providing an uncertainty metric associated with said predicted on-wafer response value for a selected set of values of said optical image parameters, said uncertainty metric comprising a function of a distance metric between said selected set of optical image parameters and said optical image parameters at said selected calibration points; applying said process model to a non-calibration mask pattern to obtain a predicted non-calibration on-wafer response; and determining whether said uncertainty metric associated with said predicted non-calibration on-wafer response violates a predetermined criterion.