Patent Document ID: 20160117501
Application ID: 14981011
Patent Status: 0

Claim One:
1. A microprocessor comprising: a multistage instruction processing pipeline, configured to receive a sequence of instructions for processing, concurrently decode the received instructions, dispatch the instructions, and to produce at least one execution result comprising alteration of at least one register of the microprocessor external to the instruction processing pipeline selectively in response to execution of at least one instruction and an authorization signal; a memory configured to store at least a predetermined encrypted reference digital signature; decryption logic elements configured to decrypt the encrypted reference signature in dependence on a decryption key to produce a reference digital signature corresponding to an expected digital signature of an authentic sequence of instructions; verification logic elements configured to verify the reference digital signature against a digital signature of the received sequence of instructions; and authorization logic elements configured, within a first mode of operation, to selectively generate the authorization signal, contingent upon verification of the reference digital signature against the digital signature