Patent Document ID: 9502216
Application ID: 13756390
Patent Status: 1

Claim One:
1. A method for determining wafer bias, the method comprising: receiving, by a processor from an output of a generator, a generator output complex voltage and current, the generator coupled to an impedance matching circuit, the impedance matching circuit coupled via a radio frequency (RF) transmission line to an electrostatic chuck (ESC) of a plasma chamber; determining, by the processor, from the generator output complex voltage and current a projected complex voltage and current at a point along a path between an output of a model of the impedance matching circuit and a model of the ESC, the determining of the projected complex voltage and current performed using a model for at least part of the path, the model for at least part of the path characterizing physical components along the path, the model for at least part of the path including an RF transmission model of the RF transmission line, wherein the RF transmission model includes a model of an RF tunnel and a model of an RF strap, the RF tunnel model coupled with the RF strap model; and applying, by the processor, the projected complex voltage and current as an input to a function to map the projected complex voltage and current to a wafer bias value at the ESC model.