Patent Document ID: 9171585
Application ID: 14090342
Patent Status: 1

Claim One:
1. A sub-system, comprising: a first number of physical memory circuits including a first physical memory circuit and a second physical memory circuit, wherein each of the first number of physical memory circuits is limited by a device command scheduling constraint; and an interface circuit electrically coupling to each one of the first number of physical memory circuits via a respective distinct bus of multiple buses including a first bus connected to the first physical memory circuit and a distinct second bus connected to the second physical memory circuit, the interface circuit configured to: interface the first number of physical memory circuits to emulate a different, second number of virtual memory circuits, wherein the second number of virtual memory circuits includes a first virtual memory circuit emulated using at least the first physical memory circuit and the second physical memory circuit; present the different, second number of virtual memory circuits to a memory controller, wherein the first virtual memory circuit appears to the memory controller as free from the device command scheduling constraint of the first physical memory circuit and the second physical memory circuit; receive, from the memory controller, a row-activation command and multiple column-access commands directed to the first virtual memory circuit; determine, based on the row activation command and the multiple column-access commands, a first physical row-activation command and a first physical column-access command directed to the first physical memory circuit and a second physical row-activation command and a second physical column-access command directed to the second physical memory circuit; and issue, using the first bus and the second bus, the first physical row-activation command and the first physical column-access command to the first physical memory circuit and the second physical row activation command and the second physical column access command to the second physical memory circuit, wherein timings for the issued first and second physical row-activation commands and the issued first and second physical column-access commands satisfy the device command scheduling constraint.