Patent Document ID: 8341571
Application ID: 13042414
Patent Status: 1

Claim One:
1. A computer implemented method for creating a pattern signature for a pattern in an electronic circuit design, comprising: using at least one to perform a process, the process comprising: identifying or determining a multi-dimensional vector representation for the pattern in the electronic circuit design; generating a first set of one or more numbers by performing a first operation with at least a first operator upon the multi-dimensional vector representation for the pattern and a second set of one or more numbers by performing a second operation with at least a second operator upon the multi-dimensional vector representation for the pattern in the electronic circuit design, wherein the first operator comprises a projection operator, and the second operation is based at least in part on the first operation and further in part on the first set of one or more numbers to generate the second set of one or more numbers; and determining the pattern signature for the object in the electronic circuit design by combining the first set of one or more numbers and the second set of one or more numbers into the pattern signature.