Patent Document ID: 7802210
Application ID: 11654340
Patent Status: 1

Claim One:
1. A method of analyzing layouts of semiconductor integrated circuit devices, the method comprising the following steps performed by a system having a random fault rate calculation unit, a systematic fault rate calculation unit, a parametric fault rate calculation unit, an area based-fault rate calculation unit, and a control unit: calculating random fault rates, systematic fault rates, parametric fault rates, and areas of a plurality of layouts of interest, wherein calculating systematic fault rates comprises: a) determining a plurality of Design Of Experiment (DOE) rule values for a design rule; b) measuring DOE design rule-based fault rates; c) counting numbers of features corresponding to each of the DOE rule values in each of the layouts of interest; d) calculating a systematic fault rate of the design rule using the DOE rule value-based fault rates and the numbers of features; performing steps a)-d) for a plurality of design rules used in the layout of interest; and calculating the systematic fault rate of the layout of interest using a plurality of the calculated systematic fault rates of the design rules; calculating area-based fault rates of the plurality of layouts of interest using the random fault rates, the systematic fault rates, the parametric fault rates, and the areas; and selecting layouts of interest to be corrected from among the plurality of layouts of interest using the area-based fault rates.