Patent Document ID: 7805691
Application ID: 11586719
Patent Status: 1

Claim One:
1. A semiconductor failure analysis apparatus for analyzing a failure of a semiconductor device, comprising: inspection information acquiring means for acquiring a failure observed image containing reaction information arising from a failure, acquired by conducting an inspection about the failure, as an observed image of the semiconductor device; layout information acquiring means for acquiring layout information of the semiconductor device; and failure analyzing means for analyzing the failure of the semiconductor device with reference to the failure observed image and the layout information; wherein the failure analyzing means has region setting means for setting an analysis region in correspondence to the reaction information with reference to the failure observed image, and net information analyzing means for analyzing the failure as to a plurality of nets included in a layout of the semiconductor device, with reference to the analysis region; and wherein the net information analyzing means has first means for, when the region setting means sets a plurality of analysis regions, extracting candidate nets passing at least one of the analysis regions, out of the plurality of nets, and passage counts of the respective candidate nets through the analysis regions, second means for selecting a candidate net with the largest passage count as a first failure net, which is a likeliest suspect net, out of the extracted candidate nets, and third means for selecting, after selection of the first failure net, a second failure net, which is a next suspect net, with attention to analysis regions where the first failure net does not pass, wherein the third means in the net information analyzing means designates one analysis region out of the analysis regions where the first failure net does not pass, and selects the second failure net out of the candidate nets passing the designated analysis region.