Patent Document ID: 9754067
Application ID: 14665242
Patent Status: 1

Claim One:
1. A method of checking layout integrity, performed on a computer system having a processor and a memory coupled with the processor, the method comprising: receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when the layout is created, from one or more parameters of the device in the processor, wherein the signature is generated from a commutative mathematical operation of one or more parameters of each shape of the respective device, the signature further generated from the coordinates of polygon vertices, perimeter and areas of each of the shapes of the respective device, storing the generated signatures for the layout with the layout in the memory, receiving the stored layout and generated signatures from the memory, regenerating each signature for each device in the stored layout after receiving the stored layout and the generated signatures, comparing each regenerated signature with the corresponding stored signature, and providing an output for each regenerated signature that does not match the corresponding stored signature.