Patent Document ID: 20090172611
Application ID: 12339652
Patent Status: 0

Claim One:
1. A method of manufacturing a semiconductor device comprising: measuring an electrical characteristic of a plurality of semiconductor elements; defining layout parameters on the basis of layout data of the plurality of semiconductor elements and deciding a functional relationship between the layout parameters and the electrical characteristic; extracting values of the layout parameters from design layout data of the semiconductor device; calculating a predicted electrical characteristic of the semiconductor device on the basis of the values of the layout parameters and the functional relationship; calculating a difference between a target electrical characteristic and the predicted electrical characteristic of the semiconductor device; generating a plurality of candidates of the values of the layout parameters; selecting a specific value from among the candidates so as to decrease the difference between the target electrical characteristic and the predicted electrical characteristic; changing the design layout data on the basis of the specific value; and manufacturing the semiconductor device on the basis of the changed design layout data.