Patent Document ID: 20090064069
Application ID: 11942744
Patent Status: 0

Claim One:
1. A method for generating a layout for an integrated circuit having a plurality of sinks ( 330 ) and at least one source ( 310 ), the source ( 310 ) supplies a plurality of signals to the respective plurality of sinks ( 330 , 335 ), wherein a first logic ( 320 ) is defined by a synthesis step, and wherein during a first layout ( 8 ) generation procedure, a placement algorithm for placing a plurality of clones ( 310 a , 310 b ) associated with the source ( 310 ) on said first layout is performed, the method comprising: identifying ( 220 ) the source ( 310 ) which supplies at least one of said respective sinks ( 330 ) and having a negative slack; finding ( 230 ) all sinks having a negative slack ( 330 ) driven by the source ( 310 ); clustering ( 240 ) said sinks (M) according to timing and placement information read from a database, yielding a plurality of clusters ( 350 , 360 ) of sinks, in which each cluster includes only a predetermined portion (N) of said plurality of sinks (M); generating ( 250 ) a plurality of clones ( 310 a , 310 b ) associated with a respective one of said clusters of sinks ( 350 , 360 ); and coupling said clones to respective ones of said clusters of sinks( 350 and 360 ) yielding a second layout.