Patent Document ID: 20170169157
Application ID: 14967140
Patent Status: 0

Claim One:
1. A method of building a wire resistance corner model for an interconnect metal level in a semiconductor device, the method comprising: determining a first nominal on-wafer width and a first nominal wire thickness at a minimum design width of the interconnect metal level; determining a second nominal on-wafer width and a second nominal wire thickness at a maximum design width of the interconnect metal level; determining a first standard deviation and a second standard deviation for global variations in wire thickness and on-wafer width, respectively; determining a relation between resistance of the interconnect metal level and on-wafer width and thickness of the interconnect metal level; determining a set of maximum statistical corner values for interconnect wire resistance; computing a first corner solution that minimizes a first maximum absolute difference between a first model corner value and a first statistical corner value of the set of maximum statistical corner values in the range of the minimum design width and the maximum design width; determining a set of minimum statistical corner values for interconnect wire resistance; and computing a second corner solution that minimizes a second maximum absolute difference between a second model corner value and a second statistical corner value of the set of minimum statistical corner values in the range of the minimum design width and the maximum design width; wherein the semiconductor device is manufactured based on the first corner solution and the second corner solution.