Patent Document ID: 20070292018
Application ID: 11586721
Patent Status: 0

Claim One:
1. A semiconductor failure analysis apparatus for analyzing a failure of a semiconductor device, comprising: inspection information acquiring means for acquiring a failure observed image containing reaction information arising from a failure, acquired by conducting an inspection about the failure, as an observed image of the semiconductor device; layout information acquiring means for acquiring layout information of the semiconductor device; and failure analyzing means for analyzing the failure of the semiconductor device with reference to the failure observed image and the layout information; wherein the failure analyzing means has region setting means for setting an analysis region in correspondence to the reaction information with reference to the failure observed image, and interconnection information analyzing means for performing an analysis of a failure in a plurality of interconnections included in a layout of the semiconductor device, with reference to the analysis region; wherein the layout information contains interconnection information to describe a configuration of the plurality of interconnections in the semiconductor device by a pattern data group of interconnection patterns in respective layers in a layer structure of the semiconductor device; and wherein the interconnection information analyzing means extracts an interconnection passing the analysis region out of the plurality of interconnections, as a candidate interconnection for a failure and, for extracting the candidate interconnection, the interconnection information analyzing means performs an equipotential trace of the interconnection patterns using the pattern data group, thereby extracting the candidate interconnection.