Patent Document ID: 10007752
Application ID: 14804132
Patent Status: 1

Claim One:
1. A method for integrated circuit (IC) design, the method comprising: generating, by a computing system, a circuit device model that approximates performance of circuit devices having non-uniform gates due to sub-wavelength lithography effects associated with lithography processes used to fabricate the circuit devices, wherein the generating includes: identifying a gate of a circuit device to be modeled, wherein the gate has a thickness in a gate length direction that varies along a gate width direction, defining a set of gate slices corresponding to the gate, wherein each gate slice of the set of gate slices has a thickness in the gate length direction that corresponds to the thickness of the gate in the gate length direction at a corresponding location, determining a set of performance parameters, wherein each performance parameter corresponds with a respective gate slice of the set of gate slices, performing a curve fitting procedure to generate a set of location-dependent weighting parameters to apply to the set of performance parameters, wherein each location-dependent weighting parameter weights a respective performance parameter based on a location of the respective gate slice relative to edges of the gate that define the gate width; and wherein each location-dependent weighting parameter of the set of location-dependent weighting parameters is further based on an impact of a narrow width related edge effect, applying the set of location-dependent weighting parameters to the set of performance parameters, generating an estimated performance parameter from the location-dependent weighted set of performance parameters, verifying an accuracy of the set of location-dependent weighting parameters by comparing the estimated performance parameter of the circuit device to a simulated performance parameter of the circuit device, wherein the estimated performance parameter and the simulated performance parameter indicate a corresponding electrical characteristic of the circuit device, after verifying the accuracy, generating the circuit device model based on the set of location-dependent weighting parameters, wherein a matrix is utilized to determine the set of location-dependent weighting parameters by taking m samples from current-voltage (I-V) curves of the circuit device with n unknowns: [ I ⁡ ( v 1 ) I ⁡ ( v 2 ) ⋮ I ⁡ ( v m ) ] 3 ⁢ ⁢ D ≅ [ I 1 ⁡ ( v 1 ) I 2 ⁡ ( v 1 ) … I n ⁡ ( v 1 ) I 1 ⁡ ( v 2 ) I 2 ⁡ ( v 2 ) … I n ⁡ ( v 1 ) ⋮ ⋮ … ⋮ I 1 ⁡ ( v m ) I 2 ⁡ ( v m ) … I n ⁡ ( v m ) ] 2 ⁢ ⁢ D ⁡ [ W ⁡ ( α 1 ) W ⁡ ( α 2 ) ⋮ W ⁡ ( α n ) ] ; generating an IC design layout for the circuit device using the circuit device model, wherein the IC design layout is used for fabricating the circuit device; fabricating a mask based on the IC design layout; and fabricating the circuit device using the mask.