Patent Document ID: 8863044
Application ID: 14020089
Patent Status: 1

Claim One:
1. A semiconductor device design layout assessment method comprising: determining at least one candidate sparse coefficient for each of at least one candidate pattern; reconstructing, by using a computer, each candidate pattern using a sparse pattern dictionary D and the respective at least one candidate sparse coefficient to obtain a reconstructed candidate pattern, the sparse pattern dictionary D including a respective atom d k representing at least part of each of at least one compliant pattern y1 i known to comply with at least one feasibility parameter; determining a candidate reconstruction error for each reconstructed candidate pattern y2 i , the candidate reconstruction error being equal to the difference between each reconstructed candidate pattern and the respective candidate pattern; and flagging a candidate pattern responsive to at least one of a respective candidate reconstruction error exceeding a predefined maximum candidate reconstruction error value ε i max or a candidate pattern sparsity s of a reconstructed candidate coefficient vector x i * exceeding a predefined sparsity level s 0 as determined using the relationship: 
 x i *=min∥ y 2 i −Dx i ∥ l 2 subject to ∥ x i ∥ l o ≦s 0 , wherein the flagging of a candidate pattern includes flagging each candidate pattern for which the candidate reconstruction error exceeds a largest learning reconstruction error determined using the relationship: 
 ε i >C adj *max∥ y 1 i −Dx i ∥ l 2 , where C adj is a predefined adjustment constant whose value determines how different a candidate pattern y2 i has to be from the at least one compliant pattern y1 i to be flagged.