Patent Document ID: 9218448
Application ID: 14158968
Patent Status: 1

Claim One:
1. A method comprising: generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit, each of the plurality of multiple patterning decompositions comprising: a first pattern associated with a first mask; a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set; a width value associated with at least one of the first pattern or the second pattern; and a spacing value between the first pattern and the second pattern; and generating a file comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions, the plurality of dielectric constant values being based on the width values and the spacing values associated with the plurality of multiple patterning decompositions, wherein generating the file comprises: simulating, for at least some of the plurality of multiple patterning decompositions, a worst-case performance value yielding the plurality of dielectric constant values for the at least some of the plurality of multiple patterning decompositions; and populating the file with the worst-case performance value.