Patent Document ID: 7703060
Application ID: 11678069
Patent Status: 1

Claim One:
1. A method, performed on at least one computing device, the method comprising: obtaining from a first entity, using the at least one computing device, a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field at a second entity, wherein the IC chip layout comprises a plurality of stitched regions, wherein at least one stitched region includes: a boundary identification identifying a boundary of the at least one stitched region at which stitching occurs and a type indicator indicating whether the at least one stitched region is one of: redundant and unique; dissecting, using the at least one computing device, the IC chip layout into stitched regions indicated as unique or redundant at the second entity; and generating, using the at least one computing device, a photolithographic reticle at the second entity based on the plurality of stitched regions, the photolithographic reticle having a size that fits within the size of the photolithography tool field at the second entity.