Patent Document ID: 9182914
Application ID: 14589940
Patent Status: 1

Claim One:
1. An apparatus, comprising: a plurality of memories including NAND flash memory and random access memory; a first circuit for receiving DDR signals and outputting SATA signals, the first circuit capable of being communicatively coupled to a first bus associated with a DDR protocol including at least one of a DDR2 protocol, a DDR3 protocol, or a DDR4 protocol; and a second circuit for receiving the SATA signals and outputting NAND flash signals, the second circuit communicatively coupled to the first circuit via a second bus associated with a SATA protocol, the second circuit further communicatively coupled to the NAND flash memory via a third bus associated with a NAND flash protocol, the second circuit further communicatively coupled to the random access memory; said DDR protocol being operable for allowing a single complete read or write operation in response to a single read or write command; said apparatus configured for: receiving, at the first circuit via the first bus, a first command for initiating a particular single complete read or write operation in connection with particular information; after the receipt of the first command, making the particular information that is in one of the plurality of memories available in another one of the plurality of memories, utilizing the second circuit; and receiving, at the first circuit via the first bus, a second command for completing the particular single complete read or write operation in connection with the particular information.