Patent Document ID: 20120079439
Application ID: 13150964
Patent Status: 0

Claim One:
1. At a failure analysis computing device, a method for identifying a candidate defect region including a possible physical defect in a semiconductor device, the method comprising: receiving an electrical test mismatch reported for a scan chain; generating a physical representation of a portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating the candidate defect region, the candidate defect region being defined, via the physical representation, to include the physical instantiations of the logical cells and the logical interconnections included in the suspect logical region; and displaying the candidate defect region.