Patent Document ID: 8619452
Application ID: 11515223
Patent Status: 1

Claim One:
1. A memory device comprising: a plurality of dynamic random access memory (â€œDRAMâ€) integrated circuits stacked in a vertical direction; and a buffer integrated circuit for providing an interface between the plurality of DRAM integrated circuits and a memory bus by buffering at least one of address, control or data signals so as to isolate electrical loads of the plurality of DRAM integrated circuits from the memory bus, wherein the buffer integrated circuit is configured to perform conversion between signal timing of a first protocol at the memory bus and signal timing of a second protocol for accessing at least one of the plurality of DRAM integrated circuits, wherein the buffer integrated circuit is configured to track addresses of â€œmâ€ previous reads and compare an address of a current read with the tracked addresses of the â€œmâ€ previous reads.