Patent Document ID: 5475624
Application ID: 07876566
Patent Status: 1

Claim One:
1. A method for generating a record of faults detected by a pattern of test vectors applied to a logic device, comprising the steps of: a. creating a first emulation of a logic device; b. creating a second emulation of the logic device; c. selectively introducing a fault into the second emulation; d. applying a pattern of test vectors to the first emulation and to the second emulation, to thereby exercise the first emulation and the second emulation; e. comparing output signals produced by the first emulation and the second emulation in response to each test vector of the pattern, to thereby detect the selectively introduced fault by detecting any difference between the output signals; f. upon detection of the selectively introduced fault, producing a record identifying the fault introduced into the second emulation; and g. repeating steps c.-f. for each of a sequence of selectively introduced faults, to thereby produce a record identifying which faults of the sequence of faults result in differences between the output signals of the first emulation and the second emulation.