Patent Document ID: 9660845
Application ID: 14876378
Patent Status: 1

Claim One:
1. A method for reduced state trellis equalization, the method comprising: receiving, over an interface of a device, a signal carrying at least a current symbol and a trailing symbol over a system exhibiting channel memory, the current symbol being received before the trailing symbol, the current symbol being mapped to a current stage of a trellis and the trailing symbol being mapped to a next stage of the trellis; selecting, by a controller in the device, a subset of candidate states at the current stage of the trellis, the current stage of the trellis including the subset of candidate states and one or more remaining candidate states that are excluded from the subset of candidate states; computing, by an equalizer in the device, a first set of accumulated path metrics (APMs) for the subset of candidate states at the current stage of the trellis without computing APMs for the one or more remaining candidate states at the current stage of the trellis such that APMs are computed for fewer than all states at the current stage of the trellis; and decoding, by the equalizer, the trailing symbol using at least the APMs for the subset of candidate states of the current stage of the trellis.