Patent Document ID: 7885269
Application ID: 12147536
Patent Status: 1

Claim One:
1. At least one processor-accessible storage device that includes processor-executable instructions for network analysis with Steiner trees, wherein the processor-executable instructions, when executed by at least one processor, direct a vertex that includes the at least one processor to perform a method comprising: receiving data specifying a network wherein the data defines vertices that form the network, the vertices including the vertex; accepting Steiner tree parameters that designate terminal vertices included in a Steiner tree solution, wherein the vertices comprise the terminal vertices; creating a Steiner tree model on the data specifying the network responsive to the Steiner tree parameters, the Steiner tree model including a local representation having a depth constraint for neighboring vertices of the vertex, the depth constraint ensuring that a depth of any given vertex of the vertices is one more than a depth of another vertex to which the given vertex points; and analyzing the data specifying the network to ascertain the Steiner tree solution based on the Steiner tree model that includes the local representation and using a locally-oriented combinatorial algorithm wherein the analyzing includes sending outgoing messages from the vertex to the neighboring vertices and further includes receiving incoming messages at the vertex from the neighboring vertices, wherein each incoming message and each outgoing message includes depth information indicating a tree depth from a root vertex to an originating vertex of the corresponding message and indicating a parent tree depth from the root vertex to a parent vertex of the originating vertex.