Patent Document ID: 8266552
Application ID: 12705640
Patent Status: 1

Claim One:
1. A pattern generating method comprising: applying OPC processing to design layout data of a semiconductor integrated circuit pattern by using a computer; performing pattern formation simulations based on the design layout data subjected to OPC processing with a plurality of process parameters set in process conditions in a predetermined range by using the computer; extracting a number of risk points having likelihood of causing a pattern formation failure higher than a predetermined value or a risk degree of the risk points, and calculating, as a worst condition, based on the number of the risk points or the risk degree of the risk points, a process condition having a process parameter that brings about a worst result when pattern formation is performed among the process parameters, the risk point being extracted from simulation results of the pattern formation simulations by using the computer; and changing the design layout data or the OPC processing such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result by using the computer.