Patent Document ID: 20050246676
Application ID: 11111720
Patent Status: 0

Claim One:
1. A routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting said integrated circuit and routes connecting said plurality of cells, comprising the steps of: (a) obtaining the sum of areas of said plurality of cells, the number of said plurality of cells or the number of said routes connecting said plurality of cells from said netlist, to be defined as a constant C, and calculating a layout area S which is an area of a layout region, by dividing said constant C by a predetermined constant U; (b) calculating a total route length L by multiplying a predetermined perimeter length H of said layout region having said layout area S obtained in said step (a) by a predetermined coefficient α; and (c) calculating a routing difficulty index by dividing said total route length L by said layout area S.