Patent Document ID: 20070101310
Application ID: 11264298
Patent Status: 0

Claim One:
1. A computer-implemented method of proximity correction of an original layout of an integrated circuit chip in a semiconductor wafer for use with a semiconductor wafer fabrication process, the method comprising: evaluating a first model of a plurality of acts in the process, in at least one location of the original layout, to obtain a distorted layout representing a manufactured shape resulting from the process; wherein the first model comprises a plurality of kernels and an expression using the plurality of kernels; wherein the plurality of surfaces is equal in number to the plurality of kernels in the first model; wherein each surface comprises results of convolution of the plurality of kernels with the original layout, at a plurality of locations in the original layout; evaluating a second model, of sensitivity of the distorted layout with respect to a change in the original layout, using values from the plurality of surfaces at said one location, thereby to obtain a sensitivity value at said one location; and determining a proximity correction to be made to the original layout at said one location, based on at least the sensitivity value and the distorted layout resulting from evaluating the first model.