Patent Document ID: 9170744
Application ID: 14589927
Patent Status: 1

Claim One:
1. An apparatus, comprising: a memory system including: NAND flash physical memory; RAM physical memory; a first buffer for receiving DDR signals, over a DDR bus, and converting the DDR signals to SATA signals; and second buffer for receiving the SATA signals and converting the SATA signals to NAND flash signals, the second buffer communicatively coupled to the first buffer via a first memory bus associated with a SATA protocol, the second buffer further communicatively coupled to the NAND flash physical memory via a second memory bus associated with a NAND flash protocol, the second buffer further communicatively coupled to the RAM physical memory; said memory system configured for: receiving, over the DDR bus, a special command and special data that are responsive to a communication from another system, after the receipt of the special command and the special data, processing at least one of the special command or the special data for causing particular data in the NAND flash physical memory to be written to the RAM physical memory, and after a status in connection with the memory system, receiving a read command to read the particular data written to the RAM physical memory after the receipt of the special command and the special data.