Patent Document ID: 8423924
Application ID: 13330566
Patent Status: 1

Claim One:
1. A computer-aided design apparatus configured to generate photolithographic data for patterning a circuit design onto a semiconductor wafer, comprising: a design tool having a processor, a memory connected to the processor, and a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of: receiving target layout data for the circuit design; performing optical proximity correction on the target layout data to generate post-OPC layout data; and calculating differences between the post-OPC layout data and the target layout data to generate post-OPC bias data; and a manufacturing tool having a processor, a memory connected to the processor, and a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of: receiving the target layout data for the circuit design and the post-OPC bias data from the design tool; and applying the post-OPC bias data to the target layout data to regenerate post-OPC layout data at the manufacturing tool.