Patent Document ID: 20100017762
Application ID: 12174924
Patent Status: 0

Claim One:
1. A method for implementing integrated circuit yield estimation, the method comprising: computing Voronoi regions for an original integrated circuit layout; for each bisector segment of the computed Voronoi regions and each of one or more identified integrated circuit failure mechanisms of interest, computing a failure probability based on geometric parameters of corresponding Voronoi edge regions associated with the bisector segment, using pre-computed failure probabilities as a function of edge orientation and spacing for the one or more identified integrated circuit failure mechanisms of interest; for each segment of a design edge bounded by bisectors, computing a change in the failure probability based on the geometric parameters of the associated Voronoi regions therewith, using pre-computed change in failure probabilities as a function of edge orientation and spacing for the one or more identified integrated circuit failure mechanisms of interest; encoding the computed failure probabilities for each Voronoi region in a manner suitable for visual differentiation by a user; and encoding the computed change in failure probabilities by directional displacement of a layout edge segment that would result in a decrease in failure probability.