Patent Document ID: 10101388
Application ID: 14969119
Patent Status: 1

Claim One:
1. A method for failure signature detection in a semiconductor using a test system comprising: using the test system, comprising a processing unit and a memory, to perform deterministic tests on a plurality of integrated circuit chips to generate defect signatures for failing latches from the plurality of integrated circuit chips, the deterministic test comprising: subjecting, by the test system, a plurality of latches to one of a plurality of testing protocols using one or more base deterministic test patterns; generating, by the test system, defect signatures for failing latches from a plurality of integrated circuit chips in response to the test pattern; comparing each of the plurality of latches with each other to create a mask; generating, by the test system, a latch to mask relationship for the failing latches; generating, by the test system, maximally descriptive masks into identities; generating, by the test system, a list of identities for comparison; determining, by the test system, commonalities between the lists of identities; generating, by the test system, details about differences and commonalities within the defect signatures; fixing, by the test system, manufacturing and materials procurement processes associated with the plurality of integrated circuit chips based on the defect signatures; and facilitating manufacturing of at least one integrated circuit using the fixed manufacturing and materials procurement processes.