Patent Document ID: 10037394
Application ID: 15182338
Patent Status: 1

Claim One:
1. A method for performing timing analysis of a circuit design, the method comprising: determining, by a computing device, a plurality of propagation points associated with a multi-instance block of the circuit design; calculating, by the computing device, for a first instance of the multi-instance block, a first set of phase values, wherein the first set of phase values comprises first corresponding phase values for each propagation point of the plurality of propagation points, wherein the first set of phase values are based on a set of circuit elements of the multi-instance blocks and a first set of context information, and wherein the first set of context information is based on first one or more elements of the circuit design outside the first instance; calculating, by the computing device for a second instance of the multi-instance block, a second set of phase values comprising second corresponding phase values for each propagation point of the plurality of propagation points, wherein the second set of phase values are based on the set of circuit elements of the multi-instance blocks and a second set of context information, wherein the second set of context information is based on second one or more elements of the circuit design outside the second instance; storing the first set of phase values and the second set of phase values as timing analysis data in a memory of the computing device; generating a plurality of timing contexts for the circuit design, each timing context of the plurality of timing contexts being generated from a different combination of an instance of the plurality of instances and an multi-mode multi-corner (MMMC) view of the plurality of MMMC views; generating an analysis view output file comprising a plurality of content MMMC views, the plurality of content MMMC views comprising the plurality of MMMC views and the plurality of timing contexts; determining a block timing merge threshold for the circuit design; comparing the block timing merge threshold with a difference between a first phase value of the first set of phase values and a second phase value of the second set of phase values, wherein the first phase value and the second phase value are both associated with a first propagation point of the plurality of propagation points; associating each propagation point with one or more input latency tags for each instance of the multi-instance block; calculating a required time for each propagation point using an associated propagated latency, the one or more input latency tags, and common clock path pessimism removal; and wherein the timing analysis of the circuit design is provided for fabricating semiconductor devices.