Patent Document ID: 8386722
Application ID: 12144396
Patent Status: 1

Claim One:
1. An interface circuit configured to re-time a plurality of data bursts returned by a plurality of memory devices to obtain a contiguous data burst, the interface circuit comprising: a system control signal interface adapted to receive a first command from a memory controller; an intelligent bufer chip; and emulation and command translation logic adapted to: translate a first address associated with the first command, issue the first command to a first memory device within the plurality of memory devices corresponding to the first address, determine that the first command is a read command, select a memory data signal interface corresponding to the first memory device, receive a first data burst from the first memory device, delay the first data burst to eliminate a first clock-to-data phase between the first memory device and the interface circuit, and re-drive the first data burst to the memory controller, wherein the plurality of memory devices are arranged in a stack, and the interface circuit is integrated within the stack, and wherein the plurality of the memory devices comprises dynamic random access memories, and the intelligent buffer chip and the dynamic random access memories are included in a dual in-line module.