Patent Document ID: 9280632
Application ID: 13668113
Patent Status: 1

Claim One:
1. A method implemented on a data processing system comprising a processor and a memory, the method, upon receipt of at least a portion of an integrated circuit design comprising: determining timing critical nets for the integrated circuit design using the processor; identifying a set of elements and nets for each of the timing critical nets; determining one or more islands from the union of timing critical nets having one or more common elements or nets; identifying one or more sub-portions of the integrated circuit design corresponding to the islands; executing a placer which places the one or more sub-portions of the integrated circuit design on a transformed representation of the integrated circuit design, wherein at least one of the determining timing critical nets, identifying a set of elements and nets, determining one or more islands, identifying one or more sub-portions, and executing a placer is performed using the processor; and storing the transformed representation of the design in the memory, wherein the stored transformed representation of the design is used in the creation of an integrated circuit.