Patent Document ID: 8959460
Application ID: 13955700
Patent Status: 1

Claim One:
1. A method of assigning layout patterns of a current layout design for an integrated circuit to a plurality of masks, the method comprising: identifying a first set of layout patterns among the layout patterns of the current layout design that is new or has been modified in comparison with a reference layout design; identifying a second set of layout patterns among the layout patterns of the current layout design, the second set of layout patterns including the first set of layout patterns and wherein a member of the second set of layout patterns that is not a member of the first set of layout patterns has a distance, less than a predetermined threshold distance, to at least another member of the second set of layout patterns; and assigning a third set of layout patterns among the layout patterns of the current layout design to the plurality of masks according to a reference pattern-assigning result of the reference layout design, the third set of layout patterns being not modified in comparison with the reference layout design, wherein at least one of the identifying a first set, identifying a second set, or assigning a third set is performed by using a hardware processor.