Patent Document ID: 20150220436
Application ID: 13976313
Patent Status: 0

Claim One:
1. A method for implementing a tag structure, the method comprising: determining a translation lookaside buffer (TLB) set associated with a virtual memory address indicated in a memory access instruction; comparing a TLB tag portion of the virtual memory address with TLB tags stored in way entries of a TLB tag array, wherein the way entries are associated with the TLB set; generating, when the TLB tag portion matches a TLB tag stored in one of the way entries, a TLB vector indicative of the TLB set and the way entry that matched; identifying a set in a level 1 (L1) tag array based on the virtual memory address; comparing the TLB vector with stored TLB vectors stored in way entries of a L1 tag array, wherein the L1 tag array way entries are associated with the L1 tag array set; and when the TLB vector matches a stored TLB vector in one of the L1 tag array way entries, generating a way select output indicative of the L1 tag array set and the L1 tag array way entry that matched.