Patent Document ID: 8392866
Application ID: 12972934
Patent Status: 1

Claim One:
1. A computer-implemented method of optimizing an integrated circuit design, the method comprising: in a parent process of a computer, generating a set of objects from the integrated circuit design upon which to perform a transform; in each of a plurality of child processes: performing the transform on each of a subset of objects from the set of objects, including determining for each of the subset of objects whether such object is a candidate object for which performance of the transform has been successful; for each candidate object for which performance of the transform has been determined to be successful, generating result data capable of being used to reduce an overhead of the parent process when performing the transform on such candidate object; and notifying the parent process of any candidate object from the subset of objects for which performance of the transform has been determined to be successful, including providing the result data generated for any such candidate object to the parent process; and in the parent process, performing the transform on each candidate object of which the parent process is notified by the plurality of child processes using the result data generated for such candidate object.