Patent Document ID: 9129345
Application ID: 13637366
Patent Status: 1

Claim One:
1. A data stream processing architecture, the data forming matrices of pixels of dimension NI×Nc, the architecture comprising: a plurality of sets of processors, each set of processors being capable of receiving an input data stream and of delivering an output data stream, and each set of processors comprising: a control circuit capable of supplying instructions, a set of neighborhood processors capable of performing the instructions received from the control circuit and of supplying data forming the output data stream of the set of processors, and a neighborhood memory enabling each neighborhood processor to access data of the input data stream received by the set of processors forming a neighborhood of pixels of dimension VI×Vc, each neighborhood memory comprising, for each neighborhood processor, a local memory for storing dynamically the data forming the neighborhoods of pixels which the neighborhood processor can access, the neighborhoods of pixels accessible to the processors being centered on contiguous pixels of the same row of a matrix, two processors being neighbors when the neighborhoods that they can access are centered on contiguous pixels in the same row of a matrix; and interconnectors capable of receiving a data stream at an input of the architecture and the output data streams of the set of processors, and capable of delivering a data stream at an output of the architecture, wherein two set of processors can be coupled on a North/South axis and each comprise: same number N of neighborhood processors; and connectors enabling each neighborhood processor, within the set of processors, to exchange data with each of its neighboring processors belonging to the same set of processors, so that the neighborhood of pixels accessible to a neighborhood processor can be extended to all the neighborhoods of pixels accessible to the neighborhood processors of the same set of processors said set forming a neighborhood of pixels of dimension VI×(Vc+N−1); and the architecture further comprises: a storage manager capable of receiving a data stream from the interconnectors and enabling the neighborhood processors of a first coupled set of processors to access neighborhoods of pixels contiguous with the neighborhoods of pixels accessible to the neighborhood processors of a second coupled set of processors, so that the neighborhoods of pixels accessible to the neighborhood processors of the two coupled set of processors can form a vicinity of dimension 2·VI×(Vc+N−1); and connectors on the North/South axis enabling each neighborhood processor of the first coupled set of processors to exchange data with one of the neighborhood processors of the second coupled set of processors, the neighborhood processors being linked in pairs so as to have access to each other's local memory and to have access to neighborhoods of pixels centered on one and the same column of a matrix, so that the neighborhood of pixels accessible to each neighborhood processor can be extended to the neighborhoods of pixels accessible to the neighborhood processor to which it is linked.