Patent Document ID: 7587694
Application ID: 11490658
Patent Status: 1

Claim One:
1. A system for designing an integrated circuit, comprising: a design engine stored in memory and executable by a processor to: utilize a cell file library configured to store cell resources comprising composite cell resources; receive at least one layout constraint; compile the at least one layout constraint into at least one composite cell implementation; generate a first layout scenario of one or more geometries in conformance with the at least one composite cell implementation; generate a second layout scenario in conformance with the first layout scenario, wherein the generation of the second layout scenario comprises generating an open standard compatible cell in conformance with the at least on composite cell implementation and saving the generated open standard compatible cell to a cell file library when a cell in conformance with the first layout scenario does not exist; and repeat the generation of the second layout scenario until all possible layout scenarios have been exhausted.