Patent Document ID: 8209479
Application ID: 11929571
Patent Status: 1

Claim One:
1. A memory apparatus for use with a host system, the memory apparatus comprising: a first plurality of memory circuits; and an interface circuit operable to interface the first plurality of memory circuits and the host system, and to present to the host system one or more emulated memory circuits, the interface circuit including: a first component of a first type; and a second component of a second type, the first and the second components being operable to present, in combination, a host-system interface to the host system and to present, in combination, a memory-circuit interface to the first plurality of memory circuits, where at least one aspect of the host-system interface is different from a respective corresponding aspect of the memory-circuit interface, where the at least one aspect of the host-system interface and the respective corresponding aspect of the memory-circuit interface each include at least one of a signal, a memory capacity, or a timing, where each memory circuit of the first plurality of memory circuits is electrically coupled to the second component, where the first component is operable to receive (1) address signals and (2) control signals other than address signals from the host system and send at least one of the control signals received from the host system to the second component, and where the second component is operable to receive a first set of data signals from the host system and send the first set of data signals received from the host system to at least one memory circuit of the first plurality of memory circuits.