Patent Document ID: 20180189241
Application ID: 15909671
Patent Status: 0

Claim One:
1. Interpolation logic comprising: fixed-function multiplier logic configured in hardware to determine an interpolated value at one or more pre-determined interpolation positions (U) within an array of data points by performing a weighted sum according to: 
 w A ( U )/ A+w B ( U ) B+w C ( U ) C+w D ( U ) D where A, B, C and D are four data points of a line in the array of data points and w A , w B , w C and w D are their corresponding weights, wherein the weights are set in the fixed-function multiplier logic to provide an imperfect representation of a Catmull-Rom interpolation to thereby simplify the hardware of the fixed-function multiplier logic compared to providing a perfect representation of the Catmull-Rom interpolation.