Patent Document ID: 9215468
Application ID: 14454647
Patent Status: 1

Claim One:
1. An encoder-side bit-rate reduction system for support layer processing of video data, the encoder-side bit-rate reduction system comprising: a decimator that down-converts an original video input with at least one of a horizontal low-pass filter, a vertical low-pass filter, a horizontal pixel count reduction block, and a vertical pixel count reduction block to reduce bit-rates of the original video input; a main compressor that receives a bit-rate reduced output from the decimator and generates a bit-rate reduced and compressed main layer output signal; an upconverter and resizer that upconverts and resizes the bit-rate reduced output from the decimator or a reconstructed low-resolution video signal (Reconstructed LR) from a decoder that receives the bit-rate reduced and compressed main layer output signal from the main compressor, wherein the upconverter and resizer generates a low-resolution full-size image video signal (Full-size Image with LR); a signal subtractor that subtracts the low-resolution full-size image video signal (Full-size Image with LR) from the original video input to generate a residual signal; a reference images matrix containing a static library of reference image elements and reference image element indexes that are independent of frame contents processed by the encoder-side bit-rate reduction system; and a reference images matrix matchmaker operatively connected to the signal subtractor and the reference images matrix, wherein the reference images matrix matchmaker matches the residual signal with a linear combination of indexed reference image elements from the reference images matrix and symbolizes the residual signal with a mathematical coefficient and one or more reference image element indexes.