Patent Document ID: 20010019509
Application ID: 09740802
Patent Status: 0

Claim One:
1. A memory controller for controlling the transfer of data to and from a memory array, wherein the memory array includes a first type of memory and a second type of memory, the first type having a different signalling protocol from the second type of memory, wherein the memory controller comprises: an address decoder having an input for receiving a memory access request, said memory access request including the address of the memory array to be accessed, and an output for outputting the address of the memory array to be accessed; a first sub-controller for generating a plurality of memory interface signals for controlling the first type of memory, said first sub-controller being operated in response to addresses within a first range of addresses output by the address decoder; and a second sub-controller for generating a plurality of memory interface signals for controlling the second type of memory, said second sub-controller being operated in response to addresses within a second, non-overlapping range of addresses output by the address decoder.