Patent Document ID: 20060126369
Application ID: 11010942
Patent Status: 0

Claim One:
1. Stacked DRAM Memory Chip for a Dual In Line Memory Module having: (a) a predetermined number of stacked DRAM memory dies; (b) wherein each DRAM memory die is selectable by a corresponding memory rank signal; (c) wherein each DRAM memory die comprises an array of memory cells; (d) wherein a common internal address bus consisting of address lines is provided for addressing the memory cells and is connected to all M stacked DRAM memory dies; (e) wherein M internal data buses consisting of internal data lines are provided for writing data into the memory cells and reading data out of the memory cells of the stacked DRAM memory dies; wherein (f) an integrated redriving unit is provided which comprises: (f1) buffers for all internal address lines provided for driving external address signals applied to address pads of said DRAM memory chip and; (f2) a multiplexer/demultiplexer which switches the internal data lines of the selected DRAM memory die to data pads of said DRAM memory chip.