Patent Document ID: 7567700
Application ID: 11390469
Patent Status: 1

Claim One:
1. A method of processing a wafer comprising: receiving a wafer, wherein the wafer comprises a plurality of dies, each die having a patterned bi-layer mask thereon, wherein the bi-layer mask includes a soft mask layer and a hard mask layer; creating a pre-processing measurement map using measured metrology data for the wafer including metrology data for at least one isolated bi-layer structure on the wafer, metrology data for at least one nested bi-layer structure on the wafer, or mask data; calculating a first pre-processing prediction map for the wafer based on the pre-processing measurement map, the first pre-processing prediction map including a first set of predicted measured data for the plurality of dies on the wafer; calculating a pre-processing confidence map for the wafer, the pre-processing confidence map including a set of confidence data for the plurality of dies on the wafer, wherein the confidence data is determined using a difference between the first pre-processing prediction map and historical data; determining a prioritized measurement site when the confidence data for one or more dies is not within the confidence limits; creating a new measurement recipe that includes the prioritized measurement site; calculating control settings for the wafer when the confidence data for substantially all of the dies is within the confidence limits; and processing the wafer using the calculated control settings; and determining a first value using a feature size for the at least one isolated structure on the wafer, wherein the soft mask layer comprises photoresist material and the hard mask layer comprises Bottom Anti-Reflective Coating (BARC)layer; determining a second value using a feature size for the at least one nested structure on the wafer; executing an Iso-Greater control strategy when the first value is greater than the second value, wherein the Iso-Greater control strategy comprises an Iso/Nested control plan for controlling an iso/nested etching process, a Trim Control plan for controlling a trimming process, or a BARC open control plan for controlling a BARC etching process, or a combination of two or more thereof; and executing a Nes-Greater control strategy when the first value is less than the second value, wherein the Nes-Greater control strategy comprises an Iso/Nested control plan for controlling an iso/nested deposition process, a Trim Control plan for controlling a trimming process, or a BARC open control plan for controlling a BARC etching process, or a combination of two or more thereof.