Patent Document ID: 5404310
Application ID: 07599030
Patent Status: 1

Claim One:
1. A method for power source wiring an integrated circuit, the method comprising the steps of: a) generating a wiring layout according to predetermined wiring rules; b) converting said wiring layout to a trial circuit having a plurality of four sided regions and storing said trial circuit; c) identifying electrical factors affecting electrical current drawn in said regions and, from said factors, determining an electrical current value flowing into a node at an intersection of power source lines in each said region; d) identifying an initial estimate of power source current to ground and a node voltage in each said region, determining admittance of said power source lines between said node and a peripheral node of said region from a selected resistivity and width of said power source lines, and determining therefrom a voltage at a said periphery of said region; e) calculating a new value of said node voltage from said admittance and said current and subsequently calculating a new value for said node voltage; f) repeating steps c) and d) until said voltage at said periphery achieves a predetermined accuracy with respect to a previously determined voltage at said periphery; g) determining if said power source wiring layout produces in said power source wiring lines currents and voltage drops within predetermined levels; h) if said currents and voltage drops are in said power source wiring lines are not within said predetermined levels, generating a plan, according to predetermined improving rules, for improving said power source wiring layout to obtain current levels and voltage drops in said power source wiring within said predetermined levels and repeating steps a) through g); and i) when said power source wiring layout produces in said power source wiring lines currents and voltages within said predetermined levels, converting said trial circuit into a practical wiring layout.