Patent Document ID: 20030005250
Application ID: 09896030
Patent Status: 0

Claim One:
1. A method of transferring digital signal packets out of a packetized memory device on a data bus, each digital signal packet including at least one packet word including a plurality of digital signals that are applied to respective latches in the packetized memory device, the method comprising: placing the packetized memory device in a synchronization mode of operation; generating a data clock signal responsive to a read clock signal and applying the data clock signal on a corresponding line of the data bus; generating a plurality of internal clock signals read clock signal, each internal clock signal having a phase shift relative to the data clock signal; storing for each digital signal a phase command in a corresponding storage circuit associated with the digital signal, the phase command having a value corresponding to one of the internal clock signals; placing each digital signal on a corresponding data bus line responsive to the internal clock signal corresponding to the phase command stored in the associated storage circuit; receiving a phase adjustment command corresponding to a particular digital signal that is being synchronized, the phase adjustment command containing adjustment information for the phase command associated with the digital signal; adjusting the value of the phase command stored in the storage circuit associated with the digital signal being synchronized responsive to the phase adjustment command until the value of the phase command defines a timing offset between the digital signal and the data clock that allows and external device to successfully capture the digital signal responsive to the data clock signal; and repeating the operations of placing each digital signal on a corresponding bus line to adjusting the value of the phase command signal for each digital signal in the packet word.