Patent Document ID: 20080059714
Application ID: 11936414
Patent Status: 0

Claim One:
1. A system for memory management, the system comprising a tag cache in communication with one or more cache devices in a storage hierarchy, wherein: the tag cache includes tags of recently accessed memory blocks, each tag corresponding to one of the memory blocks and each tag including tag contents; wherein the tag contents include a memory block real address and one bit for every memory line in the memory block, the bits referred to as prefetch bits; and wherein further, each of the prefetch bits is reset to a non-prefetch status with a selected probability of between zero and one; the tag contents control which memory lines of the corresponding memory block are prefetched into at least one of the cache devices; the tag contents are updated using a selected subset of processor references, the subset referred to as filtered references; and the tag contents are modified probabilistically at selected times or events.