Patent Document ID: 8397113
Application ID: 12903044
Patent Status: 1

Claim One:
1. A computer-implemented method, comprising: applying a plurality of test patterns to a circuit under test, the circuit under test having at least one input where the plurality of test patterns are applied and at least one output where a test result is measured, and each of the plurality of test patterns yielding a predicted test result at the output when no defect is included in the circuit; identifying failure test patterns from the plurality of test patterns by comparing the test result with the predicted test result, the test result of the failure test patterns mismatching the predicted test result; obtaining a switching activity count for each of the plurality of test patterns; providing ranks for each of the plurality of test patterns wherein the ranks are based on the switching activity count; performing a correlation analysis between the failure test patterns and the ranks of the switching activity count; determining likelihood of a power defect in the circuit based on a high correlation between the failure test patterns and the ranks of the switching activity count; and performing a power defect test on the failure test patterns under the presence of the high correlation.