Patent Document ID: 20030051219
Application ID: 09953119
Patent Status: 0

Claim One:
1. A method for analyzing a layout related to a circuit on a semiconductor chip, comprising: receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes; wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes located under the given node in the design hierarchy; modifying the design hierarchy to produce a modified design hierarchy by, examining a set of sibling nodes that are located under a parent node in the design hierarchy, identifying a set of interacting geometrical features between the set of sibling nodes, and moving the set of interacting geometrical features from the sibling nodes to the parent node, so that the interaction is visible at the parent node, wherein other geometrical features that do not interact remain at the sibling nodes and are not moved to the parent node; and performing an analysis on the modified design hierarchy; wherein performing the analysis involves analyzing the set of interacting geometrical features at the parent node.