Patent Document ID: 20120036405
Application ID: 12966687
Patent Status: 0

Claim One:
1. A failure analyzing device, comprising: a dividing unit that receives a fail bit map where non-failure/failure information of individual cells of a semiconductor memory is arranged in order of physical addresses corresponding to a physical layout of the memory cells, and divides the fail bit map for each layer; a classifying unit that classifies a failure type in the fail bit map corresponding to each layer; a storage unit that stores a rule where the failed cells of different layers are combined as the same failure type; and a determining unit that determines whether classification results based on the classifying unit are matched with the rule and groups the matched classification results, wherein the rule includes a base point failure, an association failure becoming a combination object of the base point failure, a combination condition defining a relationship between the base point failure and the association failure, and a combination failure name, and the determining unit extracts the base point failure from the classification result of one layer, extracts the association failure matched with the combination condition from the classification results of the other layers, groups the extracted base point failure and association failure, and provides the combination failure name.