Patent Document ID: 8245166
Application ID: 12871962
Patent Status: 1

Claim One:
1. A method, in a data processing system comprising a processor and a memory, for refining an abstraction of a netlist for verification or synthesis of an integrated circuit design, comprising: receiving, in the data processing system, an abstracted netlist corresponding to an original netlist of the integrated circuit design; determining, by the data processing system, elements, of an array of elements in the integrated circuit design, already present in the abstracted netlist; refining, by the data processing system, the abstracted netlist by expanding the abstracted netlist to include additional elements, of the array of elements, that are correlated with the elements already present in the abstracted netlist to thereby generate a refined abstracted netlist; and utilizing, by the data processing system, the refined abstracted netlist to perform at least one of verification or synthesis of the integrated circuit design, wherein the additional elements that are correlated with the elements already present in the abstracted netlist comprise additional elements, in the array of elements in the integrated circuit design, having a same row or column location in the array of elements as elements already present in the abstracted netlist.