Patent Document ID: 20090307643
Application ID: 12134875
Patent Status: 0

Claim One:
1. A method comprising: accessing, at a processing system, a first data representative of a first set of illegal vector sequences for a circuit design; sorting, at the processing system, the first set of illegal vector sequences based on sorting criteria to generate a second set of illegal vector sequences having a sort order; generating, at the processing system, a first binary decision diagram (BDD) for a first illegal vector sequence of the second set of illegal vector sequences; and removing, at the processing system, a first illegal vector sequence from the second set of illegal vector sequences to generate a third set of illegal vector sequences responsive to a second BDD being inclusive of the first BDD, the second BDD comprising a union of each BDD of each corresponding illegal vector sequence of the second set of illegal vector sequences that proceeds the first illegal vector sequence in the sort order.