Patent Document ID: 7552407
Application ID: 12036093
Patent Status: 1

Claim One:
1. A system for performing verification, said system comprising: means for receiving a design including one or more targets, one or more constraints, one or more registers and one or more inputs; means for computing a first function of one of said one or more targets over said one or more registers and said one or more inputs; means for computing a second function of one or more of said one or more constraints over said one or more registers and said one or more inputs; means for existentially quantifying said inputs of said first function and said second function; means for performing a bounded analysis to determine if said one of said one or more targets may be hit while adhering to said constraints; means for existentially quantifying a preimage of said inputs of said first function and said inputs of said second function to create a synthesizable preimage; means for simplifying said synthesizable preimage; means for synthesizing said synthesizable preimage to create an enlarged target; and means for performing verification of said enlarged target.