Patent Document ID: 9182991
Application ID: 13366999
Patent Status: 1

Claim One:
1. A computer system for instruction execution, the system comprising: a processor having a pipeline, wherein the system is configured to perform a method, comprising: fetching, in the pipeline, a plurality of instructions, wherein the plurality of instructions includes a plurality of branch instructions and a plurality of non-branch instructions; assigning a branch uncertainty to each of the plurality of branch instructions; for each of the plurality of instructions, assigning an instruction uncertainty that is a summation of branch uncertainties of older unresolved branches; determining a first summation of instruction uncertainties of instructions associated with a first thread that are currently in the pipeline; determining a second summation of instruction uncertainties of instructions associated with a second thread that are currently in the pipeline; and balancing dispatching of instructions associated with the first thread and instructions associated with the second thread into the pipeline based on the first summation of instruction uncertainties and the second summation of instruction uncertainties.