Patent Document ID: 20100021049
Application ID: 12458825
Patent Status: 0

Claim One:
1. A method of analyzing failure of a semiconductor integrated circuit, comprising: inspecting a physical defect in a semiconductor wafer at the time of manufacture of a semiconductor integrated circuit chip, and acquiring a chip position, an inspection step identifying information and in-chip coordinates of said physical defect; subjecting the semiconductor integrated circuit to a logic test in the wafer or after assembly, and extracting a malfunctioning chip and position of said chip; analyzing a detected signal, which is observed from the malfunctioning chip, by an analyzer, and acquiring coordinates and a layer where the detected signal was detected; extracting a layer and coordinates of a circuit with regard to a cell in which the detected signal was detected and a net connected to said cell, or a net in which the detected signal was detected and a cell connected to said net, using design data and the coordinates and layer of the detected signal; and collating the inspection step identifying information of the physical defect with the layer of the circuit, collating the in-chip coordinates of the physical defect with the circuit coordinates, and identifying the physical defect associated with the circuit.