Patent Document ID: 20100274831
Application ID: 12761946
Patent Status: 0

Claim One:
1. A computing device provided with a processor having a SIMD function executing a plurality of operations by a single instruction, the device comprising: a deciding unit which, in computation of values of nodes on a lattice in a direction where a value of m representing a horizontal axis coordinate of the lattice increases, decides dummy nodes to be added to m=n−1, so as to enable values of nodes on m=n to be calculated by adding the dummy nodes to m=n−1 and executing a vector operation through the use of the SIMD function by using values of nodes on m=n−1 and values of the added dummy nodes; an adding unit adding the dummy nodes decided by said deciding unit to m=n−1; and a calculating unit calculating the values of the nodes present on m=n by executing the vector operation through the use of the SIMD function by using the values of the nodes on m=n−1 and the values of the dummy nodes added by said adding unit.