Patent Document ID: 20060052964
Application ID: 11180896
Patent Status: 0

Claim One:
1. A test apparatus that tests a device under test, comprising: a main memory having an expectation pattern storing region storing an expectation pattern sequence to be sequentially compared with a plurality of output patterns sequentially output from a terminal of the device under test; a test pattern outputting unit operable to sequentially input a plurality of test patterns into the device under test and sequentially output the output patterns from the device under test; a capture unit operable to sequentially acquire the output patterns into an output pattern storing region on said main memory; a memory reading unit operable to read an output pattern sequence consisting of the plurality of acquired output patterns and the expectation pattern sequence from said main memory when the acquisition process acquiring the output patterns into the output pattern storing region has been terminated; and an expectation comparing unit operable to compare the read expectation pattern sequence and the output pattern sequence.