Patent Document ID: 10101965
Application ID: 14925006
Patent Status: 1

Claim One:
1. A method for sorting, by circuitry, N data elements into M most significant data elements in sorted order, wherein M<N, the method comprising: controlling, by a processing device, inputting L data elements of the N data elements at a same time into at least one sorting unit of a cascade of S sorting units, in which the L input data elements are sorted by a first comparator circuit of the circuitry only among the L input data elements before the inputting, in which the sorting units are arranged in the cascade in order of priority, in which each of the sorting units includes B registers for storing M/S data elements in sorted order and in order in relation to data elements respectively in the B registers of a neighbor sorting unit in the cascade, in which the S sorting units store a current set of most significant data elements of data elements previously input thus far, and in which S*B=M, B≥L and L≥1; controlling, by the processing device, for each sorting unit of the cascade, sorting (i) each comparison data element determined to be inserted in the sorting based on a comparison by a second comparison circuit of the circuitry of each of the L input data elements with a most significant value of the B registers of the sorting unit and (ii) by a third comparison circuit of the circuitry the data elements respectively of the B registers of the sorting unit, to obtain a sorted array of data elements in order of significance; and controlling, by the processing device, at a given sorting unit of the cascade, storing, into the B registers in sorted order, data elements determined from (i) when no shift data elements is output from a preceding neighbor sorting unit in the cascade, the B most significant values of the sorted array of data elements for the given sorting unit determined by a fourth comparison circuit of the circuitry, and (ii) when SH shift data elements is output from the preceding neighbor sorting unit in the cascade, the SH shift data elements and a subset of the data elements of the sorted array determined by a fifth comparison circuit of the circuitry in accordance with the value of SH, in which 1≤SH≤B, and outputting, as SHN shift-next data elements in order, SHN data elements from the sorted array of data elements more or less significant than the most or least significant data element of the sorted array stored in the B registers by the storing, in which 1≤SHN≤B.