Patent Document ID: 9836572
Application ID: 14946043
Patent Status: 1

Claim One:
1. A computer-implemented method of performing incremental common path pessimism analysis in integrated circuit design, the method comprising: performing, using a processor, common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism; identifying one or more post-CPPR critical paths following the CPPR analysis that provides the timing credit to the one or more paths that are subject to common path pessimism; setting flags for critical nodes of the one or more post-CPPR critical paths; performing a design fix to address the one or more post-CPPR critical paths; applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths, wherein the identifying the seed points is by identifying the critical nodes that meet one or more of the following criteria: the critical node is a sink of an edge added as a result of the performing the design fix, the critical node is a source or sink of an edge deleted as a result of the performing the design fix, the critical node is a sink of an edge with a changed arrival time based on the performing the design fix, and the critical node is a source of an edge with a changed required arrival time based on the performing the design fix; and invalidating and re-performing the CPPR analysis only for paths in a fan-out cone from the seed points, wherein the integrated circuit design resulting from the incremental common path pessimism analysis is implemented as a physical implementation of an integrated circuit.