Patent Document ID: 8539416
Application ID: 12649658
Patent Status: 1

Claim One:
1. A computer implemented method for processing a hierarchical electronic circuit design of an electronic circuit, the method comprising: using a computer system which comprises at least one processor that executes one or more threads to perform a process, the process comprising: identifying a first shape from a first layer and a first scratch layer, wherein the first scratch layer comprises a result of populating a second shape from a second layer; identifying a first shape into the first scratch layer to generate a first post-operation shape; identifying or generating a master output layer in a computer readable storage medium for a cellview master of an instance in the instance path that the first shape is in, wherein the cellview master exists at a level in the hierarchical electronic circuit design; and integrating a derived shape of the first post-operation shape into the master output layer by operating upon the hierarchical electronic circuit design, without flattening design data pertaining to the first layer or the second layer of the electronic circuit, to create the hierarchical output, wherein flattening the design data promotes the design data from a lower hierarchical level to a higher hierarchical level.