Patent Document ID: 9842187
Application ID: 15082993
Patent Status: 1

Claim One:
1. A method of processing a circuit design, comprising: performing operations by one or more processors that are coupled to a memory having a stored circuit design, the operations including: determining pin slack values for pins of circuit elements in the circuit design, respectively, wherein the pin slack value of a pin is a least of slack values of all paths that fanin to the pin; selecting a subset of endpoints of the circuit design, each endpoint of the subset being one of the circuit elements and having a pin slack value in a critical slack range; determining startpoints of the circuit design that are in a respective critical fanin cone of each endpoint of the subset, wherein all pin slack values in each respective critical fanin cone are in the critical slack range, and each startpoint is one of the circuit elements; determining for each endpoint of the subset, a respective arrival time from each startpoint in the respective critical fanin cone; determining for each pair including an endpoint of the subset and a startpoint in the respective critical fanin cone, a respective set of constraint values as a function of the respective arrival time from the startpoint; and generating a graph in the memory for endpoints of the subset and startpoints that are in the respective critical fanin cones of the endpoints of the subset, wherein first nodes in the graph represent the startpoints and second nodes in the graph represent the endpoints, and values in the respective set of constraint values are associated with edges that connect the first nodes and the second nodes; modifying the circuit design based on the constraint values associated with the edges in the graph; and generating a circuit from the modified circuit design.