Patent Document ID: 10031991
Application ID: 15221820
Patent Status: 1

Claim One:
1. An electronic design process comprising: receiving, using at least one processor, an electronic design environment including both a design under test (“DUT”) to be fabricated and a System Verilog testbench; simulating an electronic design associated with the electronic design environment; generating a coverage database associated with the electronic design; identifying one or more unexercised portions of the System Verilog testbench indicative of an absence of a stimulus; performing coverage analysis of the DUT and the System Verilog testbench using an automated System Verilog inheritance aware analysis, wherein the automated System Verilog inheritance aware analysis includes applying an object oriented programming inheritance hierarchy to the coverage analysis of the testbench; generating coverage analysis results; and applying the coverage analysis results to the testbench after simulation; wherein the electronic design is provided to a fabrication facility to manufacture integrated circuits.