Patent Document ID: 7991574
Application ID: 12021670
Patent Status: 1

Claim One:
1. A computer-performed method for visually displaying or numerically mapping systematic wafer-level circuit variation, the method comprising: collecting measurement data from electronic circuits integrated on a wafer, wherein the measurement data is collected from multiple positions within multiple regions of the wafer and is indicative of performance of the electronic circuits; within a computer system, determining a set of parameter values dependent on the measurement data for the multiple positions in the multiple regions; computing a set of normalization values from the set of parameter values for removing per-position systematic variation; adjusting the set of parameter values using the normalization values to remove the per-position systematic variation; and displaying a result of the adjusting as a visual map of wafer level variation or storing the result of the adjusting as a numerical map of wafer level variation in a storage device within the computer system, wherein the visual map or numerical map indicates parameter value levels corresponding to the position within the regions, wherein the computing comprises averaging the parameter values for each region to obtain an average parameter value corresponding to each region, computing deviations of the parameter values from the average parameter value for the corresponding region, and averaging the deviations for each position to obtain average deviations, and wherein the adjusting comprises subtracting the average deviations from the parameter values, whereby per-position systematic variation is removed from the parameter values.