Patent Document ID: 9223507
Application ID: 14589937
Patent Status: 1

Claim One:
1. An apparatus, comprising: a memory sub-system including: a first memory of a first memory class; and a second memory of a second memory class, the second memory communicatively coupled to the first memory; said memory sub-system configured for: receiving, over a standard bus associated with a DDR protocol, a command including data of which at least a portion is used in connection with a corresponding command, after the receipt of the command including the data of which the at least portion is used in connection the corresponding command, causing particular information in the first memory to be written to the second memory, and after a status check in connection with the memory sub-system, receiving a read command to read the particular information written to the second memory; wherein the apparatus is configured for writing the particular information to the second memory using a time between an execution of a plurality of threads.