Patent Document ID: 20030218930
Application ID: 10153042
Patent Status: 0

Claim One:
1. A semiconductor memory device comprising: a memory comprising a plurality of memory storage cells to store binary data; a command interface coupled to the memory, the command interface containing circuitry to decode commands provided to the device by a user and provide the decoded commands to control the operation of the device; a refresh circuit coupled to the memory and the command interface, the refresh circuit to provide an address of a portion of the memory to be refreshed, the refresh circuit comprising: a programmable counter having a first input coupled to the command interface and a second input coupled to an address bus, the programmable counter containing circuitry to store an address provided on the address bus and to provide the stored address on an output of the refresh circuit; and a selection circuit having an input coupled to the command interface and an output coupled to the second input of the programmable counter, the selection circuit having circuitry to pass the address provided by the address bus to the programmable counter based on a command from the command interface.