Patent Document ID: 8838663
Application ID: 11731580
Patent Status: 1

Claim One:
1. A processor, comprising: a reciprocal residual arithmetic logic unit (“ALU”) to compute a reciprocal residual value for a floating point value wherein the reciprocal residual ALU is implemented using a fused multiply-add ALU in the processor in response to executing a reciprocal residual value instruction and the fused multiply-add ALU comprises: a multiplier to produce a product of X′ and an approximate reciprocal value of X′, X′*recip(X′), X′ being a normalized value of the floating point value X and recip(X′) being a reciprocal value of X′, wherein the multiplier to receive the approximate reciprocal value from a (L−2) bit lookup table; an adder to perform 1−X′*recip(X′) and to obtain an intermediate result, 1−X′*recip(X′),for the reciprocal residual value of X, the reciprocal residual value of X being 1−X* recip(X) and recip(X) being the reciprocal value of X; and a normalizer/rounder to normalize the intermediate result, to round the normalized intermediate result, and to output the reciprocal residual value of X.