Patent Document ID: 9619859
Application ID: 14741121
Patent Status: 1

Claim One:
1. An apparatus, comprising: a cache comprising a plurality of rows to store a set of triangle vertex indices for a trilist primitive and control information, the set of triangle vertex indices corresponding to a set of triangle vertices most recently transmitted through a graphics pipeline, the set of triangle vertices to comprise vertices of the trilist primitive; and a vertex processing component operative on a graphics processor (GPU) to: receive the set of triangle vertices; compare an index for each vertex of the set of triangle vertices to determine matches to the set of cached triangle vertex indices; process each vertex of the set of triangle vertices based on an autostrip topology processing when exactly two matches to the set of cached triangle vertex indices are found by: shifting a single vertex index into a first empty row of the plurality of rows of the cache, the single vertex index corresponding to a vertex miss in which a given vertex of the set of triangle vertices does not match any vertex index of the set of cached triangle vertex indices, setting the control information of the first empty row to indicate processing of an autostrip primitive type, and populating the first empty row with the two matches to the set of cached triangle vertex indices as autostrip cache indices.