Patent Document ID: 10073938
Application ID: 15196050
Patent Status: 1

Claim One:
1. A computer-implemented method for verifying an integrated circuit design, the method comprising: receiving by a computer system, with respect to a verification process for the integrated circuit design, a set of design constraints; constructing, based on the set of design constraints, a constraint model by assembling a physical circuit, the constraint model representing one or more aspects of the integrated circuit design in the physical circuit, the set of design constraints applied as inputs to logic gates in the physical circuit; determining by the computer system, using the constraint model, a new global constraint; and processing by the computer system, using the new global constraint, the verification process for the integrated circuit design, wherein the constraint model uses a set of chicken switches to sort, in a selective fashion, the set of design constraints into a plurality of subsets of the set of design constraints, the chicken switches including a latch having a special configuration bit held permanently to a randomized value.