Patent Document ID: 4862347
Application ID: 06855013
Patent Status: 1

Claim One:
1. A method for simulating multi-port memory arrays, said method being executed upon a highly parallel logic simulation machine (LSM) including a memory simulator which emulates a memory array with a plurality of memory ports, said memory simulator including input and output resources, said method comprising the steps of: providing a set of array instructions through said LSM to said memory simulator, each array instruction of said set of array instructions defining a simulated memory access operation to be performed on said memory array; binding each array instruction of said set of array instructions to a respective memory port of said plurality of memory ports; storing said set of array instructions in said memory simulator; partitioning said input resources into input resource subsets, each of said input resource subsets corresponding to a respective memory port of said plurality of memory ports; permutatively entering first simulated memory access signals from said LSM into said input resource subsets according to a permutation pattern which corresponds each first simulated memory access signal with a respective memory port of said plurality of memory ports; in said memory simulator, executing each array instruction of said set of array instructions, using first simulated memory access signals which are stored in an input resource subset corresponding with the respective memory port to which said array instruction is bound to represent parameters of the simulated memory access operation defined by said array instruction; producing by execution of said array instructions second simulated memory access signals, said second simulated memory access signals representing the results of simulated memory access operations performed on said memory array; and permutatively providing through said output resources to said LSM said second simulated memory access signals.