Patent Document ID: 20160163606
Application ID: 15041016
Patent Status: 0

Claim One:
1. A system configured to generate a wafer inspection process, comprising: an inspection subsystem configured to scan a wafer to detect defects on the wafer; and a computer subsystem configured for: storing output of one or more detectors of the inspection system during the scanning regardless of whether the output corresponds to the defects detected on the wafer; separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected; applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations; and generating a wafer inspection process based on the defects detected by one or more defect detection methods at the first portion of the physical locations.