Patent Document ID: 8725658
Application ID: 13239155
Patent Status: 1

Claim One:
1. A method for managing memory in a processing system, comprising: allocating memory among a plurality of elements; configuring rules for individual elements, wherein at least a portion of the rules associated with a first element type is configured to control updates to memory allocated to a second element type; and providing a system clock defining a step interval during which a part of the rules is executed; wherein: execution of the part of the rules for two or more elements of a given type is order-independent during the step interval, the given type comprises one of the first element type or the second element type; the plurality of elements are interconnected according to a graph representative of a neuronal network; memory of a given element having allocated memory is updated consistent with a rule configured for the given element; the plurality of elements comprises: a plurality of units, individual units having an allocated memory; and a plurality of doublets, individual doublets associated with a presynaptic unit and a postsynaptic unit; and an individual doublet is operable to modify the memory of the postsynaptic unit.