Patent Document ID: 9058448
Application ID: 13613220
Patent Status: 1

Claim One:
1. A non-transitory computer readable storage medium comprising a computer readable program for computing threshold voltage degradation of transistors in one or more arrays of memory cells, wherein the computer readable program when executed on a computer causes the computer to perform the steps of: selecting a process that models an expected usage of the one or more arrays; running the process to populate the one or more arrays with data over time to simulate the expected usage of the array; compiling data that detail different durations at which each of the memory cells in the one or more arrays stores 1 or at which each of the memory cells in the one or more arrays stores 0; computing a threshold voltage shift separately for each of the transistors in the one or more arrays using at least one biased temperature instability model; for each of one or more separate groupings of memory cells that share a common duration of the different compiled durations, determining a threshold voltage degradation for each transistor in the corresponding grouping of cells based on the at least one biased temperature instability model; and determining a net cell fail probability for each of the one or more arrays based on the computed threshold voltage shift and the determined threshold degradation.