Patent Document ID: 10153162
Application ID: 15284773
Patent Status: 1

Claim One:
1. A method of fabricating a circuit structure feature, the fabricating comprising: providing a circuit structure layer over a substrate and a plurality of etch layers over the circuit structure layer; forming a pattern in at least one of the plurality of etch layers wherein forming comprises patterning at least one primary pattern feature having at least one primary pattern feature dimension and a plurality of assist pattern features having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension and at least one of the plurality of assist pattern features is formed in one etch layer of the plurality of etch layers without being formed in other layers of the plurality of etch layers; reducing the at least one primary pattern feature dimension and closing at least one assist pattern feature to form an etch pattern; and etching the circuit structure feature using the etch pattern, wherein the plurality of assist features are arranged asymmetrically with respect to each other.