Patent Document ID: 8271921
Application ID: 12888700
Patent Status: 1

Claim One:
1. A non-transitory computer-readable storage medium storing a pareto data generation program for an automatic circuit design for causing a computer to execute a procedure, the procedure comprising: first extracting a circuit configuration having a specific function from a circuit configuration data storage device storing data of a plurality of circuit configurations; for each combination of the extracted circuit configuration and a process constraint condition among a plurality of process constraint conditions, which are constraint conditions for manufacturing processes to be commonly used for said plurality of circuit configurations and are stored in a process constraint condition storage device, obtaining simulation results for a set of plural items in requirement specification by circuit simulation, while changing a value of each of plural design variables in the circuit configuration a plurality of times so as to satisfy said process constraint condition and a constraint condition of the extracted circuit configuration; second extracting, from said simulation results, pareto optimal solutions that are non-dominated solutions in a solution specification space for said set of plural items in said requirement specification, and storing values of said plural design variables and values of said set of plural items in said requirement specification for each of the extracted pareto optimal solutions into an individual pareto data storage device in association with a combination of an identifier of the process constraint condition and an identifier of the extracted circuit configuration; for each of said process constraint conditions, third extracting second pareto optimal solutions that are non-dominated solutions among all of said pareto optimal solutions stored in said individual pareto data storage device in association with the process constraint condition; for each of said process constraint conditions, storing said identifier of said circuit configuration, said values of said plural design variables and said values of said set of plural items in said requirement specification, which correspond to each of said second pareto optimal solutions, into a pareto-per-process data storage device; fourth extracting third pareto optimal solutions that are non-dominated solution among all of said pareto optimal solutions stored in said individual pareto data storage device, and storing said combination of said identifier of said extracted circuit configuration and said identifier of said process constraint condition, said values of said plural design variables and said values of said set of plural items in said requirement specification, which correspond to each of said third pareto optimal solutions, into an entire pareto data storage data storage device.