Patent Document ID: 9236219
Application ID: 13886631
Patent Status: 1

Claim One:
1. A method, comprising: providing a semiconductor structure including: a plurality of line substructures disposed in a region of the structure; and a plurality of different types of pre-layers disposed over different sub-regions of the line substructures, each line substructure comprising a first plurality of sub-regions overlaid with a first type of pre-layer and a second plurality of sub-regions overlaid with a second type of pre-layer different from the first type of pre-layer; scanning one of the line substructures to obtain data representing a single raw line image of the line substructure; sectioning the data into a first collection of data representing images of the first plurality of sub-regions overlaid with a first type of pre-layer and a second collection of data representing images of the second plurality of sub-regions overlaid with a second type of pre-layer different from the first type of pre-layer; combining the first collection of data to create a first combined line image for the first plurality of sub-regions; combining the second collection of data to create a second combined line image for the second plurality of sub-regions; and computing a measure of line roughness for each of the first combined line image and the second combined line image.