Patent Document ID: 9749568
Application ID: 14855715
Patent Status: 1

Claim One:
1. An array camera system comprising: a processor; array camera software stored in a memory readable by processor; an imaging sensor configured to capture a plurality of images using a plurality of focal planes, comprising: a plurality of focal planes, where each focal plane comprises a plurality of rows of pixels that also form a plurality of columns of pixels and each focal plane is contained within a region that does not contain pixels from another focal plane; and control circuitry configured to control the capture of image data by the pixels within the focal planes, where the control circuitry is configured so that the capture of image data by the pixels in at least two of the focal planes is separately controllable; an interface for communicating with the processor; wherein the control circuitry comprises a plurality of registers with associated register addresses; wherein the plurality of registers comprises: a plurality of parameter registers, where a given parameter register is associated with one of the plurality of focal planes and contains configuration data for the associated focal plane; and a focal plane group register that contains data identifying focal planes from the plurality of focal planes that belong to a focal plane group; wherein the control circuitry is further configured to: receive commands to write data to and read data from register addresses via the interface; map a virtual register address to the addresses of the parameter registers associated with the focal planes that belong to the focal plane group; modify the parameter registers associated with the focal planes in the focal plane group in response to receiving a command to write a value to the virtual register address via the interface; and control imaging parameters of the plurality of focal planes based upon the configuration data in the parameter register associated with each of the plurality of focal planes; and where the array camera software configures the processor to: generate the commands to write data to and read data from the register addresses; and provide the commands to the control circuitry via the interface.