Patent Document ID: 20040230932
Application ID: 10672145
Patent Status: 0

Claim One:
1. A method for operating semiconductor chips, particularly memory chips, which are arranged in groups on modules (M 1 -M 4 ) which are connected to a common data bus (DQ), where each semiconductor chip (IC 1 -IC 36 ) on each module (M 1 -M 4 ) is connected to at least one data line (DQ 1 -DQ 72 ) in the data bus (DQ), having the following method steps: a) a group of semiconductor chips (IC 1 -IC 36 ) is selected from semiconductor chips (IC 1 -IC 36 ) arranged on the modules (M 1 -M 4 ) on the basis of a prescribed selection criterion independently of module, the selected group of semiconductor chips (IC 1 -IC 36 ) using the data lines (DQ 1 -DQ 72 ) in the data bus (DQ) over the entire bus width; b) the semiconductor chips (IC 1 -IC 36 ) in the selected group are activated; and c) data interchange is performed between the data lines (DQ 1 -DQ 72 ) in the data bus (DQ) and the selected group of semiconductor chips (IC 1 -IC 36 ).