Patent Document ID: 9983967
Application ID: 15166725
Patent Status: 1

Claim One:
1. An apparatus comprising: an instruction provider configured to provide a sequence of instructions based on a representation of a sequence of test vectors, each instruction defining provision of at least one test vector to a device under test; wherein the instruction provider is configured to identify in the representation of the sequence of test vectors subsequences of test vectors which occur at least two times in the representation of the sequence of test vectors, to store the identified subsequences of test vectors in a dictionary memory structure as indexed entries, and to provide the sequence of instructions comprising a first instruction defining a first provision of a first subsequence of test vectors stored in the dictionary memory structure, and a second instruction defining a second provision of the first subsequence of test vectors; and wherein the first instruction and the second instruction reference a same indexed entry of the dictionary memory structure; wherein the instruction provider is configured to provide the sequence of instructions further comprising a third instruction defining a third provision of a true subset of the first subsequence of test vectors; and wherein the third instruction comprises an index value defining the first subsequence of test vectors stored in the dictionary memory structure to which the third instruction references, an offset value defining a first test vector of the true subset of test vectors in the first subsequence of test vectors, and a length value and/or an end value defining a last test vector of the true subset of test vectors in the first subsequence of test vectors.