Patent Document ID: 9075936
Application ID: 14076566
Patent Status: 1

Claim One:
1. A method for pre-coloring IC layout data for a multiple patterning lithography process, comprising: generating a graphical IC layout file comprising a plurality of IC shapes, wherein the plurality of IC shapes comprise an oxide definition region of a first device coupled to a data line, and an oxide definition region of a second device coupled to a complimentary data line; selectively pre-coloring one or more of the plurality of IC shapes by placing one or more pre-coloring marker shapes on the one or more of the plurality of IC shapes, to indicate that the pre-colored IC shapes are to be formed on a same mask of a multiple mask set used for the multiple patterning lithography process, wherein pre-coloring the first and second oxide definition regions reduces processing variations between on-chip structures corresponding to the first and second oxide definition regions; and operating a decomposition algorithm that assigns two or more different colors to uncolored IC shapes, to indicate that different colored IC shapes are to be formed on different masks of the multiple mask set, without changing the pre-colored colors of the pre-colored IC shapes; wherein a computer is used to generate the graphical IC layout file, to selectively pre-color the one or more of the plurality of IC shapes, or to operate the decomposition algorithm.