Patent Document ID: 8631220
Application ID: 13615008
Patent Status: 1

Claim One:
1. A sub-system, comprising: a plurality of memory devices, wherein each memory device has an actual CAS (column address strobe) latency; a serial presence detect (SPD) device configured to provide a simulated CAS latency to a memory controller, wherein the simulated CAS latency is set to a value that causes the memory controller to view the memory devices as having a larger CAS latency than the actual CAS latency of the memory devices; and one or more interface circuits configured to: perform one or more additional functions including one or more of a reliability, accessibility and serviceability (RAS) function, a power management function, or a mirroring of memory function, wherein the one or more interface circuits include additional logic to perform the additional functions; and communicate with the memory devices and a memory controller, wherein the memory devices are configured to communicate with the one or more interface circuits using a first protocol and the one or more interface circuits are configured to communicate with the memory controller using a different, second protocol, wherein the time difference between the larger simulated CAS latency and the actual CAS latency provides time in which the additional logic can perform the one or more additional functions while the sub-system is operating.