Patent Document ID: 9100548
Application ID: 12174832
Patent Status: 1

Claim One:
1. An apparatus, comprising: a plurality of hardware components realizing a plurality of pre-defined features of the apparatus, wherein at least some of the plurality of hardware components are disabled so as to disable corresponding features in the plurality of features; a digital feature register recording enablement state of each one of the plurality of hardware components; a secure processor operable to execute machine-readable instructions to perform operations comprising: validating a received feature token specifying an authorization to change the enablement state of at least one particular hardware component in the plurality of hardware components to enable at least one particular feature in the plurality of features realized by the particular hardware component; and changing the enablement state of the particular hardware component, based at least in part on the received feature token and in response to validating the received feature token; and a general purpose processor controlling access to the plurality of hardware components and operable to execute machine-readable instructions to perform operations comprising: receiving a software request to access the particular hardware component; and determining whether the particular hardware component is enabled by reading the digital feature register; wherein the digital feature register is writable to only by the secure processor and the general purpose processor has direct read-only access to the digital feature register and the enablement state of the particular feature can both be toggled from an enabled state to an unenabled state and from an unenabled state to an enabled state in response to received feature tokens authorizing a change in state of the enablement status of the particular feature.