Patent Document ID: 20020038203
Application ID: 09962827
Patent Status: 0

Claim One:
1. A system for verifying a circuit represented with a circuit description including a plurality of descriptions, the system comprising: a simulator configured to carry out a logic simulation of the circuit description with the use of a test bench for the circuit description; an extractor configured to extract descriptions unexecuted in the logic simulation according to code coverage information for the circuit description; an examiner configured to examine whether or not there is a possibility of executing the extracted unexecuted descriptions; and a prohibited-input-checker generator configured to generate a test pattern to execute the unexecuted description that there is a possibility of executing, and to generate a prohibited-input checker to check whether or not an input pattern of a logic simulation to be carried out is equal to an input pattern of the test pattern to execute the unexecuted description if the test bench is regard as a prohibited input under a specification at a logic simulation using the test pattern to execute the unexecuted description.