Patent Document ID: 5572717
Application ID: 08223914
Patent Status: 1

Claim One:
1. A method for applying timing specifications in a logic design, wherein the logic design includes logic design inputs, logic design outputs and a plurality of logic elements coupled together to form at least one path from a logic design input to one or more logic design outputs via the plurality of logic elements, wherein a logic element includes at least one logic element input and at least one logic element output for coupling to other logic elements, the logic design inputs and the logic design outputs, wherein each logic element, logic element input, logic element output, logic design input and logic design output comprises a node, wherein one or more nodes exist on the paths, the method executing on a computer system operated by a human user, the computer system including a processor coupled to a user input device and an output device, the method comprising the steps of: (a) inputting a timing specification by a user using the user input device, wherein the timing specification comprises a timing parameter assigned to a first user-selected node in a path; (b) using the processor to identify a path that originates at a logic design input, passes through the first node, and terminates at a logic design output; (c) using the processor to determine a timing property of an electrical signal transmitted through the identified path, wherein the timing property corresponds with the timing parameter; (d) using the processor to compare the timing property of the identified path with the timing parameter; and (e) using the output device to indicate the relationship of the identified path's timing property to the timing parameter.