Patent Document ID: 9047532
Application ID: 12019619
Patent Status: 1

Claim One:
1. A method of evaluating a structural element of an electrical circuit fabricated in a lithography process using a simulated contour of an element obtained by simulating a lithographic process that is responsive to a design contour corresponding to the structural element, the method comprising: scanning the electrical circuit with a scanning electon microscope (SEM) to obtain an SEM image of the actual structural element; identifying a robust portion of the simulated contour; processing the SEM image to detect a contour of the actual structural element of the electrical circuit; determining at least one spatial relationship between the robust portion of the simulated contour and a corresponding portion of the detected actual structural element contour; aligning, with a processor, the detected actual structural element contour with the simulated contour using the at least one spatial relationship to provide an aligned actual structural element contour; and comparing the aligned actual structural element contour with reference information.