Patent Document ID: 8065644
Application ID: 12048593
Patent Status: 1

Claim One:
1. A computer-implemented method of reducing susceptibility of a circuit design to single event upsets comprising: determining a susceptibility level of the circuit design to single event upsets according to a ratio of critical configuration bits to total configuration bits of the circuit design; scaling the susceptibility level of the circuit design according to actual area occupied by configuration memory cells of the integrated circuit within which the circuit design to be implemented; scaling the susceptibility level of the circuit design according to a frequency at which particles responsible for single-event upsets strike an area corresponding to an area occupied by an integrated circuit within which the circuit design is to be implemented; comparing, via a computer, the susceptibility level with a target susceptibility; selectively applying a mitigation technique to at least one of a plurality of regions of the circuit design when the susceptibility level of the circuit design exceeds the target susceptibility; and outputting the circuit design comprising the mitigated region.