Patent Document ID: 8510685
Application ID: 12649643
Patent Status: 1

Claim One:
1. A computer implemented method for processing a hierarchical electronic circuit design, the method comprising: using a computer system which comprises at least one processor to perform a processes, the process comprising: identifying one or more logical operations that are associated with a task and involves at least one logical operator, wherein the task is to be performed on the hierarchical electronic circuit design, which comprises a hierarchy including a first level and a second level; and generating a hierarchical output, rather than a flattened output, for a plurality of shapes in the hierarchical electronic circuit design for a result of performing the task on at least some shapes of the plurality of shapes in the hierarchical electronic circuit design based at least in part upon performing the one or more logical operations associated with the task on the at least some shapes on multiple hierarchical levels to determine a derivative shape having a different geometry from the at least some shapes, without flattening the multiple hierarchical levels concerning the at least some shapes in the hierarchical electronic circuit design, wherein the act of generating the hierarchical output comprises: reducing one or more overlapping geometries by at least operating on a subsequently added shape with one or more previously added shapes.