Patent Document ID: 20100299114
Application ID: 12475544
Patent Status: 0

Claim One:
1. A method of calculating the delay of a gate based on a crosstalk effect due to capacitive coupling in a digital integrated circuit (IC), the method comprising: a operation of generating a gate model of a Thevenin equivalent circuit with regard to a gate circuit in the digital IC under the condition that there is no noise current source, and calculating an output waveform with regard to an input voltage; b operation of generating an output resistance library based on an input voltage and an output voltage of the gate; c operation of generating a linear time-varying output resistance model with regard to the gate by using the output waveform and the output resistance library; d operation of generating a modified Thevenin equivalent gate model of the gate under the condition that there is no noise current source by using the linear time-varying output resistance model, and calculating an output waveform that sums a waveform output by using the modified Thevenin equivalent gate model and an output waveform calculated in response to the noise current source with regard to the linear time-varying output resistance model; and e operation of repeatedly applying the output waveform calculated in operation d to operation c, and, if the output waveform calculated in operation d converges, calculating the delay of the gate by using the converged output waveform.