Patent Document ID: 4513388
Application ID: 06601093
Patent Status: 1

Claim One:
1. An electronic device for executing on three digital variables (A, B, K) a mathematical operation of the kind K A+(1-K) B, said electronic device comprising: first and second input means for receiving a first (A) and a second (B) m-bits (m.gtoreq.0) input signals representing two of said three digital variables, and third input means for receiving an (n+1)-bits (n&gt;0) weighting factor signal K representing the third digital variable; at least n logic gates, an i.sup.th logic gate (G.sub.i) (1.ltoreq.i.ltoreq.n) having a first input for receiving the i.sup.th bit coefficient value (K.sub.i) of said weighting factor signal, each of said logic gates being a second input for receiving the zero order bit coefficient value (K.sub.00) of said weighting factor signal, said i.sup.th logic gate (G.sub.i) being provided for generating and presenting at an output thereof a weighting signal K.sub.0i =K.sub.i V K.sub.00, (where V stands for the mathematical "OR"); (n+1) x m electronic circuits (Y) which are arranged as the elements of an (n+1) by m matrix, a matrix element Y.sub.i'j' of the j'.sup.th column (1.ltoreq.j'.ltoreq.m) and the i'.sup.th row (2.ltoreq.i'.ltoreq.n+1) (or vice versa) having a first and a second input for receiving the j.sup.th (a.sub.j and b.sub.j, 0.ltoreq.j.ltoreq.m-1) bit coefficient values of said first and said second input signals, and a third input connected to the output of a respective logic gate for receiving said weighting signal K.sub.0i (i=i'-1), the matrix elements of a first row (i'=1) having a third input for receiving the zero order bit coefficient (K.sub.00) of said weighting factor signal, each of said electronic circuits being provided for generating a partial output signal by executing the mathematical operation Y.sub.ij =K.sub.0i" aj+(1-K.sub.0j")bj (o.ltoreq.i".ltoreq.n) on the bit coefficient values presented at its inputs, each of said electronic circuits having an output for supplying said partial output signal, the outputs of said electronic circuits are connected to inputs of full adders which serve to sum all said partial output signal and for generating a digital output signal of the value Z=KA+(1-K)B; and an output means for supplying said digital output signal.