Patent Document ID: 20050086276
Application ID: 10935193
Patent Status: 0

Claim One:
1. An arithmetic processing apparatus that can be reconfigured in accordance with a processing mode, comprising a plurality of arranged unit arithmetic circuits, wherein each of said unit arithmetic circuits includes: at least one input terminal; at least one output terminal; a first register that holds data; an adder operable to add two pieces of data; a second register that holds data; a bit shifter operable to shift data to one of left and right; a subtractor operable to calculate a difference between two pieces of data; an absolute value calculating unit operable to calculate an absolute value of data; and a path setting unit operable to set a connection path according to the processing mode, the connection path connecting among the input terminal, the output terminal, the first register, the adder, the second register, the bit shifter, the subtractor, and the absolute value calculating unit.