Patent Document ID: 9213799
Application ID: 14459307
Patent Status: 1

Claim One:
1. A systematic defect analyzing method, comprising: utilizing a processor to perform following steps: receiving a plurality of physical features and a plurality of equivalence classes of suspected physical sites of a portion or all of a chip; partitioning physical sites into groups to obtain a plurality of groups of physical sites according to the plurality of physical features of a chip corresponding to different potential systematic defects; computing at least one defect probability of each group of physical sites; and deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites, wherein the analysis result includes a trend result; wherein the step of computing the defect probability of each of the groups of physical sites comprises: according to the plurality of groups of physical sites and the plurality of equivalence classes of suspected physical sites obtained through defect diagnosis, computing a defect probability of each group of physical sites of a site where an equivalence class of a suspected physical site is located for each of the plurality of equivalence classes of suspected physical sites; and the step of deriving the analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of physical sites comprises: computing a variance-within-group of each of the plurality of groups of physical sites according to the plurality of defect probabilities; deriving a simultaneous confidence intervals (SCI) between two neighboring physical sites of the plurality of physical sites according to the plurality of defect probabilities and a plurality of variance-between-groups respectively corresponding to the plurality of groups of physical sites, and further obtaining a plurality of SCIs; and obtaining the trend result according to the plurality of SCIs.