Patent Document ID: 8180621
Application ID: 12209782
Patent Status: 1

Claim One:
1. A method of simulating parametric variations in an integrated circuit (IC) comprising: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal condition, wherein calculating the parametric perturbations includes: simulating the nominal condition for the IC; determining perturbation values for the IC model about the nominal conditions, wherein the perturbation values include linear time-varying matrices and parametric right-hand sides, the parametric right-hand sides characterizing an effect of the parametric perturbations in the IC model; determining a performance metric for the IC and a performance sampling vector for sampling the performance metric about the nominal condition from the perturbation values; and determining voltage-sensitivity values and performance-sensitivity values from the perturbation values and the performance-sampling vector; and saving one or more values for the parametric perturbations in a computer-readable medium.