Patent Document ID: 9990973
Application ID: 15436212
Patent Status: 1

Claim One:
1. An apparatus comprising: a memory; a memory controller coupled to the memory, wherein the memory controller is configured to convey a data strobe signal to the memory during transfers of data between the memory and the memory controller, wherein the memory controller includes a calibration control unit configured to: perform a calibration of eye openings for signals conveyed between the memory and the memory controller, wherein the calibration includes determining a plurality of calibration points, wherein the eye opening comprises a range of delays of the data strobe signal and a range of reference voltages, wherein a given reference voltage is used to distinguish between a logic zero and a logic one read from the memory; compute an initial score for each of the plurality of calibration points; compute an adjusted score for each of the plurality of calibration points, wherein the adjusted score for each of the plurality of calibration points includes a weighting based on one or more adjacent ones of the plurality of calibration points; and select one of the plurality of calibration points having a highest adjusted score as a final calibration result for the calibration.