Patent Document ID: 9892224
Application ID: 14995413
Patent Status: 1

Claim One:
1. A method of forming a set of masks for manufacturing an integrated circuit, the method comprising: determining a presence of a first via layout pattern and a power rail layout pattern in an original layout design, the first via layout pattern and the power rail layout pattern overlapping each other, the first via layout pattern being part of a first cell layout of the original layout design, the power rail layout pattern being shared by the first cell layout and a second cell layout of the original layout design and extending along a cell boundary between the first cell layout and the second cell layout, the first via layout pattern corresponding to a first via plug layer of the integrated circuit, and the shared power rail layout pattern corresponding to a first conductive layer of the integrated circuit above the first via plug layer; and identifying a pre-defined relationship between the first cell layout, the power rail layout and the second cell layout; in response to identifying the pre-defined relationship, generating a modified layout design by replacing the first via layout pattern with an enlarged via layout pattern, the enlarged via layout pattern occupying an area greater than that occupied by the first via layout pattern; and forming the set of masks based on the modified layout design.