Patent Document ID: 6017771
Application ID: 09067264
Patent Status: 1

Claim One:
1. A method for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages, said method comprising the steps of: inspecting semiconductor devices on said wafer visually to identify the location of visual defects on dies being manufactured on said wafer and to maintain a count of visual defects on said dies by location, inspecting said semiconductor dies on said wafer to determine the location and number defective dies on said wafer at each of said manufacturing stages, calculating the defective die count for each stage for said wafer, calculating the defective bad die count for each stage for said wafer, determining the percentage of the defective bad die count divided by the defective die count, plotting the trend of the percentage of yield loss and the percentage of defective bad dies for each of said manufacturing stages, and comparing said plots to determine said killer stage from analysis of the relative trends of matching between said plots of yield lost and the percentage of bad dies for said stage.