Patent Document ID: 9495502
Application ID: 14288885
Patent Status: 1

Claim One:
1. A computer program product for implementing management of layer promotion in a routing phase of integrated circuit design, the computer program product comprising: a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processor to cause the processor to perform a method comprising: identifying a set of candidate interconnects for the layer promotion; scoring and sorting the set of candidate interconnects according to a respective score, thereby establishing a respective rank; assessing routing demand and resource availability based on promoting the set of candidate interconnects; and managing, using a processor, the set of candidate interconnects based on the respective rank and the assessing, the assessing and the managing being done iteratively and the managing including, in at least one iteration, generating a second set of candidate interconnects based on reducing the set of candidate interconnects, wherein the scoring the set of candidate interconnects includes determining, for each candidate interconnect of the set of candidate interconnects, an amount of time by which the candidate interconnect exceeds a timing requirement and a degree to which a length of a path including the candidate interconnect exceeds a minimum possible length of the path, and the scoring the set of candidate interconnects includes calculating, for the respective candidate interconnect, a score given by: 
 score=scaling t *t _metric+scaling p *p _metric, where scaling t and scaling p are scaling factors, t_metric relates to the amount of time by which the candidate interconnect exceeds the timing requirement, and p_metric relates to the degree to which the length of the path including the candidate interconnect exceeds the minimum possible length of the path.