Patent Document ID: 5465216
Application ID: 08071244
Patent Status: 1

Claim One:
1. In a computer system, an automatic method for formal verification of a portion of a logic circuit, comprising the following steps: a. receiving a parameterized model of said logic circuit from a first file, said parameterized model of said logic circuit including parameterized expressions representing components in said logic circuit, wherein said expressions include parameters which may be defined externally; b. defining said parameters externally to said parameterized model, said defining including assigning values to certain of said parameters which specify that fewer components are in said parameterized model of said logic circuit than a full model of said logic circuit: c. for each of said parameterized expressions in said parameterized model, generating component description statements in a hardware description language (HDL) for said components using said externally defined parameters, and storing a reduced model of said logic circuit in a second file for further processing, wherein said reduced model of said logic circuit comprises a subset of said full model of said logic circuit; and d. transmitting said second file to a process for formal verification, said process for formal verification performing formal verification on said reduced model of said logic circuit using said second file.