Patent Document ID: 8401339
Application ID: 12800266
Patent Status: 1

Claim One:
1. A digital image processing apparatus to process video data information of a captured input digital image comprising: a first programmable register to store a first value that corresponds to the captured input digital image width; a second programmable register to store a second value that corresponds to the captured input digital image height; a third programmable register to store a third value that corresponds to a first size information of a first quadrangle digital image; a fourth programmable register to store a fourth value that corresponds to a first location information of the first quadrangle digital image within the captured input digital image, wherein the first quadrangle digital image comprises a first portion of the captured input digital image; a fifth programmable register to store a fifth value that corresponds to a second size information of a second quadrangle digital image; a sixth programmable register to store a sixth value that corresponds to a second location information of the second quadrangle digital image within the captured input digital image, wherein the second quadrangle digital image comprises a second portion of the captured input digital image; a first logic circuitry that is coupled to the first, second, third, fourth, fifth, and sixth programmable registers, and is configured to: (i) receive, in accordance with a first video format, the first value, and the second value, the video data information of the captured input digital image, (ii) extract a first video data information that corresponds to the first quadrangle digital image, in accordance with the third and fourth value, (iii) extract a second video data information that corresponds to the second quadrangle digital image, in accordance with the fifth and sixth values, and (iv) store the first and second video data information using a first memory device; a second logic circuitry that is coupled to the first memory device, the third programmable register, and the fourth programmable register, and is configured to: (i) retrieve from the first memory device the first video data information, using at least one of the third value and the fourth value, (ii) generate video data information for at least one of a first top margin and a first bottom margin, (iii) process, in the vertical direction, the retrieved video data information and the video data information corresponding to at least one of the first top margin and the first bottom margin, and (iv) store the resultant vertically processed video data information using a first buffer; a third logic circuitry that is coupled to the first buffer and a fourth logic circuitry, and is configured to: (i) retrieve from the first buffer the resultant vertically processed video data information, (ii) generate video data information for at least one of a first left margin and a first right margin, (iii) process, in the horizontal direction, the resultant vertically processed video data information and the video data information corresponding to at least one of the first left margin and the first right margin, and (iv) stream the resultant vertically and horizontally processed video data information to the fourth logic circuitry; and the fourth logic circuitry, which is coupled to a first output port, and is configured to: (i) receive the resultant vertically and horizontally processed video data information, (ii) process the resultant vertically and horizontally processed video data information in accordance with the first video format, and (ii) output a first vertically and horizontally processed video data information stream to the first output port.