Patent Document ID: 8037428
Application ID: 12129617
Patent Status: 1

Claim One:
1. A method for verifying an integrated circuit (IC) chip layout, the method comprising: receiving a layout of an IC chip after the layout has gone through a place-and-route operation; performing a lithography compliance checking (LCC) operation on the layout to detect lithography hotspots within the layout, wherein each lithography hotspot is associated with a local routing pattern around the lithography hotspot; associating each detected lithography hotspot with a bounding box which encloses the associated local routing pattern; and for each detected lithography hotspot, comparing, by computer, the associated local routing pattern against a hotspot database to determine if the local routing pattern matches an entry in the hotspot database, which stores both a set of known hotspot configurations and correction guidance information associated with each hotspot configuration in the set of known hotspot configurations, and: if a match is found, correcting the lithography hotspot using the correction guidance information associated with the hotspot configuration stored in the hotspot database, otherwise, correcting the lithography hotspot by performing a local rip-up and reroute on the local routing pattern.