Patent Document ID: 20170370989
Application ID: 15194645
Patent Status: 0

Claim One:
1. A quantum-logic test-development system comprising a processor, a memory coupled to the processor, and a computer-readable hardware storage device coupled to the processor, the storage device containing program code configured to be run by the processor via the memory to implement a method for using direct sums and invariance groups to test partially symmetric quantum-logic circuits, the method comprising: the system receiving architectural information about a quantum-logic circuit that has at least four inputs and at least one output; the system, as a function of the architectural information, dividing the at least four inputs into two or more non-intersecting subsets; the system creating a set of groups that each comprise a subset, selected from the set of two or more non-intersecting subsets, and one or more permutation operations capable of being performed upon inputs comprised by the selected subset; the system generating a direct sum of the set of groups, where the direct sum identifies an invariance group of a function that represents functionality of the quantum-logic circuit, where the invariance group comprises a set of invariant permutations, where each permutation of the set of invariant permutations identifies a permutation of two or more inputs comprised by one and only one subset of the two or more non-intersecting subsets, and where no output of the quantum-logic circuit changes state when any permutation of the set of invariant permutations is performed upon the at least four inputs of the quantum-logic circuit.