Patent Document ID: 8359187
Application ID: 11461420
Patent Status: 1

Claim One:
1. An apparatus, comprising: an interface circuit operable to communicate with a first number of separate physical memory circuit devices and a system, wherein the interface circuit is operable to: present to the system a second number of simulated memory circuit devices such that the first number of physical memory circuit devices appear to the system as the second number of simulated memory circuit devices, wherein presenting the simulated memory circuit devices to the system includes simulating one or more mode register operation control signals, and wherein the second number is less than the first number; receive, from the system, address or control signals sent to the second number of simulated memory circuit devices for performing one or more operations on the second number of simulated memory circuit devices; communicate the address or control signals to the first number of memory circuit devices; present to the system a first column address strobe (CAS) latency associated with each simulated memory circuit device, wherein the first CAS latency is a higher value than a second CAS latency associated with each physical memory circuit device; receive, from a memory controller of the system, write commands sent to the second number of simulated memory circuit devices; and delay communicating the write commands to the first number of physical memory circuit devices by an amount of time equal to the difference between the first CAS latency and the second CAS latency.