Patent Document ID: 20010016937
Application ID: 09785007
Patent Status: 0

Claim One:
1. An LSI mask writing data compressing system comprising: an individual layout pattern one-dimensional array generating unit for generating first-coordinate-axial one-dimensional arrays for each individual layout pattern and second-coordinate-axial one-dimensional arrays for each individual layout pattern by using layout pattern data of unit section regions of LSI design data, which comprise a plurality of unit section regions and which correspond to said unit section regions of LSI mask writing data to be compressed, from layout patterns of said unit section regions, and for setting layout pattern data of the residual layout patterns as random layout pattern data, each of said first-coordinate-axial one-dimensional arrays for each individual layout pattern being formed by repeatedly arranging individual layout patterns having the same shape on an LSI mask writing plane at regular intervals in the direction of a first coordinate axis, each of said second-coordinate-axial one-dimensional arrays for each individual layout pattern being formed by repeatedly arranging individual layout patterns having the same shape on the LSI mask writing plane at regular intervals in the direction of a second coordinate axis perpendicular to said first coordinate axis; an individual layout pattern two-dimensional array generating unit for generating two-dimensional arrays for each individual layout pattern from selected first-coordinate-axial one-dimensional arrays for each individual layout pattern, which are selected from said first-coordinate-axial one-dimensional arrays for each individual layout pattern, each of said selected first-coordinate-axial one-dimensional arrays for each individual layout pattern including the same number of said individual layout patterns having the same shape arranged at the same regular intervals in the direction of said first coordinate axis, each of said two-dimensional arrays for each individual layout pattern being formed by repeatedly arranging said selected first-coordinate-axial one-dimensional arrays for each individual layout pattern on said LSI mask writing plane at regular intervals in the direction of said second coordinate axis; a multiple layout pattern block array generating unit for generating a first-coordinate-axial block array of multiple layout patterns from the residual first-coordinate-axial one-dimensional arrays for each individual layout pattern other than said selected first-coordinate-axial one-dimensional arrays for each individual layout pattern which have constituted any one of said two-dimensional arrays for each individual layout pattern, said first-coordinate-axial block array of multiple layout patterns being formed by grouping the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of said first coordinate axis regardless of the shape of individual layout patterns included in said first-coordinate-axial block array of multiple layout patterns, for generating a second-coordinate-axial block array of multiple layout patterns from the residual second-coordinate-axial one-dimensional arrays for each individual layout pattern other than said selected second-coordinate-axial one-dimensional arrays for each individual layout pattern which have constituted any one of said two-dimensional arrays for each individual layout pattern, said second-coordinate-axial block array of multiple layout patterns being formed by grouping the same number of individual layout patterns repeatedly arranged at the same regular intervals in the direction of said second coordinate axis regardless of the shape of individual layout patterns included in said second-coordinate-axial block array of multiple layout patterns, and for generating a two-dimensional block array of multiple layout patterns from said two-dimensional arrays for each individual layout pattern, said two-dimensional block array of multiple layout patterns being formed by grouping the same number of individual layout patterns of said two-dimensional arrays of individual layout patterns repeatedly arranged at the same regular intervals regardless of the shape of individual layout patterns included in said two-dimensional arrays of individual layout patterns.