Patent Document ID: 8194968
Application ID: 11970294
Patent Status: 1

Claim One:
1. A computer-implemented method, comprising: generating electrical information for a device being fabricated on a wafer by processing design data for the device, wherein the design data cormprises physical layout information, three-dimensional structure information, netlist information, or some combination thereof; and using the electrical information to perform one or more defect-related functions, wherein the one or more defect-related functions comprise one or more post-mask, defect-related functions, wherein the one or more defect-related functions further comprise using the electrical information and defect information generated by a defect review tool to determine electrical effects on the device due to defects detected on the wafer and using the electrical effects to determine a classification or ranking for the defects and wherein said generating and said using the electrical information are performed using a computer system.