Patent Document ID: 20120173597
Application ID: 12985180
Patent Status: 0

Claim One:
1. An apparatus for performing an effective subtraction of two floating point inputs each having an unsigned magnitude mantissa and an exponent, the apparatus comprising: wires and logic, configured to: zero-extend by one bit, left-shift by one bit, and invert the mantissa of one of the two inputs having an exponent that is one larger than the exponent of the other of the two inputs to produce a first addend; and zero-extend by one bit the mantissa of the other input of the two inputs to produce a second addend; an adder, configured to add the first and second addends, wherein a negative difference is produced by the adder in response to production of the first and second addends by the wires and logic; an inverter, configured to invert the negative difference to produce an unnormal mantissa; a plurality of two-input NAND (NOT-AND) gates, configured to perform a Boolean NAND function on the first and second addends to produce a prediction string; and a shifter, configured to left-shift the unnormal mantissa by a shift amount based on the prediction string to produce a normalized mantissa result.