Patent Document ID: 8340953
Application ID: 11553372
Patent Status: 1

Claim One:
1. A memory apparatus for use with a host system, the memory apparatus comprising: a plurality of physical memory circuits; a component coupled to the plurality of physical memory circuits and couplable to the host system to provide an interface between the host system and the plurality of physical memory circuits, wherein the component is operable to: provide to the host system an interface to a simulated memory circuit that differs in at least one aspect from a corresponding aspect of at least one of the plurality of physical memory circuits; and for each physical memory circuit of the plurality of physical memory circuits coupled to the component, (1) determine whether the physical memory circuit is being accessed, and (2) perform a power-saving operation on the physical memory circuit, subsequent to determining that the physical memory circuit is not being accessed, to reduce a power dissipation of the physical memory circuit, wherein the plurality of physical memory circuits comprises a first number (P) of physical memory circuits, and the memory apparatus is operable such that a second number (N) of physical memory circuits is continuously subjected to the power-saving operation, wherein N<P.