Patent Document ID: 9032340
Application ID: 14215635
Patent Status: 1

Claim One:
1. A layout decomposition method, executed by a logic processor of a computing system, comprising: receiving a design layout by the logic processor; identifying a design rule for layout decomposition by the logic processor, comprising: identifying a plurality of dense areas on a substrate; and identifying first areas with odd-numbered features; and generating a set of masks for forming the odd-numbered features in the first areas of the dense areas according to results of design rule identification by the computing system, wherein the set of masks comprises: a first mask having a first pattern for fabricating, in at least the dense areas, patterns of spacers with pitches required in the dense areas; and a second mask having a second pattern including correction regions related to the dense areas for correcting the patterns of the spacers, wherein the correction regions of the second mask includes opaque regions and transmissive regions, respectively for shielding and cutting the spacers formed on substrate.