Patent Document ID: 8881084
Application ID: 12780426
Patent Status: 1

Claim One:
1. A method of generating a layout for a semiconductor device, comprising: receiving a first layout; defining a portion of the first layout as a first FinFET region, the first FinFET region having first and second sides that each extend approximately in a first direction; performing, using an electronic design rule simulator that contains computer hardware, a first design rule check (DRC) simulation; obtaining a first DRC simulation result; defining a plurality of mandrel regions, the mandrel regions each including a first elongate edge and a second elongate edge opposite the first elongate edge, wherein the first and second elongate edges each extend approximately in the first direction; defining a plurality of first fin regions and a plurality of second fin regions different from the first fin regions, wherein the plurality of first fin regions are defined to be bordering the first elongate edges of a subset of the mandrel regions, respectively, and wherein the plurality of second fin regions are defined to be bordering the second elongate edges of the subset of the mandrel regions, respectively; thereafter defining a second FinFET region by moving the first side in a second direction perpendicular to the first direction, wherein the defining the second FinFET region further includes moving the mandrel regions, without changing spacings between adjacent mandrel regions, in the second direction together with the first side; performing, using the electronic design rule simulator, a second DRC simulation; obtaining a second DRC simulation result; selecting one of the first and second FinFET regions based on the first and second DRC simulation results; generating a second layout using the selected FinFET region; and storing the second layout in a non-transitory, tangible computer readable medium.