Patent Document ID: 9542353
Application ID: 11929225
Patent Status: 1

Claim One:
1. A sub-system, comprising: a first number of physical memory circuits limited by one or more device command scheduling constraints; an interface circuit electrically connected to the physical memory circuits via multiple independent data paths and electrically coupled to a memory controller via a separate data path, the interface circuit configured to: communicate with the first number of physical memory circuits and the memory controller, interface the first number of physical memory circuits to simulate a different, second number of virtual memory circuits, present the different, second number of virtual memory circuits to the memory controller, translate row-activation commands or column-access commands, received from the memory controller directed to at least one of the different, second number of virtual memory circuits, to corresponding row-activation commands or column-access commands, issue the corresponding row-activation commands or column-access commands to at least one of the first number of physical memory circuits, combine data received on the data paths from any of the first number of physical memory circuits, and provide the combined data to the memory controller, such that the different, second number of virtual memory circuits appear to the memory controller as free from the one or more device command scheduling constraints; wherein each of the first number of physical memory circuits comprises a respective plurality of physical memory banks, and wherein, for each of the second number of virtual memory circuits, the interface circuit is configured to simulate a respective plurality of virtual memory banks using two or more physical memory banks of at least two physical memory circuits of the first number of physical memory circuits.