Patent Document ID: 5566344
Application ID: 08445006
Patent Status: 1

Claim One:
1. A multiple chip package processor having multiple operational modes, including a run mode and an in-system programming mode, said multiple chip package processor comprising; a processor die, including a central processing unit having a data output terminal for outputting data and a program counter terminal for outputting addresses for instruction fetching from a program counter in said central processing unit, a memory die, including a primary memory for storing instructions for operating said central processing unit in said run mode, said primary memory having a plurality of addressable storage locations, an address input terminal for accepting addresses for accessing said storage locations, a data input terminal for accepting data to be stored in said storage locations, and a data output terminal for outputting data stored in said storage locations, a package enclosing said processor die and said memory die, a second memory on said processor die for storing an instruction set for programming said primary memory in said in-system programming mode, a first multiplexer having a first input coupled to said program counter terminal and a second input coupled to said data output terminal of said central processing unit and an output terminal coupled to said primary memory, and a control circuit for controlling said first multiplexer to select its first input in said run mode so that said primary memory is addressed by said program counter and to select its second input in said in-system programming mode so that said primary memory is addressed by data at said data output terminal of said central processing unit.