Patent Document ID: 9985654
Application ID: 15098709
Patent Status: 1

Claim One:
1. A method of erasure error correction in an integrated circuit (IC), comprising: receiving input data from a channel coupled to the IC; determining a bit pattern indicating survived blocks and erased blocks of a plurality of blocks in the input data; determining, at an address generator circuit, a number of integers, in a finite set of integers, greater than or less than an integer representing the bit pattern, the finite set of integers representing a finite set of possible values of the bit pattern based on an (m, k) erasure coding scheme; generating, at the address generator circuit, an address signal for a memory, from the determined number of integers to obtain a pre-computed decoding matrix associated with the bit pattern; receiving the address signal from the address generator circuit at a memory that stores a plurality pre-computed decoding matrices based on the (m, k) erasure coding scheme; receiving the survived blocks, and a signal from the memory indicative of the pre-computed decoding matrix, at a matrix multiplication circuit and recovering the erased blocks through matrix multiplication using the pre-computed decoding matrix and the survived blocks as parametric input.