Patent Document ID: 20050047192
Application ID: 10895394
Patent Status: 0

Claim One:
1. A semiconductor integrated circuit comprising: a memory interface circuit; a data processing circuit; and a clock generator, wherein the memory interface circuit is capable of coupling to a double data rate type synchronous memory which outputs read data in synchronization with a data strobe signal together with the data strobe signal, wherein the clock generator generates internal clock signals and memory clock signals supplied to the synchronous memory, and wherein the memory interface circuit determines a delay of arrival of the data strobe signal relative to the internal clock signal by using a data strobe signal inputted in a read cycle with respect to the synchronous memory, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay.