Patent Document ID: 10002217
Application ID: 14332240
Patent Status: 1

Claim One:
1. A computer implemented method of performing region based device bypass in circuit simulation, comprising: receiving a subcircuit for simulation, wherein the subcircuit includes a plurality of devices; determining node tolerance of the plurality of devices, including examining variations of each node voltage with respect to a corresponding predetermined node tolerance; for each device in the plurality of devices, determining whether the device has entered into a bypass region using the node tolerance of the plurality of devices; performing model evaluation in response to the device has not entered the bypass region; skipping model evaluation in response to the device has entered the bypass region, comprising preloading conductance of the device its a bypass aggregation conductance matrix, and adding the bypass aggregation conductance matrix to a conductance matrix of the subcircuit at each time step, wherein a sum of the bypass aggregation conductance matrix and the conductance matrix is used to reduce computation in a model evaluation process of the circuit simulation.