Patent Document ID: 20020064073
Application ID: 09726473
Patent Status: 0

Claim One:
1. A DRAM module using a SRAM to replace a damaged DRAM cell, the DRAM module coupled to a system bus and being activated by a power up signal, comprising: a damaged address recorder, to pre-store a plurality of damaged address data, and to output the damaged address data by a power up signal; a content addressable memory, coupled to the damaged address recorder, to write the damaged address data therein, and to receive a DRAM address data to compare to the damaged address data to output a match signal; a SRAM, coupled to the content addressable memory to receive the match signal, and to access a data signal according to the match signal and a DRAM control signal; a DRAM, coupled to the content addressable memory to receive the match signal and the DRAM address data, and to access the data signal according to the match signal, the DRAM address signal and the DRAM control signal; and a DRAM control logic circuit, coupled to the system bus, the content addressable memory, the DRAM control signal and the data signal, to perform one of the following operations: data signal access in the SRAM; data signal access in the DRAM; and data written into the content addressable memory.