Patent Document ID: 20030021175
Application ID: 10206702
Patent Status: 0

Claim One:
1. A low power type Rambus DRAM comprising: a top memory bank unit comprising a plurality of banks for storing data; a bottom memory bank unit comprising a plurality of banks for storing data; a top serial/parallel shifter unit connected between the top memory bank unit and input/output block unit for converting data received by read or write command into serial or parallel data and outputting the result; and a bottom serial/parallel shifter unit connected between the bottom memory bank unit and input/output block unit for converting data received by read or write command into serial or parallel data and outputting the result, the Rambus DRAM including an interface logic circuit unit for generating first read clock signal R 1 and top read selection signal R_top or bottom read selection signal R_bot for selecting the top or the bottom memory bank unit according to read command received from the external and generating first write clock signal W 1 and top write selection signal W_top or bottom write selection signal W_bot for selecting the top or the bottom memory bank unit according to write command received from the external; a delay lock loop (DLL) unit for receiving the first write clock signal W 1 to generate first write clock signal W 2 and receiving the first read clock signal R 1 to generate synchronized second read clock signal R 2 ; and an input/output block unit for generating signals for selectively controlling the operation of top serial/parallel shifter unit or bottom serial/parallel shifter unit by buffering the first write clock signal W 2 or the first read clock signal R 2 received from the DLL according to the top read selection signal R_top, the bottom read selection signal R_bot, the top write selection signal W_top and the bottom write selection signal W_bot received from the interface logic circuit unit.