Patent Document ID: 20020184562
Application ID: 09843307
Patent Status: 0

Claim One:
1. In a method of designing a circuit containing a plurality of Test Access Port (TAP) interfaces, each said TAP having a Test Data Input (TDI), a Test Data Output (TDO), a Test Mode Select (TMS) input, a Test Clock Input and a Test Reset input (TRSTN), an instruction register and at least one test data register, the method comprising the steps of: providing a master TAP for at least controlling data transfer operations with other TAPs in said circuit; connecting master TAP test inputs and output to corresponding circuit test inputs and outputs; adding to said master TAP: an instruction register having a length equal to the length of the longest instruction register of each other TAP plus a predetermined number of bits for storing a TAP selection code for selecting one of the TAPs; a TDO circuit responsive to the TAP selection code for selectively connecting the TDO of one of the TAPs to the circuit TDO; and for each other TAP: adding a padding register having a length equal to the length of said master TAP instruction register less the length of the instruction register of said each other TAP and having an input connected to the circuit TDI, and an output; adding a TMS circuit responsive to a predetermined TAP selection code of said each other TAP for gating TMS pulses applied to the circuit TMS input to said each other TAP; adding a TDI circuit responsive to a shift state signal for connecting the TAP TDI to either the circuit TDI and or the output of said padding register.