Patent Document ID: 10014229
Application ID: 15041016
Patent Status: 1

Claim One:
1. A system configured to generate a wafer inspection process, comprising: an inspection subsystem configured to scan a wafer to detect defects on the wafer; and one or more computer subsystems configured for: storing output of one or more detectors of the inspection subsystem during the scanning regardless of whether the output corresponds to the defects detected on the wafer; separating physical locations on the wafer that correspond to bit failures detected by testing of the wafer into a first portion of the physical locations at which the defects were not detected and a second portion of the physical locations at which the defects were detected; storing information for the first portion of the physical locations as hot spots; applying one or more defect detection methods to the stored output corresponding to the first portion of the physical locations to detect defects at the first portion of the physical locations, wherein said applying comprises iteratively applying the one or more defect detection methods to the stored output corresponding to the first portion of the physical locations, comparing the defects detected at the first portion of the physical locations to the bit failures, and changing one or more parameters of the one or more defect detection methods until the defects are detected at the first portion of the physical locations; and generating a wafer inspection process based on the defects detected by the one or more defect detection methods at the first portion of the physical locations.