Patent Document ID: 20020010560
Application ID: 09732339
Patent Status: 0

Claim One:
1. A method of automated defect localization in the testing of semiconductor integrated circuits, comprising the steps of: creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, each potential bridging fault being associated with at least two tested nets of the circuit; receiving physical data associated with each of the tested nets of the circuit; applying adjacency criteria to the physical data associated with the at least two tested nets that are associated with each of the listed potential bridging faults; generating the pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria; performing in-line inspection of the integrated circuits to obtain second localized probable defect data; and correlating the pruned diagnostic list of potential bridging faults with said second localized probable defect data.