Patent Document ID: 9106857
Application ID: 14273832
Patent Status: 1

Claim One:
1. A method for limiting fixed pattern noise (FPN) in a time delay and integration (TDI) mode of operation of a complementary metal oxide semiconductor (CMOS) imaging device, the method comprising: for each line time, selecting a pixel for each column of photosensitive elements in the along track direction to capture dark information such that the selected pixel does not correspond to a portion of a scene that was previously selected to capture dark information in a current TDI period; for each line time, capturing dark information for the selected pixel to capture FPN effects associated with the selected pixel; summing the dark information captured from each pixel for each column of photosensitive elements over the current TDI period to provide a dark information sum for each column of photosensitive elements; and, correcting TDI pixel output for each column during a next TDI period using the corresponding dark information sum during each line time of the next TDI period.