Patent Document ID: 20030035335
Application ID: 10227779
Patent Status: 0

Claim One:
1. A semiconductor memory comprising: a memory core which executes a write operation by using row address data, column address data and write data; a command detecting circuit which detects an operation mode in each of successive first and second cycles, wherein when the operation mode in the first cycle is a write mode, the write mode is completed by the first cycle loading the row address data, the column address data and the write data into a chip and the second cycle transferring the row address data, the column address data and the write data to the memory core and executing the write operation; and a controller which controls an operation of the chip, wherein when the operation mode in the second cycle is a refresh mode, a loading of the row address data, the column address data and the write data is inhibited in the second cycle, and a refresh operation is executed after the write operation.