Patent Document ID: 9501747
Application ID: 14109663
Patent Status: 1

Claim One:
1. A method for use in embedding a problem in a target processor, the problem represented as a problem graph having a number of decision variables and the target processor comprising qubits coupleable by couplers and represented as a hardware graph having a plurality of vertices corresponding to qubits coupleable via a number of edges corresponding to couplers, the method comprising: in a first stage, successively generating a number of sets of connected subgraphs, each set including a respective subgraph for each decision variable in the problem graph, where adjacent decisions variables in the problem graph are mapped to respective vertices in the hardware graph, the respective vertices which are connected by at least one respective edge in the hardware graph, wherein successively generating a number of sets of connected subgraphs includes using used vertices in the hardware graph to represent the decision variables if no unused vertex in the hardware graph is available; and in a second stage, following the first stage, refining the connected subgraphs created in the first stage such that no vertex represents more than a single decision variable; creating a problem formulation executable by the target processor based on the refining of the connected subgraphs; and transmitting the problem formulation to the target processor for execution by the target processor.