Patent Document ID: 20010017891
Application ID: 09853123
Patent Status: 0

Claim One:
1. A decoder circuit for decoding digital video signals including one of a high definition and a standard definition digital video signal, wherein the high definition video signal includes digital video data representing high definition pictures and the standard definition digital video signal includes digital video data representing standard definition pictures, the decoder circuit comprising: a channel buffer for temporarily storing the digital video data; a downsampler module coupled to the channel buffer, the downsampler module being adapted for receiving a mode control signal having one of a first state and a second state, the downsampler module downsampling and outputting the digital video data representing the pictures when the mode control signal is in the first state and outputting the digital video data representing the pictures without performing downsampling when the mode control signal is in the second state;.and a picture memory coupled to the downsampler module for storing the digital video data representing the pictures output by the downsampler module.