Patent Document ID: 7669175
Application ID: 11747485
Patent Status: 1

Claim One:
1. A method for designing a layout for manufacturing an integrated circuit, the method implemented in a computer, said method comprising the steps of: providing a design layout comprising a layout of an integrated circuit, said design layout including functional design shapes; discretizing said functional design shapes into a plurality of computational subunits, said computation units comprising finite elements of said functional shapes; identifying a geometrical context region around each of said plurality of computational subunits; identifying a representative subunit of said plurality of computational subunits wherein said representative subunit represents a subset of said plurality of computational subunits each subunit of said subset having essentially identical geometrical context regions; performing a computation for said representative subunit of said subset, said computation comprising simulation of an electrical characteristic of said integrated circuit; applying said computation to all occurrences of said representative subunit in said design layout, and storing said applied computation in a computer memory.