Patent Document ID: 4566082
Application ID: 06478181
Patent Status: 1

Claim One:
1. An expandable memory pack addressing system for a microprocessor system, comprising: an address bus provided within said microprocessor system, said address bus having a plurality of parallel-bit address lines coupled to respective first contacts of a memory pack connector; memory selection means provided within said microprocessor system, said memory selection means having a plurality of input lines coupled to respective second contacts of said memory pack connector and a plurality of memory select output lines coupled to respective third contacts of said memory pack connector; and memory pack means connectable to said memory pack connector, said memory pack means comprising a plurality of selectable memories, a plurality of address lines connected to said memories, a plurality of memory selection lines connected to said memories, and a plurality of feedback signal lines, wherein said address lines are connectable to some, but not all, of said first contacts of said memory pack connector, said feedback signal lines are connectable between predetermined said first contacts and second contacts of said memory pack connector, and said memory selection lines are connectable to said third contacts of said memory pack connector.