Patent Document ID: 20110153271
Application ID: 12646623
Patent Status: 0

Claim One:
1. In an integrated circuit yield analysis tool implemented in a computer system having one or more computer processors and a computer-readable storage medium, a method for estimating a failure probability of an integrated circuit associated with a plurality of parameters, the values of the parameters being described by a first probability distribution function, the method comprising: selecting with one or more of the computer processors a first plurality of samples using a uniform distribution in the values of the plurality of parameters; performing a first test to determine an outcome for each of the first plurality of samples and identifying failed samples based on the determined outcomes; clustering the failed samples using a computer-implemented cluster forming method that, in some cases, returns multiple clusters; forming with one or more of the computer processors a probability distribution function for each of the one or more clusters; forming with one or more of the computer processors a composite probability distribution function that includes a weighted combination of the first probability distribution function and the probability distribution function for each of the one or more clusters; selecting with one or more of the computer processors a second plurality of samples using the composite probability distribution function; performing a second test with one or more of the computer processors to determine an outcome for each of the second plurality of samples; and computing a failure probability with one or more of the computer processors using the outcome for each of the second plurality of samples, the first probability distribution function, and the composite probability distribution function.