Patent Document ID: 7885799
Application ID: 11945991
Patent Status: 1

Claim One:
1. A method for building an MOS transistor model including a statistical variation of noise, comprising: measuring noise in MOS transistors from different dies, wherein the noise is a 1/f noise of PMOS transistors and NMOS transistors; creating a noise distribution diagram in accordance with the obtained noise data of the MOS transistors; adding a variation of a noise parameter in at least one noise model file into a library file of an MOS transistor to simulate noise in MOS transistors; if a simulation result does not cover the noise data in the noise distribution diagram, continuously changing the variation of the noise parameter until the simulation result covers the noise data in the noise distribution diagram, wherein the simulation result is a range determined with 1/f noise of four MOS transistors in extreme situations of FF, SS, FNSP and SNFP at a frequency as four vertices, wherein the simulation result does not cover the noise data in the noise distribution diagram when the noise data is not totally within a quadrangle constructed by the four vertices, wherein the continuously changing is made toward a trend to cover the noise data in the noise distribution diagram, and wherein FF is fast NMOS and fast PMOS, SS is slow NMOS and slow PMOS, FNSP is fast NMOS and slow PMOS, and SNFP is slow NMOS and fast PMOS ; and if the simulation result covers the noise data in the noise distribution diagram, adding a corresponding variation of the noise parameter into the library file of the MOS transistor as the MOS transistor model including a statistical variation of noise.