Patent Document ID: 20030131160
Application ID: 10278478
Patent Status: 0

Claim One:
1. A memory system, comprising: a memory controller; a memory component having a memory core for holding read data information and an interface that is coupled to at least one bus that is also coupled to the memory controller for conveying signals between the memory controller and the memory component; the interface of the memory component configured to: receive a first signal from the memory controller with read request information; retrieve the read data information from the memory core in response to the request information; and transmit to the memory controller a second signal containing the read data information, wherein the read data information is comprised of read data symbols and where the average duration of the read data symbols, measured at the interface, defines a symbol time interval, wherein the read request information includes a first read request and a second read request having an internal access time similar to an internal read access time of the first read request; wherein operation of the memory component is characterized by: a first external access time interval, measured at the interface, between the first read request and respective first read data transmitted by the interface in response to the first read request; a second external access time interval, measured at the interface, between the second read request and respective second read data transmitted by the interface in response to the second read request; and the difference between the first external access time and the second external access time is greater than one-half of the symbol time interval.