Patent Document ID: 20130019215
Application ID: 13550130
Patent Status: 0

Claim One:
1. A system for optimizing Boolean logic, the system comprising: a processor; and a non-transitory, computer-readable medium in communication with the processor, wherein the non-transitory, computer-readable medium comprises one or more programming instructions for: generating a one-dimensional array having a plurality of values corresponding to a plurality of indices; determining a first location of a Karnaugh map in a first dimension thereof, wherein the first location corresponds to a first index of the one-dimensional array and to a target location of the Karnaugh map, wherein the first location is determined using a first value of the one-dimensional array corresponding to the first index of the one-dimensional array; determining a second location of the Karnaugh map in a second dimension thereof, wherein the second location corresponds to a second index of the one-dimensional array and to the target location of the Karnaugh map, wherein the second location is determined using a second value of the one-dimensional array corresponding to the second index of the one-dimensional array; evaluating the target location within the Karnaugh map corresponding to the first and second indices of the one-dimensional array in the first and second dimensions of the Karnaugh map, respectively; and searching for at least one of a simplified minterm and a simplified implicant having the target location using the one-dimensional array.