Patent Document ID: 8789002
Application ID: 12339652
Patent Status: 1

Claim One:
1. A method of manufacturing a semiconductor device comprising: measuring an electrical characteristic of a plurality of semiconductor elements; defining layout parameters on the basis of layout data of the plurality of semiconductor elements and deciding a functional relationship between the layout parameters and the electrical characteristic; extracting values of the layout parameters from design layout data of the semiconductor device; calculating a predicted electrical characteristic of the semiconductor device on the basis of the values of the layout parameters and the functional relationship; calculating a difference between a target electrical characteristic and the predicted electrical characteristic of the semiconductor device; obtaining a second mapping relationship from the electrical characteristic to the layout parameters, which is an inverse function of a first mapping relationship from the layout parameters to the electrical characteristic, based on the first mapping relationship; generating, by using the second mapping relationship, a plurality of candidates of the values of the layout parameters which make the predicted electrical characteristic approximate to the target electrical characteristic; selecting a specific value from among the candidates so as to decrease the difference between the target electrical characteristic and the predicted electrical characteristic; changing the design layout data based on the specific value; manufacturing the semiconductor device on the basis of the changed design layout data; calculating a partial differential coefficient by differentiating the functional relationship with respect to the layout parameters; and selecting the specific value in a range where the partial differential coefficient is equal to or larger than a predetermined reference value in a direction in which square of the difference decreases.