source
stringclasses 2
values | commit_hash
stringlengths 40
40
| repo_name
stringlengths 7
39
| repo_url
stringlengths 26
58
| commit_url
stringlengths 74
106
| function
stringlengths 12
142k
| labels
class label 2
classes |
|---|---|---|---|---|---|---|
Devign | 973b1a6b9070e2bf17d17568cbaf4043ce931f51 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/973b1a6b9070e2bf17d17568cbaf4043ce931f51 | static av_cold int vdadec_init(AVCodecContext *avctx)
{
VDADecoderContext *ctx = avctx->priv_data;
struct vda_context *vda_ctx = &ctx->vda_ctx;
OSStatus status;
int ret;
ctx->h264_initialized = 0;
/* init pix_fmts of codec */
if (!ff_h264_vda_decoder.pix_fmts) {
if (kCFCoreFoundationVersionNumber < kCFCoreFoundationVersionNumber10_7)
ff_h264_vda_decoder.pix_fmts = vda_pixfmts_prior_10_7;
else
ff_h264_vda_decoder.pix_fmts = vda_pixfmts;
}
/* init vda */
memset(vda_ctx, 0, sizeof(struct vda_context));
vda_ctx->width = avctx->width;
vda_ctx->height = avctx->height;
vda_ctx->format = 'avc1';
vda_ctx->use_sync_decoding = 1;
vda_ctx->use_ref_buffer = 1;
ctx->pix_fmt = avctx->get_format(avctx, avctx->codec->pix_fmts);
switch (ctx->pix_fmt) {
case AV_PIX_FMT_UYVY422:
vda_ctx->cv_pix_fmt_type = '2vuy';
break;
case AV_PIX_FMT_YUYV422:
vda_ctx->cv_pix_fmt_type = 'yuvs';
break;
case AV_PIX_FMT_NV12:
vda_ctx->cv_pix_fmt_type = '420v';
break;
case AV_PIX_FMT_YUV420P:
vda_ctx->cv_pix_fmt_type = 'y420';
break;
default:
av_log(avctx, AV_LOG_ERROR, "Unsupported pixel format: %d\n", avctx->pix_fmt);
goto failed;
}
status = ff_vda_create_decoder(vda_ctx,
avctx->extradata, avctx->extradata_size);
if (status != kVDADecoderNoErr) {
av_log(avctx, AV_LOG_ERROR,
"Failed to init VDA decoder: %d.\n", status);
goto failed;
}
avctx->hwaccel_context = vda_ctx;
/* changes callback functions */
avctx->get_format = get_format;
avctx->get_buffer2 = get_buffer2;
#if FF_API_GET_BUFFER
// force the old get_buffer to be empty
avctx->get_buffer = NULL;
#endif
/* init H.264 decoder */
ret = ff_h264_decoder.init(avctx);
if (ret < 0) {
av_log(avctx, AV_LOG_ERROR, "Failed to open H.264 decoder.\n");
goto failed;
}
ctx->h264_initialized = 1;
return 0;
failed:
vdadec_close(avctx);
return -1;
}
| 0Non-vulnerable
|
Devign | a8170e5e97ad17ca169c64ba87ae2f53850dab4c | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a8170e5e97ad17ca169c64ba87ae2f53850dab4c | static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
}
switch (addr) {
case 0x000: /* PRCM_REVISION */
case 0x054: /* PRCM_VOLTST */
case 0x084: /* PRCM_CLKCFG_STATUS */
case 0x1e4: /* PM_PWSTST_MPU */
case 0x220: /* CM_IDLEST1_CORE */
case 0x224: /* CM_IDLEST2_CORE */
case 0x22c: /* CM_IDLEST4_CORE */
case 0x2c8: /* PM_WKDEP_CORE */
case 0x2e4: /* PM_PWSTST_CORE */
case 0x320: /* CM_IDLEST_GFX */
case 0x3e4: /* PM_PWSTST_GFX */
case 0x420: /* CM_IDLEST_WKUP */
case 0x520: /* CM_IDLEST_CKGEN */
case 0x820: /* CM_IDLEST_DSP */
case 0x8e4: /* PM_PWSTST_DSP */
OMAP_RO_REG(addr);
return;
case 0x010: /* PRCM_SYSCONFIG */
s->sysconfig = value & 1;
break;
case 0x018: /* PRCM_IRQSTATUS_MPU */
s->irqst[0] &= ~value;
omap_prcm_int_update(s, 0);
break;
case 0x01c: /* PRCM_IRQENABLE_MPU */
s->irqen[0] = value & 0x3f;
omap_prcm_int_update(s, 0);
break;
case 0x050: /* PRCM_VOLTCTRL */
s->voltctrl = value & 0xf1c3;
break;
case 0x060: /* PRCM_CLKSRC_CTRL */
s->clksrc[0] = value & 0xdb;
/* TODO update clocks */
break;
case 0x070: /* PRCM_CLKOUT_CTRL */
s->clkout[0] = value & 0xbbbb;
/* TODO update clocks */
break;
case 0x078: /* PRCM_CLKEMUL_CTRL */
s->clkemul[0] = value & 1;
/* TODO update clocks */
break;
case 0x080: /* PRCM_CLKCFG_CTRL */
break;
case 0x090: /* PRCM_VOLTSETUP */
s->setuptime[0] = value & 0xffff;
break;
case 0x094: /* PRCM_CLKSSETUP */
s->setuptime[1] = value & 0xffff;
break;
case 0x098: /* PRCM_POLCTRL */
s->clkpol[0] = value & 0x701;
break;
case 0x0b0: /* GENERAL_PURPOSE1 */
case 0x0b4: /* GENERAL_PURPOSE2 */
case 0x0b8: /* GENERAL_PURPOSE3 */
case 0x0bc: /* GENERAL_PURPOSE4 */
case 0x0c0: /* GENERAL_PURPOSE5 */
case 0x0c4: /* GENERAL_PURPOSE6 */
case 0x0c8: /* GENERAL_PURPOSE7 */
case 0x0cc: /* GENERAL_PURPOSE8 */
case 0x0d0: /* GENERAL_PURPOSE9 */
case 0x0d4: /* GENERAL_PURPOSE10 */
case 0x0d8: /* GENERAL_PURPOSE11 */
case 0x0dc: /* GENERAL_PURPOSE12 */
case 0x0e0: /* GENERAL_PURPOSE13 */
case 0x0e4: /* GENERAL_PURPOSE14 */
case 0x0e8: /* GENERAL_PURPOSE15 */
case 0x0ec: /* GENERAL_PURPOSE16 */
case 0x0f0: /* GENERAL_PURPOSE17 */
case 0x0f4: /* GENERAL_PURPOSE18 */
case 0x0f8: /* GENERAL_PURPOSE19 */
case 0x0fc: /* GENERAL_PURPOSE20 */
s->scratch[(addr - 0xb0) >> 2] = value;
break;
case 0x140: /* CM_CLKSEL_MPU */
s->clksel[0] = value & 0x1f;
/* TODO update clocks */
break;
case 0x148: /* CM_CLKSTCTRL_MPU */
s->clkctrl[0] = value & 0x1f;
break;
case 0x158: /* RM_RSTST_MPU */
s->rst[0] &= ~value;
break;
case 0x1c8: /* PM_WKDEP_MPU */
s->wkup[0] = value & 0x15;
break;
case 0x1d4: /* PM_EVGENCTRL_MPU */
s->ev = value & 0x1f;
break;
case 0x1d8: /* PM_EVEGENONTIM_MPU */
s->evtime[0] = value;
break;
case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
s->evtime[1] = value;
break;
case 0x1e0: /* PM_PWSTCTRL_MPU */
s->power[0] = value & 0xc0f;
break;
case 0x200: /* CM_FCLKEN1_CORE */
s->clken[0] = value & 0xbfffffff;
/* TODO update clocks */
/* The EN_EAC bit only gets/puts func_96m_clk. */
break;
case 0x204: /* CM_FCLKEN2_CORE */
s->clken[1] = value & 0x00000007;
/* TODO update clocks */
break;
case 0x210: /* CM_ICLKEN1_CORE */
s->clken[2] = value & 0xfffffff9;
/* TODO update clocks */
/* The EN_EAC bit only gets/puts core_l4_iclk. */
break;
case 0x214: /* CM_ICLKEN2_CORE */
s->clken[3] = value & 0x00000007;
/* TODO update clocks */
break;
case 0x21c: /* CM_ICLKEN4_CORE */
s->clken[4] = value & 0x0000001f;
/* TODO update clocks */
break;
case 0x230: /* CM_AUTOIDLE1_CORE */
s->clkidle[0] = value & 0xfffffff9;
/* TODO update clocks */
break;
case 0x234: /* CM_AUTOIDLE2_CORE */
s->clkidle[1] = value & 0x00000007;
/* TODO update clocks */
break;
case 0x238: /* CM_AUTOIDLE3_CORE */
s->clkidle[2] = value & 0x00000007;
/* TODO update clocks */
break;
case 0x23c: /* CM_AUTOIDLE4_CORE */
s->clkidle[3] = value & 0x0000001f;
/* TODO update clocks */
break;
case 0x240: /* CM_CLKSEL1_CORE */
s->clksel[1] = value & 0x0fffbf7f;
/* TODO update clocks */
break;
case 0x244: /* CM_CLKSEL2_CORE */
s->clksel[2] = value & 0x00fffffc;
/* TODO update clocks */
break;
case 0x248: /* CM_CLKSTCTRL_CORE */
s->clkctrl[1] = value & 0x7;
break;
case 0x2a0: /* PM_WKEN1_CORE */
s->wken[0] = value & 0x04667ff8;
break;
case 0x2a4: /* PM_WKEN2_CORE */
s->wken[1] = value & 0x00000005;
break;
case 0x2b0: /* PM_WKST1_CORE */
s->wkst[0] &= ~value;
break;
case 0x2b4: /* PM_WKST2_CORE */
s->wkst[1] &= ~value;
break;
case 0x2e0: /* PM_PWSTCTRL_CORE */
s->power[1] = (value & 0x00fc3f) | (1 << 2);
break;
case 0x300: /* CM_FCLKEN_GFX */
s->clken[5] = value & 6;
/* TODO update clocks */
break;
case 0x310: /* CM_ICLKEN_GFX */
s->clken[6] = value & 1;
/* TODO update clocks */
break;
case 0x340: /* CM_CLKSEL_GFX */
s->clksel[3] = value & 7;
/* TODO update clocks */
break;
case 0x348: /* CM_CLKSTCTRL_GFX */
s->clkctrl[2] = value & 1;
break;
case 0x350: /* RM_RSTCTRL_GFX */
s->rstctrl[0] = value & 1;
/* TODO: reset */
break;
case 0x358: /* RM_RSTST_GFX */
s->rst[1] &= ~value;
break;
case 0x3c8: /* PM_WKDEP_GFX */
s->wkup[1] = value & 0x13;
break;
case 0x3e0: /* PM_PWSTCTRL_GFX */
s->power[2] = (value & 0x00c0f) | (3 << 2);
break;
case 0x400: /* CM_FCLKEN_WKUP */
s->clken[7] = value & 0xd;
/* TODO update clocks */
break;
case 0x410: /* CM_ICLKEN_WKUP */
s->clken[8] = value & 0x3f;
/* TODO update clocks */
break;
case 0x430: /* CM_AUTOIDLE_WKUP */
s->clkidle[4] = value & 0x0000003f;
/* TODO update clocks */
break;
case 0x440: /* CM_CLKSEL_WKUP */
s->clksel[4] = value & 3;
/* TODO update clocks */
break;
case 0x450: /* RM_RSTCTRL_WKUP */
/* TODO: reset */
if (value & 2)
qemu_system_reset_request();
break;
case 0x454: /* RM_RSTTIME_WKUP */
s->rsttime_wkup = value & 0x1fff;
break;
case 0x458: /* RM_RSTST_WKUP */
s->rst[2] &= ~value;
break;
case 0x4a0: /* PM_WKEN_WKUP */
s->wken[2] = value & 0x00000005;
break;
case 0x4b0: /* PM_WKST_WKUP */
s->wkst[2] &= ~value;
break;
case 0x500: /* CM_CLKEN_PLL */
if (value & 0xffffff30)
fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
"future compatibility\n", __FUNCTION__);
if ((s->clken[9] ^ value) & 0xcc) {
s->clken[9] &= ~0xcc;
s->clken[9] |= value & 0xcc;
omap_prcm_apll_update(s);
}
if ((s->clken[9] ^ value) & 3) {
s->clken[9] &= ~3;
s->clken[9] |= value & 3;
omap_prcm_dpll_update(s);
}
break;
case 0x530: /* CM_AUTOIDLE_PLL */
s->clkidle[5] = value & 0x000000cf;
/* TODO update clocks */
break;
case 0x540: /* CM_CLKSEL1_PLL */
if (value & 0xfc4000d7)
fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
"future compatibility\n", __FUNCTION__);
if ((s->clksel[5] ^ value) & 0x003fff00) {
s->clksel[5] = value & 0x03bfff28;
omap_prcm_dpll_update(s);
}
/* TODO update the other clocks */
s->clksel[5] = value & 0x03bfff28;
break;
case 0x544: /* CM_CLKSEL2_PLL */
if (value & ~3)
fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
"future compatibility\n", __FUNCTION__);
if (s->clksel[6] != (value & 3)) {
s->clksel[6] = value & 3;
omap_prcm_dpll_update(s);
}
break;
case 0x800: /* CM_FCLKEN_DSP */
s->clken[10] = value & 0x501;
/* TODO update clocks */
break;
case 0x810: /* CM_ICLKEN_DSP */
s->clken[11] = value & 0x2;
/* TODO update clocks */
break;
case 0x830: /* CM_AUTOIDLE_DSP */
s->clkidle[6] = value & 0x2;
/* TODO update clocks */
break;
case 0x840: /* CM_CLKSEL_DSP */
s->clksel[7] = value & 0x3fff;
/* TODO update clocks */
break;
case 0x848: /* CM_CLKSTCTRL_DSP */
s->clkctrl[3] = value & 0x101;
break;
case 0x850: /* RM_RSTCTRL_DSP */
/* TODO: reset */
break;
case 0x858: /* RM_RSTST_DSP */
s->rst[3] &= ~value;
break;
case 0x8c8: /* PM_WKDEP_DSP */
s->wkup[2] = value & 0x13;
break;
case 0x8e0: /* PM_PWSTCTRL_DSP */
s->power[3] = (value & 0x03017) | (3 << 2);
break;
case 0x8f0: /* PRCM_IRQSTATUS_DSP */
s->irqst[1] &= ~value;
omap_prcm_int_update(s, 1);
break;
case 0x8f4: /* PRCM_IRQENABLE_DSP */
s->irqen[1] = value & 0x7;
omap_prcm_int_update(s, 1);
break;
case 0x8f8: /* PRCM_IRQSTATUS_IVA */
s->irqst[2] &= ~value;
omap_prcm_int_update(s, 2);
break;
case 0x8fc: /* PRCM_IRQENABLE_IVA */
s->irqen[2] = value & 0x7;
omap_prcm_int_update(s, 2);
break;
default:
OMAP_BAD_REG(addr);
return;
}
}
| 0Non-vulnerable
|
Devign | a8170e5e97ad17ca169c64ba87ae2f53850dab4c | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a8170e5e97ad17ca169c64ba87ae2f53850dab4c | static uint64_t dchip_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
/* Skip this. It's all related to DRAM timing and setup. */
return 0;
}
| 0Non-vulnerable
|
Devign | 7848c8d19f8556666df25044bbd5d8b29439c368 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/7848c8d19f8556666df25044bbd5d8b29439c368 | void helper_syscall(CPUX86State *env, int next_eip_addend)
{
int selector;
if (!(env->efer & MSR_EFER_SCE)) {
raise_exception_err(env, EXCP06_ILLOP, 0);
}
selector = (env->star >> 32) & 0xffff;
if (env->hflags & HF_LMA_MASK) {
int code64;
env->regs[R_ECX] = env->eip + next_eip_addend;
env->regs[11] = cpu_compute_eflags(env);
code64 = env->hflags & HF_CS64_MASK;
env->eflags &= ~env->fmask;
cpu_load_eflags(env, env->eflags, 0);
cpu_x86_set_cpl(env, 0);
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
0, 0xffffffff,
DESC_G_MASK | DESC_P_MASK |
DESC_S_MASK |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK |
DESC_L_MASK);
cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
0, 0xffffffff,
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK |
DESC_W_MASK | DESC_A_MASK);
if (code64) {
env->eip = env->lstar;
} else {
env->eip = env->cstar;
}
} else {
env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend);
env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK);
cpu_x86_set_cpl(env, 0);
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
0, 0xffffffff,
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc,
0, 0xffffffff,
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK |
DESC_S_MASK |
DESC_W_MASK | DESC_A_MASK);
env->eip = (uint32_t)env->star;
}
}
| 0Non-vulnerable
|
Devign | 68f593b48433842f3407586679fe07f3e5199ab9 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/68f593b48433842f3407586679fe07f3e5199ab9 | static inline void dv_decode_video_segment(DVVideoDecodeContext *s,
UINT8 *buf_ptr1,
const UINT16 *mb_pos_ptr)
{
int quant, dc, dct_mode, class1, j;
int mb_index, mb_x, mb_y, v, last_index;
DCTELEM *block, *block1;
int c_offset, bits_left;
UINT8 *y_ptr;
BlockInfo mb_data[5 * 6], *mb, *mb1;
void (*idct_put)(UINT8 *dest, int line_size, DCTELEM *block);
UINT8 *buf_ptr;
PutBitContext pb, vs_pb;
UINT8 mb_bit_buffer[80 + 4]; /* allow some slack */
int mb_bit_count;
UINT8 vs_bit_buffer[5 * 80 + 4]; /* allow some slack */
int vs_bit_count;
memset(s->block, 0, sizeof(s->block));
/* pass 1 : read DC and AC coefficients in blocks */
buf_ptr = buf_ptr1;
block1 = &s->block[0][0];
mb1 = mb_data;
init_put_bits(&vs_pb, vs_bit_buffer, 5 * 80, NULL, NULL);
vs_bit_count = 0;
for(mb_index = 0; mb_index < 5; mb_index++) {
/* skip header */
quant = buf_ptr[3] & 0x0f;
buf_ptr += 4;
init_put_bits(&pb, mb_bit_buffer, 80, NULL, NULL);
mb_bit_count = 0;
mb = mb1;
block = block1;
for(j = 0;j < 6; j++) {
/* NOTE: size is not important here */
init_get_bits(&s->gb, buf_ptr, 14);
/* get the dc */
dc = get_bits(&s->gb, 9);
dc = (dc << (32 - 9)) >> (32 - 9);
dct_mode = get_bits1(&s->gb);
mb->dct_mode = dct_mode;
mb->scan_table = s->dv_zigzag[dct_mode];
class1 = get_bits(&s->gb, 2);
mb->shift_offset = (class1 == 3);
mb->shift_table = s->dv_shift[dct_mode]
[quant + dv_quant_offset[class1]];
dc = dc << 2;
/* convert to unsigned because 128 is not added in the
standard IDCT */
dc += 1024;
block[0] = dc;
last_index = block_sizes[j];
buf_ptr += last_index >> 3;
mb->pos = 0;
mb->partial_bit_count = 0;
dv_decode_ac(s, mb, block, last_index);
/* write the remaining bits in a new buffer only if the
block is finished */
bits_left = last_index - s->gb.index;
if (mb->eob_reached) {
mb->partial_bit_count = 0;
mb_bit_count += bits_left;
bit_copy(&pb, &s->gb, bits_left);
} else {
/* should be < 16 bits otherwise a codeword could have
been parsed */
mb->partial_bit_count = bits_left;
mb->partial_bit_buffer = get_bits(&s->gb, bits_left);
}
block += 64;
mb++;
}
flush_put_bits(&pb);
/* pass 2 : we can do it just after */
#ifdef VLC_DEBUG
printf("***pass 2 size=%d\n", mb_bit_count);
#endif
block = block1;
mb = mb1;
init_get_bits(&s->gb, mb_bit_buffer, 80);
for(j = 0;j < 6; j++) {
if (!mb->eob_reached && s->gb.index < mb_bit_count) {
dv_decode_ac(s, mb, block, mb_bit_count);
/* if still not finished, no need to parse other blocks */
if (!mb->eob_reached) {
/* we could not parse the current AC coefficient,
so we add the remaining bytes */
bits_left = mb_bit_count - s->gb.index;
if (bits_left > 0) {
mb->partial_bit_count += bits_left;
mb->partial_bit_buffer =
(mb->partial_bit_buffer << bits_left) |
get_bits(&s->gb, bits_left);
}
goto next_mb;
}
}
block += 64;
mb++;
}
/* all blocks are finished, so the extra bytes can be used at
the video segment level */
bits_left = mb_bit_count - s->gb.index;
vs_bit_count += bits_left;
bit_copy(&vs_pb, &s->gb, bits_left);
next_mb:
mb1 += 6;
block1 += 6 * 64;
}
/* we need a pass other the whole video segment */
flush_put_bits(&vs_pb);
#ifdef VLC_DEBUG
printf("***pass 3 size=%d\n", vs_bit_count);
#endif
block = &s->block[0][0];
mb = mb_data;
init_get_bits(&s->gb, vs_bit_buffer, 5 * 80);
for(mb_index = 0; mb_index < 5; mb_index++) {
for(j = 0;j < 6; j++) {
if (!mb->eob_reached) {
#ifdef VLC_DEBUG
printf("start %d:%d\n", mb_index, j);
#endif
dv_decode_ac(s, mb, block, vs_bit_count);
}
block += 64;
mb++;
}
}
/* compute idct and place blocks */
block = &s->block[0][0];
mb = mb_data;
for(mb_index = 0; mb_index < 5; mb_index++) {
v = *mb_pos_ptr++;
mb_x = v & 0xff;
mb_y = v >> 8;
y_ptr = s->current_picture[0] + (mb_y * s->linesize[0] * 8) + (mb_x * 8);
if (s->sampling_411)
c_offset = (mb_y * s->linesize[1] * 8) + ((mb_x >> 2) * 8);
else
c_offset = ((mb_y >> 1) * s->linesize[1] * 8) + ((mb_x >> 1) * 8);
for(j = 0;j < 6; j++) {
idct_put = s->idct_put[mb->dct_mode];
if (j < 4) {
if (s->sampling_411 && mb_x < (704 / 8)) {
/* NOTE: at end of line, the macroblock is handled as 420 */
idct_put(y_ptr + (j * 8), s->linesize[0], block);
} else {
idct_put(y_ptr + ((j & 1) * 8) + ((j >> 1) * 8 * s->linesize[0]),
s->linesize[0], block);
}
} else {
if (s->sampling_411 && mb_x >= (704 / 8)) {
uint8_t pixels[64], *c_ptr, *c_ptr1, *ptr;
int y, linesize;
/* NOTE: at end of line, the macroblock is handled as 420 */
idct_put(pixels, 8, block);
linesize = s->linesize[6 - j];
c_ptr = s->current_picture[6 - j] + c_offset;
ptr = pixels;
for(y = 0;y < 8; y++) {
/* convert to 411P */
c_ptr1 = c_ptr + linesize;
c_ptr1[0] = c_ptr[0] = (ptr[0] + ptr[1]) >> 1;
c_ptr1[1] = c_ptr[1] = (ptr[2] + ptr[3]) >> 1;
c_ptr1[2] = c_ptr[2] = (ptr[4] + ptr[5]) >> 1;
c_ptr1[3] = c_ptr[3] = (ptr[6] + ptr[7]) >> 1;
c_ptr += linesize * 2;
ptr += 8;
}
} else {
/* don't ask me why they inverted Cb and Cr ! */
idct_put(s->current_picture[6 - j] + c_offset,
s->linesize[6 - j], block);
}
}
block += 64;
mb++;
}
}
}
| 0Non-vulnerable
|
Devign | 1acd7d594c15aa491729c837ad3519d3469e620a | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/1acd7d594c15aa491729c837ad3519d3469e620a | static void FUNCC(pred8x8_vertical_add)(uint8_t *pix, const int *block_offset,
const int16_t *block, ptrdiff_t stride)
{
int i;
for(i=0; i<4; i++)
FUNCC(pred4x4_vertical_add)(pix + block_offset[i], block + i*16*sizeof(pixel), stride);
}
| 0Non-vulnerable
|
Devign | e68c5958668596a5023e30ddf8368410878f7682 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/e68c5958668596a5023e30ddf8368410878f7682 | static void register_types(void)
{
register_char_driver_qapi("null", CHARDEV_BACKEND_KIND_NULL, NULL);
register_char_driver("socket", qemu_chr_open_socket);
register_char_driver("udp", qemu_chr_open_udp);
register_char_driver("memory", qemu_chr_open_ringbuf);
register_char_driver_qapi("file", CHARDEV_BACKEND_KIND_FILE,
qemu_chr_parse_file_out);
register_char_driver_qapi("stdio", CHARDEV_BACKEND_KIND_STDIO,
qemu_chr_parse_stdio);
register_char_driver_qapi("serial", CHARDEV_BACKEND_KIND_SERIAL,
qemu_chr_parse_serial);
register_char_driver_qapi("tty", CHARDEV_BACKEND_KIND_SERIAL,
qemu_chr_parse_serial);
register_char_driver_qapi("parallel", CHARDEV_BACKEND_KIND_PARALLEL,
qemu_chr_parse_parallel);
register_char_driver_qapi("parport", CHARDEV_BACKEND_KIND_PARALLEL,
qemu_chr_parse_parallel);
#ifdef _WIN32
register_char_driver("pipe", qemu_chr_open_win_pipe);
register_char_driver("console", qemu_chr_open_win_con);
#else
register_char_driver("pipe", qemu_chr_open_pipe);
#endif
#ifdef HAVE_CHARDEV_TTY
register_char_driver("pty", qemu_chr_open_pty);
#endif
}
| 0Non-vulnerable
|
Devign | 1181d93231e9b807965724587d363c1cfd5a1d0d | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/1181d93231e9b807965724587d363c1cfd5a1d0d | void ff_avg_h264_qpel4_mc11_msa(uint8_t *dst, const uint8_t *src,
ptrdiff_t stride)
{
avc_luma_hv_qrt_and_aver_dst_4x4_msa(src - 2,
src - (stride * 2),
stride, dst, stride);
}
| 0Non-vulnerable
|
Devign | a8170e5e97ad17ca169c64ba87ae2f53850dab4c | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a8170e5e97ad17ca169c64ba87ae2f53850dab4c | e1000_mmio_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
E1000State *s = opaque;
unsigned int index = (addr & 0x1ffff) >> 2;
if (index < NREADOPS && macreg_readops[index])
{
return macreg_readops[index](s, index);
}
DBGOUT(UNKNOWN, "MMIO unknown read addr=0x%08x\n", index<<2);
return 0;
}
| 0Non-vulnerable
|
Devign | ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/ecf5e8eae8b0b5fa41f00b53d67747b42fd1b8b9 | static inline bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx)
{
if (arm_feature(env, ARM_FEATURE_M)) {
switch (env->v7m.mpu_ctrl &
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
case R_V7M_MPU_CTRL_ENABLE_MASK:
/* Enabled, but not for HardFault and NMI */
return mmu_idx == ARMMMUIdx_MNegPri ||
mmu_idx == ARMMMUIdx_MSNegPri;
case R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK:
/* Enabled for all cases */
return false;
case 0:
default:
/* HFNMIENA set and ENABLE clear is UNPREDICTABLE, but
* we warned about that in armv7m_nvic.c when the guest set it.
*/
return true;
}
}
if (mmu_idx == ARMMMUIdx_S2NS) {
return (env->cp15.hcr_el2 & HCR_VM) == 0;
}
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
}
| 0Non-vulnerable
|
Devign | 364031f17932814484657e5551ba12957d993d7e | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/364031f17932814484657e5551ba12957d993d7e | static int v9fs_synth_lsetxattr(FsContext *ctx, V9fsPath *path,
const char *name, void *value,
size_t size, int flags)
{
errno = ENOTSUP;
return -1;
}
| 0Non-vulnerable
|
Devign | 4a1418e07bdcfaa3177739e04707ecaec75d89e1 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/4a1418e07bdcfaa3177739e04707ecaec75d89e1 | void cpu_outl(CPUState *env, pio_addr_t addr, uint32_t val)
{
LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
ioport_write(2, addr, val);
#ifdef CONFIG_KQEMU
if (env)
env->last_io_time = cpu_get_time_fast();
#endif
}
| 0Non-vulnerable
|
Devign | b2bedb214469af55179d907a60cd67fed6b0779e | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/b2bedb214469af55179d907a60cd67fed6b0779e | int tcp_ctl(struct socket *so)
{
Slirp *slirp = so->slirp;
struct sbuf *sb = &so->so_snd;
struct ex_list *ex_ptr;
int do_pty;
DEBUG_CALL("tcp_ctl");
DEBUG_ARG("so = %lx", (long )so);
if (so->so_faddr.s_addr != slirp->vhost_addr.s_addr) {
/* Check if it's pty_exec */
for (ex_ptr = slirp->exec_list; ex_ptr; ex_ptr = ex_ptr->ex_next) {
if (ex_ptr->ex_fport == so->so_fport &&
so->so_faddr.s_addr == ex_ptr->ex_addr.s_addr) {
if (ex_ptr->ex_pty == 3) {
so->s = -1;
so->extra = (void *)ex_ptr->ex_exec;
return 1;
}
do_pty = ex_ptr->ex_pty;
DEBUG_MISC((dfd, " executing %s \n",ex_ptr->ex_exec));
return fork_exec(so, ex_ptr->ex_exec, do_pty);
}
}
}
sb->sb_cc =
snprintf(sb->sb_wptr, sb->sb_datalen - (sb->sb_wptr - sb->sb_data),
"Error: No application configured.\r\n");
sb->sb_wptr += sb->sb_cc;
return 0;
}
| 0Non-vulnerable
|
Devign | 90e496386fe7fd32c189561f846b7913f95b8cf4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/90e496386fe7fd32c189561f846b7913f95b8cf4 | static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
{
int rd = extract32(insn, 0, 5);
int cmode = extract32(insn, 12, 4);
int cmode_3_1 = extract32(cmode, 1, 3);
int cmode_0 = extract32(cmode, 0, 1);
int o2 = extract32(insn, 11, 1);
uint64_t abcdefgh = extract32(insn, 5, 5) | (extract32(insn, 16, 3) << 5);
bool is_neg = extract32(insn, 29, 1);
bool is_q = extract32(insn, 30, 1);
uint64_t imm = 0;
TCGv_i64 tcg_rd, tcg_imm;
int i;
if (o2 != 0 || ((cmode == 0xf) && is_neg && !is_q)) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
}
/* See AdvSIMDExpandImm() in ARM ARM */
switch (cmode_3_1) {
case 0: /* Replicate(Zeros(24):imm8, 2) */
case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
case 3: /* Replicate(imm8:Zeros(24), 2) */
{
int shift = cmode_3_1 * 8;
imm = bitfield_replicate(abcdefgh << shift, 32);
break;
}
case 4: /* Replicate(Zeros(8):imm8, 4) */
case 5: /* Replicate(imm8:Zeros(8), 4) */
{
int shift = (cmode_3_1 & 0x1) * 8;
imm = bitfield_replicate(abcdefgh << shift, 16);
break;
}
case 6:
if (cmode_0) {
/* Replicate(Zeros(8):imm8:Ones(16), 2) */
imm = (abcdefgh << 16) | 0xffff;
} else {
/* Replicate(Zeros(16):imm8:Ones(8), 2) */
imm = (abcdefgh << 8) | 0xff;
}
imm = bitfield_replicate(imm, 32);
break;
case 7:
if (!cmode_0 && !is_neg) {
imm = bitfield_replicate(abcdefgh, 8);
} else if (!cmode_0 && is_neg) {
int i;
imm = 0;
for (i = 0; i < 8; i++) {
if ((abcdefgh) & (1 << i)) {
imm |= 0xffULL << (i * 8);
}
}
} else if (cmode_0) {
if (is_neg) {
imm = (abcdefgh & 0x3f) << 48;
if (abcdefgh & 0x80) {
imm |= 0x8000000000000000ULL;
}
if (abcdefgh & 0x40) {
imm |= 0x3fc0000000000000ULL;
} else {
imm |= 0x4000000000000000ULL;
}
} else {
imm = (abcdefgh & 0x3f) << 19;
if (abcdefgh & 0x80) {
imm |= 0x80000000;
}
if (abcdefgh & 0x40) {
imm |= 0x3e000000;
} else {
imm |= 0x40000000;
}
imm |= (imm << 32);
}
}
break;
}
if (cmode_3_1 != 7 && is_neg) {
imm = ~imm;
}
tcg_imm = tcg_const_i64(imm);
tcg_rd = new_tmp_a64(s);
for (i = 0; i < 2; i++) {
int foffs = i ? fp_reg_hi_offset(rd) : fp_reg_offset(rd, MO_64);
if (i == 1 && !is_q) {
/* non-quad ops clear high half of vector */
tcg_gen_movi_i64(tcg_rd, 0);
} else if ((cmode & 0x9) == 0x1 || (cmode & 0xd) == 0x9) {
tcg_gen_ld_i64(tcg_rd, cpu_env, foffs);
if (is_neg) {
/* AND (BIC) */
tcg_gen_and_i64(tcg_rd, tcg_rd, tcg_imm);
} else {
/* ORR */
tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_imm);
}
} else {
/* MOVI */
tcg_gen_mov_i64(tcg_rd, tcg_imm);
}
tcg_gen_st_i64(tcg_rd, cpu_env, foffs);
}
tcg_temp_free_i64(tcg_imm);
}
| 0Non-vulnerable
|
Devign | eabb7b91b36b202b4dac2df2d59d698e3aff197a | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/eabb7b91b36b202b4dac2df2d59d698e3aff197a | static inline void patch_reloc(tcg_insn_unit *code_ptr, int type,
intptr_t value, intptr_t addend)
{
assert(addend == 0);
switch (type) {
case R_AARCH64_JUMP26:
case R_AARCH64_CALL26:
reloc_pc26(code_ptr, (tcg_insn_unit *)value);
break;
case R_AARCH64_CONDBR19:
reloc_pc19(code_ptr, (tcg_insn_unit *)value);
break;
default:
tcg_abort();
}
}
| 0Non-vulnerable
|
Devign | 2adba0a18a7950d14827e82d8068c1142ee87789 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/2adba0a18a7950d14827e82d8068c1142ee87789 | static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
AcpiCpuInfo *cpu, AcpiPmInfo *pm)
{
int i;
Aml *dev;
Aml *crs;
Aml *pkg;
Aml *field;
Aml *ifctx;
Aml *method;
/* The current AML generator can cover the APIC ID range [0..255],
* inclusive, for VCPU hotplug. */
QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
/* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
aml_append(dev,
aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
);
/* device present, functioning, decoding, not shown in UI */
aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
crs = aml_resource_template();
aml_append(crs,
aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
pm->cpu_hp_io_len)
);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(sb_scope, dev);
/* declare CPU hotplug MMIO region and PRS field to access it */
aml_append(sb_scope, aml_operation_region(
"PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
aml_append(field, aml_named_field("PRS", 256));
aml_append(sb_scope, field);
/* build Processor object for each processor */
for (i = 0; i < acpi_cpus; i++) {
dev = aml_processor(i, 0, 0, "CP%.02X", i);
method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
aml_append(method,
aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
aml_append(dev, method);
method = aml_method("_STA", 0, AML_NOTSERIALIZED);
aml_append(method,
aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
aml_append(dev, method);
method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
aml_append(method,
aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
);
aml_append(dev, method);
aml_append(sb_scope, dev);
}
/* build this code:
* Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
*/
/* Arg0 = Processor ID = APIC ID */
method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
for (i = 0; i < acpi_cpus; i++) {
ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
aml_append(ifctx,
aml_notify(aml_name("CP%.02X", i), aml_arg(1))
);
aml_append(method, ifctx);
}
aml_append(sb_scope, method);
/* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
*
* Note: The ability to create variable-sized packages was first
* introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
* ith up to 255 elements. Windows guests up to win2k8 fail when
* VarPackageOp is used.
*/
pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
aml_varpackage(acpi_cpus);
for (i = 0; i < acpi_cpus; i++) {
uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
aml_append(pkg, aml_int(b));
}
aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
}
| 0Non-vulnerable
|
Devign | 59ffb6e2cc0974f3090a10facdedf8da5f6bf742 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/59ffb6e2cc0974f3090a10facdedf8da5f6bf742 | static int ra144_decode_frame(AVCodecContext * avctx,
void *vdata, int *data_size,
const uint8_t * buf, int buf_size)
{
static const uint8_t sizes[10] = {6, 5, 5, 4, 4, 3, 3, 3, 3, 2};
unsigned int a, b, c;
int i;
signed short *shptr;
int16_t *data = vdata;
unsigned int val;
Real144_internal *glob = avctx->priv_data;
GetBitContext gb;
if(buf_size == 0)
return 0;
init_get_bits(&gb, buf, 20 * 8);
for (i=0; i<10; i++)
// "<< 1"? Doesn't this make one value out of two of the table useless?
glob->swapbuf1[i] = decodetable[i][get_bits(&gb, sizes[i]) << 1];
do_voice(glob->swapbuf1, glob->swapbuf2);
val = decodeval[get_bits(&gb, 5) << 1]; // Useless table entries?
a = t_sqrt(val*glob->oldval) >> 12;
for (c=0; c < NBLOCKS; c++) {
if (c == (NBLOCKS - 1)) {
dec1(glob, glob->swapbuf1, glob->swapbuf2, 3, val);
} else {
if (c * 2 == (NBLOCKS - 2)) {
if (glob->oldval < val) {
dec2(glob, glob->swapbuf1, glob->swapbuf2, 3, a, glob->swapbuf2alt, c);
} else {
dec2(glob, glob->swapbuf1alt, glob->swapbuf2alt, 3, a, glob->swapbuf2, c);
}
} else {
if (c * 2 < (NBLOCKS - 2)) {
dec2(glob, glob->swapbuf1alt, glob->swapbuf2alt, 3, glob->oldval, glob->swapbuf2, c);
} else {
dec2(glob, glob->swapbuf1, glob->swapbuf2, 3, val, glob->swapbuf2alt, c);
}
}
}
}
/* do output */
for (b=0, c=0; c<4; c++) {
unsigned int gval = glob->gbuf1[c * 2];
unsigned short *gsp = glob->gbuf2 + b;
signed short output_buffer[40];
do_output_subblock(glob, gsp, gval, output_buffer, &gb);
shptr = output_buffer;
while (shptr < output_buffer + BLOCKSIZE)
*data++ = av_clip_int16(*(shptr++) << 2);
b += 30;
}
glob->oldval = val;
FFSWAP(unsigned int *, glob->swapbuf1alt, glob->swapbuf1);
FFSWAP(unsigned int *, glob->swapbuf2alt, glob->swapbuf2);
*data_size = 2*160;
return 20;
}
| 0Non-vulnerable
|
Devign | 719dbe86ea0e85b3b89f492c69e10bb0e733bcbb | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/719dbe86ea0e85b3b89f492c69e10bb0e733bcbb | static int h261_decode_picture_header(H261Context *h)
{
MpegEncContext *const s = &h->s;
int format, i;
uint32_t startcode = 0;
for (i = get_bits_left(&s->gb); i > 24; i -= 1) {
startcode = ((startcode << 1) | get_bits(&s->gb, 1)) & 0x000FFFFF;
if (startcode == 0x10)
break;
}
if (startcode != 0x10) {
av_log(s->avctx, AV_LOG_ERROR, "Bad picture start code\n");
return -1;
}
/* temporal reference */
i = get_bits(&s->gb, 5); /* picture timestamp */
if (i < (s->picture_number & 31))
i += 32;
s->picture_number = (s->picture_number & ~31) + i;
s->avctx->time_base = (AVRational) { 1001, 30000 };
/* PTYPE starts here */
skip_bits1(&s->gb); /* split screen off */
skip_bits1(&s->gb); /* camera off */
skip_bits1(&s->gb); /* freeze picture release off */
format = get_bits1(&s->gb);
// only 2 formats possible
if (format == 0) { // QCIF
s->width = 176;
s->height = 144;
s->mb_width = 11;
s->mb_height = 9;
} else { // CIF
s->width = 352;
s->height = 288;
s->mb_width = 22;
s->mb_height = 18;
}
s->mb_num = s->mb_width * s->mb_height;
skip_bits1(&s->gb); /* still image mode off */
skip_bits1(&s->gb); /* Reserved */
/* PEI */
while (get_bits1(&s->gb) != 0)
skip_bits(&s->gb, 8);
/* H.261 has no I-frames, but if we pass AV_PICTURE_TYPE_I for the first
* frame, the codec crashes if it does not contain all I-blocks
* (e.g. when a packet is lost). */
s->pict_type = AV_PICTURE_TYPE_P;
h->gob_number = 0;
return 0;
}
| 0Non-vulnerable
|
Devign | 17dc7c7a60798d3e1f78bad97423fb49c8dc1c1d | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/17dc7c7a60798d3e1f78bad97423fb49c8dc1c1d | void ff_h264_pred_init_x86(H264PredContext *h, int codec_id)
{
mm_flags = mm_support();
#if HAVE_YASM
if (mm_flags & FF_MM_MMX) {
h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_mmx;
h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_mmx;
h->pred8x8 [VERT_PRED8x8] = ff_pred8x8_vertical_mmx;
h->pred8x8 [HOR_PRED8x8 ] = ff_pred8x8_horizontal_mmx;
if (codec_id == CODEC_ID_VP8) {
h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_tm_vp8_mmx;
h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_tm_vp8_mmx;
h->pred4x4 [TM_VP8_PRED ] = ff_pred4x4_tm_vp8_mmx;
}
}
if (mm_flags & FF_MM_MMX2) {
h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_mmxext;
h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_mmxext;
h->pred8x8 [HOR_PRED8x8 ] = ff_pred8x8_horizontal_mmxext;
h->pred4x4 [DC_PRED ] = ff_pred4x4_dc_mmxext;
if (codec_id == CODEC_ID_VP8) {
h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_tm_vp8_mmxext;
h->pred8x8 [DC_PRED8x8 ] = ff_pred8x8_dc_rv40_mmxext;
h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_tm_vp8_mmxext;
h->pred4x4 [TM_VP8_PRED ] = ff_pred4x4_tm_vp8_mmxext;
h->pred4x4 [VERT_PRED ] = ff_pred4x4_vertical_vp8_mmxext;
}
}
if (mm_flags & FF_MM_SSE) {
h->pred16x16[VERT_PRED8x8] = ff_pred16x16_vertical_sse;
h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_sse;
}
if (mm_flags & FF_MM_SSE2) {
h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_sse2;
if (codec_id == CODEC_ID_VP8) {
h->pred16x16[PLANE_PRED8x8] = ff_pred16x16_tm_vp8_sse2;
h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_tm_vp8_sse2;
}
}
if (mm_flags & FF_MM_SSSE3) {
h->pred16x16[HOR_PRED8x8 ] = ff_pred16x16_horizontal_ssse3;
h->pred16x16[DC_PRED8x8 ] = ff_pred16x16_dc_ssse3;
h->pred8x8 [HOR_PRED8x8 ] = ff_pred8x8_horizontal_ssse3;
if (codec_id == CODEC_ID_VP8) {
h->pred8x8 [PLANE_PRED8x8] = ff_pred8x8_tm_vp8_ssse3;
h->pred4x4 [TM_VP8_PRED ] = ff_pred4x4_tm_vp8_ssse3;
}
}
#endif
}
| 0Non-vulnerable
|
Devign | 8d5c773e323b22402abdd0beef4c7d2fc91dd0eb | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/8d5c773e323b22402abdd0beef4c7d2fc91dd0eb | static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
if (env->cp15.c1_sys == value) {
/* Skip the TLB flush if nothing actually changed; Linux likes
* to do a lot of pointless SCTLR writes.
*/
return;
}
env->cp15.c1_sys = value;
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu), 1);
}
| 0Non-vulnerable
|
Devign | fd56e0612b6454a282fa6a953fdb09281a98c589 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/fd56e0612b6454a282fa6a953fdb09281a98c589 | static void vmxnet3_pci_realize(PCIDevice *pci_dev, Error **errp)
{
DeviceState *dev = DEVICE(pci_dev);
VMXNET3State *s = VMXNET3(pci_dev);
int ret;
VMW_CBPRN("Starting init...");
memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s,
"vmxnet3-b0", VMXNET3_PT_REG_SIZE);
pci_register_bar(pci_dev, VMXNET3_BAR0_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
memory_region_init_io(&s->bar1, OBJECT(s), &b1_ops, s,
"vmxnet3-b1", VMXNET3_VD_REG_SIZE);
pci_register_bar(pci_dev, VMXNET3_BAR1_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
memory_region_init(&s->msix_bar, OBJECT(s), "vmxnet3-msix-bar",
VMXNET3_MSIX_BAR_SIZE);
pci_register_bar(pci_dev, VMXNET3_MSIX_BAR_IDX,
PCI_BASE_ADDRESS_SPACE_MEMORY, &s->msix_bar);
vmxnet3_reset_interrupt_states(s);
/* Interrupt pin A */
pci_dev->config[PCI_INTERRUPT_PIN] = 0x01;
ret = msi_init(pci_dev, VMXNET3_MSI_OFFSET(s), VMXNET3_MAX_NMSIX_INTRS,
VMXNET3_USE_64BIT, VMXNET3_PER_VECTOR_MASK, NULL);
/* Any error other than -ENOTSUP(board's MSI support is broken)
* is a programming error. Fall back to INTx silently on -ENOTSUP */
assert(!ret || ret == -ENOTSUP);
if (!vmxnet3_init_msix(s)) {
VMW_WRPRN("Failed to initialize MSI-X, configuration is inconsistent.");
}
vmxnet3_net_init(s);
if (pci_is_express(pci_dev)) {
if (pci_bus_is_express(pci_dev->bus)) {
pcie_endpoint_cap_init(pci_dev, VMXNET3_EXP_EP_OFFSET);
}
pcie_dev_ser_num_init(pci_dev, VMXNET3_DSN_OFFSET,
vmxnet3_device_serial_num(s));
}
register_savevm_live(dev, "vmxnet3-msix", -1, 1, &savevm_vmxnet3_msix, s);
}
| 0Non-vulnerable
|
Devign | e1f8c729fa890c67bb4532f22c22ace6fb0e1aaf | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/e1f8c729fa890c67bb4532f22c22ace6fb0e1aaf | static void mainstone_common_init(ram_addr_t ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
{
uint32_t sector_len = 256 * 1024;
target_phys_addr_t mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 };
PXA2xxState *cpu;
DeviceState *mst_irq;
DriveInfo *dinfo;
int i;
int be;
if (!cpu_model)
cpu_model = "pxa270-c5";
/* Setup CPU & memory */
cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
cpu_register_physical_memory(0, MAINSTONE_ROM,
qemu_ram_alloc(NULL, "mainstone.rom",
MAINSTONE_ROM) | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
/* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) {
dinfo = drive_get(IF_PFLASH, 0, i);
if (!dinfo) {
fprintf(stderr, "Two flash images must be given with the "
"'pflash' parameter\n");
exit(1);
}
if (!pflash_cfi01_register(mainstone_flash_base[i],
qemu_ram_alloc(NULL, i ? "mainstone.flash1" :
"mainstone.flash0",
MAINSTONE_FLASH),
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
}
mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS,
cpu->pic[PXA2XX_PIC_GPIO_0]);
/* setup keypad */
printf("map addr %p\n", &map);
pxa27x_register_keypad(cpu->kp, map, 0xe0);
/* MMC/SD host */
pxa2xx_mmci_handlers(cpu->mmc, NULL, qdev_get_gpio_in(mst_irq, MMC_IRQ));
smc91c111_init(&nd_table[0], MST_ETH_PHYS,
qdev_get_gpio_in(mst_irq, ETHERNET_IRQ));
mainstone_binfo.kernel_filename = kernel_filename;
mainstone_binfo.kernel_cmdline = kernel_cmdline;
mainstone_binfo.initrd_filename = initrd_filename;
mainstone_binfo.board_id = arm_id;
arm_load_kernel(cpu->env, &mainstone_binfo);
}
| 0Non-vulnerable
|
Devign | 4be746345f13e99e468c60acbd3a355e8183e3ce | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/4be746345f13e99e468c60acbd3a355e8183e3ce | petalogix_s3adsp1800_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *cpu_model = machine->cpu_model;
DeviceState *dev;
MicroBlazeCPU *cpu;
DriveInfo *dinfo;
int i;
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory();
/* init CPUs */
if (cpu_model == NULL) {
cpu_model = "microblaze";
}
cpu = cpu_mb_init(cpu_model);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL,
"petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE,
&error_abort);
vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram",
ram_size, &error_abort);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(sysmem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? blk_bs(blk_by_legacy_dinfo(dinfo)) : NULL,
(64 * 1024), FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);
dev = qdev_create(NULL, "xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR,
irq[UARTLITE_IRQ]);
/* 2 timers at irq 2 @ 62 Mhz. */
dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
microblaze_load_kernel(cpu, ddr_base, ram_size,
machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
}
| 0Non-vulnerable
|
Devign | 9f2130f58d5dd4e1fcb435cca08bf77e7c32e6c6 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/9f2130f58d5dd4e1fcb435cca08bf77e7c32e6c6 | static void xenfb_update(void *opaque)
{
struct XenFB *xenfb = opaque;
DisplaySurface *surface;
int i;
if (xenfb->c.xendev.be_state != XenbusStateConnected)
return;
if (!xenfb->feature_update) {
/* we don't get update notifications, thus use the
* sledge hammer approach ... */
xenfb->up_fullscreen = 1;
}
/* resize if needed */
if (xenfb->do_resize) {
pixman_format_code_t format;
xenfb->do_resize = 0;
switch (xenfb->depth) {
case 16:
case 32:
/* console.c supported depth -> buffer can be used directly */
format = qemu_default_pixman_format(xenfb->depth, true);
surface = qemu_create_displaysurface_from
(xenfb->width, xenfb->height, format,
xenfb->row_stride, xenfb->pixels + xenfb->offset);
break;
default:
/* we must convert stuff */
surface = qemu_create_displaysurface(xenfb->width, xenfb->height);
break;
}
dpy_gfx_replace_surface(xenfb->c.con, surface);
xen_pv_printf(&xenfb->c.xendev, 1,
"update: resizing: %dx%d @ %d bpp%s\n",
xenfb->width, xenfb->height, xenfb->depth,
is_buffer_shared(surface) ? " (shared)" : "");
xenfb->up_fullscreen = 1;
}
/* run queued updates */
if (xenfb->up_fullscreen) {
xen_pv_printf(&xenfb->c.xendev, 3, "update: fullscreen\n");
xenfb_guest_copy(xenfb, 0, 0, xenfb->width, xenfb->height);
} else if (xenfb->up_count) {
xen_pv_printf(&xenfb->c.xendev, 3, "update: %d rects\n",
xenfb->up_count);
for (i = 0; i < xenfb->up_count; i++)
xenfb_guest_copy(xenfb,
xenfb->up_rects[i].x,
xenfb->up_rects[i].y,
xenfb->up_rects[i].w,
xenfb->up_rects[i].h);
} else {
xen_pv_printf(&xenfb->c.xendev, 3, "update: nothing\n");
}
xenfb->up_count = 0;
xenfb->up_fullscreen = 0;
}
| 0Non-vulnerable
|
Devign | e6c90ce94f1b07f50cea2babf7471af455cca0ff | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/e6c90ce94f1b07f50cea2babf7471af455cca0ff | static void loop_filter(H264Context *h, H264SliceContext *sl, int start_x, int end_x)
{
uint8_t *dest_y, *dest_cb, *dest_cr;
int linesize, uvlinesize, mb_x, mb_y;
const int end_mb_y = h->mb_y + FRAME_MBAFF(h);
const int old_slice_type = sl->slice_type;
const int pixel_shift = h->pixel_shift;
const int block_h = 16 >> h->chroma_y_shift;
if (h->deblocking_filter) {
for (mb_x = start_x; mb_x < end_x; mb_x++)
for (mb_y = end_mb_y - FRAME_MBAFF(h); mb_y <= end_mb_y; mb_y++) {
int mb_xy, mb_type;
mb_xy = h->mb_xy = mb_x + mb_y * h->mb_stride;
sl->slice_num = h->slice_table[mb_xy];
mb_type = h->cur_pic.mb_type[mb_xy];
sl->list_count = h->list_counts[mb_xy];
if (FRAME_MBAFF(h))
h->mb_mbaff =
h->mb_field_decoding_flag = !!IS_INTERLACED(mb_type);
h->mb_x = mb_x;
h->mb_y = mb_y;
dest_y = h->cur_pic.f.data[0] +
((mb_x << pixel_shift) + mb_y * h->linesize) * 16;
dest_cb = h->cur_pic.f.data[1] +
(mb_x << pixel_shift) * (8 << CHROMA444(h)) +
mb_y * h->uvlinesize * block_h;
dest_cr = h->cur_pic.f.data[2] +
(mb_x << pixel_shift) * (8 << CHROMA444(h)) +
mb_y * h->uvlinesize * block_h;
// FIXME simplify above
if (MB_FIELD(h)) {
linesize = sl->mb_linesize = h->linesize * 2;
uvlinesize = sl->mb_uvlinesize = h->uvlinesize * 2;
if (mb_y & 1) { // FIXME move out of this function?
dest_y -= h->linesize * 15;
dest_cb -= h->uvlinesize * (block_h - 1);
dest_cr -= h->uvlinesize * (block_h - 1);
}
} else {
linesize = sl->mb_linesize = h->linesize;
uvlinesize = sl->mb_uvlinesize = h->uvlinesize;
}
backup_mb_border(h, dest_y, dest_cb, dest_cr, linesize,
uvlinesize, 0);
if (fill_filter_caches(h, sl, mb_type))
continue;
sl->chroma_qp[0] = get_chroma_qp(h, 0, h->cur_pic.qscale_table[mb_xy]);
sl->chroma_qp[1] = get_chroma_qp(h, 1, h->cur_pic.qscale_table[mb_xy]);
if (FRAME_MBAFF(h)) {
ff_h264_filter_mb(h, sl, mb_x, mb_y, dest_y, dest_cb, dest_cr,
linesize, uvlinesize);
} else {
ff_h264_filter_mb_fast(h, sl, mb_x, mb_y, dest_y, dest_cb,
dest_cr, linesize, uvlinesize);
}
}
}
sl->slice_type = old_slice_type;
h->mb_x = end_x;
h->mb_y = end_mb_y - FRAME_MBAFF(h);
sl->chroma_qp[0] = get_chroma_qp(h, 0, sl->qscale);
sl->chroma_qp[1] = get_chroma_qp(h, 1, sl->qscale);
}
| 0Non-vulnerable
|
Devign | 6f864e6ec8812d5a5525a7861ca599c6bcabdebe | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/6f864e6ec8812d5a5525a7861ca599c6bcabdebe | static int vfio_get_device(VFIOGroup *group, const char *name, VFIODevice *vdev)
{
struct vfio_device_info dev_info = { .argsz = sizeof(dev_info) };
struct vfio_region_info reg_info = { .argsz = sizeof(reg_info) };
struct vfio_irq_info irq_info = { .argsz = sizeof(irq_info) };
int ret, i;
ret = ioctl(group->fd, VFIO_GROUP_GET_DEVICE_FD, name);
if (ret < 0) {
error_report("vfio: error getting device %s from group %d: %m",
name, group->groupid);
error_printf("Verify all devices in group %d are bound to vfio-pci "
"or pci-stub and not already in use\n", group->groupid);
return ret;
}
vdev->fd = ret;
vdev->group = group;
QLIST_INSERT_HEAD(&group->device_list, vdev, next);
/* Sanity check device */
ret = ioctl(vdev->fd, VFIO_DEVICE_GET_INFO, &dev_info);
if (ret) {
error_report("vfio: error getting device info: %m");
goto error;
}
DPRINTF("Device %s flags: %u, regions: %u, irgs: %u\n", name,
dev_info.flags, dev_info.num_regions, dev_info.num_irqs);
if (!(dev_info.flags & VFIO_DEVICE_FLAGS_PCI)) {
error_report("vfio: Um, this isn't a PCI device");
goto error;
}
vdev->reset_works = !!(dev_info.flags & VFIO_DEVICE_FLAGS_RESET);
if (!vdev->reset_works) {
error_report("Warning, device %s does not support reset", name);
}
if (dev_info.num_regions < VFIO_PCI_CONFIG_REGION_INDEX + 1) {
error_report("vfio: unexpected number of io regions %u",
dev_info.num_regions);
goto error;
}
if (dev_info.num_irqs < VFIO_PCI_MSIX_IRQ_INDEX + 1) {
error_report("vfio: unexpected number of irqs %u", dev_info.num_irqs);
goto error;
}
for (i = VFIO_PCI_BAR0_REGION_INDEX; i < VFIO_PCI_ROM_REGION_INDEX; i++) {
reg_info.index = i;
ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, ®_info);
if (ret) {
error_report("vfio: Error getting region %d info: %m", i);
goto error;
}
DPRINTF("Device %s region %d:\n", name, i);
DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
(unsigned long)reg_info.size, (unsigned long)reg_info.offset,
(unsigned long)reg_info.flags);
vdev->bars[i].flags = reg_info.flags;
vdev->bars[i].size = reg_info.size;
vdev->bars[i].fd_offset = reg_info.offset;
vdev->bars[i].fd = vdev->fd;
vdev->bars[i].nr = i;
QLIST_INIT(&vdev->bars[i].quirks);
}
reg_info.index = VFIO_PCI_ROM_REGION_INDEX;
ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, ®_info);
if (ret) {
error_report("vfio: Error getting ROM info: %m");
goto error;
}
DPRINTF("Device %s ROM:\n", name);
DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
(unsigned long)reg_info.size, (unsigned long)reg_info.offset,
(unsigned long)reg_info.flags);
vdev->rom_size = reg_info.size;
vdev->rom_offset = reg_info.offset;
reg_info.index = VFIO_PCI_CONFIG_REGION_INDEX;
ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, ®_info);
if (ret) {
error_report("vfio: Error getting config info: %m");
goto error;
}
DPRINTF("Device %s config:\n", name);
DPRINTF(" size: 0x%lx, offset: 0x%lx, flags: 0x%lx\n",
(unsigned long)reg_info.size, (unsigned long)reg_info.offset,
(unsigned long)reg_info.flags);
vdev->config_size = reg_info.size;
if (vdev->config_size == PCI_CONFIG_SPACE_SIZE) {
vdev->pdev.cap_present &= ~QEMU_PCI_CAP_EXPRESS;
}
vdev->config_offset = reg_info.offset;
if ((vdev->features & VFIO_FEATURE_ENABLE_VGA) &&
dev_info.num_regions > VFIO_PCI_VGA_REGION_INDEX) {
struct vfio_region_info vga_info = {
.argsz = sizeof(vga_info),
.index = VFIO_PCI_VGA_REGION_INDEX,
};
ret = ioctl(vdev->fd, VFIO_DEVICE_GET_REGION_INFO, &vga_info);
if (ret) {
error_report(
"vfio: Device does not support requested feature x-vga");
goto error;
}
if (!(vga_info.flags & VFIO_REGION_INFO_FLAG_READ) ||
!(vga_info.flags & VFIO_REGION_INFO_FLAG_WRITE) ||
vga_info.size < 0xbffff + 1) {
error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx",
(unsigned long)vga_info.flags,
(unsigned long)vga_info.size);
goto error;
}
vdev->vga.fd_offset = vga_info.offset;
vdev->vga.fd = vdev->fd;
vdev->vga.region[QEMU_PCI_VGA_MEM].offset = QEMU_PCI_VGA_MEM_BASE;
vdev->vga.region[QEMU_PCI_VGA_MEM].nr = QEMU_PCI_VGA_MEM;
QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_MEM].quirks);
vdev->vga.region[QEMU_PCI_VGA_IO_LO].offset = QEMU_PCI_VGA_IO_LO_BASE;
vdev->vga.region[QEMU_PCI_VGA_IO_LO].nr = QEMU_PCI_VGA_IO_LO;
QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_IO_LO].quirks);
vdev->vga.region[QEMU_PCI_VGA_IO_HI].offset = QEMU_PCI_VGA_IO_HI_BASE;
vdev->vga.region[QEMU_PCI_VGA_IO_HI].nr = QEMU_PCI_VGA_IO_HI;
QLIST_INIT(&vdev->vga.region[QEMU_PCI_VGA_IO_HI].quirks);
vdev->has_vga = true;
}
irq_info.index = VFIO_PCI_ERR_IRQ_INDEX;
ret = ioctl(vdev->fd, VFIO_DEVICE_GET_IRQ_INFO, &irq_info);
if (ret) {
/* This can fail for an old kernel or legacy PCI dev */
DPRINTF("VFIO_DEVICE_GET_IRQ_INFO failure ret=%d\n", ret);
ret = 0;
} else if (irq_info.count == 1) {
vdev->pci_aer = true;
} else {
error_report("vfio: Warning: "
"Could not enable error recovery for the device\n");
}
error:
if (ret) {
QLIST_REMOVE(vdev, next);
vdev->group = NULL;
close(vdev->fd);
}
return ret;
}
| 0Non-vulnerable
|
Devign | 738012bec4c67e697e766edadab3f522c552a04d | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/738012bec4c67e697e766edadab3f522c552a04d | static void mv88w8618_register_devices(void)
{
#ifdef HAS_AUDIO
sysbus_register_withprop(&mv88w8618_audio_info);
#endif
}
| 0Non-vulnerable
|
Devign | 36778660d7fd0748a6129916e47ecedd67bdb758 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/36778660d7fd0748a6129916e47ecedd67bdb758 | hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash)
{
CPUPPCState *env = &cpu->env;
return (hash * HASH_PTEG_SIZE_32) & env->htab_mask;
}
| 0Non-vulnerable
|
Devign | 72cf2d4f0e181d0d3a3122e04129c58a95da713e | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/72cf2d4f0e181d0d3a3122e04129c58a95da713e | static void do_getfd(Monitor *mon, const QDict *qdict)
{
const char *fdname = qdict_get_str(qdict, "fdname");
mon_fd_t *monfd;
int fd;
fd = qemu_chr_get_msgfd(mon->chr);
if (fd == -1) {
monitor_printf(mon, "getfd: no file descriptor supplied via SCM_RIGHTS\n");
return;
}
if (qemu_isdigit(fdname[0])) {
monitor_printf(mon, "getfd: monitor names may not begin with a number\n");
return;
}
fd = dup(fd);
if (fd == -1) {
monitor_printf(mon, "Failed to dup() file descriptor: %s\n",
strerror(errno));
return;
}
LIST_FOREACH(monfd, &mon->fds, next) {
if (strcmp(monfd->name, fdname) != 0) {
continue;
}
close(monfd->fd);
monfd->fd = fd;
return;
}
monfd = qemu_mallocz(sizeof(mon_fd_t));
monfd->name = qemu_strdup(fdname);
monfd->fd = fd;
LIST_INSERT_HEAD(&mon->fds, monfd, next);
}
| 0Non-vulnerable
|
Devign | 5039d6e23586fe6bbedc5e4fe302b48a66890ade | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/5039d6e23586fe6bbedc5e4fe302b48a66890ade | void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
{
}
| 0Non-vulnerable
|
Devign | 019eb2c77b7c315580200a5dbe6dabb1c97a3764 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/019eb2c77b7c315580200a5dbe6dabb1c97a3764 | static int svq3_decode_mb(SVQ3Context *s, unsigned int mb_type)
{
H264Context *h = &s->h;
int i, j, k, m, dir, mode;
int cbp = 0;
uint32_t vlc;
int8_t *top, *left;
const int mb_xy = h->mb_xy;
const int b_xy = 4 * h->mb_x + 4 * h->mb_y * h->b_stride;
h->top_samples_available = (h->mb_y == 0) ? 0x33FF : 0xFFFF;
h->left_samples_available = (h->mb_x == 0) ? 0x5F5F : 0xFFFF;
h->topright_samples_available = 0xFFFF;
if (mb_type == 0) { /* SKIP */
if (h->pict_type == AV_PICTURE_TYPE_P ||
s->next_pic->mb_type[mb_xy] == -1) {
svq3_mc_dir_part(s, 16 * h->mb_x, 16 * h->mb_y, 16, 16,
0, 0, 0, 0, 0, 0);
if (h->pict_type == AV_PICTURE_TYPE_B)
svq3_mc_dir_part(s, 16 * h->mb_x, 16 * h->mb_y, 16, 16,
0, 0, 0, 0, 1, 1);
mb_type = MB_TYPE_SKIP;
} else {
mb_type = FFMIN(s->next_pic->mb_type[mb_xy], 6);
if (svq3_mc_dir(s, mb_type, PREDICT_MODE, 0, 0) < 0)
return -1;
if (svq3_mc_dir(s, mb_type, PREDICT_MODE, 1, 1) < 0)
return -1;
mb_type = MB_TYPE_16x16;
}
} else if (mb_type < 8) { /* INTER */
if (s->thirdpel_flag && s->halfpel_flag == !get_bits1(&h->gb))
mode = THIRDPEL_MODE;
else if (s->halfpel_flag &&
s->thirdpel_flag == !get_bits1(&h->gb))
mode = HALFPEL_MODE;
else
mode = FULLPEL_MODE;
/* fill caches */
/* note ref_cache should contain here:
* ????????
* ???11111
* N??11111
* N??11111
* N??11111
*/
for (m = 0; m < 2; m++) {
if (h->mb_x > 0 && h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - 1] + 6] != -1) {
for (i = 0; i < 4; i++)
AV_COPY32(h->mv_cache[m][scan8[0] - 1 + i * 8],
h->cur_pic.motion_val[m][b_xy - 1 + i * h->b_stride]);
} else {
for (i = 0; i < 4; i++)
AV_ZERO32(h->mv_cache[m][scan8[0] - 1 + i * 8]);
}
if (h->mb_y > 0) {
memcpy(h->mv_cache[m][scan8[0] - 1 * 8],
h->cur_pic.motion_val[m][b_xy - h->b_stride],
4 * 2 * sizeof(int16_t));
memset(&h->ref_cache[m][scan8[0] - 1 * 8],
(h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride]] == -1) ? PART_NOT_AVAILABLE : 1, 4);
if (h->mb_x < h->mb_width - 1) {
AV_COPY32(h->mv_cache[m][scan8[0] + 4 - 1 * 8],
h->cur_pic.motion_val[m][b_xy - h->b_stride + 4]);
h->ref_cache[m][scan8[0] + 4 - 1 * 8] =
(h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride + 1] + 6] == -1 ||
h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride]] == -1) ? PART_NOT_AVAILABLE : 1;
} else
h->ref_cache[m][scan8[0] + 4 - 1 * 8] = PART_NOT_AVAILABLE;
if (h->mb_x > 0) {
AV_COPY32(h->mv_cache[m][scan8[0] - 1 - 1 * 8],
h->cur_pic.motion_val[m][b_xy - h->b_stride - 1]);
h->ref_cache[m][scan8[0] - 1 - 1 * 8] =
(h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride - 1] + 3] == -1) ? PART_NOT_AVAILABLE : 1;
} else
h->ref_cache[m][scan8[0] - 1 - 1 * 8] = PART_NOT_AVAILABLE;
} else
memset(&h->ref_cache[m][scan8[0] - 1 * 8 - 1],
PART_NOT_AVAILABLE, 8);
if (h->pict_type != AV_PICTURE_TYPE_B)
break;
}
/* decode motion vector(s) and form prediction(s) */
if (h->pict_type == AV_PICTURE_TYPE_P) {
if (svq3_mc_dir(s, mb_type - 1, mode, 0, 0) < 0)
return -1;
} else { /* AV_PICTURE_TYPE_B */
if (mb_type != 2) {
if (svq3_mc_dir(s, 0, mode, 0, 0) < 0)
return -1;
} else {
for (i = 0; i < 4; i++)
memset(h->cur_pic.motion_val[0][b_xy + i * h->b_stride],
0, 4 * 2 * sizeof(int16_t));
}
if (mb_type != 1) {
if (svq3_mc_dir(s, 0, mode, 1, mb_type == 3) < 0)
return -1;
} else {
for (i = 0; i < 4; i++)
memset(h->cur_pic.motion_val[1][b_xy + i * h->b_stride],
0, 4 * 2 * sizeof(int16_t));
}
}
mb_type = MB_TYPE_16x16;
} else if (mb_type == 8 || mb_type == 33) { /* INTRA4x4 */
memset(h->intra4x4_pred_mode_cache, -1, 8 * 5 * sizeof(int8_t));
if (mb_type == 8) {
if (h->mb_x > 0) {
for (i = 0; i < 4; i++)
h->intra4x4_pred_mode_cache[scan8[0] - 1 + i * 8] = h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - 1] + 6 - i];
if (h->intra4x4_pred_mode_cache[scan8[0] - 1] == -1)
h->left_samples_available = 0x5F5F;
}
if (h->mb_y > 0) {
h->intra4x4_pred_mode_cache[4 + 8 * 0] = h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride] + 0];
h->intra4x4_pred_mode_cache[5 + 8 * 0] = h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride] + 1];
h->intra4x4_pred_mode_cache[6 + 8 * 0] = h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride] + 2];
h->intra4x4_pred_mode_cache[7 + 8 * 0] = h->intra4x4_pred_mode[h->mb2br_xy[mb_xy - h->mb_stride] + 3];
if (h->intra4x4_pred_mode_cache[4 + 8 * 0] == -1)
h->top_samples_available = 0x33FF;
}
/* decode prediction codes for luma blocks */
for (i = 0; i < 16; i += 2) {
vlc = svq3_get_ue_golomb(&h->gb);
if (vlc >= 25U) {
av_log(h->avctx, AV_LOG_ERROR, "luma prediction:%d\n", vlc);
return -1;
}
left = &h->intra4x4_pred_mode_cache[scan8[i] - 1];
top = &h->intra4x4_pred_mode_cache[scan8[i] - 8];
left[1] = svq3_pred_1[top[0] + 1][left[0] + 1][svq3_pred_0[vlc][0]];
left[2] = svq3_pred_1[top[1] + 1][left[1] + 1][svq3_pred_0[vlc][1]];
if (left[1] == -1 || left[2] == -1) {
av_log(h->avctx, AV_LOG_ERROR, "weird prediction\n");
return -1;
}
}
} else { /* mb_type == 33, DC_128_PRED block type */
for (i = 0; i < 4; i++)
memset(&h->intra4x4_pred_mode_cache[scan8[0] + 8 * i], DC_PRED, 4);
}
write_back_intra_pred_mode(h);
if (mb_type == 8) {
ff_h264_check_intra4x4_pred_mode(h);
h->top_samples_available = (h->mb_y == 0) ? 0x33FF : 0xFFFF;
h->left_samples_available = (h->mb_x == 0) ? 0x5F5F : 0xFFFF;
} else {
for (i = 0; i < 4; i++)
memset(&h->intra4x4_pred_mode_cache[scan8[0] + 8 * i], DC_128_PRED, 4);
h->top_samples_available = 0x33FF;
h->left_samples_available = 0x5F5F;
}
mb_type = MB_TYPE_INTRA4x4;
} else { /* INTRA16x16 */
dir = i_mb_type_info[mb_type - 8].pred_mode;
dir = (dir >> 1) ^ 3 * (dir & 1) ^ 1;
if ((h->intra16x16_pred_mode = ff_h264_check_intra_pred_mode(h, dir, 0)) == -1) {
av_log(h->avctx, AV_LOG_ERROR, "check_intra_pred_mode = -1\n");
return -1;
}
cbp = i_mb_type_info[mb_type - 8].cbp;
mb_type = MB_TYPE_INTRA16x16;
}
if (!IS_INTER(mb_type) && h->pict_type != AV_PICTURE_TYPE_I) {
for (i = 0; i < 4; i++)
memset(h->cur_pic.motion_val[0][b_xy + i * h->b_stride],
0, 4 * 2 * sizeof(int16_t));
if (h->pict_type == AV_PICTURE_TYPE_B) {
for (i = 0; i < 4; i++)
memset(h->cur_pic.motion_val[1][b_xy + i * h->b_stride],
0, 4 * 2 * sizeof(int16_t));
}
}
if (!IS_INTRA4x4(mb_type)) {
memset(h->intra4x4_pred_mode + h->mb2br_xy[mb_xy], DC_PRED, 8);
}
if (!IS_SKIP(mb_type) || h->pict_type == AV_PICTURE_TYPE_B) {
memset(h->non_zero_count_cache + 8, 0, 14 * 8 * sizeof(uint8_t));
}
if (!IS_INTRA16x16(mb_type) &&
(!IS_SKIP(mb_type) || h->pict_type == AV_PICTURE_TYPE_B)) {
if ((vlc = svq3_get_ue_golomb(&h->gb)) >= 48U){
av_log(h->avctx, AV_LOG_ERROR, "cbp_vlc=%d\n", vlc);
return -1;
}
cbp = IS_INTRA(mb_type) ? golomb_to_intra4x4_cbp[vlc]
: golomb_to_inter_cbp[vlc];
}
if (IS_INTRA16x16(mb_type) ||
(h->pict_type != AV_PICTURE_TYPE_I && s->adaptive_quant && cbp)) {
h->qscale += svq3_get_se_golomb(&h->gb);
if (h->qscale > 31u) {
av_log(h->avctx, AV_LOG_ERROR, "qscale:%d\n", h->qscale);
return -1;
}
}
if (IS_INTRA16x16(mb_type)) {
AV_ZERO128(h->mb_luma_dc[0] + 0);
AV_ZERO128(h->mb_luma_dc[0] + 8);
if (svq3_decode_block(&h->gb, h->mb_luma_dc[0], 0, 1)) {
av_log(h->avctx, AV_LOG_ERROR,
"error while decoding intra luma dc\n");
return -1;
}
}
if (cbp) {
const int index = IS_INTRA16x16(mb_type) ? 1 : 0;
const int type = ((h->qscale < 24 && IS_INTRA4x4(mb_type)) ? 2 : 1);
for (i = 0; i < 4; i++)
if ((cbp & (1 << i))) {
for (j = 0; j < 4; j++) {
k = index ? (1 * (j & 1) + 2 * (i & 1) +
2 * (j & 2) + 4 * (i & 2))
: (4 * i + j);
h->non_zero_count_cache[scan8[k]] = 1;
if (svq3_decode_block(&h->gb, &h->mb[16 * k], index, type)) {
av_log(h->avctx, AV_LOG_ERROR,
"error while decoding block\n");
return -1;
}
}
}
if ((cbp & 0x30)) {
for (i = 1; i < 3; ++i)
if (svq3_decode_block(&h->gb, &h->mb[16 * 16 * i], 0, 3)) {
av_log(h->avctx, AV_LOG_ERROR,
"error while decoding chroma dc block\n");
return -1;
}
if ((cbp & 0x20)) {
for (i = 1; i < 3; i++) {
for (j = 0; j < 4; j++) {
k = 16 * i + j;
h->non_zero_count_cache[scan8[k]] = 1;
if (svq3_decode_block(&h->gb, &h->mb[16 * k], 1, 1)) {
av_log(h->avctx, AV_LOG_ERROR,
"error while decoding chroma ac block\n");
return -1;
}
}
}
}
}
}
h->cbp = cbp;
h->cur_pic.mb_type[mb_xy] = mb_type;
if (IS_INTRA(mb_type))
h->chroma_pred_mode = ff_h264_check_intra_pred_mode(h, DC_PRED8x8, 1);
return 0;
}
| 0Non-vulnerable
|
Devign | 324ff59444ff5470bb325ff1e2be7c4b054fc944 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/324ff59444ff5470bb325ff1e2be7c4b054fc944 | int ff_interleave_packet_per_dts(AVFormatContext *s, AVPacket *out,
AVPacket *pkt, int flush)
{
AVPacketList *pktl;
int stream_count = 0;
int i;
if (pkt) {
ff_interleave_add_packet(s, pkt, interleave_compare_dts);
}
if (s->max_interleave_delta > 0 && s->packet_buffer && !flush) {
AVPacket *top_pkt = &s->packet_buffer->pkt;
int64_t delta_dts = INT64_MIN;
int64_t top_dts = av_rescale_q(top_pkt->dts,
s->streams[top_pkt->stream_index]->time_base,
AV_TIME_BASE_Q);
for (i = 0; i < s->nb_streams; i++) {
int64_t last_dts;
const AVPacketList *last = s->streams[i]->last_in_packet_buffer;
if (!last)
continue;
last_dts = av_rescale_q(last->pkt.dts,
s->streams[i]->time_base,
AV_TIME_BASE_Q);
delta_dts = FFMAX(delta_dts, last_dts - top_dts);
stream_count++;
}
if (delta_dts > s->max_interleave_delta) {
av_log(s, AV_LOG_DEBUG,
"Delay between the first packet and last packet in the "
"muxing queue is %"PRId64" > %"PRId64": forcing output\n",
delta_dts, s->max_interleave_delta);
flush = 1;
}
} else {
for (i = 0; i < s->nb_streams; i++)
stream_count += !!s->streams[i]->last_in_packet_buffer;
}
if (stream_count && (s->internal->nb_interleaved_streams == stream_count || flush)) {
pktl = s->packet_buffer;
*out = pktl->pkt;
s->packet_buffer = pktl->next;
if (!s->packet_buffer)
s->packet_buffer_end = NULL;
if (s->streams[out->stream_index]->last_in_packet_buffer == pktl)
s->streams[out->stream_index]->last_in_packet_buffer = NULL;
av_freep(&pktl);
return 1;
} else {
av_init_packet(out);
return 0;
}
}
| 0Non-vulnerable
|
Devign | a6ca08f1af31badb7fef93bc1cbfa78bffae6be7 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/a6ca08f1af31badb7fef93bc1cbfa78bffae6be7 | static int gxf_write_trailer(AVFormatContext *s)
{
GXFContext *gxf = s->priv_data;
AVIOContext *pb = s->pb;
int64_t end;
int i;
ff_audio_interleave_close(s);
gxf_write_eos_packet(pb);
end = avio_tell(pb);
avio_seek(pb, 0, SEEK_SET);
/* overwrite map, flt and umf packets with new values */
gxf_write_map_packet(s, 1);
gxf_write_flt_packet(s);
gxf_write_umf_packet(s);
avio_flush(pb);
/* update duration in all map packets */
for (i = 1; i < gxf->map_offsets_nb; i++) {
avio_seek(pb, gxf->map_offsets[i], SEEK_SET);
gxf_write_map_packet(s, 1);
avio_flush(pb);
}
avio_seek(pb, end, SEEK_SET);
av_freep(&gxf->flt_entries);
av_freep(&gxf->map_offsets);
return 0;
}
| 0Non-vulnerable
|
Devign | c8eca438a953b4a8ee3b863abac38491357b46a1 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/c8eca438a953b4a8ee3b863abac38491357b46a1 | static int asf_read_header(AVFormatContext *s)
{
ASFContext *asf = s->priv_data;
ff_asf_guid g;
AVIOContext *pb = s->pb;
int i;
int64_t gsize;
ff_get_guid(pb, &g);
if (ff_guidcmp(&g, &ff_asf_header))
return AVERROR_INVALIDDATA;
avio_rl64(pb);
avio_rl32(pb);
avio_r8(pb);
avio_r8(pb);
memset(&asf->asfid2avid, -1, sizeof(asf->asfid2avid));
for (i = 0; i<128; i++)
asf->streams[i].stream_language_index = 128; // invalid stream index means no language info
for (;;) {
uint64_t gpos = avio_tell(pb);
ff_get_guid(pb, &g);
gsize = avio_rl64(pb);
print_guid(&g);
if (!ff_guidcmp(&g, &ff_asf_data_header)) {
asf->data_object_offset = avio_tell(pb);
/* If not streaming, gsize is not unlimited (how?),
* and there is enough space in the file.. */
if (!(asf->hdr.flags & 0x01) && gsize >= 100)
asf->data_object_size = gsize - 24;
else
asf->data_object_size = (uint64_t)-1;
break;
}
if (gsize < 24)
return AVERROR_INVALIDDATA;
if (!ff_guidcmp(&g, &ff_asf_file_header)) {
int ret = asf_read_file_properties(s, gsize);
if (ret < 0)
return ret;
} else if (!ff_guidcmp(&g, &ff_asf_stream_header)) {
int ret = asf_read_stream_properties(s, gsize);
if (ret < 0)
return ret;
} else if (!ff_guidcmp(&g, &ff_asf_comment_header)) {
asf_read_content_desc(s, gsize);
} else if (!ff_guidcmp(&g, &ff_asf_language_guid)) {
asf_read_language_list(s, gsize);
} else if (!ff_guidcmp(&g, &ff_asf_extended_content_header)) {
asf_read_ext_content_desc(s, gsize);
} else if (!ff_guidcmp(&g, &ff_asf_metadata_header)) {
asf_read_metadata(s, gsize);
} else if (!ff_guidcmp(&g, &ff_asf_metadata_library_header)) {
asf_read_metadata(s, gsize);
} else if (!ff_guidcmp(&g, &ff_asf_ext_stream_header)) {
asf_read_ext_stream_properties(s, gsize);
// there could be a optional stream properties object to follow
// if so the next iteration will pick it up
continue;
} else if (!ff_guidcmp(&g, &ff_asf_head1_guid)) {
ff_get_guid(pb, &g);
avio_skip(pb, 6);
continue;
} else if (!ff_guidcmp(&g, &ff_asf_marker_header)) {
asf_read_marker(s, gsize);
} else if (avio_feof(pb)) {
return AVERROR_EOF;
} else {
if (!s->keylen) {
if (!ff_guidcmp(&g, &ff_asf_content_encryption)) {
unsigned int len;
int ret;
AVPacket pkt;
av_log(s, AV_LOG_WARNING,
"DRM protected stream detected, decoding will likely fail!\n");
len= avio_rl32(pb);
av_log(s, AV_LOG_DEBUG, "Secret data:\n");
if ((ret = av_get_packet(pb, &pkt, len)) < 0)
return ret;
av_hex_dump_log(s, AV_LOG_DEBUG, pkt.data, pkt.size);
av_free_packet(&pkt);
len= avio_rl32(pb);
get_tag(s, "ASF_Protection_Type", -1, len, 32);
len= avio_rl32(pb);
get_tag(s, "ASF_Key_ID", -1, len, 32);
len= avio_rl32(pb);
get_tag(s, "ASF_License_URL", -1, len, 32);
} else if (!ff_guidcmp(&g, &ff_asf_ext_content_encryption)) {
av_log(s, AV_LOG_WARNING,
"Ext DRM protected stream detected, decoding will likely fail!\n");
av_dict_set(&s->metadata, "encryption", "ASF Extended Content Encryption", 0);
} else if (!ff_guidcmp(&g, &ff_asf_digital_signature)) {
av_log(s, AV_LOG_INFO, "Digital signature detected!\n");
}
}
}
if (avio_tell(pb) != gpos + gsize)
av_log(s, AV_LOG_DEBUG,
"gpos mismatch our pos=%"PRIu64", end=%"PRId64"\n",
avio_tell(pb) - gpos, gsize);
avio_seek(pb, gpos + gsize, SEEK_SET);
}
ff_get_guid(pb, &g);
avio_rl64(pb);
avio_r8(pb);
avio_r8(pb);
if (avio_feof(pb))
return AVERROR_EOF;
asf->data_offset = avio_tell(pb);
asf->packet_size_left = 0;
for (i = 0; i < 128; i++) {
int stream_num = asf->asfid2avid[i];
if (stream_num >= 0) {
AVStream *st = s->streams[stream_num];
if (!st->codec->bit_rate)
st->codec->bit_rate = asf->stream_bitrates[i];
if (asf->dar[i].num > 0 && asf->dar[i].den > 0) {
av_reduce(&st->sample_aspect_ratio.num,
&st->sample_aspect_ratio.den,
asf->dar[i].num, asf->dar[i].den, INT_MAX);
} else if ((asf->dar[0].num > 0) && (asf->dar[0].den > 0) &&
// Use ASF container value if the stream doesn't set AR.
(st->codec->codec_type == AVMEDIA_TYPE_VIDEO))
av_reduce(&st->sample_aspect_ratio.num,
&st->sample_aspect_ratio.den,
asf->dar[0].num, asf->dar[0].den, INT_MAX);
av_log(s, AV_LOG_TRACE, "i=%d, st->codec->codec_type:%d, asf->dar %d:%d sar=%d:%d\n",
i, st->codec->codec_type, asf->dar[i].num, asf->dar[i].den,
st->sample_aspect_ratio.num, st->sample_aspect_ratio.den);
// copy and convert language codes to the frontend
if (asf->streams[i].stream_language_index < 128) {
const char *rfc1766 = asf->stream_languages[asf->streams[i].stream_language_index];
if (rfc1766 && strlen(rfc1766) > 1) {
const char primary_tag[3] = { rfc1766[0], rfc1766[1], '\0' }; // ignore country code if any
const char *iso6392 = av_convert_lang_to(primary_tag,
AV_LANG_ISO639_2_BIBL);
if (iso6392)
av_dict_set(&st->metadata, "language", iso6392, 0);
}
}
}
}
ff_metadata_conv(&s->metadata, NULL, ff_asf_metadata_conv);
return 0;
}
| 0Non-vulnerable
|
Devign | 0919ac787641db11024912651f3bc5764d4f1286 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/0919ac787641db11024912651f3bc5764d4f1286 | static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
target_phys_addr_t base,
qemu_irq *irq, omap_clk clk)
{
struct omap_rtc_s *s = (struct omap_rtc_s *)
g_malloc0(sizeof(struct omap_rtc_s));
s->irq = irq[0];
s->alarm = irq[1];
s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
memory_region_init_io(&s->iomem, &omap_rtc_ops, s,
"omap-rtc", 0x800);
memory_region_add_subregion(system_memory, base, &s->iomem);
return s;
}
| 0Non-vulnerable
|
Devign | ae100046ca32b0b83031a60d0c3cdfc5ceb9f874 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/ae100046ca32b0b83031a60d0c3cdfc5ceb9f874 | int avpriv_exif_decode_ifd(void *logctx, GetByteContext *gbytes, int le,
int depth, AVDictionary **metadata)
{
int i, ret;
int entries;
entries = ff_tget_short(gbytes, le);
if (bytestream2_get_bytes_left(gbytes) < entries * 12) {
return AVERROR_INVALIDDATA;
}
for (i = 0; i < entries; i++) {
if ((ret = exif_decode_tag(logctx, gbytes, le, depth, metadata)) < 0) {
return ret;
}
}
// return next IDF offset or 0x000000000 or a value < 0 for failure
return ff_tget_long(gbytes, le);
}
| 0Non-vulnerable
|
Devign | 67a0fd2a9bca204d2b39f910a97c7137636a0715 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/67a0fd2a9bca204d2b39f910a97c7137636a0715 | static int64_t coroutine_fn qcow2_co_get_block_status(BlockDriverState *bs,
int64_t sector_num, int nb_sectors, int *pnum)
{
BDRVQcow2State *s = bs->opaque;
uint64_t cluster_offset;
int index_in_cluster, ret;
int64_t status = 0;
*pnum = nb_sectors;
qemu_co_mutex_lock(&s->lock);
ret = qcow2_get_cluster_offset(bs, sector_num << 9, pnum, &cluster_offset);
qemu_co_mutex_unlock(&s->lock);
if (ret < 0) {
return ret;
}
if (cluster_offset != 0 && ret != QCOW2_CLUSTER_COMPRESSED &&
!s->cipher) {
index_in_cluster = sector_num & (s->cluster_sectors - 1);
cluster_offset |= (index_in_cluster << BDRV_SECTOR_BITS);
status |= BDRV_BLOCK_OFFSET_VALID | cluster_offset;
}
if (ret == QCOW2_CLUSTER_ZERO) {
status |= BDRV_BLOCK_ZERO;
} else if (ret != QCOW2_CLUSTER_UNALLOCATED) {
status |= BDRV_BLOCK_DATA;
}
return status;
}
| 0Non-vulnerable
|
Devign | 36778660d7fd0748a6129916e47ecedd67bdb758 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/36778660d7fd0748a6129916e47ecedd67bdb758 | const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
hwaddr ptex, int n)
{
ppc_hash_pte64_t *hptes = NULL;
hwaddr pte_offset = ptex * HASH_PTE_SIZE_64;
if (cpu->env.external_htab == MMU_HASH64_KVM_MANAGED_HPT) {
/*
* HTAB is controlled by KVM. Fetch into temporary buffer
*/
hptes = g_malloc(HASH_PTEG_SIZE_64);
kvmppc_read_hptes(hptes, ptex, n);
} else if (cpu->env.external_htab) {
/*
* HTAB is controlled by QEMU. Just point to the internally
* accessible PTEG.
*/
hptes = (ppc_hash_pte64_t *)(cpu->env.external_htab + pte_offset);
} else if (cpu->env.htab_base) {
hwaddr plen = n * HASH_PTE_SIZE_64;
hptes = address_space_map(CPU(cpu)->as, cpu->env.htab_base + pte_offset,
&plen, false);
if (plen < (n * HASH_PTE_SIZE_64)) {
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
}
}
return hptes;
}
| 0Non-vulnerable
|
Devign | 84aa07f109f0afaeeec63c159f3a578b955c3de9 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/84aa07f109f0afaeeec63c159f3a578b955c3de9 | uint32_t HELPER(clcle)(CPUS390XState *env, uint32_t r1, uint64_t a2,
uint32_t r3)
{
uintptr_t ra = GETPC();
uint64_t destlen = get_length(env, r1 + 1);
uint64_t dest = get_address(env, r1);
uint64_t srclen = get_length(env, r3 + 1);
uint64_t src = get_address(env, r3);
uint8_t pad = a2 & 0xff;
uint32_t cc = 0;
if (!(destlen || srclen)) {
return cc;
}
if (srclen > destlen) {
srclen = destlen;
}
for (; destlen || srclen; src++, dest++, destlen--, srclen--) {
uint8_t v1 = srclen ? cpu_ldub_data_ra(env, src, ra) : pad;
uint8_t v2 = destlen ? cpu_ldub_data_ra(env, dest, ra) : pad;
if (v1 != v2) {
cc = (v1 < v2) ? 1 : 2;
break;
}
}
set_length(env, r1 + 1, destlen);
/* can't use srclen here, we trunc'ed it */
set_length(env, r3 + 1, env->regs[r3 + 1] - src - env->regs[r3]);
set_address(env, r1, dest);
set_address(env, r3, src);
return cc;
}
| 0Non-vulnerable
|
Devign | 90e496386fe7fd32c189561f846b7913f95b8cf4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/90e496386fe7fd32c189561f846b7913f95b8cf4 | static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v)
{
TCGv_i64 tcg_zero = tcg_const_i64(0);
tcg_gen_st_i64(v, cpu_env, fp_reg_offset(reg, MO_64));
tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(reg));
tcg_temp_free_i64(tcg_zero);
}
| 0Non-vulnerable
|
Devign | bd5c51ee6c4f1c79cae5ad2516d711a27b4ea8ec | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/bd5c51ee6c4f1c79cae5ad2516d711a27b4ea8ec | void qemu_chr_be_generic_open(CharDriverState *s)
{
if (s->idle_tag == 0) {
s->idle_tag = g_idle_add(qemu_chr_be_generic_open_bh, s);
}
}
| 0Non-vulnerable
|
Devign | 413bfb7cfc4e7f886ad35d610056ad8da8deab8a | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/413bfb7cfc4e7f886ad35d610056ad8da8deab8a | static void sdl_resize(DisplayState *ds)
{
int flags;
// printf("resizing to %d %d\n", w, h);
flags = SDL_HWSURFACE|SDL_ASYNCBLIT|SDL_HWACCEL;
if (gui_fullscreen)
flags |= SDL_FULLSCREEN;
if (gui_noframe)
flags |= SDL_NOFRAME;
again:
real_screen = SDL_SetVideoMode(ds_get_width(ds), ds_get_height(ds), 0, flags);
if (!real_screen) {
fprintf(stderr, "Could not open SDL display\n");
exit(1);
}
if (!real_screen->pixels && (flags & SDL_HWSURFACE) && (flags & SDL_FULLSCREEN)) {
flags &= ~SDL_HWSURFACE;
goto again;
}
if (!real_screen->pixels) {
fprintf(stderr, "Could not open SDL display\n");
exit(1);
}
sdl_setdata(ds);
}
| 0Non-vulnerable
|
Devign | 7ccc0ed6a0cedbe80443779a805ec90335cd832f | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/7ccc0ed6a0cedbe80443779a805ec90335cd832f | static uint64_t get_fourcc(AVIOContext *bc)
{
unsigned int len = ffio_read_varlen(bc);
if (len == 2)
return avio_rl16(bc);
else if (len == 4)
return avio_rl32(bc);
else
return -1;
}
| 0Non-vulnerable
|
Devign | 6acbe4c6f18e7de00481ff30574262b58526de45 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/6acbe4c6f18e7de00481ff30574262b58526de45 | static void s390_virtio_serial_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
VirtIOS390DeviceClass *k = VIRTIO_S390_DEVICE_CLASS(klass);
k->init = s390_virtio_serial_init;
dc->props = s390_virtio_serial_properties;
dc->alias = "virtio-serial";
}
| 0Non-vulnerable
|
Devign | be08e65e01f1c50fa1552c4f892443cb25bb98e4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/be08e65e01f1c50fa1552c4f892443cb25bb98e4 | static gboolean fd_trampoline(GIOChannel *chan, GIOCondition cond, gpointer opaque)
{
IOTrampoline *tramp = opaque;
if ((cond & G_IO_IN) && tramp->fd_read) {
tramp->fd_read(tramp->opaque);
}
if ((cond & G_IO_OUT) && tramp->fd_write) {
tramp->fd_write(tramp->opaque);
}
return TRUE;
}
| 0Non-vulnerable
|
Devign | bf89e87427fb99b994eb0dfb710bb4b45785f733 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/bf89e87427fb99b994eb0dfb710bb4b45785f733 | int vhdx_parse_log(BlockDriverState *bs, BDRVVHDXState *s, bool *flushed,
Error **errp)
{
int ret = 0;
VHDXHeader *hdr;
VHDXLogSequence logs = { 0 };
hdr = s->headers[s->curr_header];
*flushed = false;
/* s->log.hdr is freed in vhdx_close() */
if (s->log.hdr == NULL) {
s->log.hdr = qemu_blockalign(bs, sizeof(VHDXLogEntryHeader));
}
s->log.offset = hdr->log_offset;
s->log.length = hdr->log_length;
if (s->log.offset < VHDX_LOG_MIN_SIZE ||
s->log.offset % VHDX_LOG_MIN_SIZE) {
ret = -EINVAL;
goto exit;
}
/* per spec, only log version of 0 is supported */
if (hdr->log_version != 0) {
ret = -EINVAL;
goto exit;
}
/* If either the log guid, or log length is zero,
* then a replay log is not present */
if (guid_eq(hdr->log_guid, zero_guid)) {
goto exit;
}
if (hdr->log_length == 0) {
goto exit;
}
if (hdr->log_length % VHDX_LOG_MIN_SIZE) {
ret = -EINVAL;
goto exit;
}
/* The log is present, we need to find if and where there is an active
* sequence of valid entries present in the log. */
ret = vhdx_log_search(bs, s, &logs);
if (ret < 0) {
goto exit;
}
if (logs.valid) {
if (bs->read_only) {
ret = -EPERM;
error_setg_errno(errp, EPERM,
"VHDX image file '%s' opened read-only, but "
"contains a log that needs to be replayed. To "
"replay the log, execute:\n qemu-img check -r "
"all '%s'",
bs->filename, bs->filename);
goto exit;
}
/* now flush the log */
ret = vhdx_log_flush(bs, s, &logs);
if (ret < 0) {
goto exit;
}
*flushed = true;
}
exit:
return ret;
}
| 0Non-vulnerable
|
Devign | bb593904c18e22ea0671dfa1b02e24982f2bf0ea | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/bb593904c18e22ea0671dfa1b02e24982f2bf0ea | static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
int sdr_sh,
target_phys_addr_t hash,
target_phys_addr_t mask)
{
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
}
| 0Non-vulnerable
|
Devign | fb7b5c0df6e3c501973ce4d57eb2b1d4344a519d | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/fb7b5c0df6e3c501973ce4d57eb2b1d4344a519d | static void scsi_block_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SCSIDeviceClass *sc = SCSI_DEVICE_CLASS(klass);
sc->realize = scsi_block_realize;
sc->unrealize = scsi_unrealize;
sc->alloc_req = scsi_block_new_request;
sc->parse_cdb = scsi_block_parse_cdb;
dc->fw_name = "disk";
dc->desc = "SCSI block device passthrough";
dc->reset = scsi_disk_reset;
dc->props = scsi_block_properties;
dc->vmsd = &vmstate_scsi_disk_state;
}
| 0Non-vulnerable
|
Devign | d55f83de4d419d22d2fd2c0b9ff4ce6bf93847d6 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/d55f83de4d419d22d2fd2c0b9ff4ce6bf93847d6 | static inline void quantize_coefs(double *coef, int *idx, float *lpc, int order,
int c_bits)
{
int i;
const float *quant_arr = tns_tmp2_map[c_bits];
for (i = 0; i < order; i++) {
idx[i] = quant_array_idx((float)coef[i], quant_arr, c_bits ? 16 : 8);
lpc[i] = quant_arr[idx[i]];
}
}
| 0Non-vulnerable
|
Devign | 5f634480d1c4ed7711a15d1be07e49177cf351c1 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/5f634480d1c4ed7711a15d1be07e49177cf351c1 | static int filter_samples(AVFilterLink *inlink, AVFilterBufferRef *insamples)
{
AVFilterContext *ctx = inlink->dst;
AVFilterLink *outlink = ctx->outputs[0];
ShowWavesContext *showwaves = ctx->priv;
const int nb_samples = insamples->audio->nb_samples;
AVFilterBufferRef *outpicref = showwaves->outpicref;
int linesize = outpicref ? outpicref->linesize[0] : 0;
int16_t *p = (int16_t *)insamples->data[0];
int nb_channels = av_get_channel_layout_nb_channels(insamples->audio->channel_layout);
int i, j, h;
const int n = showwaves->n;
const int x = 255 / (nb_channels * n); /* multiplication factor, pre-computed to avoid in-loop divisions */
/* draw data in the buffer */
for (i = 0; i < nb_samples; i++) {
if (showwaves->buf_idx == 0 && showwaves->sample_count_mod == 0) {
showwaves->outpicref = outpicref =
ff_get_video_buffer(outlink, AV_PERM_WRITE|AV_PERM_ALIGN,
outlink->w, outlink->h);
outpicref->video->w = outlink->w;
outpicref->video->h = outlink->h;
outpicref->pts = insamples->pts +
av_rescale_q((p - (int16_t *)insamples->data[0]) / nb_channels,
(AVRational){ 1, inlink->sample_rate },
outlink->time_base);
linesize = outpicref->linesize[0];
memset(outpicref->data[0], 0, showwaves->h*linesize);
}
for (j = 0; j < nb_channels; j++) {
h = showwaves->h/2 - av_rescale(*p++, showwaves->h/2, MAX_INT16);
if (h >= 0 && h < outlink->h)
*(outpicref->data[0] + showwaves->buf_idx + h * linesize) += x;
}
showwaves->sample_count_mod++;
if (showwaves->sample_count_mod == n) {
showwaves->sample_count_mod = 0;
showwaves->buf_idx++;
}
if (showwaves->buf_idx == showwaves->w)
push_frame(outlink);
}
avfilter_unref_buffer(insamples);
return 0;
}
| 0Non-vulnerable
|
Devign | 72dbc610be3272ba36603f78a39cc2d2d8fe0cc3 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/72dbc610be3272ba36603f78a39cc2d2d8fe0cc3 | static void avc_luma_midh_qrt_and_aver_dst_4w_msa(const uint8_t *src,
int32_t src_stride,
uint8_t *dst,
int32_t dst_stride,
int32_t height,
uint8_t horiz_offset)
{
uint32_t row;
v16i8 src0, src1, src2, src3, src4, src5, src6;
v16u8 dst0, dst1, res;
v8i16 vt_res0, vt_res1, vt_res2, vt_res3;
v4i32 hz_res0, hz_res1;
v8i16 res0, res1;
v8i16 shf_vec0, shf_vec1, shf_vec2, shf_vec3, shf_vec4, shf_vec5;
v8i16 mask0 = { 0, 5, 1, 6, 2, 7, 3, 8 };
v8i16 mask1 = { 1, 4, 2, 5, 3, 6, 4, 7 };
v8i16 mask2 = { 2, 3, 3, 4, 4, 5, 5, 6 };
v8i16 minus5h = __msa_ldi_h(-5);
v8i16 plus20h = __msa_ldi_h(20);
v8i16 zeros = { 0 };
LD_SB5(src, src_stride, src0, src1, src2, src3, src4);
src += (5 * src_stride);
XORI_B5_128_SB(src0, src1, src2, src3, src4);
for (row = (height >> 1); row--;) {
LD_SB2(src, src_stride, src5, src6);
src += (2 * src_stride);
XORI_B2_128_SB(src5, src6);
LD_UB2(dst, dst_stride, dst0, dst1);
dst0 = (v16u8) __msa_ilvr_w((v4i32) dst1, (v4i32) dst0);
AVC_CALC_DPADD_B_6PIX_2COEFF_SH(src0, src1, src2, src3, src4, src5,
vt_res0, vt_res1);
AVC_CALC_DPADD_B_6PIX_2COEFF_SH(src1, src2, src3, src4, src5, src6,
vt_res2, vt_res3);
VSHF_H3_SH(vt_res0, vt_res1, vt_res0, vt_res1, vt_res0, vt_res1,
mask0, mask1, mask2, shf_vec0, shf_vec1, shf_vec2);
VSHF_H3_SH(vt_res2, vt_res3, vt_res2, vt_res3, vt_res2, vt_res3,
mask0, mask1, mask2, shf_vec3, shf_vec4, shf_vec5);
hz_res0 = __msa_hadd_s_w(shf_vec0, shf_vec0);
DPADD_SH2_SW(shf_vec1, shf_vec2, minus5h, plus20h, hz_res0, hz_res0);
hz_res1 = __msa_hadd_s_w(shf_vec3, shf_vec3);
DPADD_SH2_SW(shf_vec4, shf_vec5, minus5h, plus20h, hz_res1, hz_res1);
SRARI_W2_SW(hz_res0, hz_res1, 10);
SAT_SW2_SW(hz_res0, hz_res1, 7);
res0 = __msa_srari_h(shf_vec2, 5);
res1 = __msa_srari_h(shf_vec5, 5);
SAT_SH2_SH(res0, res1, 7);
if (horiz_offset) {
res0 = __msa_ilvod_h(zeros, res0);
res1 = __msa_ilvod_h(zeros, res1);
} else {
ILVEV_H2_SH(res0, zeros, res1, zeros, res0, res1);
}
hz_res0 = __msa_aver_s_w(hz_res0, (v4i32) res0);
hz_res1 = __msa_aver_s_w(hz_res1, (v4i32) res1);
res0 = __msa_pckev_h((v8i16) hz_res1, (v8i16) hz_res0);
res = PCKEV_XORI128_UB(res0, res0);
dst0 = __msa_aver_u_b(res, dst0);
ST4x2_UB(dst0, dst, dst_stride);
dst += (2 * dst_stride);
src0 = src2;
src1 = src3;
src2 = src4;
src3 = src5;
src4 = src6;
}
}
| 0Non-vulnerable
|
Devign | 859a579e9bbf47fae2e09494c43bcf813dcb2fad | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/859a579e9bbf47fae2e09494c43bcf813dcb2fad | static int decode_frame(AVCodecContext *avctx, void *data, int *data_size,
AVPacket *avpkt) {
const uint8_t *buf = avpkt->data;
int buf_size = avpkt->size;
NuvContext *c = avctx->priv_data;
AVFrame *picture = data;
int orig_size = buf_size;
int keyframe;
int result;
enum {NUV_UNCOMPRESSED = '0', NUV_RTJPEG = '1',
NUV_RTJPEG_IN_LZO = '2', NUV_LZO = '3',
NUV_BLACK = 'N', NUV_COPY_LAST = 'L'} comptype;
if (buf_size < 12) {
av_log(avctx, AV_LOG_ERROR, "coded frame too small\n");
return -1;
}
// codec data (rtjpeg quant tables)
if (buf[0] == 'D' && buf[1] == 'R') {
int ret;
// skip rest of the frameheader.
buf = &buf[12];
buf_size -= 12;
ret = get_quant(avctx, c, buf, buf_size);
if (ret < 0)
return ret;
ff_rtjpeg_decode_init(&c->rtj, &c->dsp, c->width, c->height, c->lq, c->cq);
return orig_size;
}
if (buf[0] != 'V' || buf_size < 12) {
av_log(avctx, AV_LOG_ERROR, "not a nuv video frame\n");
return -1;
}
comptype = buf[1];
switch (comptype) {
case NUV_RTJPEG_IN_LZO:
case NUV_RTJPEG:
keyframe = !buf[2]; break;
case NUV_COPY_LAST:
keyframe = 0; break;
default:
keyframe = 1; break;
}
// skip rest of the frameheader.
buf = &buf[12];
buf_size -= 12;
if (comptype == NUV_RTJPEG_IN_LZO || comptype == NUV_LZO) {
int outlen = c->decomp_size, inlen = buf_size;
if (av_lzo1x_decode(c->decomp_buf, &outlen, buf, &inlen))
av_log(avctx, AV_LOG_ERROR, "error during lzo decompression\n");
buf = c->decomp_buf;
buf_size = c->decomp_size;
}
if (c->codec_frameheader) {
int w, h, q;
if (buf_size < 12) {
av_log(avctx, AV_LOG_ERROR, "invalid nuv video frame\n");
return -1;
}
w = AV_RL16(&buf[6]);
h = AV_RL16(&buf[8]);
q = buf[10];
if (!codec_reinit(avctx, w, h, q))
return -1;
buf = &buf[12];
buf_size -= 12;
}
if (keyframe && c->pic.data[0])
avctx->release_buffer(avctx, &c->pic);
c->pic.reference = 3;
c->pic.buffer_hints = FF_BUFFER_HINTS_VALID | FF_BUFFER_HINTS_READABLE |
FF_BUFFER_HINTS_PRESERVE | FF_BUFFER_HINTS_REUSABLE;
result = avctx->reget_buffer(avctx, &c->pic);
if (result < 0) {
av_log(avctx, AV_LOG_ERROR, "get_buffer() failed\n");
return -1;
}
c->pic.pict_type = keyframe ? AV_PICTURE_TYPE_I : AV_PICTURE_TYPE_P;
c->pic.key_frame = keyframe;
// decompress/copy/whatever data
switch (comptype) {
case NUV_LZO:
case NUV_UNCOMPRESSED: {
int height = c->height;
if (buf_size < c->width * height * 3 / 2) {
av_log(avctx, AV_LOG_ERROR, "uncompressed frame too short\n");
height = buf_size / c->width / 3 * 2;
}
copy_frame(&c->pic, buf, c->width, height);
break;
}
case NUV_RTJPEG_IN_LZO:
case NUV_RTJPEG: {
ff_rtjpeg_decode_frame_yuv420(&c->rtj, &c->pic, buf, buf_size);
break;
}
case NUV_BLACK: {
memset(c->pic.data[0], 0, c->width * c->height);
memset(c->pic.data[1], 128, c->width * c->height / 4);
memset(c->pic.data[2], 128, c->width * c->height / 4);
break;
}
case NUV_COPY_LAST: {
/* nothing more to do here */
break;
}
default:
av_log(avctx, AV_LOG_ERROR, "unknown compression\n");
return -1;
}
*picture = c->pic;
*data_size = sizeof(AVFrame);
return orig_size;
}
| 0Non-vulnerable
|
Devign | 87e8788680e16c51f6048af26f3f7830c35207a5 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/87e8788680e16c51f6048af26f3f7830c35207a5 | static int avs_probe(AVProbeData * p)
{
const uint8_t *d;
if (p->buf_size < 2)
return 0;
d = p->buf;
if (d[0] == 'w' && d[1] == 'W' && d[2] == 0x10 && d[3] == 0)
return 50;
return 0;
}
| 0Non-vulnerable
|
Devign | d1a4544de904cc76fea32d9d22252152ebb18edb | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/d1a4544de904cc76fea32d9d22252152ebb18edb | static int ac3_probe(AVProbeData *p)
{
int max_frames, first_frames = 0, frames;
uint8_t *buf, *buf2, *end;
AC3HeaderInfo hdr;
if(p->buf_size < 7)
return 0;
max_frames = 0;
buf = p->buf;
end = buf + p->buf_size;
for(; buf < end; buf++) {
buf2 = buf;
for(frames = 0; buf2 < end; frames++) {
if(ff_ac3_parse_header(buf2, &hdr) < 0)
break;
buf2 += hdr.frame_size;
}
max_frames = FFMAX(max_frames, frames);
if(buf == p->buf)
first_frames = frames;
}
if (first_frames>=3) return AVPROBE_SCORE_MAX * 3 / 4;
else if(max_frames>=3) return AVPROBE_SCORE_MAX / 2;
else if(max_frames>=1) return 1;
else return 0;
}
| 0Non-vulnerable
|
Devign | b3db211f3c80bb996a704d665fe275619f728bd4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/b3db211f3c80bb996a704d665fe275619f728bd4 | static Visitor *validate_test_init_internal(TestInputVisitorData *data,
const char *json_string,
va_list *ap)
{
validate_teardown(data, NULL);
data->obj = qobject_from_jsonv(json_string, ap);
g_assert(data->obj);
data->qiv = qmp_input_visitor_new(data->obj, true);
g_assert(data->qiv);
return data->qiv;
}
| 0Non-vulnerable
|
Devign | 465e1dadbef7596a3eb87089a66bb4ecdc26d3c4 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/465e1dadbef7596a3eb87089a66bb4ecdc26d3c4 | int init_put_byte(ByteIOContext *s,
unsigned char *buffer,
int buffer_size,
int write_flag,
void *opaque,
int (*read_packet)(void *opaque, uint8_t *buf, int buf_size),
void (*write_packet)(void *opaque, uint8_t *buf, int buf_size),
int (*seek)(void *opaque, offset_t offset, int whence))
{
s->buffer = buffer;
s->buffer_size = buffer_size;
s->buf_ptr = buffer;
s->write_flag = write_flag;
if (!s->write_flag)
s->buf_end = buffer;
else
s->buf_end = buffer + buffer_size;
s->opaque = opaque;
s->write_packet = write_packet;
s->read_packet = read_packet;
s->seek = seek;
s->pos = 0;
s->must_flush = 0;
s->eof_reached = 0;
s->is_streamed = 0;
s->max_packet_size = 0;
s->checksum_ptr= NULL;
s->update_checksum= NULL;
return 0;
}
| 0Non-vulnerable
|
Devign | acc4af3fec335bb0778456f72bfb2c3591c11da4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/acc4af3fec335bb0778456f72bfb2c3591c11da4 | static bool object_is_type(Object *obj, const char *typename)
{
TypeImpl *target_type = type_get_by_name(typename);
TypeImpl *type = obj->class->type;
GSList *i;
/* Check if typename is a direct ancestor of type */
while (type) {
if (type == target_type) {
return true;
}
type = type_get_parent(type);
}
/* Check if obj has an interface of typename */
for (i = obj->interfaces; i; i = i->next) {
Interface *iface = i->data;
if (object_is_type(OBJECT(iface), typename)) {
return true;
}
}
return false;
}
| 0Non-vulnerable
|
Devign | 65c0f1e9558c7c762cdb333406243fff1d687117 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/65c0f1e9558c7c762cdb333406243fff1d687117 | static QObject *parse_object(JSONParserContext *ctxt, QList **tokens, va_list *ap)
{
QDict *dict = NULL;
QObject *token, *peek;
QList *working = qlist_copy(*tokens);
token = qlist_pop(working);
if (token == NULL) {
goto out;
}
if (!token_is_operator(token, '{')) {
goto out;
}
qobject_decref(token);
token = NULL;
dict = qdict_new();
peek = qlist_peek(working);
if (peek == NULL) {
parse_error(ctxt, NULL, "premature EOI");
goto out;
}
if (!token_is_operator(peek, '}')) {
if (parse_pair(ctxt, dict, &working, ap) == -1) {
goto out;
}
token = qlist_pop(working);
if (token == NULL) {
parse_error(ctxt, NULL, "premature EOI");
goto out;
}
while (!token_is_operator(token, '}')) {
if (!token_is_operator(token, ',')) {
parse_error(ctxt, token, "expected separator in dict");
goto out;
}
qobject_decref(token);
token = NULL;
if (parse_pair(ctxt, dict, &working, ap) == -1) {
goto out;
}
token = qlist_pop(working);
if (token == NULL) {
parse_error(ctxt, NULL, "premature EOI");
goto out;
}
}
qobject_decref(token);
token = NULL;
} else {
token = qlist_pop(working);
qobject_decref(token);
token = NULL;
}
QDECREF(*tokens);
*tokens = working;
return QOBJECT(dict);
out:
qobject_decref(token);
QDECREF(working);
QDECREF(dict);
return NULL;
}
| 0Non-vulnerable
|
Devign | 318347234d7069b62d38391dd27e269a3107d668 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/318347234d7069b62d38391dd27e269a3107d668 | static void spapr_phb_remove_pci_device_cb(DeviceState *dev, void *opaque)
{
/* some version guests do not wait for completion of a device
* cleanup (generally done asynchronously by the kernel) before
* signaling to QEMU that the device is safe, but instead sleep
* for some 'safe' period of time. unfortunately on a busy host
* this sleep isn't guaranteed to be long enough, resulting in
* bad things like IRQ lines being left asserted during final
* device removal. to deal with this we call reset just prior
* to finalizing the device, which will put the device back into
* an 'idle' state, as the device cleanup code expects.
*/
pci_device_reset(PCI_DEVICE(dev));
object_unparent(OBJECT(dev));
}
| 0Non-vulnerable
|
Devign | 730b00bbfdc15f914f47e03a703fa7647c10c4a9 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/730b00bbfdc15f914f47e03a703fa7647c10c4a9 | static int qemu_rbd_set_keypairs(rados_t cluster, const char *keypairs,
Error **errp)
{
char *p, *buf;
char *name;
char *value;
Error *local_err = NULL;
int ret = 0;
buf = g_strdup(keypairs);
p = buf;
while (p) {
name = qemu_rbd_next_tok(RBD_MAX_CONF_NAME_SIZE, p,
'=', "conf option name", &p, &local_err);
if (local_err) {
break;
}
if (!p) {
error_setg(errp, "conf option %s has no value", name);
ret = -EINVAL;
break;
}
value = qemu_rbd_next_tok(RBD_MAX_CONF_VAL_SIZE, p,
':', "conf option value", &p, &local_err);
if (local_err) {
break;
}
ret = rados_conf_set(cluster, name, value);
if (ret < 0) {
error_setg_errno(errp, -ret, "invalid conf option %s", name);
ret = -EINVAL;
break;
}
}
if (local_err) {
error_propagate(errp, local_err);
ret = -EINVAL;
}
g_free(buf);
return ret;
}
| 0Non-vulnerable
|
Devign | 364031f17932814484657e5551ba12957d993d7e | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/364031f17932814484657e5551ba12957d993d7e | static ssize_t v9fs_synth_llistxattr(FsContext *ctx, V9fsPath *path,
void *value, size_t size)
{
errno = ENOTSUP;
return -1;
}
| 0Non-vulnerable
|
Devign | 9ef91a677110ec200d7b2904fc4bcae5a77329ad | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/9ef91a677110ec200d7b2904fc4bcae5a77329ad | int qemu_paio_write(struct qemu_paiocb *aiocb)
{
return qemu_paio_submit(aiocb, QEMU_PAIO_WRITE);
}
| 0Non-vulnerable
|
Devign | c4d9d19645a484298a67e9021060bc7c2b081d0f | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/c4d9d19645a484298a67e9021060bc7c2b081d0f | static void test_cancel(void)
{
WorkerTestData data[100];
int num_canceled;
int i;
/* Start more work items than there will be threads, to ensure
* the pool is full.
*/
test_submit_many();
/* Start long running jobs, to ensure we can cancel some. */
for (i = 0; i < 100; i++) {
data[i].n = 0;
data[i].ret = -EINPROGRESS;
data[i].aiocb = thread_pool_submit_aio(long_cb, &data[i],
done_cb, &data[i]);
}
/* Starting the threads may be left to a bottom half. Let it
* run, but do not waste too much time...
*/
active = 100;
qemu_aio_wait_nonblocking();
/* Wait some time for the threads to start, with some sanity
* testing on the behavior of the scheduler...
*/
g_assert_cmpint(active, ==, 100);
g_usleep(1000000);
g_assert_cmpint(active, >, 50);
/* Cancel the jobs that haven't been started yet. */
num_canceled = 0;
for (i = 0; i < 100; i++) {
if (__sync_val_compare_and_swap(&data[i].n, 0, 3) == 0) {
data[i].ret = -ECANCELED;
bdrv_aio_cancel(data[i].aiocb);
active--;
num_canceled++;
}
}
g_assert_cmpint(active, >, 0);
g_assert_cmpint(num_canceled, <, 100);
/* Canceling the others will be a blocking operation. */
for (i = 0; i < 100; i++) {
if (data[i].n != 3) {
bdrv_aio_cancel(data[i].aiocb);
}
}
/* Finish execution and execute any remaining callbacks. */
qemu_aio_wait_all();
g_assert_cmpint(active, ==, 0);
for (i = 0; i < 100; i++) {
if (data[i].n == 3) {
g_assert_cmpint(data[i].ret, ==, -ECANCELED);
g_assert(data[i].aiocb != NULL);
} else {
g_assert_cmpint(data[i].n, ==, 2);
g_assert_cmpint(data[i].ret, ==, 0);
g_assert(data[i].aiocb == NULL);
}
}
}
| 0Non-vulnerable
|
Devign | a8170e5e97ad17ca169c64ba87ae2f53850dab4c | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a8170e5e97ad17ca169c64ba87ae2f53850dab4c | static void assigned_dev_msix_mmio_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned size)
{
AssignedDevice *adev = opaque;
PCIDevice *pdev = &adev->dev;
uint16_t ctrl;
MSIXTableEntry orig;
int i = addr >> 4;
if (i >= adev->msix_max) {
return; /* Drop write */
}
ctrl = pci_get_word(pdev->config + pdev->msix_cap + PCI_MSIX_FLAGS);
DEBUG("write to MSI-X table offset 0x%lx, val 0x%lx\n", addr, val);
if (ctrl & PCI_MSIX_FLAGS_ENABLE) {
orig = adev->msix_table[i];
}
memcpy((uint8_t *)adev->msix_table + addr, &val, size);
if (ctrl & PCI_MSIX_FLAGS_ENABLE) {
MSIXTableEntry *entry = &adev->msix_table[i];
if (!assigned_dev_msix_masked(&orig) &&
assigned_dev_msix_masked(entry)) {
/*
* Vector masked, disable it
*
* XXX It's not clear if we can or should actually attempt
* to mask or disable the interrupt. KVM doesn't have
* support for pending bits and kvm_assign_set_msix_entry
* doesn't modify the device hardware mask. Interrupts
* while masked are simply not injected to the guest, so
* are lost. Can we get away with always injecting an
* interrupt on unmask?
*/
} else if (assigned_dev_msix_masked(&orig) &&
!assigned_dev_msix_masked(entry)) {
/* Vector unmasked */
if (i >= adev->msi_virq_nr || adev->msi_virq[i] < 0) {
/* Previously unassigned vector, start from scratch */
assigned_dev_update_msix(pdev);
return;
} else {
/* Update an existing, previously masked vector */
MSIMessage msg;
int ret;
msg.address = entry->addr_lo |
((uint64_t)entry->addr_hi << 32);
msg.data = entry->data;
ret = kvm_irqchip_update_msi_route(kvm_state,
adev->msi_virq[i], msg);
if (ret) {
error_report("Error updating irq routing entry (%d)", ret);
}
}
}
}
}
| 0Non-vulnerable
|
Devign | edf779ffccc836661a7b654d320571a6c220caea | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/edf779ffccc836661a7b654d320571a6c220caea | static unsigned int * create_elf_tables(char *p, int argc, int envc,
struct elfhdr * exec,
unsigned long load_addr,
unsigned long load_bias,
unsigned long interp_load_addr, int ibcs,
struct image_info *info)
{
target_ulong *argv, *envp;
target_ulong *sp, *csp;
/*
* Force 16 byte _final_ alignment here for generality.
*/
sp = (unsigned int *) (~15UL & (unsigned long) p);
csp = sp;
csp -= (DLINFO_ITEMS + 1) * 2;
#ifdef DLINFO_ARCH_ITEMS
csp -= DLINFO_ARCH_ITEMS*2;
#endif
csp -= envc+1;
csp -= argc+1;
csp -= (!ibcs ? 3 : 1); /* argc itself */
if ((unsigned long)csp & 15UL)
sp -= ((unsigned long)csp & 15UL) / sizeof(*sp);
#define NEW_AUX_ENT(nr, id, val) \
put_user (tswapl(id), sp + (nr * 2)); \
put_user (tswapl(val), sp + (nr * 2 + 1))
sp -= 2;
NEW_AUX_ENT (0, AT_NULL, 0);
sp -= DLINFO_ITEMS*2;
NEW_AUX_ENT( 0, AT_PHDR, (target_ulong)(load_addr + exec->e_phoff));
NEW_AUX_ENT( 1, AT_PHENT, (target_ulong)(sizeof (struct elf_phdr)));
NEW_AUX_ENT( 2, AT_PHNUM, (target_ulong)(exec->e_phnum));
NEW_AUX_ENT( 3, AT_PAGESZ, (target_ulong)(TARGET_PAGE_SIZE));
NEW_AUX_ENT( 4, AT_BASE, (target_ulong)(interp_load_addr));
NEW_AUX_ENT( 5, AT_FLAGS, (target_ulong)0);
NEW_AUX_ENT( 6, AT_ENTRY, load_bias + exec->e_entry);
NEW_AUX_ENT( 7, AT_UID, (target_ulong) getuid());
NEW_AUX_ENT( 8, AT_EUID, (target_ulong) geteuid());
NEW_AUX_ENT( 9, AT_GID, (target_ulong) getgid());
NEW_AUX_ENT(11, AT_EGID, (target_ulong) getegid());
#ifdef ARCH_DLINFO
/*
* ARCH_DLINFO must come last so platform specific code can enforce
* special alignment requirements on the AUXV if necessary (eg. PPC).
*/
ARCH_DLINFO;
#endif
#undef NEW_AUX_ENT
sp -= envc+1;
envp = sp;
sp -= argc+1;
argv = sp;
if (!ibcs) {
put_user(tswapl((target_ulong)envp),--sp);
put_user(tswapl((target_ulong)argv),--sp);
}
put_user(tswapl(argc),--sp);
info->arg_start = (unsigned int)((unsigned long)p & 0xffffffff);
while (argc-->0) {
put_user(tswapl((target_ulong)p),argv++);
while (get_user(p++)) /* nothing */ ;
}
put_user(0,argv);
info->arg_end = info->env_start = (unsigned int)((unsigned long)p & 0xffffffff);
while (envc-->0) {
put_user(tswapl((target_ulong)p),envp++);
while (get_user(p++)) /* nothing */ ;
}
put_user(0,envp);
info->env_end = (unsigned int)((unsigned long)p & 0xffffffff);
return sp;
}
| 0Non-vulnerable
|
Devign | e938637b2ca7587c2b349458189f1f7d7da87040 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/e938637b2ca7587c2b349458189f1f7d7da87040 | static int truespeech_decode_frame(AVCodecContext *avctx,
void *data, int *data_size,
uint8_t *buf, int buf_size)
{
TSContext *c = avctx->priv_data;
int i;
short *samples = data;
int consumed = 0;
int16_t out_buf[240];
if (!buf_size)
return 0;
while (consumed < buf_size) {
truespeech_read_frame(c, buf + consumed);
consumed += 32;
truespeech_correlate_filter(c);
truespeech_filters_merge(c);
memset(out_buf, 0, 240 * 2);
for(i = 0; i < 4; i++) {
truespeech_apply_twopoint_filter(c, i);
truespeech_place_pulses(c, out_buf + i * 60, i);
truespeech_update_filters(c, out_buf + i * 60, i);
truespeech_synth(c, out_buf + i * 60, i);
}
truespeech_save_prevvec(c);
/* finally output decoded frame */
for(i = 0; i < 240; i++)
*samples++ = out_buf[i];
}
*data_size = consumed * 15;
return buf_size;
}
| 0Non-vulnerable
|
Devign | 0e9b9edae7bebfd31fdbead4ccbbce03876a7edd | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/0e9b9edae7bebfd31fdbead4ccbbce03876a7edd | void *bios_linker_loader_cleanup(GArray *linker)
{
return g_array_free(linker, false);
}
| 0Non-vulnerable
|
Devign | b3db211f3c80bb996a704d665fe275619f728bd4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/b3db211f3c80bb996a704d665fe275619f728bd4 | static void qmp_output_type_bool(Visitor *v, const char *name, bool *obj,
Error **errp)
{
QmpOutputVisitor *qov = to_qov(v);
qmp_output_add(qov, name, qbool_from_bool(*obj));
}
| 0Non-vulnerable
|
Devign | 7d553f27fce284805d7f94603932045ee3bbb979 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/7d553f27fce284805d7f94603932045ee3bbb979 | static void usb_device_class_init(ObjectClass *klass, void *data)
{
DeviceClass *k = DEVICE_CLASS(klass);
k->bus_type = TYPE_USB_BUS;
k->init = usb_qdev_init;
k->unplug = qdev_simple_unplug_cb;
k->exit = usb_qdev_exit;
k->props = usb_props;
}
| 0Non-vulnerable
|
Devign | 100f738850639a108d6767316ce4dcc1d1ea4ae4 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/100f738850639a108d6767316ce4dcc1d1ea4ae4 | static void pnv_icp_realize(DeviceState *dev, Error **errp)
{
PnvICPState *icp = PNV_ICP(dev);
memory_region_init_io(&icp->mmio, OBJECT(dev), &pnv_icp_ops,
icp, "icp-thread", 0x1000);
}
| 0Non-vulnerable
|
Devign | cc84de9570ffe01a9c3c169bd62ab9586a9a080c | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/cc84de9570ffe01a9c3c169bd62ab9586a9a080c | static void pause_all_vcpus(void)
{
CPUState *penv = first_cpu;
while (penv) {
penv->stop = 1;
qemu_thread_signal(penv->thread, SIGUSR1);
qemu_cpu_kick(penv);
penv = (CPUState *)penv->next_cpu;
}
while (!all_vcpus_paused()) {
qemu_cond_timedwait(&qemu_pause_cond, &qemu_global_mutex, 100);
penv = first_cpu;
while (penv) {
qemu_thread_signal(penv->thread, SIGUSR1);
penv = (CPUState *)penv->next_cpu;
}
}
}
| 0Non-vulnerable
|
Devign | 51941e4695c6f6c1f786bacef7e8c3a477570e04 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/51941e4695c6f6c1f786bacef7e8c3a477570e04 | static void vncws_tls_handshake_io(void *opaque)
{
struct VncState *vs = (struct VncState *)opaque;
VNC_DEBUG("Handshake IO continue\n");
vncws_start_tls_handshake(vs);
}
| 0Non-vulnerable
|
Devign | 6fd33a750214a866772dd77573cfa24c27ad956d | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/6fd33a750214a866772dd77573cfa24c27ad956d | static int kvmppc_get_pvinfo(CPUPPCState *env, struct kvm_ppc_pvinfo *pvinfo)
{
PowerPCCPU *cpu = ppc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
if (kvm_check_extension(cs->kvm_state, KVM_CAP_PPC_GET_PVINFO) &&
!kvm_vm_ioctl(cs->kvm_state, KVM_PPC_GET_PVINFO, pvinfo)) {
return 0;
}
return 1;
}
| 0Non-vulnerable
|
Devign | c60bf3391bf4cb79b7adc6650094e21671ddaabd | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/c60bf3391bf4cb79b7adc6650094e21671ddaabd | static void monitor_find_completion(Monitor *mon,
const char *cmdline)
{
char *args[MAX_ARGS];
int nb_args, len;
/* 1. parse the cmdline */
if (parse_cmdline(cmdline, &nb_args, args) < 0) {
return;
}
#ifdef DEBUG_COMPLETION
for (i = 0; i < nb_args; i++) {
monitor_printf(mon, "arg%d = '%s'\n", i, args[i]);
}
#endif
/* if the line ends with a space, it means we want to complete the
next arg */
len = strlen(cmdline);
if (len > 0 && qemu_isspace(cmdline[len - 1])) {
if (nb_args >= MAX_ARGS) {
goto cleanup;
}
args[nb_args++] = g_strdup("");
}
/* 2. auto complete according to args */
monitor_find_completion_by_table(mon, mon->cmd_table, args, nb_args);
cleanup:
free_cmdline_args(args, nb_args);
}
| 0Non-vulnerable
|
Devign | ff1d1977ffe1c276f5937a6ad4b6a5b6d2b1c6ae | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/ff1d1977ffe1c276f5937a6ad4b6a5b6d2b1c6ae | static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
{
#if defined(TARGET_I386)
cpu_synchronize_state(s->c_cpu);
s->c_cpu->eip = pc;
#elif defined (TARGET_PPC)
s->c_cpu->nip = pc;
#elif defined (TARGET_SPARC)
s->c_cpu->pc = pc;
s->c_cpu->npc = pc + 4;
#elif defined (TARGET_ARM)
s->c_cpu->regs[15] = pc;
#elif defined (TARGET_SH4)
s->c_cpu->pc = pc;
#elif defined (TARGET_MIPS)
s->c_cpu->active_tc.PC = pc;
#elif defined (TARGET_MICROBLAZE)
s->c_cpu->sregs[SR_PC] = pc;
#elif defined (TARGET_CRIS)
s->c_cpu->pc = pc;
#elif defined (TARGET_ALPHA)
s->c_cpu->pc = pc;
#elif defined (TARGET_S390X)
cpu_synchronize_state(s->c_cpu);
s->c_cpu->psw.addr = pc;
#endif
}
| 0Non-vulnerable
|
Devign | b7394c8394d38cb38b6db14eb431cac7a91e7140 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/b7394c8394d38cb38b6db14eb431cac7a91e7140 | bool hvf_inject_interrupts(CPUState *cpu_state)
{
int allow_nmi = !(rvmcs(cpu_state->hvf_fd, VMCS_GUEST_INTERRUPTIBILITY) &
VMCS_INTERRUPTIBILITY_NMI_BLOCKING);
X86CPU *x86cpu = X86_CPU(cpu_state);
CPUX86State *env = &x86cpu->env;
uint64_t idt_info = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_INFO);
uint64_t info = 0;
if (idt_info & VMCS_IDT_VEC_VALID) {
uint8_t vector = idt_info & 0xff;
uint64_t intr_type = idt_info & VMCS_INTR_T_MASK;
info = idt_info;
uint64_t reason = rvmcs(cpu_state->hvf_fd, VMCS_EXIT_REASON);
if (intr_type == VMCS_INTR_T_NMI && reason != EXIT_REASON_TASK_SWITCH) {
allow_nmi = 1;
vmx_clear_nmi_blocking(cpu_state);
}
if ((allow_nmi || intr_type != VMCS_INTR_T_NMI)) {
info &= ~(1 << 12); /* clear undefined bit */
if (intr_type == VMCS_INTR_T_SWINTR ||
intr_type == VMCS_INTR_T_PRIV_SWEXCEPTION ||
intr_type == VMCS_INTR_T_SWEXCEPTION) {
uint64_t ins_len = rvmcs(cpu_state->hvf_fd,
VMCS_EXIT_INSTRUCTION_LENGTH);
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
}
if (vector == EXCEPTION_BP || vector == EXCEPTION_OF) {
/*
* VT-x requires #BP and #OF to be injected as software
* exceptions.
*/
info &= ~VMCS_INTR_T_MASK;
info |= VMCS_INTR_T_SWEXCEPTION;
uint64_t ins_len = rvmcs(cpu_state->hvf_fd,
VMCS_EXIT_INSTRUCTION_LENGTH);
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INST_LENGTH, ins_len);
}
uint64_t err = 0;
if (idt_info & VMCS_INTR_DEL_ERRCODE) {
err = rvmcs(cpu_state->hvf_fd, VMCS_IDT_VECTORING_ERROR);
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_EXCEPTION_ERROR, err);
}
/*printf("reinject %lx err %d\n", info, err);*/
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
};
}
if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {
if (allow_nmi && !(info & VMCS_INTR_VALID)) {
cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | NMI_VEC;
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info);
} else {
vmx_set_nmi_window_exiting(cpu_state);
}
}
if (env->hvf_emul->interruptable &&
(cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
(EFLAGS(env) & IF_MASK) && !(info & VMCS_INTR_VALID)) {
int line = cpu_get_pic_interrupt(&x86cpu->env);
cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
if (line >= 0) {
wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line |
VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
}
}
if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) {
vmx_set_int_window_exiting(cpu_state);
}
}
| 0Non-vulnerable
|
Devign | 130257dc443574a9da91dc293665be2cfc40245a | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/130257dc443574a9da91dc293665be2cfc40245a | static void qemu_chr_parse_parallel(QemuOpts *opts, ChardevBackend *backend,
Error **errp)
{
const char *device = qemu_opt_get(opts, "path");
if (device == NULL) {
error_setg(errp, "chardev: parallel: no device path given");
return;
}
backend->parallel = g_new0(ChardevHostdev, 1);
backend->parallel->device = g_strdup(device);
}
| 0Non-vulnerable
|
Devign | 35c648078aa493c3b976840eb7cf2e53ab5b7a2d | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/35c648078aa493c3b976840eb7cf2e53ab5b7a2d | static uint8_t eeprom24c0x_read(void)
{
logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
eeprom.tick, eeprom.scl, eeprom.sda, eeprom.data);
return eeprom.sda;
}
| 0Non-vulnerable
|
Devign | 4438c8a9469d79fa2c58189418befb506da54d97 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/4438c8a9469d79fa2c58189418befb506da54d97 | static inline void code_gen_alloc(size_t tb_size)
{
code_gen_buffer_size = size_code_gen_buffer(tb_size);
code_gen_buffer = alloc_code_gen_buffer();
if (code_gen_buffer == NULL) {
fprintf(stderr, "Could not allocate dynamic translator buffer\n");
exit(1);
}
map_exec(code_gen_prologue, sizeof(code_gen_prologue));
code_gen_buffer_max_size = code_gen_buffer_size -
(TCG_MAX_OP_SIZE * OPC_BUF_SIZE);
code_gen_max_blocks = code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE;
tbs = g_malloc(code_gen_max_blocks * sizeof(TranslationBlock));
}
| 0Non-vulnerable
|
Devign | c2b38b277a7882a592f4f2ec955084b2b756daaa | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/c2b38b277a7882a592f4f2ec955084b2b756daaa | void aio_notify_accept(AioContext *ctx)
{
if (atomic_xchg(&ctx->notified, false)) {
event_notifier_test_and_clear(&ctx->notifier);
}
}
| 0Non-vulnerable
|
Devign | b2bedb214469af55179d907a60cd67fed6b0779e | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/b2bedb214469af55179d907a60cd67fed6b0779e | static uint32_t superio_ioport_readb(void *opaque, uint32_t addr)
{
SuperIOConfig *superio_conf = opaque;
DPRINTF("superio_ioport_readb address 0x%x \n", addr);
return (superio_conf->config[superio_conf->index]);
}
| 0Non-vulnerable
|
Devign | a89f364ae8740dfc31b321eed9ee454e996dc3c1 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a89f364ae8740dfc31b321eed9ee454e996dc3c1 | static void l2cap_frame_in(struct l2cap_instance_s *l2cap,
const l2cap_hdr *frame)
{
uint16_t cid = le16_to_cpu(frame->cid);
uint16_t len = le16_to_cpu(frame->len);
if (unlikely(cid >= L2CAP_CID_MAX || !l2cap->cid[cid])) {
fprintf(stderr, "%s: frame addressed to a non-existent L2CAP "
"channel %04x received.\n", __FUNCTION__, cid);
return;
}
l2cap->cid[cid]->frame_in(l2cap->cid[cid], cid, frame, len);
}
| 0Non-vulnerable
|
Devign | be394968c81019887ef996a78a526bdd85d1e216 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/be394968c81019887ef996a78a526bdd85d1e216 | static int resample(ResampleContext *c, void *dst, const void *src,
int *consumed, int src_size, int dst_size, int update_ctx,
int nearest_neighbour)
{
int dst_index;
int index = c->index;
int frac = c->frac;
int dst_incr_frac = c->dst_incr % c->src_incr;
int dst_incr = c->dst_incr / c->src_incr;
int compensation_distance = c->compensation_distance;
if (!dst != !src)
return AVERROR(EINVAL);
if (nearest_neighbour) {
int64_t index2 = ((int64_t)index) << 32;
int64_t incr = (1LL << 32) * c->dst_incr / c->src_incr;
dst_size = FFMIN(dst_size,
(src_size-1-index) * (int64_t)c->src_incr /
c->dst_incr);
if (dst) {
for(dst_index = 0; dst_index < dst_size; dst_index++) {
c->resample_nearest(dst, dst_index, src, index2 >> 32);
index2 += incr;
}
} else {
dst_index = dst_size;
}
index += dst_index * dst_incr;
index += (frac + dst_index * (int64_t)dst_incr_frac) / c->src_incr;
frac = (frac + dst_index * (int64_t)dst_incr_frac) % c->src_incr;
} else {
for (dst_index = 0; dst_index < dst_size; dst_index++) {
int sample_index = index >> c->phase_shift;
if (sample_index + c->filter_length > src_size ||
-sample_index >= src_size)
break;
if (dst)
c->resample_one(c, dst, dst_index, src, src_size, index, frac);
frac += dst_incr_frac;
index += dst_incr;
if (frac >= c->src_incr) {
frac -= c->src_incr;
index++;
}
if (dst_index + 1 == compensation_distance) {
compensation_distance = 0;
dst_incr_frac = c->ideal_dst_incr % c->src_incr;
dst_incr = c->ideal_dst_incr / c->src_incr;
}
}
}
if (consumed)
*consumed = FFMAX(index, 0) >> c->phase_shift;
if (update_ctx) {
if (index >= 0)
index &= c->phase_mask;
if (compensation_distance) {
compensation_distance -= dst_index;
if (compensation_distance <= 0)
return AVERROR_BUG;
}
c->frac = frac;
c->index = index;
c->dst_incr = dst_incr_frac + c->src_incr*dst_incr;
c->compensation_distance = compensation_distance;
}
return dst_index;
}
| 0Non-vulnerable
|
Devign | 72cf2d4f0e181d0d3a3122e04129c58a95da713e | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/72cf2d4f0e181d0d3a3122e04129c58a95da713e | static int calculate_new_instance_id(const char *idstr)
{
SaveStateEntry *se;
int instance_id = 0;
TAILQ_FOREACH(se, &savevm_handlers, entry) {
if (strcmp(idstr, se->idstr) == 0
&& instance_id <= se->instance_id) {
instance_id = se->instance_id + 1;
}
}
return instance_id;
}
| 0Non-vulnerable
|
Devign | a7812ae412311d7d47f8aa85656faadac9d64b56 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a7812ae412311d7d47f8aa85656faadac9d64b56 | static unsigned int dec_abs_r(DisasContext *dc)
{
TCGv t0;
DIS(fprintf (logfile, "abs $r%u, $r%u\n",
dc->op1, dc->op2));
cris_cc_mask(dc, CC_MASK_NZ);
t0 = tcg_temp_new(TCG_TYPE_TL);
tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
tcg_temp_free(t0);
cris_alu(dc, CC_OP_MOVE,
cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
return 2;
}
| 0Non-vulnerable
|
Devign | 7c72ac49ae9f38fa0125296e05988655157decb5 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/7c72ac49ae9f38fa0125296e05988655157decb5 | static bool vregs_needed(void *opaque)
{
#ifdef CONFIG_KVM
if (kvm_enabled()) {
return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
}
#endif
return 0;
}
| 0Non-vulnerable
|
Devign | 44bc910794eff956ceba0030f0751a26bed748b5 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/44bc910794eff956ceba0030f0751a26bed748b5 | static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
target_ulong eaddr, int rw, int access_type)
{
int ret;
#if 0
qemu_log("%s\n", __func__);
#endif
if ((access_type == ACCESS_CODE && msr_ir == 0) ||
(access_type != ACCESS_CODE && msr_dr == 0)) {
if (env->mmu_model == POWERPC_MMU_BOOKE) {
/* The BookE MMU always performs address translation. The
IS and DS bits only affect the address space. */
ret = mmubooke_get_physical_address(env, ctx, eaddr,
rw, access_type);
} else if (env->mmu_model == POWERPC_MMU_BOOKE206) {
ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
access_type);
} else {
/* No address translation. */
ret = check_physical(env, ctx, eaddr, rw);
}
} else {
ret = -1;
switch (env->mmu_model) {
case POWERPC_MMU_32B:
case POWERPC_MMU_601:
/* Try to find a BAT */
if (env->nb_BATs != 0) {
ret = get_bat(env, ctx, eaddr, rw, access_type);
}
if (ret < 0) {
/* We didn't match any BAT entry or don't have BATs */
ret = get_segment32(env, ctx, eaddr, rw, access_type);
}
break;
case POWERPC_MMU_SOFT_6xx:
case POWERPC_MMU_SOFT_74xx:
/* Try to find a BAT */
if (env->nb_BATs != 0) {
ret = get_bat(env, ctx, eaddr, rw, access_type);
}
if (ret < 0) {
/* We didn't match any BAT entry or don't have BATs */
ret = get_segment_6xx_tlb(env, ctx, eaddr, rw, access_type);
}
break;
#if defined(TARGET_PPC64)
case POWERPC_MMU_64B:
case POWERPC_MMU_2_06:
case POWERPC_MMU_2_06d:
ret = get_segment64(env, ctx, eaddr, rw, access_type);
break;
#endif
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
ret = mmu40x_get_physical_address(env, ctx, eaddr,
rw, access_type);
break;
case POWERPC_MMU_BOOKE:
ret = mmubooke_get_physical_address(env, ctx, eaddr,
rw, access_type);
break;
case POWERPC_MMU_BOOKE206:
ret = mmubooke206_get_physical_address(env, ctx, eaddr, rw,
access_type);
break;
case POWERPC_MMU_MPC8xx:
/* XXX: TODO */
cpu_abort(env, "MPC8xx MMU model is not implemented\n");
break;
case POWERPC_MMU_REAL:
cpu_abort(env, "PowerPC in real mode do not do any translation\n");
return -1;
default:
cpu_abort(env, "Unknown or invalid MMU model\n");
return -1;
}
}
#if 0
qemu_log("%s address " TARGET_FMT_lx " => %d " TARGET_FMT_plx "\n",
__func__, eaddr, ret, ctx->raddr);
#endif
return ret;
}
| 0Non-vulnerable
|
Devign | d5e6f437c5508614803d11e59ee16a758dde09ef | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/d5e6f437c5508614803d11e59ee16a758dde09ef | BdrvChild *bdrv_attach_child(BlockDriverState *parent_bs,
BlockDriverState *child_bs,
const char *child_name,
const BdrvChildRole *child_role,
Error **errp)
{
BdrvChild *child = bdrv_root_attach_child(child_bs, child_name, child_role,
parent_bs);
QLIST_INSERT_HEAD(&parent_bs->children, child, next);
return child;
}
| 0Non-vulnerable
|
Devign | 4083733db5e4120939acee57019ff52db1f45b9d | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/4083733db5e4120939acee57019ff52db1f45b9d | static DisplaySurface *qemu_create_message_surface(int w, int h,
const char *msg)
{
DisplaySurface *surface = qemu_create_displaysurface(w, h);
pixman_color_t bg = color_table_rgb[0][COLOR_BLACK];
pixman_color_t fg = color_table_rgb[0][COLOR_WHITE];
pixman_image_t *glyph;
int len, x, y, i;
len = strlen(msg);
x = (w / FONT_WIDTH - len) / 2;
y = (h / FONT_HEIGHT - 1) / 2;
for (i = 0; i < len; i++) {
glyph = qemu_pixman_glyph_from_vgafont(FONT_HEIGHT, vgafont16, msg[i]);
qemu_pixman_glyph_render(glyph, surface->image, &fg, &bg,
x+i, y, FONT_WIDTH, FONT_HEIGHT);
qemu_pixman_image_unref(glyph);
}
return surface;
}
| 0Non-vulnerable
|
Devign | a7812ae412311d7d47f8aa85656faadac9d64b56 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a7812ae412311d7d47f8aa85656faadac9d64b56 | static inline void neon_store_reg64(TCGv var, int reg)
{
tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg));
}
| 0Non-vulnerable
|
Devign | 1a29cc8f5ebd657e159dbe4be340102595846d42 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/1a29cc8f5ebd657e159dbe4be340102595846d42 | void serial_realize_core(SerialState *s, Error **errp)
{
if (!qemu_chr_fe_backend_connected(&s->chr)) {
error_setg(errp, "Can't create serial device, empty char device");
return;
}
s->modem_status_poll = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) serial_update_msl, s);
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, (QEMUTimerCB *) fifo_timeout_int, s);
qemu_register_reset(serial_reset, s);
qemu_chr_fe_set_handlers(&s->chr, serial_can_receive1, serial_receive1,
serial_event, NULL, s, NULL, true);
fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
serial_reset(s);
}
| 0Non-vulnerable
|
Devign | 4be746345f13e99e468c60acbd3a355e8183e3ce | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/4be746345f13e99e468c60acbd3a355e8183e3ce | static void guess_chs_for_size(BlockDriverState *bs,
uint32_t *pcyls, uint32_t *pheads, uint32_t *psecs)
{
uint64_t nb_sectors;
int cylinders;
bdrv_get_geometry(bs, &nb_sectors);
cylinders = nb_sectors / (16 * 63);
if (cylinders > 16383) {
cylinders = 16383;
} else if (cylinders < 2) {
cylinders = 2;
}
*pcyls = cylinders;
*pheads = 16;
*psecs = 63;
}
| 0Non-vulnerable
|
Devign | 6369ba3c9cc74becfaad2a8882dff3dd3e7ae3c0 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/6369ba3c9cc74becfaad2a8882dff3dd3e7ae3c0 | av_cold void ff_vc1dsp_init_x86(VC1DSPContext *dsp)
{
int cpu_flags = av_get_cpu_flags();
if (INLINE_MMX(cpu_flags))
ff_vc1dsp_init_mmx(dsp);
if (INLINE_MMXEXT(cpu_flags))
ff_vc1dsp_init_mmxext(dsp);
#define ASSIGN_LF(EXT) \
dsp->vc1_v_loop_filter4 = ff_vc1_v_loop_filter4_ ## EXT; \
dsp->vc1_h_loop_filter4 = ff_vc1_h_loop_filter4_ ## EXT; \
dsp->vc1_v_loop_filter8 = ff_vc1_v_loop_filter8_ ## EXT; \
dsp->vc1_h_loop_filter8 = ff_vc1_h_loop_filter8_ ## EXT; \
dsp->vc1_v_loop_filter16 = vc1_v_loop_filter16_ ## EXT; \
dsp->vc1_h_loop_filter16 = vc1_h_loop_filter16_ ## EXT
#if HAVE_YASM
if (cpu_flags & AV_CPU_FLAG_MMX) {
dsp->put_no_rnd_vc1_chroma_pixels_tab[0] = ff_put_vc1_chroma_mc8_nornd_mmx;
}
if (cpu_flags & AV_CPU_FLAG_MMXEXT) {
ASSIGN_LF(mmxext);
dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_nornd_mmxext;
dsp->avg_vc1_mspel_pixels_tab[0] = avg_vc1_mspel_mc00_mmxext;
} else if (cpu_flags & AV_CPU_FLAG_3DNOW) {
dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_nornd_3dnow;
}
if (cpu_flags & AV_CPU_FLAG_SSE2) {
dsp->vc1_v_loop_filter8 = ff_vc1_v_loop_filter8_sse2;
dsp->vc1_h_loop_filter8 = ff_vc1_h_loop_filter8_sse2;
dsp->vc1_v_loop_filter16 = vc1_v_loop_filter16_sse2;
dsp->vc1_h_loop_filter16 = vc1_h_loop_filter16_sse2;
}
if (cpu_flags & AV_CPU_FLAG_SSSE3) {
ASSIGN_LF(ssse3);
dsp->put_no_rnd_vc1_chroma_pixels_tab[0] = ff_put_vc1_chroma_mc8_nornd_ssse3;
dsp->avg_no_rnd_vc1_chroma_pixels_tab[0] = ff_avg_vc1_chroma_mc8_nornd_ssse3;
}
if (cpu_flags & AV_CPU_FLAG_SSE4) {
dsp->vc1_h_loop_filter8 = ff_vc1_h_loop_filter8_sse4;
dsp->vc1_h_loop_filter16 = vc1_h_loop_filter16_sse4;
}
#endif /* HAVE_YASM */
}
| 0Non-vulnerable
|
Devign | 6a8f9661dc3c088ed0d2f5b41d940190407cbdc5 | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/6a8f9661dc3c088ed0d2f5b41d940190407cbdc5 | static void blockdev_do_action(int kind, void *data, Error **errp)
{
TransactionAction action;
TransactionActionList list;
action.kind = kind;
action.data = data;
list.value = &action;
list.next = NULL;
qmp_transaction(&list, errp);
}
| 0Non-vulnerable
|
Devign | 1f00b27f17518a1bcb4cedca49eaec96a4d560bd | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/1f00b27f17518a1bcb4cedca49eaec96a4d560bd | static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
TCGReg addrlo, TCGReg addrhi,
int mem_index, bool is_read)
{
int cmp_off
= (is_read
? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
TCGReg base = TCG_AREG0;
TCGMemOp s_bits = opc & MO_SIZE;
/* Extract the page index, shifted into place for tlb index. */
if (TCG_TARGET_REG_BITS == 64) {
if (TARGET_LONG_BITS == 32) {
/* Zero-extend the address into a place helpful for further use. */
tcg_out_ext32u(s, TCG_REG_R4, addrlo);
addrlo = TCG_REG_R4;
} else {
tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
}
}
/* Compensate for very large offsets. */
if (add_off >= 0x8000) {
/* Most target env are smaller than 32k; none are larger than 64k.
Simplify the logic here merely to offset by 0x7ff0, giving us a
range just shy of 64k. Check this assumption. */
QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
tlb_table[NB_MMU_MODES - 1][1])
> 0x7ff0 + 0x7fff);
tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
base = TCG_REG_TMP1;
cmp_off -= 0x7ff0;
add_off -= 0x7ff0;
}
/* Extraction and shifting, part 2. */
if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
31 - CPU_TLB_ENTRY_BITS);
} else {
tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
}
tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
/* Load the tlb comparator. */
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
} else {
tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
}
/* Load the TLB addend for use on the fast path. Do this asap
to minimize any load use delay. */
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
/* Clear the non-page, non-alignment bits from the address */
if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
/* We don't support unaligned accesses on 32-bits, preserve
* the bottom bits and thus trigger a comparison failure on
* unaligned accesses
*/
tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
(32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
} else if (s_bits) {
/* > byte access, we need to handle alignment */
if ((opc & MO_AMASK) == MO_ALIGN) {
/* Alignment required by the front-end, same as 32-bits */
tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
} else {
/* We support unaligned accesses, we need to make sure we fail
* if we cross a page boundary. The trick is to add the
* access_size-1 to the address before masking the low bits.
* That will make the address overflow to the next page if we
* cross a page boundary which will then force a mismatch of
* the TLB compare since the next page cannot possibly be in
* the same TLB index.
*/
tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, (1 << s_bits) - 1));
tcg_out_rld(s, RLDICR, TCG_REG_R0, TCG_REG_R0,
0, 63 - TARGET_PAGE_BITS);
}
} else {
/* Byte access, just chop off the bits below the page index */
tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo, 0, 63 - TARGET_PAGE_BITS);
}
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
0, 7, TCG_TYPE_I32);
tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
} else {
tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
0, 7, TCG_TYPE_TL);
}
return addrlo;
}
| 0Non-vulnerable
|
Devign | a31f053129f378ff0e8f6e855b3f35d21143b9ef | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/a31f053129f378ff0e8f6e855b3f35d21143b9ef | GuestNetworkInterfaceList *qmp_guest_network_get_interfaces(Error **errp)
{
GuestNetworkInterfaceList *head = NULL, *cur_item = NULL;
struct ifaddrs *ifap, *ifa;
char err_msg[512];
if (getifaddrs(&ifap) < 0) {
snprintf(err_msg, sizeof(err_msg),
"getifaddrs failed: %s", strerror(errno));
error_set(errp, QERR_QGA_COMMAND_FAILED, err_msg);
goto error;
}
for (ifa = ifap; ifa; ifa = ifa->ifa_next) {
GuestNetworkInterfaceList *info;
GuestIpAddressList **address_list = NULL, *address_item = NULL;
char addr4[INET_ADDRSTRLEN];
char addr6[INET6_ADDRSTRLEN];
int sock;
struct ifreq ifr;
unsigned char *mac_addr;
void *p;
g_debug("Processing %s interface", ifa->ifa_name);
info = guest_find_interface(head, ifa->ifa_name);
if (!info) {
info = g_malloc0(sizeof(*info));
info->value = g_malloc0(sizeof(*info->value));
info->value->name = g_strdup(ifa->ifa_name);
if (!cur_item) {
head = cur_item = info;
} else {
cur_item->next = info;
cur_item = info;
}
}
if (!info->value->has_hardware_address &&
ifa->ifa_flags & SIOCGIFHWADDR) {
/* we haven't obtained HW address yet */
sock = socket(PF_INET, SOCK_STREAM, 0);
if (sock == -1) {
snprintf(err_msg, sizeof(err_msg),
"failed to create socket: %s", strerror(errno));
error_set(errp, QERR_QGA_COMMAND_FAILED, err_msg);
goto error;
}
memset(&ifr, 0, sizeof(ifr));
strncpy(ifr.ifr_name, info->value->name, IF_NAMESIZE);
if (ioctl(sock, SIOCGIFHWADDR, &ifr) == -1) {
snprintf(err_msg, sizeof(err_msg),
"failed to get MAC addres of %s: %s",
ifa->ifa_name,
strerror(errno));
error_set(errp, QERR_QGA_COMMAND_FAILED, err_msg);
goto error;
}
mac_addr = (unsigned char *) &ifr.ifr_hwaddr.sa_data;
if (asprintf(&info->value->hardware_address,
"%02x:%02x:%02x:%02x:%02x:%02x",
(int) mac_addr[0], (int) mac_addr[1],
(int) mac_addr[2], (int) mac_addr[3],
(int) mac_addr[4], (int) mac_addr[5]) == -1) {
snprintf(err_msg, sizeof(err_msg),
"failed to format MAC: %s", strerror(errno));
error_set(errp, QERR_QGA_COMMAND_FAILED, err_msg);
goto error;
}
info->value->has_hardware_address = true;
close(sock);
}
if (ifa->ifa_addr &&
ifa->ifa_addr->sa_family == AF_INET) {
/* interface with IPv4 address */
address_item = g_malloc0(sizeof(*address_item));
address_item->value = g_malloc0(sizeof(*address_item->value));
p = &((struct sockaddr_in *)ifa->ifa_addr)->sin_addr;
if (!inet_ntop(AF_INET, p, addr4, sizeof(addr4))) {
snprintf(err_msg, sizeof(err_msg),
"inet_ntop failed : %s", strerror(errno));
error_set(errp, QERR_QGA_COMMAND_FAILED, err_msg);
goto error;
}
address_item->value->ip_address = g_strdup(addr4);
address_item->value->ip_address_type = GUEST_IP_ADDRESS_TYPE_IPV4;
if (ifa->ifa_netmask) {
/* Count the number of set bits in netmask.
* This is safe as '1' and '0' cannot be shuffled in netmask. */
p = &((struct sockaddr_in *)ifa->ifa_netmask)->sin_addr;
address_item->value->prefix = ctpop32(((uint32_t *) p)[0]);
}
} else if (ifa->ifa_addr &&
ifa->ifa_addr->sa_family == AF_INET6) {
/* interface with IPv6 address */
address_item = g_malloc0(sizeof(*address_item));
address_item->value = g_malloc0(sizeof(*address_item->value));
p = &((struct sockaddr_in6 *)ifa->ifa_addr)->sin6_addr;
if (!inet_ntop(AF_INET6, p, addr6, sizeof(addr6))) {
snprintf(err_msg, sizeof(err_msg),
"inet_ntop failed : %s", strerror(errno));
error_set(errp, QERR_QGA_COMMAND_FAILED, err_msg);
goto error;
}
address_item->value->ip_address = g_strdup(addr6);
address_item->value->ip_address_type = GUEST_IP_ADDRESS_TYPE_IPV6;
if (ifa->ifa_netmask) {
/* Count the number of set bits in netmask.
* This is safe as '1' and '0' cannot be shuffled in netmask. */
p = &((struct sockaddr_in6 *)ifa->ifa_netmask)->sin6_addr;
address_item->value->prefix =
ctpop32(((uint32_t *) p)[0]) +
ctpop32(((uint32_t *) p)[1]) +
ctpop32(((uint32_t *) p)[2]) +
ctpop32(((uint32_t *) p)[3]);
}
}
if (!address_item) {
continue;
}
address_list = &info->value->ip_addresses;
while (*address_list && (*address_list)->next) {
address_list = &(*address_list)->next;
}
if (!*address_list) {
*address_list = address_item;
} else {
(*address_list)->next = address_item;
}
info->value->has_ip_addresses = true;
}
freeifaddrs(ifap);
return head;
error:
freeifaddrs(ifap);
qapi_free_GuestNetworkInterfaceList(head);
return NULL;
}
| 0Non-vulnerable
|
Devign | b2af43cc379e1d4c30d92af257bedebf0e3f618a | qemu/qemu | https://github.com/qemu/qemu | https://github.com/qemu/qemu/commit/b2af43cc379e1d4c30d92af257bedebf0e3f618a | void qemu_spice_display_switch(SimpleSpiceDisplay *ssd,
DisplaySurface *surface)
{
SimpleSpiceUpdate *update;
bool need_destroy;
if (surface && ssd->surface &&
surface_width(surface) == pixman_image_get_width(ssd->surface) &&
surface_height(surface) == pixman_image_get_height(ssd->surface)) {
/* no-resize fast path: just swap backing store */
dprint(1, "%s/%d: fast (%dx%d)\n", __func__, ssd->qxl.id,
surface_width(surface), surface_height(surface));
qemu_mutex_lock(&ssd->lock);
ssd->ds = surface;
pixman_image_unref(ssd->surface);
ssd->surface = pixman_image_ref(ssd->ds->image);
qemu_mutex_unlock(&ssd->lock);
qemu_spice_display_update(ssd, 0, 0,
surface_width(surface),
surface_height(surface));
return;
}
/* full mode switch */
dprint(1, "%s/%d: full (%dx%d -> %dx%d)\n", __func__, ssd->qxl.id,
ssd->surface ? pixman_image_get_width(ssd->surface) : 0,
ssd->surface ? pixman_image_get_height(ssd->surface) : 0,
surface ? surface_width(surface) : 0,
surface ? surface_height(surface) : 0);
memset(&ssd->dirty, 0, sizeof(ssd->dirty));
if (ssd->surface) {
pixman_image_unref(ssd->surface);
ssd->surface = NULL;
pixman_image_unref(ssd->mirror);
ssd->mirror = NULL;
}
qemu_mutex_lock(&ssd->lock);
need_destroy = (ssd->ds != NULL);
ssd->ds = surface;
while ((update = QTAILQ_FIRST(&ssd->updates)) != NULL) {
QTAILQ_REMOVE(&ssd->updates, update, next);
qemu_spice_destroy_update(ssd, update);
}
qemu_mutex_unlock(&ssd->lock);
if (need_destroy) {
qemu_spice_destroy_host_primary(ssd);
}
if (ssd->ds) {
ssd->surface = pixman_image_ref(ssd->ds->image);
ssd->mirror = qemu_pixman_mirror_create(ssd->ds->format,
ssd->ds->image);
qemu_spice_create_host_primary(ssd);
}
memset(&ssd->dirty, 0, sizeof(ssd->dirty));
ssd->notify++;
}
| 0Non-vulnerable
|
Devign | 9937362c54be085e75c90c55dad443329be59e69 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/9937362c54be085e75c90c55dad443329be59e69 | void swri_resample_dsp_x86_init(ResampleContext *c)
{
int av_unused mm_flags = av_get_cpu_flags();
switch(c->format){
case AV_SAMPLE_FMT_S16P:
if (ARCH_X86_32 && HAVE_MMXEXT_EXTERNAL && mm_flags & AV_CPU_FLAG_MMX2) {
c->dsp.resample = c->linear ? ff_resample_linear_int16_mmxext
: ff_resample_common_int16_mmxext;
}
if (HAVE_SSE2_EXTERNAL && mm_flags & AV_CPU_FLAG_SSE2) {
c->dsp.resample = c->linear ? ff_resample_linear_int16_sse2
: ff_resample_common_int16_sse2;
}
if (HAVE_XOP_EXTERNAL && mm_flags & AV_CPU_FLAG_XOP) {
c->dsp.resample = c->linear ? ff_resample_linear_int16_xop
: ff_resample_common_int16_xop;
}
break;
case AV_SAMPLE_FMT_FLTP:
if (HAVE_SSE_EXTERNAL && mm_flags & AV_CPU_FLAG_SSE) {
c->dsp.resample = c->linear ? ff_resample_linear_float_sse
: ff_resample_common_float_sse;
}
if (HAVE_AVX_EXTERNAL && mm_flags & AV_CPU_FLAG_AVX) {
c->dsp.resample = c->linear ? ff_resample_linear_float_avx
: ff_resample_common_float_avx;
}
if (HAVE_FMA3_EXTERNAL && mm_flags & AV_CPU_FLAG_FMA3) {
c->dsp.resample = c->linear ? ff_resample_linear_float_fma3
: ff_resample_common_float_fma3;
}
if (HAVE_FMA4_EXTERNAL && mm_flags & AV_CPU_FLAG_FMA4) {
c->dsp.resample = c->linear ? ff_resample_linear_float_fma4
: ff_resample_common_float_fma4;
}
break;
case AV_SAMPLE_FMT_DBLP:
if (HAVE_SSE2_EXTERNAL && mm_flags & AV_CPU_FLAG_SSE2) {
c->dsp.resample = c->linear ? ff_resample_linear_double_sse2
: ff_resample_common_double_sse2;
}
break;
}
}
| 0Non-vulnerable
|
Devign | 4b1f5e5090abed6c618c8ba380cd7d28d140f867 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/4b1f5e5090abed6c618c8ba380cd7d28d140f867 | static void coded_frame_add(void *list, struct FrameListData *cx_frame)
{
struct FrameListData **p = list;
while (*p != NULL)
p = &(*p)->next;
*p = cx_frame;
cx_frame->next = NULL;
}
| 0Non-vulnerable
|
Devign | 659d4ba5af5d72716ee370bb367c741bd15e75b4 | FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg | https://github.com/FFmpeg/FFmpeg/commit/659d4ba5af5d72716ee370bb367c741bd15e75b4 | static void h263_h_loop_filter_mmx(uint8_t *src, int stride, int qscale)
{
if (CONFIG_H263_DECODER || CONFIG_H263_ENCODER) {
const int strength = ff_h263_loop_filter_strength[qscale];
DECLARE_ALIGNED(8, uint64_t, temp)[4];
uint8_t *btemp = (uint8_t*)temp;
src -= 2;
transpose4x4(btemp, src, 8, stride);
transpose4x4(btemp + 4, src + 4 * stride, 8, stride);
__asm__ volatile (
H263_LOOP_FILTER // 5 3 4 6
: "+m"(temp[0]),
"+m"(temp[1]),
"+m"(temp[2]),
"+m"(temp[3])
: "g"(2 * strength), "m"(ff_pb_FC)
);
__asm__ volatile (
"movq %%mm5, %%mm1 \n\t"
"movq %%mm4, %%mm0 \n\t"
"punpcklbw %%mm3, %%mm5 \n\t"
"punpcklbw %%mm6, %%mm4 \n\t"
"punpckhbw %%mm3, %%mm1 \n\t"
"punpckhbw %%mm6, %%mm0 \n\t"
"movq %%mm5, %%mm3 \n\t"
"movq %%mm1, %%mm6 \n\t"
"punpcklwd %%mm4, %%mm5 \n\t"
"punpcklwd %%mm0, %%mm1 \n\t"
"punpckhwd %%mm4, %%mm3 \n\t"
"punpckhwd %%mm0, %%mm6 \n\t"
"movd %%mm5, (%0) \n\t"
"punpckhdq %%mm5, %%mm5 \n\t"
"movd %%mm5, (%0, %2) \n\t"
"movd %%mm3, (%0, %2, 2) \n\t"
"punpckhdq %%mm3, %%mm3 \n\t"
"movd %%mm3, (%0, %3) \n\t"
"movd %%mm1, (%1) \n\t"
"punpckhdq %%mm1, %%mm1 \n\t"
"movd %%mm1, (%1, %2) \n\t"
"movd %%mm6, (%1, %2, 2) \n\t"
"punpckhdq %%mm6, %%mm6 \n\t"
"movd %%mm6, (%1, %3) \n\t"
:: "r"(src),
"r"(src + 4 * stride),
"r"((x86_reg)stride),
"r"((x86_reg)(3 * stride))
);
}
}
| 0Non-vulnerable
|
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